1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_PHY_H__ 6 #define __RTW89_PHY_H__ 7 8 #include "core.h" 9 10 #define RTW89_PHY_ADDR_OFFSET 0x10000 11 12 #define get_phy_headline(addr) FIELD_GET(GENMASK(31, 28), addr) 13 #define PHY_HEADLINE_VALID 0xf 14 #define get_phy_target(addr) FIELD_GET(GENMASK(27, 0), addr) 15 #define get_phy_compare(rfe, cv) (FIELD_PREP(GENMASK(23, 16), rfe) | \ 16 FIELD_PREP(GENMASK(7, 0), cv)) 17 18 #define get_phy_cond(addr) FIELD_GET(GENMASK(31, 28), addr) 19 #define get_phy_cond_rfe(addr) FIELD_GET(GENMASK(23, 16), addr) 20 #define get_phy_cond_pkg(addr) FIELD_GET(GENMASK(15, 8), addr) 21 #define get_phy_cond_cv(addr) FIELD_GET(GENMASK(7, 0), addr) 22 #define phy_div(a, b) ({typeof(b) _b = (b); (_b) ? ((a) / (_b)) : 0; }) 23 #define PHY_COND_BRANCH_IF 0x8 24 #define PHY_COND_BRANCH_ELIF 0x9 25 #define PHY_COND_BRANCH_ELSE 0xa 26 #define PHY_COND_BRANCH_END 0xb 27 #define PHY_COND_CHECK 0x4 28 #define PHY_COND_DONT_CARE 0xff 29 30 #define RA_MASK_CCK_RATES GENMASK_ULL(3, 0) 31 #define RA_MASK_OFDM_RATES GENMASK_ULL(11, 4) 32 #define RA_MASK_SUBCCK_RATES 0x5ULL 33 #define RA_MASK_SUBOFDM_RATES 0x10ULL 34 #define RA_MASK_HT_1SS_RATES GENMASK_ULL(19, 12) 35 #define RA_MASK_HT_2SS_RATES GENMASK_ULL(31, 24) 36 #define RA_MASK_HT_3SS_RATES GENMASK_ULL(43, 36) 37 #define RA_MASK_HT_4SS_RATES GENMASK_ULL(55, 48) 38 #define RA_MASK_HT_RATES GENMASK_ULL(55, 12) 39 #define RA_MASK_VHT_1SS_RATES GENMASK_ULL(21, 12) 40 #define RA_MASK_VHT_2SS_RATES GENMASK_ULL(33, 24) 41 #define RA_MASK_VHT_3SS_RATES GENMASK_ULL(45, 36) 42 #define RA_MASK_VHT_4SS_RATES GENMASK_ULL(57, 48) 43 #define RA_MASK_VHT_RATES GENMASK_ULL(57, 12) 44 #define RA_MASK_HE_1SS_RATES GENMASK_ULL(23, 12) 45 #define RA_MASK_HE_2SS_RATES GENMASK_ULL(35, 24) 46 #define RA_MASK_HE_3SS_RATES GENMASK_ULL(47, 36) 47 #define RA_MASK_HE_4SS_RATES GENMASK_ULL(59, 48) 48 #define RA_MASK_HE_RATES GENMASK_ULL(59, 12) 49 50 #define CFO_TRK_ENABLE_TH (2 << 2) 51 #define CFO_TRK_STOP_TH_4 (30 << 2) 52 #define CFO_TRK_STOP_TH_3 (20 << 2) 53 #define CFO_TRK_STOP_TH_2 (10 << 2) 54 #define CFO_TRK_STOP_TH_1 (00 << 2) 55 #define CFO_TRK_STOP_TH (2 << 2) 56 #define CFO_SW_COMP_FINE_TUNE (2 << 2) 57 #define CFO_PERIOD_CNT 15 58 #define CFO_TP_UPPER 100 59 #define CFO_TP_LOWER 50 60 #define CFO_COMP_PERIOD 250 61 #define CFO_COMP_WEIGHT 8 62 #define MAX_CFO_TOLERANCE 30 63 64 #define CCX_MAX_PERIOD 2097 65 #define CCX_MAX_PERIOD_UNIT 32 66 #define MS_TO_4US_RATIO 250 67 #define ENV_MNTR_FAIL_DWORD 0xffffffff 68 #define ENV_MNTR_IFSCLM_HIS_MAX 127 69 #define PERMIL 1000 70 #define PERCENT 100 71 #define IFS_CLM_TH0_UPPER 64 72 #define IFS_CLM_TH_MUL 4 73 #define IFS_CLM_TH_START_IDX 0 74 75 #define TIA0_GAIN_A 12 76 #define TIA0_GAIN_G 16 77 #define LNA0_GAIN (-24) 78 #define U4_MAX_BIT 3 79 #define U8_MAX_BIT 7 80 #define DIG_GAIN_SHIFT 2 81 #define DIG_GAIN 8 82 83 #define LNA_IDX_MAX 6 84 #define LNA_IDX_MIN 0 85 #define TIA_IDX_MAX 1 86 #define TIA_IDX_MIN 0 87 #define RXB_IDX_MAX 31 88 #define RXB_IDX_MIN 0 89 90 #define PD_TH_MAX_RSSI 70 91 #define PD_TH_MIN_RSSI 8 92 #define PD_TH_BW80_CMP_VAL 6 93 #define PD_TH_BW40_CMP_VAL 3 94 #define PD_TH_BW20_CMP_VAL 0 95 #define PD_TH_CMP_VAL 3 96 #define PD_TH_SB_FLTR_CMP_VAL 7 97 98 #define PHYSTS_MGNT BIT(RTW89_RX_TYPE_MGNT) 99 #define PHYSTS_CTRL BIT(RTW89_RX_TYPE_CTRL) 100 #define PHYSTS_DATA BIT(RTW89_RX_TYPE_DATA) 101 #define PHYSTS_RSVD BIT(RTW89_RX_TYPE_RSVD) 102 #define PPDU_FILTER_BITMAP (PHYSTS_MGNT | PHYSTS_DATA) 103 104 enum rtw89_phy_c2h_ra_func { 105 RTW89_PHY_C2H_FUNC_STS_RPT, 106 RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT, 107 RTW89_PHY_C2H_FUNC_TXSTS, 108 RTW89_PHY_C2H_FUNC_RA_MAX, 109 }; 110 111 enum rtw89_phy_c2h_class { 112 RTW89_PHY_C2H_CLASS_RUA, 113 RTW89_PHY_C2H_CLASS_RA, 114 RTW89_PHY_C2H_CLASS_DM, 115 RTW89_PHY_C2H_CLASS_BTC_MIN = 0x10, 116 RTW89_PHY_C2H_CLASS_BTC_MAX = 0x17, 117 RTW89_PHY_C2H_CLASS_MAX, 118 }; 119 120 enum rtw89_env_monitor_result_level { 121 RTW89_PHY_ENV_MON_CCX_FAIL = 0, 122 RTW89_PHY_ENV_MON_NHM = BIT(0), 123 RTW89_PHY_ENV_MON_CLM = BIT(1), 124 RTW89_PHY_ENV_MON_FAHM = BIT(2), 125 RTW89_PHY_ENV_MON_IFS_CLM = BIT(3), 126 RTW89_PHY_ENV_MON_EDCCA_CLM = BIT(4), 127 }; 128 129 #define CCX_US_BASE_RATIO 4 130 enum rtw89_ccx_unit { 131 RTW89_CCX_4_US = 0, 132 RTW89_CCX_8_US = 1, 133 RTW89_CCX_16_US = 2, 134 RTW89_CCX_32_US = 3 135 }; 136 137 enum rtw89_dig_gain_type { 138 RTW89_DIG_GAIN_LNA_G = 0, 139 RTW89_DIG_GAIN_TIA_G = 1, 140 RTW89_DIG_GAIN_LNA_A = 2, 141 RTW89_DIG_GAIN_TIA_A = 3, 142 RTW89_DIG_GAIN_MAX = 4 143 }; 144 145 enum rtw89_dig_gain_lna_idx { 146 RTW89_DIG_GAIN_LNA_IDX1 = 1, 147 RTW89_DIG_GAIN_LNA_IDX2 = 2, 148 RTW89_DIG_GAIN_LNA_IDX3 = 3, 149 RTW89_DIG_GAIN_LNA_IDX4 = 4, 150 RTW89_DIG_GAIN_LNA_IDX5 = 5, 151 RTW89_DIG_GAIN_LNA_IDX6 = 6 152 }; 153 154 enum rtw89_dig_gain_tia_idx { 155 RTW89_DIG_GAIN_TIA_IDX0 = 0, 156 RTW89_DIG_GAIN_TIA_IDX1 = 1 157 }; 158 159 struct rtw89_txpwr_byrate_cfg { 160 enum rtw89_band band; 161 enum rtw89_nss nss; 162 enum rtw89_rate_section rs; 163 u8 shf; 164 u8 len; 165 u32 data; 166 }; 167 168 #define DELTA_SWINGIDX_SIZE 30 169 170 struct rtw89_txpwr_track_cfg { 171 const u8 (*delta_swingidx_5gb_n)[DELTA_SWINGIDX_SIZE]; 172 const u8 (*delta_swingidx_5gb_p)[DELTA_SWINGIDX_SIZE]; 173 const u8 (*delta_swingidx_5ga_n)[DELTA_SWINGIDX_SIZE]; 174 const u8 (*delta_swingidx_5ga_p)[DELTA_SWINGIDX_SIZE]; 175 const u8 *delta_swingidx_2gb_n; 176 const u8 *delta_swingidx_2gb_p; 177 const u8 *delta_swingidx_2ga_n; 178 const u8 *delta_swingidx_2ga_p; 179 const u8 *delta_swingidx_2g_cck_b_n; 180 const u8 *delta_swingidx_2g_cck_b_p; 181 const u8 *delta_swingidx_2g_cck_a_n; 182 const u8 *delta_swingidx_2g_cck_a_p; 183 }; 184 185 struct rtw89_phy_dig_gain_cfg { 186 const struct rtw89_reg_def *table; 187 u8 size; 188 }; 189 190 struct rtw89_phy_dig_gain_table { 191 const struct rtw89_phy_dig_gain_cfg *cfg_lna_g; 192 const struct rtw89_phy_dig_gain_cfg *cfg_tia_g; 193 const struct rtw89_phy_dig_gain_cfg *cfg_lna_a; 194 const struct rtw89_phy_dig_gain_cfg *cfg_tia_a; 195 }; 196 197 struct rtw89_phy_reg3_tbl { 198 const struct rtw89_reg3_def *reg3; 199 int size; 200 }; 201 202 #define DECLARE_PHY_REG3_TBL(_name) \ 203 const struct rtw89_phy_reg3_tbl _name ## _tbl = { \ 204 .reg3 = _name, \ 205 .size = ARRAY_SIZE(_name), \ 206 } 207 208 static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev, 209 u32 addr, u8 data) 210 { 211 rtw89_write8(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data); 212 } 213 214 static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev, 215 u32 addr, u16 data) 216 { 217 rtw89_write16(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data); 218 } 219 220 static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev, 221 u32 addr, u32 data) 222 { 223 rtw89_write32(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data); 224 } 225 226 static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev, 227 u32 addr, u32 bits) 228 { 229 rtw89_write32_set(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, bits); 230 } 231 232 static inline void rtw89_phy_write32_clr(struct rtw89_dev *rtwdev, 233 u32 addr, u32 bits) 234 { 235 rtw89_write32_clr(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, bits); 236 } 237 238 static inline void rtw89_phy_write32_mask(struct rtw89_dev *rtwdev, 239 u32 addr, u32 mask, u32 data) 240 { 241 rtw89_write32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask, data); 242 } 243 244 static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr) 245 { 246 return rtw89_read8(rtwdev, addr | RTW89_PHY_ADDR_OFFSET); 247 } 248 249 static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr) 250 { 251 return rtw89_read16(rtwdev, addr | RTW89_PHY_ADDR_OFFSET); 252 } 253 254 static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr) 255 { 256 return rtw89_read32(rtwdev, addr | RTW89_PHY_ADDR_OFFSET); 257 } 258 259 static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev, 260 u32 addr, u32 mask) 261 { 262 return rtw89_read32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask); 263 } 264 265 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 266 const struct rtw89_phy_reg3_tbl *tbl); 267 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 268 struct rtw89_channel_params *param, 269 enum rtw89_bandwidth dbw); 270 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 271 u32 addr, u32 mask); 272 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 273 u32 addr, u32 mask, u32 data); 274 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev); 275 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev); 276 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev); 277 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 278 u32 data, enum rtw89_phy_idx phy_idx); 279 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 280 const struct rtw89_txpwr_table *tbl); 281 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, 282 const struct rtw89_rate_desc *rate_desc); 283 void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev, 284 struct rtw89_txpwr_limit *lmt, 285 u8 ntx); 286 void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev, 287 struct rtw89_txpwr_limit_ru *lmt_ru, 288 u8 ntx); 289 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, 290 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch); 291 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta); 292 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev); 293 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta); 294 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 295 struct ieee80211_vif *vif, 296 const struct cfg80211_bitrate_mask *mask); 297 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 298 u32 len, u8 class, u8 func); 299 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev); 300 void rtw89_phy_cfo_track_work(struct work_struct *work); 301 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 302 struct rtw89_rx_phy_ppdu *phy_ppdu); 303 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev); 304 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev); 305 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 306 u32 val); 307 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev); 308 void rtw89_phy_dig(struct rtw89_dev *rtwdev); 309 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 310 311 #endif 312