1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_PHY_H__ 6 #define __RTW89_PHY_H__ 7 8 #include "core.h" 9 10 #define RTW89_RF_ADDR_ADSEL_MASK BIT(16) 11 12 #define get_phy_headline(addr) FIELD_GET(GENMASK(31, 28), addr) 13 #define PHY_HEADLINE_VALID 0xf 14 #define get_phy_target(addr) FIELD_GET(GENMASK(27, 0), addr) 15 #define get_phy_compare(rfe, cv) (FIELD_PREP(GENMASK(23, 16), rfe) | \ 16 FIELD_PREP(GENMASK(7, 0), cv)) 17 18 #define get_phy_cond(addr) FIELD_GET(GENMASK(31, 28), addr) 19 #define get_phy_cond_rfe(addr) FIELD_GET(GENMASK(23, 16), addr) 20 #define get_phy_cond_pkg(addr) FIELD_GET(GENMASK(15, 8), addr) 21 #define get_phy_cond_cv(addr) FIELD_GET(GENMASK(7, 0), addr) 22 #define phy_div(a, b) ({typeof(b) _b = (b); (_b) ? ((a) / (_b)) : 0; }) 23 #define PHY_COND_BRANCH_IF 0x8 24 #define PHY_COND_BRANCH_ELIF 0x9 25 #define PHY_COND_BRANCH_ELSE 0xa 26 #define PHY_COND_BRANCH_END 0xb 27 #define PHY_COND_CHECK 0x4 28 #define PHY_COND_DONT_CARE 0xff 29 30 #define RA_MASK_CCK_RATES GENMASK_ULL(3, 0) 31 #define RA_MASK_OFDM_RATES GENMASK_ULL(11, 4) 32 #define RA_MASK_SUBCCK_RATES 0x5ULL 33 #define RA_MASK_SUBOFDM_RATES 0x10ULL 34 #define RA_MASK_HT_1SS_RATES GENMASK_ULL(19, 12) 35 #define RA_MASK_HT_2SS_RATES GENMASK_ULL(31, 24) 36 #define RA_MASK_HT_3SS_RATES GENMASK_ULL(43, 36) 37 #define RA_MASK_HT_4SS_RATES GENMASK_ULL(55, 48) 38 #define RA_MASK_HT_RATES GENMASK_ULL(55, 12) 39 #define RA_MASK_VHT_1SS_RATES GENMASK_ULL(21, 12) 40 #define RA_MASK_VHT_2SS_RATES GENMASK_ULL(33, 24) 41 #define RA_MASK_VHT_3SS_RATES GENMASK_ULL(45, 36) 42 #define RA_MASK_VHT_4SS_RATES GENMASK_ULL(57, 48) 43 #define RA_MASK_VHT_RATES GENMASK_ULL(57, 12) 44 #define RA_MASK_HE_1SS_RATES GENMASK_ULL(23, 12) 45 #define RA_MASK_HE_2SS_RATES GENMASK_ULL(35, 24) 46 #define RA_MASK_HE_3SS_RATES GENMASK_ULL(47, 36) 47 #define RA_MASK_HE_4SS_RATES GENMASK_ULL(59, 48) 48 #define RA_MASK_HE_RATES GENMASK_ULL(59, 12) 49 50 #define CFO_TRK_ENABLE_TH (2 << 2) 51 #define CFO_TRK_STOP_TH_4 (30 << 2) 52 #define CFO_TRK_STOP_TH_3 (20 << 2) 53 #define CFO_TRK_STOP_TH_2 (10 << 2) 54 #define CFO_TRK_STOP_TH_1 (00 << 2) 55 #define CFO_TRK_STOP_TH (2 << 2) 56 #define CFO_SW_COMP_FINE_TUNE (2 << 2) 57 #define CFO_PERIOD_CNT 15 58 #define CFO_BOUND 64 59 #define CFO_TP_UPPER 100 60 #define CFO_TP_LOWER 50 61 #define CFO_COMP_PERIOD 250 62 #define CFO_COMP_WEIGHT 8 63 #define MAX_CFO_TOLERANCE 30 64 #define CFO_TF_CNT_TH 300 65 66 #define UL_TB_TF_CNT_L2H_TH 100 67 #define UL_TB_TF_CNT_H2L_TH 70 68 69 #define ANTDIV_TRAINNING_CNT 2 70 #define ANTDIV_TRAINNING_INTVL 30 71 #define ANTDIV_DELAY 110 72 #define ANTDIV_TP_DIFF_TH_HIGH 100 73 #define ANTDIV_TP_DIFF_TH_LOW 5 74 #define ANTDIV_EVM_DIFF_TH 8 75 #define ANTDIV_RSSI_DIFF_TH 3 76 77 #define CCX_MAX_PERIOD 2097 78 #define CCX_MAX_PERIOD_UNIT 32 79 #define MS_TO_4US_RATIO 250 80 #define ENV_MNTR_FAIL_DWORD 0xffffffff 81 #define ENV_MNTR_IFSCLM_HIS_MAX 127 82 #define PERMIL 1000 83 #define PERCENT 100 84 #define IFS_CLM_TH0_UPPER 64 85 #define IFS_CLM_TH_MUL 4 86 #define IFS_CLM_TH_START_IDX 0 87 88 #define TIA0_GAIN_A 12 89 #define TIA0_GAIN_G 16 90 #define LNA0_GAIN (-24) 91 #define U4_MAX_BIT 3 92 #define U8_MAX_BIT 7 93 #define DIG_GAIN_SHIFT 2 94 #define DIG_GAIN 8 95 96 #define LNA_IDX_MAX 6 97 #define LNA_IDX_MIN 0 98 #define TIA_IDX_MAX 1 99 #define TIA_IDX_MIN 0 100 #define RXB_IDX_MAX 31 101 #define RXB_IDX_MIN 0 102 103 #define IGI_RSSI_MAX 110 104 #define PD_TH_MAX_RSSI 70 105 #define PD_TH_MIN_RSSI 8 106 #define CCKPD_TH_MIN_RSSI (-18) 107 #define PD_TH_BW160_CMP_VAL 9 108 #define PD_TH_BW80_CMP_VAL 6 109 #define PD_TH_BW40_CMP_VAL 3 110 #define PD_TH_BW20_CMP_VAL 0 111 #define PD_TH_CMP_VAL 3 112 #define PD_TH_SB_FLTR_CMP_VAL 7 113 114 #define PHYSTS_MGNT BIT(RTW89_RX_TYPE_MGNT) 115 #define PHYSTS_CTRL BIT(RTW89_RX_TYPE_CTRL) 116 #define PHYSTS_DATA BIT(RTW89_RX_TYPE_DATA) 117 #define PHYSTS_RSVD BIT(RTW89_RX_TYPE_RSVD) 118 #define PPDU_FILTER_BITMAP (PHYSTS_MGNT | PHYSTS_DATA) 119 120 enum rtw89_phy_c2h_ra_func { 121 RTW89_PHY_C2H_FUNC_STS_RPT, 122 RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT, 123 RTW89_PHY_C2H_FUNC_TXSTS, 124 RTW89_PHY_C2H_FUNC_RA_MAX, 125 }; 126 127 enum rtw89_phy_c2h_dm_func { 128 RTW89_PHY_C2H_DM_FUNC_FW_TEST, 129 RTW89_PHY_C2H_DM_FUNC_FW_TRIG_TX_RPT, 130 RTW89_PHY_C2H_DM_FUNC_SIGB, 131 RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY, 132 RTW89_PHY_C2H_DM_FUNC_MCC_DIG, 133 RTW89_PHY_C2H_DM_FUNC_NUM, 134 }; 135 136 enum rtw89_phy_c2h_class { 137 RTW89_PHY_C2H_CLASS_RUA, 138 RTW89_PHY_C2H_CLASS_RA, 139 RTW89_PHY_C2H_CLASS_DM, 140 RTW89_PHY_C2H_CLASS_BTC_MIN = 0x10, 141 RTW89_PHY_C2H_CLASS_BTC_MAX = 0x17, 142 RTW89_PHY_C2H_CLASS_MAX, 143 }; 144 145 enum rtw89_env_monitor_result_level { 146 RTW89_PHY_ENV_MON_CCX_FAIL = 0, 147 RTW89_PHY_ENV_MON_NHM = BIT(0), 148 RTW89_PHY_ENV_MON_CLM = BIT(1), 149 RTW89_PHY_ENV_MON_FAHM = BIT(2), 150 RTW89_PHY_ENV_MON_IFS_CLM = BIT(3), 151 RTW89_PHY_ENV_MON_EDCCA_CLM = BIT(4), 152 }; 153 154 #define CCX_US_BASE_RATIO 4 155 enum rtw89_ccx_unit { 156 RTW89_CCX_4_US = 0, 157 RTW89_CCX_8_US = 1, 158 RTW89_CCX_16_US = 2, 159 RTW89_CCX_32_US = 3 160 }; 161 162 enum rtw89_phy_status_ie_type { 163 RTW89_PHYSTS_IE00_CMN_CCK = 0, 164 RTW89_PHYSTS_IE01_CMN_OFDM = 1, 165 RTW89_PHYSTS_IE02_CMN_EXT_AX = 2, 166 RTW89_PHYSTS_IE03_CMN_EXT_SEG_1 = 3, 167 RTW89_PHYSTS_IE04_CMN_EXT_PATH_A = 4, 168 RTW89_PHYSTS_IE05_CMN_EXT_PATH_B = 5, 169 RTW89_PHYSTS_IE06_CMN_EXT_PATH_C = 6, 170 RTW89_PHYSTS_IE07_CMN_EXT_PATH_D = 7, 171 RTW89_PHYSTS_IE08_FTR_CH = 8, 172 RTW89_PHYSTS_IE09_FTR_0 = 9, 173 RTW89_PHYSTS_IE10_FTR_PLCP_EXT = 10, 174 RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM = 11, 175 RTW89_PHYSTS_IE12_MU_EIGEN_INFO = 12, 176 RTW89_PHYSTS_IE13_DL_MU_DEF = 13, 177 RTW89_PHYSTS_IE14_TB_UL_CQI = 14, 178 RTW89_PHYSTS_IE15_TB_UL_DEF = 15, 179 RTW89_PHYSTS_IE16_RSVD16 = 16, 180 RTW89_PHYSTS_IE17_TB_UL_CTRL = 17, 181 RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN = 18, 182 RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN = 19, 183 RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0 = 20, 184 RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1 = 21, 185 RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC = 22, 186 RTW89_PHYSTS_IE23_RSVD23 = 23, 187 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A = 24, 188 RTW89_PHYSTS_IE25_OFDM_TD_PATH_B = 25, 189 RTW89_PHYSTS_IE26_OFDM_TD_PATH_C = 26, 190 RTW89_PHYSTS_IE27_OFDM_TD_PATH_D = 27, 191 RTW89_PHYSTS_IE28_DBG_CCK_PATH_A = 28, 192 RTW89_PHYSTS_IE29_DBG_CCK_PATH_B = 29, 193 RTW89_PHYSTS_IE30_DBG_CCK_PATH_C = 30, 194 RTW89_PHYSTS_IE31_DBG_CCK_PATH_D = 31, 195 196 /* keep last */ 197 RTW89_PHYSTS_IE_NUM, 198 RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1 199 }; 200 201 enum rtw89_phy_status_bitmap { 202 RTW89_TD_SEARCH_FAIL = 0, 203 RTW89_BRK_BY_TX_PKT = 1, 204 RTW89_CCA_SPOOF = 2, 205 RTW89_OFDM_BRK = 3, 206 RTW89_CCK_BRK = 4, 207 RTW89_DL_MU_SPOOFING = 5, 208 RTW89_HE_MU = 6, 209 RTW89_VHT_MU = 7, 210 RTW89_UL_TB_SPOOFING = 8, 211 RTW89_RSVD_9 = 9, 212 RTW89_TRIG_BASE_PPDU = 10, 213 RTW89_CCK_PKT = 11, 214 RTW89_LEGACY_OFDM_PKT = 12, 215 RTW89_HT_PKT = 13, 216 RTW89_VHT_PKT = 14, 217 RTW89_HE_PKT = 15, 218 219 RTW89_PHYSTS_BITMAP_NUM 220 }; 221 222 enum rtw89_dig_gain_type { 223 RTW89_DIG_GAIN_LNA_G = 0, 224 RTW89_DIG_GAIN_TIA_G = 1, 225 RTW89_DIG_GAIN_LNA_A = 2, 226 RTW89_DIG_GAIN_TIA_A = 3, 227 RTW89_DIG_GAIN_MAX = 4 228 }; 229 230 enum rtw89_dig_gain_lna_idx { 231 RTW89_DIG_GAIN_LNA_IDX1 = 1, 232 RTW89_DIG_GAIN_LNA_IDX2 = 2, 233 RTW89_DIG_GAIN_LNA_IDX3 = 3, 234 RTW89_DIG_GAIN_LNA_IDX4 = 4, 235 RTW89_DIG_GAIN_LNA_IDX5 = 5, 236 RTW89_DIG_GAIN_LNA_IDX6 = 6 237 }; 238 239 enum rtw89_dig_gain_tia_idx { 240 RTW89_DIG_GAIN_TIA_IDX0 = 0, 241 RTW89_DIG_GAIN_TIA_IDX1 = 1 242 }; 243 244 enum rtw89_tssi_bandedge_cfg { 245 RTW89_TSSI_BANDEDGE_FLAT, 246 RTW89_TSSI_BANDEDGE_LOW, 247 RTW89_TSSI_BANDEDGE_MID, 248 RTW89_TSSI_BANDEDGE_HIGH, 249 250 RTW89_TSSI_CFG_NUM, 251 }; 252 253 enum rtw89_tssi_sbw_idx { 254 RTW89_TSSI_SBW20, 255 RTW89_TSSI_SBW40_0, 256 RTW89_TSSI_SBW40_1, 257 RTW89_TSSI_SBW80_0, 258 RTW89_TSSI_SBW80_1, 259 RTW89_TSSI_SBW80_2, 260 RTW89_TSSI_SBW80_3, 261 RTW89_TSSI_SBW160_0, 262 RTW89_TSSI_SBW160_1, 263 RTW89_TSSI_SBW160_2, 264 RTW89_TSSI_SBW160_3, 265 RTW89_TSSI_SBW160_4, 266 RTW89_TSSI_SBW160_5, 267 RTW89_TSSI_SBW160_6, 268 RTW89_TSSI_SBW160_7, 269 270 RTW89_TSSI_SBW_NUM, 271 }; 272 273 struct rtw89_txpwr_byrate_cfg { 274 enum rtw89_band band; 275 enum rtw89_nss nss; 276 enum rtw89_rate_section rs; 277 u8 shf; 278 u8 len; 279 u32 data; 280 }; 281 282 #define DELTA_SWINGIDX_SIZE 30 283 284 struct rtw89_txpwr_track_cfg { 285 const s8 (*delta_swingidx_6gb_n)[DELTA_SWINGIDX_SIZE]; 286 const s8 (*delta_swingidx_6gb_p)[DELTA_SWINGIDX_SIZE]; 287 const s8 (*delta_swingidx_6ga_n)[DELTA_SWINGIDX_SIZE]; 288 const s8 (*delta_swingidx_6ga_p)[DELTA_SWINGIDX_SIZE]; 289 const s8 (*delta_swingidx_5gb_n)[DELTA_SWINGIDX_SIZE]; 290 const s8 (*delta_swingidx_5gb_p)[DELTA_SWINGIDX_SIZE]; 291 const s8 (*delta_swingidx_5ga_n)[DELTA_SWINGIDX_SIZE]; 292 const s8 (*delta_swingidx_5ga_p)[DELTA_SWINGIDX_SIZE]; 293 const s8 *delta_swingidx_2gb_n; 294 const s8 *delta_swingidx_2gb_p; 295 const s8 *delta_swingidx_2ga_n; 296 const s8 *delta_swingidx_2ga_p; 297 const s8 *delta_swingidx_2g_cck_b_n; 298 const s8 *delta_swingidx_2g_cck_b_p; 299 const s8 *delta_swingidx_2g_cck_a_n; 300 const s8 *delta_swingidx_2g_cck_a_p; 301 }; 302 303 struct rtw89_phy_dig_gain_cfg { 304 const struct rtw89_reg_def *table; 305 u8 size; 306 }; 307 308 struct rtw89_phy_dig_gain_table { 309 const struct rtw89_phy_dig_gain_cfg *cfg_lna_g; 310 const struct rtw89_phy_dig_gain_cfg *cfg_tia_g; 311 const struct rtw89_phy_dig_gain_cfg *cfg_lna_a; 312 const struct rtw89_phy_dig_gain_cfg *cfg_tia_a; 313 }; 314 315 struct rtw89_phy_tssi_dbw_table { 316 u32 data[RTW89_TSSI_CFG_NUM][RTW89_TSSI_SBW_NUM]; 317 }; 318 319 struct rtw89_phy_reg3_tbl { 320 const struct rtw89_reg3_def *reg3; 321 int size; 322 }; 323 324 #define DECLARE_PHY_REG3_TBL(_name) \ 325 const struct rtw89_phy_reg3_tbl _name ## _tbl = { \ 326 .reg3 = _name, \ 327 .size = ARRAY_SIZE(_name), \ 328 } 329 330 struct rtw89_nbi_reg_def { 331 struct rtw89_reg_def notch1_idx; 332 struct rtw89_reg_def notch1_frac_idx; 333 struct rtw89_reg_def notch1_en; 334 struct rtw89_reg_def notch2_idx; 335 struct rtw89_reg_def notch2_frac_idx; 336 struct rtw89_reg_def notch2_en; 337 }; 338 339 struct rtw89_ccx_regs { 340 u32 setting_addr; 341 u32 edcca_opt_mask; 342 u32 measurement_trig_mask; 343 u32 trig_opt_mask; 344 u32 en_mask; 345 u32 ifs_cnt_addr; 346 u32 ifs_clm_period_mask; 347 u32 ifs_clm_cnt_unit_mask; 348 u32 ifs_clm_cnt_clear_mask; 349 u32 ifs_collect_en_mask; 350 u32 ifs_t1_addr; 351 u32 ifs_t1_th_h_mask; 352 u32 ifs_t1_en_mask; 353 u32 ifs_t1_th_l_mask; 354 u32 ifs_t2_addr; 355 u32 ifs_t2_th_h_mask; 356 u32 ifs_t2_en_mask; 357 u32 ifs_t2_th_l_mask; 358 u32 ifs_t3_addr; 359 u32 ifs_t3_th_h_mask; 360 u32 ifs_t3_en_mask; 361 u32 ifs_t3_th_l_mask; 362 u32 ifs_t4_addr; 363 u32 ifs_t4_th_h_mask; 364 u32 ifs_t4_en_mask; 365 u32 ifs_t4_th_l_mask; 366 u32 ifs_clm_tx_cnt_addr; 367 u32 ifs_clm_edcca_excl_cca_fa_mask; 368 u32 ifs_clm_tx_cnt_msk; 369 u32 ifs_clm_cca_addr; 370 u32 ifs_clm_ofdmcca_excl_fa_mask; 371 u32 ifs_clm_cckcca_excl_fa_mask; 372 u32 ifs_clm_fa_addr; 373 u32 ifs_clm_ofdm_fa_mask; 374 u32 ifs_clm_cck_fa_mask; 375 u32 ifs_his_addr; 376 u32 ifs_t4_his_mask; 377 u32 ifs_t3_his_mask; 378 u32 ifs_t2_his_mask; 379 u32 ifs_t1_his_mask; 380 u32 ifs_avg_l_addr; 381 u32 ifs_t2_avg_mask; 382 u32 ifs_t1_avg_mask; 383 u32 ifs_avg_h_addr; 384 u32 ifs_t4_avg_mask; 385 u32 ifs_t3_avg_mask; 386 u32 ifs_cca_l_addr; 387 u32 ifs_t2_cca_mask; 388 u32 ifs_t1_cca_mask; 389 u32 ifs_cca_h_addr; 390 u32 ifs_t4_cca_mask; 391 u32 ifs_t3_cca_mask; 392 u32 ifs_total_addr; 393 u32 ifs_cnt_done_mask; 394 u32 ifs_total_mask; 395 }; 396 397 struct rtw89_physts_regs { 398 u32 setting_addr; 399 u32 dis_trigger_fail_mask; 400 u32 dis_trigger_brk_mask; 401 }; 402 403 struct rtw89_phy_gen_def { 404 u32 cr_base; 405 const struct rtw89_ccx_regs *ccx; 406 const struct rtw89_physts_regs *physts; 407 }; 408 409 extern const struct rtw89_phy_gen_def rtw89_phy_gen_ax; 410 extern const struct rtw89_phy_gen_def rtw89_phy_gen_be; 411 412 static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev, 413 u32 addr, u8 data) 414 { 415 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 416 417 rtw89_write8(rtwdev, addr + phy->cr_base, data); 418 } 419 420 static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev, 421 u32 addr, u16 data) 422 { 423 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 424 425 rtw89_write16(rtwdev, addr + phy->cr_base, data); 426 } 427 428 static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev, 429 u32 addr, u32 data) 430 { 431 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 432 433 rtw89_write32(rtwdev, addr + phy->cr_base, data); 434 } 435 436 static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev, 437 u32 addr, u32 bits) 438 { 439 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 440 441 rtw89_write32_set(rtwdev, addr + phy->cr_base, bits); 442 } 443 444 static inline void rtw89_phy_write32_clr(struct rtw89_dev *rtwdev, 445 u32 addr, u32 bits) 446 { 447 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 448 449 rtw89_write32_clr(rtwdev, addr + phy->cr_base, bits); 450 } 451 452 static inline void rtw89_phy_write32_mask(struct rtw89_dev *rtwdev, 453 u32 addr, u32 mask, u32 data) 454 { 455 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 456 457 rtw89_write32_mask(rtwdev, addr + phy->cr_base, mask, data); 458 } 459 460 static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr) 461 { 462 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 463 464 return rtw89_read8(rtwdev, addr + phy->cr_base); 465 } 466 467 static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr) 468 { 469 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 470 471 return rtw89_read16(rtwdev, addr + phy->cr_base); 472 } 473 474 static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr) 475 { 476 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 477 478 return rtw89_read32(rtwdev, addr + phy->cr_base); 479 } 480 481 static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev, 482 u32 addr, u32 mask) 483 { 484 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 485 486 return rtw89_read32_mask(rtwdev, addr + phy->cr_base, mask); 487 } 488 489 static inline 490 enum rtw89_gain_offset rtw89_subband_to_gain_offset_band_of_ofdm(enum rtw89_subband subband) 491 { 492 switch (subband) { 493 default: 494 case RTW89_CH_2G: 495 return RTW89_GAIN_OFFSET_2G_OFDM; 496 case RTW89_CH_5G_BAND_1: 497 return RTW89_GAIN_OFFSET_5G_LOW; 498 case RTW89_CH_5G_BAND_3: 499 return RTW89_GAIN_OFFSET_5G_MID; 500 case RTW89_CH_5G_BAND_4: 501 return RTW89_GAIN_OFFSET_5G_HIGH; 502 } 503 } 504 505 static inline 506 enum rtw89_phy_bb_gain_band rtw89_subband_to_bb_gain_band(enum rtw89_subband subband) 507 { 508 switch (subband) { 509 default: 510 case RTW89_CH_2G: 511 return RTW89_BB_GAIN_BAND_2G; 512 case RTW89_CH_5G_BAND_1: 513 return RTW89_BB_GAIN_BAND_5G_L; 514 case RTW89_CH_5G_BAND_3: 515 return RTW89_BB_GAIN_BAND_5G_M; 516 case RTW89_CH_5G_BAND_4: 517 return RTW89_BB_GAIN_BAND_5G_H; 518 case RTW89_CH_6G_BAND_IDX0: 519 case RTW89_CH_6G_BAND_IDX1: 520 return RTW89_BB_GAIN_BAND_6G_L; 521 case RTW89_CH_6G_BAND_IDX2: 522 case RTW89_CH_6G_BAND_IDX3: 523 return RTW89_BB_GAIN_BAND_6G_M; 524 case RTW89_CH_6G_BAND_IDX4: 525 case RTW89_CH_6G_BAND_IDX5: 526 return RTW89_BB_GAIN_BAND_6G_H; 527 case RTW89_CH_6G_BAND_IDX6: 528 case RTW89_CH_6G_BAND_IDX7: 529 return RTW89_BB_GAIN_BAND_6G_UH; 530 } 531 } 532 533 enum rtw89_rfk_flag { 534 RTW89_RFK_F_WRF = 0, 535 RTW89_RFK_F_WM = 1, 536 RTW89_RFK_F_WS = 2, 537 RTW89_RFK_F_WC = 3, 538 RTW89_RFK_F_DELAY = 4, 539 RTW89_RFK_F_NUM, 540 }; 541 542 struct rtw89_rfk_tbl { 543 const struct rtw89_reg5_def *defs; 544 u32 size; 545 }; 546 547 #define RTW89_DECLARE_RFK_TBL(_name) \ 548 const struct rtw89_rfk_tbl _name ## _tbl = { \ 549 .defs = _name, \ 550 .size = ARRAY_SIZE(_name), \ 551 } 552 553 #define RTW89_DECL_RFK_WRF(_path, _addr, _mask, _data) \ 554 {.flag = RTW89_RFK_F_WRF, \ 555 .path = _path, \ 556 .addr = _addr, \ 557 .mask = _mask, \ 558 .data = _data,} 559 560 #define RTW89_DECL_RFK_WM(_addr, _mask, _data) \ 561 {.flag = RTW89_RFK_F_WM, \ 562 .addr = _addr, \ 563 .mask = _mask, \ 564 .data = _data,} 565 566 #define RTW89_DECL_RFK_WS(_addr, _mask) \ 567 {.flag = RTW89_RFK_F_WS, \ 568 .addr = _addr, \ 569 .mask = _mask,} 570 571 #define RTW89_DECL_RFK_WC(_addr, _mask) \ 572 {.flag = RTW89_RFK_F_WC, \ 573 .addr = _addr, \ 574 .mask = _mask,} 575 576 #define RTW89_DECL_RFK_DELAY(_data) \ 577 {.flag = RTW89_RFK_F_DELAY, \ 578 .data = _data,} 579 580 void 581 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl); 582 583 #define rtw89_rfk_parser_by_cond(dev, cond, tbl_t, tbl_f) \ 584 do { \ 585 typeof(dev) __dev = (dev); \ 586 if (cond) \ 587 rtw89_rfk_parser(__dev, (tbl_t)); \ 588 else \ 589 rtw89_rfk_parser(__dev, (tbl_f)); \ 590 } while (0) 591 592 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 593 const struct rtw89_phy_reg3_tbl *tbl); 594 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 595 const struct rtw89_chan *chan, 596 enum rtw89_bandwidth dbw); 597 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 598 u32 addr, u32 mask); 599 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 600 u32 addr, u32 mask); 601 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 602 u32 addr, u32 mask, u32 data); 603 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 604 u32 addr, u32 mask, u32 data); 605 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev); 606 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio); 607 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 608 const struct rtw89_reg2_def *reg, 609 enum rtw89_rf_path rf_path, 610 void *extra_data); 611 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev); 612 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 613 u32 data, enum rtw89_phy_idx phy_idx); 614 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 615 enum rtw89_phy_idx phy_idx); 616 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 617 const struct rtw89_txpwr_table *tbl); 618 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, 619 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch); 620 void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev, 621 const struct rtw89_chan *chan, 622 enum rtw89_phy_idx phy_idx); 623 void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev, 624 const struct rtw89_chan *chan, 625 enum rtw89_phy_idx phy_idx); 626 void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev, 627 const struct rtw89_chan *chan, 628 enum rtw89_phy_idx phy_idx); 629 void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, 630 const struct rtw89_chan *chan, 631 enum rtw89_phy_idx phy_idx); 632 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta); 633 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev); 634 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 635 u32 changed); 636 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 637 struct ieee80211_vif *vif, 638 const struct cfg80211_bitrate_mask *mask); 639 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 640 u32 len, u8 class, u8 func); 641 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev); 642 void rtw89_phy_cfo_track_work(struct work_struct *work); 643 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 644 struct rtw89_rx_phy_ppdu *phy_ppdu); 645 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev); 646 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev); 647 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 648 u32 val); 649 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev); 650 void rtw89_phy_dig(struct rtw89_dev *rtwdev); 651 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev); 652 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev, 653 struct rtw89_rx_phy_ppdu *phy_ppdu); 654 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev); 655 void rtw89_phy_antdiv_work(struct work_struct *work); 656 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 657 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 658 enum rtw89_mac_idx mac_idx, 659 enum rtw89_tssi_bandedge_cfg bandedge_cfg); 660 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 661 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev); 662 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band); 663 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx, 664 u8 *ch, enum nl80211_band *band); 665 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, bool scan); 666 667 #endif 668