1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_PHY_H__ 6 #define __RTW89_PHY_H__ 7 8 #include "core.h" 9 10 #define RTW89_PHY_ADDR_OFFSET 0x10000 11 #define RTW89_RF_ADDR_ADSEL_MASK BIT(16) 12 13 #define get_phy_headline(addr) FIELD_GET(GENMASK(31, 28), addr) 14 #define PHY_HEADLINE_VALID 0xf 15 #define get_phy_target(addr) FIELD_GET(GENMASK(27, 0), addr) 16 #define get_phy_compare(rfe, cv) (FIELD_PREP(GENMASK(23, 16), rfe) | \ 17 FIELD_PREP(GENMASK(7, 0), cv)) 18 19 #define get_phy_cond(addr) FIELD_GET(GENMASK(31, 28), addr) 20 #define get_phy_cond_rfe(addr) FIELD_GET(GENMASK(23, 16), addr) 21 #define get_phy_cond_pkg(addr) FIELD_GET(GENMASK(15, 8), addr) 22 #define get_phy_cond_cv(addr) FIELD_GET(GENMASK(7, 0), addr) 23 #define phy_div(a, b) ({typeof(b) _b = (b); (_b) ? ((a) / (_b)) : 0; }) 24 #define PHY_COND_BRANCH_IF 0x8 25 #define PHY_COND_BRANCH_ELIF 0x9 26 #define PHY_COND_BRANCH_ELSE 0xa 27 #define PHY_COND_BRANCH_END 0xb 28 #define PHY_COND_CHECK 0x4 29 #define PHY_COND_DONT_CARE 0xff 30 31 #define RA_MASK_CCK_RATES GENMASK_ULL(3, 0) 32 #define RA_MASK_OFDM_RATES GENMASK_ULL(11, 4) 33 #define RA_MASK_SUBCCK_RATES 0x5ULL 34 #define RA_MASK_SUBOFDM_RATES 0x10ULL 35 #define RA_MASK_HT_1SS_RATES GENMASK_ULL(19, 12) 36 #define RA_MASK_HT_2SS_RATES GENMASK_ULL(31, 24) 37 #define RA_MASK_HT_3SS_RATES GENMASK_ULL(43, 36) 38 #define RA_MASK_HT_4SS_RATES GENMASK_ULL(55, 48) 39 #define RA_MASK_HT_RATES GENMASK_ULL(55, 12) 40 #define RA_MASK_VHT_1SS_RATES GENMASK_ULL(21, 12) 41 #define RA_MASK_VHT_2SS_RATES GENMASK_ULL(33, 24) 42 #define RA_MASK_VHT_3SS_RATES GENMASK_ULL(45, 36) 43 #define RA_MASK_VHT_4SS_RATES GENMASK_ULL(57, 48) 44 #define RA_MASK_VHT_RATES GENMASK_ULL(57, 12) 45 #define RA_MASK_HE_1SS_RATES GENMASK_ULL(23, 12) 46 #define RA_MASK_HE_2SS_RATES GENMASK_ULL(35, 24) 47 #define RA_MASK_HE_3SS_RATES GENMASK_ULL(47, 36) 48 #define RA_MASK_HE_4SS_RATES GENMASK_ULL(59, 48) 49 #define RA_MASK_HE_RATES GENMASK_ULL(59, 12) 50 51 #define CFO_TRK_ENABLE_TH (2 << 2) 52 #define CFO_TRK_STOP_TH_4 (30 << 2) 53 #define CFO_TRK_STOP_TH_3 (20 << 2) 54 #define CFO_TRK_STOP_TH_2 (10 << 2) 55 #define CFO_TRK_STOP_TH_1 (00 << 2) 56 #define CFO_TRK_STOP_TH (2 << 2) 57 #define CFO_SW_COMP_FINE_TUNE (2 << 2) 58 #define CFO_PERIOD_CNT 15 59 #define CFO_BOUND 64 60 #define CFO_TP_UPPER 100 61 #define CFO_TP_LOWER 50 62 #define CFO_COMP_PERIOD 250 63 #define CFO_COMP_WEIGHT 8 64 #define MAX_CFO_TOLERANCE 30 65 #define CFO_TF_CNT_TH 300 66 67 #define CCX_MAX_PERIOD 2097 68 #define CCX_MAX_PERIOD_UNIT 32 69 #define MS_TO_4US_RATIO 250 70 #define ENV_MNTR_FAIL_DWORD 0xffffffff 71 #define ENV_MNTR_IFSCLM_HIS_MAX 127 72 #define PERMIL 1000 73 #define PERCENT 100 74 #define IFS_CLM_TH0_UPPER 64 75 #define IFS_CLM_TH_MUL 4 76 #define IFS_CLM_TH_START_IDX 0 77 78 #define TIA0_GAIN_A 12 79 #define TIA0_GAIN_G 16 80 #define LNA0_GAIN (-24) 81 #define U4_MAX_BIT 3 82 #define U8_MAX_BIT 7 83 #define DIG_GAIN_SHIFT 2 84 #define DIG_GAIN 8 85 86 #define LNA_IDX_MAX 6 87 #define LNA_IDX_MIN 0 88 #define TIA_IDX_MAX 1 89 #define TIA_IDX_MIN 0 90 #define RXB_IDX_MAX 31 91 #define RXB_IDX_MIN 0 92 93 #define IGI_RSSI_MAX 110 94 #define PD_TH_MAX_RSSI 70 95 #define PD_TH_MIN_RSSI 8 96 #define CCKPD_TH_MIN_RSSI (-18) 97 #define PD_TH_BW160_CMP_VAL 9 98 #define PD_TH_BW80_CMP_VAL 6 99 #define PD_TH_BW40_CMP_VAL 3 100 #define PD_TH_BW20_CMP_VAL 0 101 #define PD_TH_CMP_VAL 3 102 #define PD_TH_SB_FLTR_CMP_VAL 7 103 104 #define PHYSTS_MGNT BIT(RTW89_RX_TYPE_MGNT) 105 #define PHYSTS_CTRL BIT(RTW89_RX_TYPE_CTRL) 106 #define PHYSTS_DATA BIT(RTW89_RX_TYPE_DATA) 107 #define PHYSTS_RSVD BIT(RTW89_RX_TYPE_RSVD) 108 #define PPDU_FILTER_BITMAP (PHYSTS_MGNT | PHYSTS_DATA) 109 110 enum rtw89_phy_c2h_ra_func { 111 RTW89_PHY_C2H_FUNC_STS_RPT, 112 RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT, 113 RTW89_PHY_C2H_FUNC_TXSTS, 114 RTW89_PHY_C2H_FUNC_RA_MAX, 115 }; 116 117 enum rtw89_phy_c2h_dm_func { 118 RTW89_PHY_C2H_DM_FUNC_FW_TEST, 119 RTW89_PHY_C2H_DM_FUNC_FW_TRIG_TX_RPT, 120 RTW89_PHY_C2H_DM_FUNC_SIGB, 121 RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY, 122 RTW89_PHY_C2H_DM_FUNC_MCC_DIG, 123 RTW89_PHY_C2H_DM_FUNC_NUM, 124 }; 125 126 enum rtw89_phy_c2h_class { 127 RTW89_PHY_C2H_CLASS_RUA, 128 RTW89_PHY_C2H_CLASS_RA, 129 RTW89_PHY_C2H_CLASS_DM, 130 RTW89_PHY_C2H_CLASS_BTC_MIN = 0x10, 131 RTW89_PHY_C2H_CLASS_BTC_MAX = 0x17, 132 RTW89_PHY_C2H_CLASS_MAX, 133 }; 134 135 enum rtw89_env_monitor_result_level { 136 RTW89_PHY_ENV_MON_CCX_FAIL = 0, 137 RTW89_PHY_ENV_MON_NHM = BIT(0), 138 RTW89_PHY_ENV_MON_CLM = BIT(1), 139 RTW89_PHY_ENV_MON_FAHM = BIT(2), 140 RTW89_PHY_ENV_MON_IFS_CLM = BIT(3), 141 RTW89_PHY_ENV_MON_EDCCA_CLM = BIT(4), 142 }; 143 144 #define CCX_US_BASE_RATIO 4 145 enum rtw89_ccx_unit { 146 RTW89_CCX_4_US = 0, 147 RTW89_CCX_8_US = 1, 148 RTW89_CCX_16_US = 2, 149 RTW89_CCX_32_US = 3 150 }; 151 152 enum rtw89_phy_status_ie_type { 153 RTW89_PHYSTS_IE00_CMN_CCK = 0, 154 RTW89_PHYSTS_IE01_CMN_OFDM = 1, 155 RTW89_PHYSTS_IE02_CMN_EXT_AX = 2, 156 RTW89_PHYSTS_IE03_CMN_EXT_SEG_1 = 3, 157 RTW89_PHYSTS_IE04_CMN_EXT_PATH_A = 4, 158 RTW89_PHYSTS_IE05_CMN_EXT_PATH_B = 5, 159 RTW89_PHYSTS_IE06_CMN_EXT_PATH_C = 6, 160 RTW89_PHYSTS_IE07_CMN_EXT_PATH_D = 7, 161 RTW89_PHYSTS_IE08_FTR_CH = 8, 162 RTW89_PHYSTS_IE09_FTR_0 = 9, 163 RTW89_PHYSTS_IE10_FTR_PLCP_EXT = 10, 164 RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM = 11, 165 RTW89_PHYSTS_IE12_MU_EIGEN_INFO = 12, 166 RTW89_PHYSTS_IE13_DL_MU_DEF = 13, 167 RTW89_PHYSTS_IE14_TB_UL_CQI = 14, 168 RTW89_PHYSTS_IE15_TB_UL_DEF = 15, 169 RTW89_PHYSTS_IE16_RSVD16 = 16, 170 RTW89_PHYSTS_IE17_TB_UL_CTRL = 17, 171 RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN = 18, 172 RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN = 19, 173 RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0 = 20, 174 RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1 = 21, 175 RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC = 22, 176 RTW89_PHYSTS_IE23_RSVD23 = 23, 177 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A = 24, 178 RTW89_PHYSTS_IE25_OFDM_TD_PATH_B = 25, 179 RTW89_PHYSTS_IE26_OFDM_TD_PATH_C = 26, 180 RTW89_PHYSTS_IE27_OFDM_TD_PATH_D = 27, 181 RTW89_PHYSTS_IE28_DBG_CCK_PATH_A = 28, 182 RTW89_PHYSTS_IE29_DBG_CCK_PATH_B = 29, 183 RTW89_PHYSTS_IE30_DBG_CCK_PATH_C = 30, 184 RTW89_PHYSTS_IE31_DBG_CCK_PATH_D = 31, 185 186 /* keep last */ 187 RTW89_PHYSTS_IE_NUM, 188 RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1 189 }; 190 191 enum rtw89_phy_status_bitmap { 192 RTW89_TD_SEARCH_FAIL = 0, 193 RTW89_BRK_BY_TX_PKT = 1, 194 RTW89_CCA_SPOOF = 2, 195 RTW89_OFDM_BRK = 3, 196 RTW89_CCK_BRK = 4, 197 RTW89_DL_MU_SPOOFING = 5, 198 RTW89_HE_MU = 6, 199 RTW89_VHT_MU = 7, 200 RTW89_UL_TB_SPOOFING = 8, 201 RTW89_RSVD_9 = 9, 202 RTW89_TRIG_BASE_PPDU = 10, 203 RTW89_CCK_PKT = 11, 204 RTW89_LEGACY_OFDM_PKT = 12, 205 RTW89_HT_PKT = 13, 206 RTW89_VHT_PKT = 14, 207 RTW89_HE_PKT = 15, 208 209 RTW89_PHYSTS_BITMAP_NUM 210 }; 211 212 enum rtw89_dig_gain_type { 213 RTW89_DIG_GAIN_LNA_G = 0, 214 RTW89_DIG_GAIN_TIA_G = 1, 215 RTW89_DIG_GAIN_LNA_A = 2, 216 RTW89_DIG_GAIN_TIA_A = 3, 217 RTW89_DIG_GAIN_MAX = 4 218 }; 219 220 enum rtw89_dig_gain_lna_idx { 221 RTW89_DIG_GAIN_LNA_IDX1 = 1, 222 RTW89_DIG_GAIN_LNA_IDX2 = 2, 223 RTW89_DIG_GAIN_LNA_IDX3 = 3, 224 RTW89_DIG_GAIN_LNA_IDX4 = 4, 225 RTW89_DIG_GAIN_LNA_IDX5 = 5, 226 RTW89_DIG_GAIN_LNA_IDX6 = 6 227 }; 228 229 enum rtw89_dig_gain_tia_idx { 230 RTW89_DIG_GAIN_TIA_IDX0 = 0, 231 RTW89_DIG_GAIN_TIA_IDX1 = 1 232 }; 233 234 enum rtw89_tssi_bandedge_cfg { 235 RTW89_TSSI_BANDEDGE_FLAT, 236 RTW89_TSSI_BANDEDGE_LOW, 237 RTW89_TSSI_BANDEDGE_MID, 238 RTW89_TSSI_BANDEDGE_HIGH, 239 240 RTW89_TSSI_CFG_NUM, 241 }; 242 243 enum rtw89_tssi_sbw_idx { 244 RTW89_TSSI_SBW20, 245 RTW89_TSSI_SBW40_0, 246 RTW89_TSSI_SBW40_1, 247 RTW89_TSSI_SBW80_0, 248 RTW89_TSSI_SBW80_1, 249 RTW89_TSSI_SBW80_2, 250 RTW89_TSSI_SBW80_3, 251 RTW89_TSSI_SBW160_0, 252 RTW89_TSSI_SBW160_1, 253 RTW89_TSSI_SBW160_2, 254 RTW89_TSSI_SBW160_3, 255 RTW89_TSSI_SBW160_4, 256 RTW89_TSSI_SBW160_5, 257 RTW89_TSSI_SBW160_6, 258 RTW89_TSSI_SBW160_7, 259 260 RTW89_TSSI_SBW_NUM, 261 }; 262 263 struct rtw89_txpwr_byrate_cfg { 264 enum rtw89_band band; 265 enum rtw89_nss nss; 266 enum rtw89_rate_section rs; 267 u8 shf; 268 u8 len; 269 u32 data; 270 }; 271 272 #define DELTA_SWINGIDX_SIZE 30 273 274 struct rtw89_txpwr_track_cfg { 275 const s8 (*delta_swingidx_6gb_n)[DELTA_SWINGIDX_SIZE]; 276 const s8 (*delta_swingidx_6gb_p)[DELTA_SWINGIDX_SIZE]; 277 const s8 (*delta_swingidx_6ga_n)[DELTA_SWINGIDX_SIZE]; 278 const s8 (*delta_swingidx_6ga_p)[DELTA_SWINGIDX_SIZE]; 279 const s8 (*delta_swingidx_5gb_n)[DELTA_SWINGIDX_SIZE]; 280 const s8 (*delta_swingidx_5gb_p)[DELTA_SWINGIDX_SIZE]; 281 const s8 (*delta_swingidx_5ga_n)[DELTA_SWINGIDX_SIZE]; 282 const s8 (*delta_swingidx_5ga_p)[DELTA_SWINGIDX_SIZE]; 283 const s8 *delta_swingidx_2gb_n; 284 const s8 *delta_swingidx_2gb_p; 285 const s8 *delta_swingidx_2ga_n; 286 const s8 *delta_swingidx_2ga_p; 287 const s8 *delta_swingidx_2g_cck_b_n; 288 const s8 *delta_swingidx_2g_cck_b_p; 289 const s8 *delta_swingidx_2g_cck_a_n; 290 const s8 *delta_swingidx_2g_cck_a_p; 291 }; 292 293 struct rtw89_phy_dig_gain_cfg { 294 const struct rtw89_reg_def *table; 295 u8 size; 296 }; 297 298 struct rtw89_phy_dig_gain_table { 299 const struct rtw89_phy_dig_gain_cfg *cfg_lna_g; 300 const struct rtw89_phy_dig_gain_cfg *cfg_tia_g; 301 const struct rtw89_phy_dig_gain_cfg *cfg_lna_a; 302 const struct rtw89_phy_dig_gain_cfg *cfg_tia_a; 303 }; 304 305 struct rtw89_phy_tssi_dbw_table { 306 u32 data[RTW89_TSSI_CFG_NUM][RTW89_TSSI_SBW_NUM]; 307 }; 308 309 struct rtw89_phy_reg3_tbl { 310 const struct rtw89_reg3_def *reg3; 311 int size; 312 }; 313 314 #define DECLARE_PHY_REG3_TBL(_name) \ 315 const struct rtw89_phy_reg3_tbl _name ## _tbl = { \ 316 .reg3 = _name, \ 317 .size = ARRAY_SIZE(_name), \ 318 } 319 320 struct rtw89_nbi_reg_def { 321 struct rtw89_reg_def notch1_idx; 322 struct rtw89_reg_def notch1_frac_idx; 323 struct rtw89_reg_def notch1_en; 324 struct rtw89_reg_def notch2_idx; 325 struct rtw89_reg_def notch2_frac_idx; 326 struct rtw89_reg_def notch2_en; 327 }; 328 329 static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev, 330 u32 addr, u8 data) 331 { 332 rtw89_write8(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data); 333 } 334 335 static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev, 336 u32 addr, u16 data) 337 { 338 rtw89_write16(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data); 339 } 340 341 static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev, 342 u32 addr, u32 data) 343 { 344 rtw89_write32(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data); 345 } 346 347 static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev, 348 u32 addr, u32 bits) 349 { 350 rtw89_write32_set(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, bits); 351 } 352 353 static inline void rtw89_phy_write32_clr(struct rtw89_dev *rtwdev, 354 u32 addr, u32 bits) 355 { 356 rtw89_write32_clr(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, bits); 357 } 358 359 static inline void rtw89_phy_write32_mask(struct rtw89_dev *rtwdev, 360 u32 addr, u32 mask, u32 data) 361 { 362 rtw89_write32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask, data); 363 } 364 365 static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr) 366 { 367 return rtw89_read8(rtwdev, addr | RTW89_PHY_ADDR_OFFSET); 368 } 369 370 static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr) 371 { 372 return rtw89_read16(rtwdev, addr | RTW89_PHY_ADDR_OFFSET); 373 } 374 375 static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr) 376 { 377 return rtw89_read32(rtwdev, addr | RTW89_PHY_ADDR_OFFSET); 378 } 379 380 static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev, 381 u32 addr, u32 mask) 382 { 383 return rtw89_read32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask); 384 } 385 386 static inline 387 enum rtw89_gain_offset rtw89_subband_to_gain_offset_band_of_ofdm(enum rtw89_subband subband) 388 { 389 switch (subband) { 390 default: 391 case RTW89_CH_2G: 392 return RTW89_GAIN_OFFSET_2G_OFDM; 393 case RTW89_CH_5G_BAND_1: 394 return RTW89_GAIN_OFFSET_5G_LOW; 395 case RTW89_CH_5G_BAND_3: 396 return RTW89_GAIN_OFFSET_5G_MID; 397 case RTW89_CH_5G_BAND_4: 398 return RTW89_GAIN_OFFSET_5G_HIGH; 399 } 400 } 401 402 static inline 403 enum rtw89_phy_bb_gain_band rtw89_subband_to_bb_gain_band(enum rtw89_subband subband) 404 { 405 switch (subband) { 406 default: 407 case RTW89_CH_2G: 408 return RTW89_BB_GAIN_BAND_2G; 409 case RTW89_CH_5G_BAND_1: 410 return RTW89_BB_GAIN_BAND_5G_L; 411 case RTW89_CH_5G_BAND_3: 412 return RTW89_BB_GAIN_BAND_5G_M; 413 case RTW89_CH_5G_BAND_4: 414 return RTW89_BB_GAIN_BAND_5G_H; 415 case RTW89_CH_6G_BAND_IDX0: 416 case RTW89_CH_6G_BAND_IDX1: 417 return RTW89_BB_GAIN_BAND_6G_L; 418 case RTW89_CH_6G_BAND_IDX2: 419 case RTW89_CH_6G_BAND_IDX3: 420 return RTW89_BB_GAIN_BAND_6G_M; 421 case RTW89_CH_6G_BAND_IDX4: 422 case RTW89_CH_6G_BAND_IDX5: 423 return RTW89_BB_GAIN_BAND_6G_H; 424 case RTW89_CH_6G_BAND_IDX6: 425 case RTW89_CH_6G_BAND_IDX7: 426 return RTW89_BB_GAIN_BAND_6G_UH; 427 } 428 } 429 430 enum rtw89_rfk_flag { 431 RTW89_RFK_F_WRF = 0, 432 RTW89_RFK_F_WM = 1, 433 RTW89_RFK_F_WS = 2, 434 RTW89_RFK_F_WC = 3, 435 RTW89_RFK_F_DELAY = 4, 436 RTW89_RFK_F_NUM, 437 }; 438 439 struct rtw89_rfk_tbl { 440 const struct rtw89_reg5_def *defs; 441 u32 size; 442 }; 443 444 #define RTW89_DECLARE_RFK_TBL(_name) \ 445 const struct rtw89_rfk_tbl _name ## _tbl = { \ 446 .defs = _name, \ 447 .size = ARRAY_SIZE(_name), \ 448 } 449 450 #define RTW89_DECL_RFK_WRF(_path, _addr, _mask, _data) \ 451 {.flag = RTW89_RFK_F_WRF, \ 452 .path = _path, \ 453 .addr = _addr, \ 454 .mask = _mask, \ 455 .data = _data,} 456 457 #define RTW89_DECL_RFK_WM(_addr, _mask, _data) \ 458 {.flag = RTW89_RFK_F_WM, \ 459 .addr = _addr, \ 460 .mask = _mask, \ 461 .data = _data,} 462 463 #define RTW89_DECL_RFK_WS(_addr, _mask) \ 464 {.flag = RTW89_RFK_F_WS, \ 465 .addr = _addr, \ 466 .mask = _mask,} 467 468 #define RTW89_DECL_RFK_WC(_addr, _mask) \ 469 {.flag = RTW89_RFK_F_WC, \ 470 .addr = _addr, \ 471 .mask = _mask,} 472 473 #define RTW89_DECL_RFK_DELAY(_data) \ 474 {.flag = RTW89_RFK_F_DELAY, \ 475 .data = _data,} 476 477 void 478 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl); 479 480 #define rtw89_rfk_parser_by_cond(dev, cond, tbl_t, tbl_f) \ 481 do { \ 482 typeof(dev) __dev = (dev); \ 483 if (cond) \ 484 rtw89_rfk_parser(__dev, (tbl_t)); \ 485 else \ 486 rtw89_rfk_parser(__dev, (tbl_f)); \ 487 } while (0) 488 489 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 490 const struct rtw89_phy_reg3_tbl *tbl); 491 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 492 const struct rtw89_chan *chan, 493 enum rtw89_bandwidth dbw); 494 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 495 u32 addr, u32 mask); 496 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 497 u32 addr, u32 mask); 498 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 499 u32 addr, u32 mask, u32 data); 500 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 501 u32 addr, u32 mask, u32 data); 502 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev); 503 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev); 504 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 505 const struct rtw89_reg2_def *reg, 506 enum rtw89_rf_path rf_path, 507 void *extra_data); 508 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev); 509 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 510 u32 data, enum rtw89_phy_idx phy_idx); 511 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 512 enum rtw89_phy_idx phy_idx); 513 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 514 const struct rtw89_txpwr_table *tbl); 515 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, 516 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch); 517 void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev, 518 const struct rtw89_chan *chan, 519 enum rtw89_phy_idx phy_idx); 520 void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev, 521 const struct rtw89_chan *chan, 522 enum rtw89_phy_idx phy_idx); 523 void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev, 524 const struct rtw89_chan *chan, 525 enum rtw89_phy_idx phy_idx); 526 void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, 527 const struct rtw89_chan *chan, 528 enum rtw89_phy_idx phy_idx); 529 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta); 530 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev); 531 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 532 u32 changed); 533 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 534 struct ieee80211_vif *vif, 535 const struct cfg80211_bitrate_mask *mask); 536 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 537 u32 len, u8 class, u8 func); 538 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev); 539 void rtw89_phy_cfo_track_work(struct work_struct *work); 540 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 541 struct rtw89_rx_phy_ppdu *phy_ppdu); 542 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev); 543 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev); 544 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 545 u32 val); 546 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev); 547 void rtw89_phy_dig(struct rtw89_dev *rtwdev); 548 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev); 549 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 550 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 551 enum rtw89_mac_idx mac_idx, 552 enum rtw89_tssi_bandedge_cfg bandedge_cfg); 553 554 #endif 555