1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * RTL8XXXU mac80211 USB driver 4 * 5 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> 6 * 7 * Portions, notably calibration code: 8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 9 * 10 * This driver was written as a replacement for the vendor provided 11 * rtl8723au driver. As the Realtek 8xxx chips are very similar in 12 * their programming interface, I have started adding support for 13 * additional 8xxx chips like the 8192cu, 8188cus, etc. 14 */ 15 16 #include <linux/init.h> 17 #include <linux/kernel.h> 18 #include <linux/sched.h> 19 #include <linux/errno.h> 20 #include <linux/slab.h> 21 #include <linux/module.h> 22 #include <linux/spinlock.h> 23 #include <linux/list.h> 24 #include <linux/usb.h> 25 #include <linux/netdevice.h> 26 #include <linux/etherdevice.h> 27 #include <linux/ethtool.h> 28 #include <linux/wireless.h> 29 #include <linux/firmware.h> 30 #include <linux/moduleparam.h> 31 #include <net/mac80211.h> 32 #include "rtl8xxxu.h" 33 #include "rtl8xxxu_regs.h" 34 35 #define DRIVER_NAME "rtl8xxxu" 36 37 int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE; 38 static bool rtl8xxxu_ht40_2g; 39 static bool rtl8xxxu_dma_aggregation; 40 static int rtl8xxxu_dma_agg_timeout = -1; 41 static int rtl8xxxu_dma_agg_pages = -1; 42 43 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@gmail.com>"); 44 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver"); 45 MODULE_LICENSE("GPL"); 46 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin"); 47 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin"); 48 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin"); 49 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin"); 50 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin"); 51 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin"); 52 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin"); 53 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin"); 54 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin"); 55 56 module_param_named(debug, rtl8xxxu_debug, int, 0600); 57 MODULE_PARM_DESC(debug, "Set debug mask"); 58 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600); 59 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band"); 60 module_param_named(dma_aggregation, rtl8xxxu_dma_aggregation, bool, 0600); 61 MODULE_PARM_DESC(dma_aggregation, "Enable DMA packet aggregation"); 62 module_param_named(dma_agg_timeout, rtl8xxxu_dma_agg_timeout, int, 0600); 63 MODULE_PARM_DESC(dma_agg_timeout, "Set DMA aggregation timeout (range 1-127)"); 64 module_param_named(dma_agg_pages, rtl8xxxu_dma_agg_pages, int, 0600); 65 MODULE_PARM_DESC(dma_agg_pages, "Set DMA aggregation pages (range 1-127, 0 to disable)"); 66 67 #define USB_VENDOR_ID_REALTEK 0x0bda 68 #define RTL8XXXU_RX_URBS 32 69 #define RTL8XXXU_RX_URB_PENDING_WATER 8 70 #define RTL8XXXU_TX_URBS 64 71 #define RTL8XXXU_TX_URB_LOW_WATER 25 72 #define RTL8XXXU_TX_URB_HIGH_WATER 32 73 74 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv, 75 struct rtl8xxxu_rx_urb *rx_urb); 76 77 static struct ieee80211_rate rtl8xxxu_rates[] = { 78 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 }, 79 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 }, 80 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 }, 81 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 }, 82 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 }, 83 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 }, 84 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 }, 85 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 }, 86 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 }, 87 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 }, 88 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 }, 89 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 }, 90 }; 91 92 static struct ieee80211_channel rtl8xxxu_channels_2g[] = { 93 { .band = NL80211_BAND_2GHZ, .center_freq = 2412, 94 .hw_value = 1, .max_power = 30 }, 95 { .band = NL80211_BAND_2GHZ, .center_freq = 2417, 96 .hw_value = 2, .max_power = 30 }, 97 { .band = NL80211_BAND_2GHZ, .center_freq = 2422, 98 .hw_value = 3, .max_power = 30 }, 99 { .band = NL80211_BAND_2GHZ, .center_freq = 2427, 100 .hw_value = 4, .max_power = 30 }, 101 { .band = NL80211_BAND_2GHZ, .center_freq = 2432, 102 .hw_value = 5, .max_power = 30 }, 103 { .band = NL80211_BAND_2GHZ, .center_freq = 2437, 104 .hw_value = 6, .max_power = 30 }, 105 { .band = NL80211_BAND_2GHZ, .center_freq = 2442, 106 .hw_value = 7, .max_power = 30 }, 107 { .band = NL80211_BAND_2GHZ, .center_freq = 2447, 108 .hw_value = 8, .max_power = 30 }, 109 { .band = NL80211_BAND_2GHZ, .center_freq = 2452, 110 .hw_value = 9, .max_power = 30 }, 111 { .band = NL80211_BAND_2GHZ, .center_freq = 2457, 112 .hw_value = 10, .max_power = 30 }, 113 { .band = NL80211_BAND_2GHZ, .center_freq = 2462, 114 .hw_value = 11, .max_power = 30 }, 115 { .band = NL80211_BAND_2GHZ, .center_freq = 2467, 116 .hw_value = 12, .max_power = 30 }, 117 { .band = NL80211_BAND_2GHZ, .center_freq = 2472, 118 .hw_value = 13, .max_power = 30 }, 119 { .band = NL80211_BAND_2GHZ, .center_freq = 2484, 120 .hw_value = 14, .max_power = 30 } 121 }; 122 123 static struct ieee80211_supported_band rtl8xxxu_supported_band = { 124 .channels = rtl8xxxu_channels_2g, 125 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g), 126 .bitrates = rtl8xxxu_rates, 127 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates), 128 }; 129 130 struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[] = { 131 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00}, 132 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, 133 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00}, 134 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05}, 135 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01}, 136 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f}, 137 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72}, 138 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08}, 139 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, 140 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, 141 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, 142 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, 143 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, 144 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, 145 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16}, 146 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00}, 147 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02}, 148 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, 149 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, 150 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, 151 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, 152 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff}, 153 }; 154 155 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = { 156 {0x800, 0x80040000}, {0x804, 0x00000003}, 157 {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, 158 {0x810, 0x10001331}, {0x814, 0x020c3d10}, 159 {0x818, 0x02200385}, {0x81c, 0x00000000}, 160 {0x820, 0x01000100}, {0x824, 0x00390004}, 161 {0x828, 0x00000000}, {0x82c, 0x00000000}, 162 {0x830, 0x00000000}, {0x834, 0x00000000}, 163 {0x838, 0x00000000}, {0x83c, 0x00000000}, 164 {0x840, 0x00010000}, {0x844, 0x00000000}, 165 {0x848, 0x00000000}, {0x84c, 0x00000000}, 166 {0x850, 0x00000000}, {0x854, 0x00000000}, 167 {0x858, 0x569a569a}, {0x85c, 0x001b25a4}, 168 {0x860, 0x66f60110}, {0x864, 0x061f0130}, 169 {0x868, 0x00000000}, {0x86c, 0x32323200}, 170 {0x870, 0x07000760}, {0x874, 0x22004000}, 171 {0x878, 0x00000808}, {0x87c, 0x00000000}, 172 {0x880, 0xc0083070}, {0x884, 0x000004d5}, 173 {0x888, 0x00000000}, {0x88c, 0xccc000c0}, 174 {0x890, 0x00000800}, {0x894, 0xfffffffe}, 175 {0x898, 0x40302010}, {0x89c, 0x00706050}, 176 {0x900, 0x00000000}, {0x904, 0x00000023}, 177 {0x908, 0x00000000}, {0x90c, 0x81121111}, 178 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c}, 179 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f}, 180 {0xa10, 0x9500bb78}, {0xa14, 0x11144028}, 181 {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, 182 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, 183 {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, 184 {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, 185 {0xa78, 0x00000900}, 186 {0xc00, 0x48071d40}, {0xc04, 0x03a05611}, 187 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, 188 {0xc10, 0x08800000}, {0xc14, 0x40000100}, 189 {0xc18, 0x08800000}, {0xc1c, 0x40000100}, 190 {0xc20, 0x00000000}, {0xc24, 0x00000000}, 191 {0xc28, 0x00000000}, {0xc2c, 0x00000000}, 192 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af}, 193 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, 194 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, 195 {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, 196 {0xc50, 0x69543420}, {0xc54, 0x43bc0094}, 197 {0xc58, 0x69543420}, {0xc5c, 0x433c0094}, 198 {0xc60, 0x00000000}, {0xc64, 0x7112848b}, 199 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, 200 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db}, 201 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612}, 202 {0xc80, 0x40000100}, {0xc84, 0x20f60000}, 203 {0xc88, 0x40000100}, {0xc8c, 0x20200000}, 204 {0xc90, 0x00121820}, {0xc94, 0x00000000}, 205 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, 206 {0xca0, 0x00000000}, {0xca4, 0x00000080}, 207 {0xca8, 0x00000000}, {0xcac, 0x00000000}, 208 {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, 209 {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, 210 {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, 211 {0xcc8, 0x00000000}, {0xccc, 0x00000000}, 212 {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, 213 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, 214 {0xce0, 0x00222222}, {0xce4, 0x00000000}, 215 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, 216 {0xd00, 0x00080740}, {0xd04, 0x00020401}, 217 {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, 218 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, 219 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975}, 220 {0xd30, 0x00000000}, {0xd34, 0x80608000}, 221 {0xd38, 0x00000000}, {0xd3c, 0x00027293}, 222 {0xd40, 0x00000000}, {0xd44, 0x00000000}, 223 {0xd48, 0x00000000}, {0xd4c, 0x00000000}, 224 {0xd50, 0x6437140a}, {0xd54, 0x00000000}, 225 {0xd58, 0x00000000}, {0xd5c, 0x30032064}, 226 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, 227 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, 228 {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, 229 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a}, 230 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a}, 231 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a}, 232 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a}, 233 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, 234 {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, 235 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, 236 {0xe44, 0x01004800}, {0xe48, 0xfb000000}, 237 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, 238 {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, 239 {0xe5c, 0x28160d05}, {0xe60, 0x00000008}, 240 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0}, 241 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0}, 242 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0}, 243 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0}, 244 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0}, 245 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0}, 246 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0}, 247 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0}, 248 {0xf14, 0x00000003}, {0xf4c, 0x00000000}, 249 {0xf00, 0x00000300}, 250 {0xffff, 0xffffffff}, 251 }; 252 253 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = { 254 {0x024, 0x0011800f}, {0x028, 0x00ffdb83}, 255 {0x800, 0x80040002}, {0x804, 0x00000003}, 256 {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, 257 {0x810, 0x10000330}, {0x814, 0x020c3d10}, 258 {0x818, 0x02200385}, {0x81c, 0x00000000}, 259 {0x820, 0x01000100}, {0x824, 0x00390004}, 260 {0x828, 0x01000100}, {0x82c, 0x00390004}, 261 {0x830, 0x27272727}, {0x834, 0x27272727}, 262 {0x838, 0x27272727}, {0x83c, 0x27272727}, 263 {0x840, 0x00010000}, {0x844, 0x00010000}, 264 {0x848, 0x27272727}, {0x84c, 0x27272727}, 265 {0x850, 0x00000000}, {0x854, 0x00000000}, 266 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4}, 267 {0x860, 0x66e60230}, {0x864, 0x061f0130}, 268 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27}, 269 {0x870, 0x07000700}, {0x874, 0x22184000}, 270 {0x878, 0x08080808}, {0x87c, 0x00000000}, 271 {0x880, 0xc0083070}, {0x884, 0x000004d5}, 272 {0x888, 0x00000000}, {0x88c, 0xcc0000c0}, 273 {0x890, 0x00000800}, {0x894, 0xfffffffe}, 274 {0x898, 0x40302010}, {0x89c, 0x00706050}, 275 {0x900, 0x00000000}, {0x904, 0x00000023}, 276 {0x908, 0x00000000}, {0x90c, 0x81121313}, 277 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c}, 278 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f}, 279 {0xa10, 0x9500bb78}, {0xa14, 0x11144028}, 280 {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, 281 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, 282 {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, 283 {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, 284 {0xc00, 0x48071d40}, {0xc04, 0x03a05633}, 285 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, 286 {0xc10, 0x08800000}, {0xc14, 0x40000100}, 287 {0xc18, 0x08800000}, {0xc1c, 0x40000100}, 288 {0xc20, 0x00000000}, {0xc24, 0x00000000}, 289 {0xc28, 0x00000000}, {0xc2c, 0x00000000}, 290 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf}, 291 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, 292 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, 293 {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, 294 {0xc50, 0x69543420}, {0xc54, 0x43bc0094}, 295 {0xc58, 0x69543420}, {0xc5c, 0x433c0094}, 296 {0xc60, 0x00000000}, {0xc64, 0x5116848b}, 297 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, 298 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b}, 299 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612}, 300 {0xc80, 0x40000100}, {0xc84, 0x20f60000}, 301 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000}, 302 {0xc90, 0x00121820}, {0xc94, 0x00000000}, 303 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, 304 {0xca0, 0x00000000}, {0xca4, 0x00000080}, 305 {0xca8, 0x00000000}, {0xcac, 0x00000000}, 306 {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, 307 {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, 308 {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, 309 {0xcc8, 0x00000000}, {0xccc, 0x00000000}, 310 {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, 311 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, 312 {0xce0, 0x00222222}, {0xce4, 0x00000000}, 313 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, 314 {0xd00, 0x00080740}, {0xd04, 0x00020403}, 315 {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, 316 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, 317 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975}, 318 {0xd30, 0x00000000}, {0xd34, 0x80608000}, 319 {0xd38, 0x00000000}, {0xd3c, 0x00027293}, 320 {0xd40, 0x00000000}, {0xd44, 0x00000000}, 321 {0xd48, 0x00000000}, {0xd4c, 0x00000000}, 322 {0xd50, 0x6437140a}, {0xd54, 0x00000000}, 323 {0xd58, 0x00000000}, {0xd5c, 0x30032064}, 324 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, 325 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, 326 {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, 327 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a}, 328 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a}, 329 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a}, 330 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a}, 331 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, 332 {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, 333 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, 334 {0xe44, 0x01004800}, {0xe48, 0xfb000000}, 335 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, 336 {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, 337 {0xe5c, 0x28160d05}, {0xe60, 0x00000010}, 338 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4}, 339 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4}, 340 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4}, 341 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4}, 342 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4}, 343 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4}, 344 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4}, 345 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4}, 346 {0xf14, 0x00000003}, {0xf4c, 0x00000000}, 347 {0xf00, 0x00000300}, 348 {0xffff, 0xffffffff}, 349 }; 350 351 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = { 352 {0x024, 0x0011800f}, {0x028, 0x00ffdb83}, 353 {0x040, 0x000c0004}, {0x800, 0x80040000}, 354 {0x804, 0x00000001}, {0x808, 0x0000fc00}, 355 {0x80c, 0x0000000a}, {0x810, 0x10005388}, 356 {0x814, 0x020c3d10}, {0x818, 0x02200385}, 357 {0x81c, 0x00000000}, {0x820, 0x01000100}, 358 {0x824, 0x00390204}, {0x828, 0x00000000}, 359 {0x82c, 0x00000000}, {0x830, 0x00000000}, 360 {0x834, 0x00000000}, {0x838, 0x00000000}, 361 {0x83c, 0x00000000}, {0x840, 0x00010000}, 362 {0x844, 0x00000000}, {0x848, 0x00000000}, 363 {0x84c, 0x00000000}, {0x850, 0x00000000}, 364 {0x854, 0x00000000}, {0x858, 0x569a569a}, 365 {0x85c, 0x001b25a4}, {0x860, 0x66e60230}, 366 {0x864, 0x061f0130}, {0x868, 0x00000000}, 367 {0x86c, 0x20202000}, {0x870, 0x03000300}, 368 {0x874, 0x22004000}, {0x878, 0x00000808}, 369 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070}, 370 {0x884, 0x000004d5}, {0x888, 0x00000000}, 371 {0x88c, 0xccc000c0}, {0x890, 0x00000800}, 372 {0x894, 0xfffffffe}, {0x898, 0x40302010}, 373 {0x89c, 0x00706050}, {0x900, 0x00000000}, 374 {0x904, 0x00000023}, {0x908, 0x00000000}, 375 {0x90c, 0x81121111}, {0xa00, 0x00d047c8}, 376 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300}, 377 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78}, 378 {0xa14, 0x11144028}, {0xa18, 0x00881117}, 379 {0xa1c, 0x89140f00}, {0xa20, 0x15160000}, 380 {0xa24, 0x070b0f12}, {0xa28, 0x00000104}, 381 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00}, 382 {0xa74, 0x00000007}, {0xc00, 0x48071d40}, 383 {0xc04, 0x03a05611}, {0xc08, 0x000000e4}, 384 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000}, 385 {0xc14, 0x40000100}, {0xc18, 0x08800000}, 386 {0xc1c, 0x40000100}, {0xc20, 0x00000000}, 387 {0xc24, 0x00000000}, {0xc28, 0x00000000}, 388 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44}, 389 {0xc34, 0x469652cf}, {0xc38, 0x49795994}, 390 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f}, 391 {0xc44, 0x000100b7}, {0xc48, 0xec020107}, 392 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e}, 393 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f}, 394 {0xc5c, 0x433c0094}, {0xc60, 0x00000000}, 395 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff}, 396 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d}, 397 {0xc74, 0x018610db}, {0xc78, 0x0000001f}, 398 {0xc7c, 0x00b91612}, {0xc80, 0x24000090}, 399 {0xc84, 0x20f60000}, {0xc88, 0x24000090}, 400 {0xc8c, 0x20200000}, {0xc90, 0x00121820}, 401 {0xc94, 0x00000000}, {0xc98, 0x00121820}, 402 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000}, 403 {0xca4, 0x00000080}, {0xca8, 0x00000000}, 404 {0xcac, 0x00000000}, {0xcb0, 0x00000000}, 405 {0xcb4, 0x00000000}, {0xcb8, 0x00000000}, 406 {0xcbc, 0x28000000}, {0xcc0, 0x00000000}, 407 {0xcc4, 0x00000000}, {0xcc8, 0x00000000}, 408 {0xccc, 0x00000000}, {0xcd0, 0x00000000}, 409 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427}, 410 {0xcdc, 0x00766932}, {0xce0, 0x00222222}, 411 {0xce4, 0x00000000}, {0xce8, 0x37644302}, 412 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740}, 413 {0xd04, 0x00020401}, {0xd08, 0x0000907f}, 414 {0xd0c, 0x20010201}, {0xd10, 0xa0633333}, 415 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b}, 416 {0xd2c, 0xcc979975}, {0xd30, 0x00000000}, 417 {0xd34, 0x80608000}, {0xd38, 0x00000000}, 418 {0xd3c, 0x00027293}, {0xd40, 0x00000000}, 419 {0xd44, 0x00000000}, {0xd48, 0x00000000}, 420 {0xd4c, 0x00000000}, {0xd50, 0x6437140a}, 421 {0xd54, 0x00000000}, {0xd58, 0x00000000}, 422 {0xd5c, 0x30032064}, {0xd60, 0x4653de68}, 423 {0xd64, 0x04518a3c}, {0xd68, 0x00002101}, 424 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e}, 425 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24}, 426 {0xe00, 0x24242424}, {0xe04, 0x24242424}, 427 {0xe08, 0x03902024}, {0xe10, 0x24242424}, 428 {0xe14, 0x24242424}, {0xe18, 0x24242424}, 429 {0xe1c, 0x24242424}, {0xe28, 0x00000000}, 430 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f}, 431 {0xe38, 0x02140102}, {0xe3c, 0x681604c2}, 432 {0xe40, 0x01007c00}, {0xe44, 0x01004800}, 433 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1}, 434 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f}, 435 {0xe58, 0x02140102}, {0xe5c, 0x28160d05}, 436 {0xe60, 0x00000008}, {0xe68, 0x001b25a4}, 437 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0}, 438 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0}, 439 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0}, 440 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0}, 441 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0}, 442 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0}, 443 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0}, 444 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448}, 445 {0xf14, 0x00000003}, {0xf4c, 0x00000000}, 446 {0xf00, 0x00000300}, 447 {0xffff, 0xffffffff}, 448 }; 449 450 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = { 451 {0xc78, 0x7b000001}, {0xc78, 0x7b010001}, 452 {0xc78, 0x7b020001}, {0xc78, 0x7b030001}, 453 {0xc78, 0x7b040001}, {0xc78, 0x7b050001}, 454 {0xc78, 0x7a060001}, {0xc78, 0x79070001}, 455 {0xc78, 0x78080001}, {0xc78, 0x77090001}, 456 {0xc78, 0x760a0001}, {0xc78, 0x750b0001}, 457 {0xc78, 0x740c0001}, {0xc78, 0x730d0001}, 458 {0xc78, 0x720e0001}, {0xc78, 0x710f0001}, 459 {0xc78, 0x70100001}, {0xc78, 0x6f110001}, 460 {0xc78, 0x6e120001}, {0xc78, 0x6d130001}, 461 {0xc78, 0x6c140001}, {0xc78, 0x6b150001}, 462 {0xc78, 0x6a160001}, {0xc78, 0x69170001}, 463 {0xc78, 0x68180001}, {0xc78, 0x67190001}, 464 {0xc78, 0x661a0001}, {0xc78, 0x651b0001}, 465 {0xc78, 0x641c0001}, {0xc78, 0x631d0001}, 466 {0xc78, 0x621e0001}, {0xc78, 0x611f0001}, 467 {0xc78, 0x60200001}, {0xc78, 0x49210001}, 468 {0xc78, 0x48220001}, {0xc78, 0x47230001}, 469 {0xc78, 0x46240001}, {0xc78, 0x45250001}, 470 {0xc78, 0x44260001}, {0xc78, 0x43270001}, 471 {0xc78, 0x42280001}, {0xc78, 0x41290001}, 472 {0xc78, 0x402a0001}, {0xc78, 0x262b0001}, 473 {0xc78, 0x252c0001}, {0xc78, 0x242d0001}, 474 {0xc78, 0x232e0001}, {0xc78, 0x222f0001}, 475 {0xc78, 0x21300001}, {0xc78, 0x20310001}, 476 {0xc78, 0x06320001}, {0xc78, 0x05330001}, 477 {0xc78, 0x04340001}, {0xc78, 0x03350001}, 478 {0xc78, 0x02360001}, {0xc78, 0x01370001}, 479 {0xc78, 0x00380001}, {0xc78, 0x00390001}, 480 {0xc78, 0x003a0001}, {0xc78, 0x003b0001}, 481 {0xc78, 0x003c0001}, {0xc78, 0x003d0001}, 482 {0xc78, 0x003e0001}, {0xc78, 0x003f0001}, 483 {0xc78, 0x7b400001}, {0xc78, 0x7b410001}, 484 {0xc78, 0x7b420001}, {0xc78, 0x7b430001}, 485 {0xc78, 0x7b440001}, {0xc78, 0x7b450001}, 486 {0xc78, 0x7a460001}, {0xc78, 0x79470001}, 487 {0xc78, 0x78480001}, {0xc78, 0x77490001}, 488 {0xc78, 0x764a0001}, {0xc78, 0x754b0001}, 489 {0xc78, 0x744c0001}, {0xc78, 0x734d0001}, 490 {0xc78, 0x724e0001}, {0xc78, 0x714f0001}, 491 {0xc78, 0x70500001}, {0xc78, 0x6f510001}, 492 {0xc78, 0x6e520001}, {0xc78, 0x6d530001}, 493 {0xc78, 0x6c540001}, {0xc78, 0x6b550001}, 494 {0xc78, 0x6a560001}, {0xc78, 0x69570001}, 495 {0xc78, 0x68580001}, {0xc78, 0x67590001}, 496 {0xc78, 0x665a0001}, {0xc78, 0x655b0001}, 497 {0xc78, 0x645c0001}, {0xc78, 0x635d0001}, 498 {0xc78, 0x625e0001}, {0xc78, 0x615f0001}, 499 {0xc78, 0x60600001}, {0xc78, 0x49610001}, 500 {0xc78, 0x48620001}, {0xc78, 0x47630001}, 501 {0xc78, 0x46640001}, {0xc78, 0x45650001}, 502 {0xc78, 0x44660001}, {0xc78, 0x43670001}, 503 {0xc78, 0x42680001}, {0xc78, 0x41690001}, 504 {0xc78, 0x406a0001}, {0xc78, 0x266b0001}, 505 {0xc78, 0x256c0001}, {0xc78, 0x246d0001}, 506 {0xc78, 0x236e0001}, {0xc78, 0x226f0001}, 507 {0xc78, 0x21700001}, {0xc78, 0x20710001}, 508 {0xc78, 0x06720001}, {0xc78, 0x05730001}, 509 {0xc78, 0x04740001}, {0xc78, 0x03750001}, 510 {0xc78, 0x02760001}, {0xc78, 0x01770001}, 511 {0xc78, 0x00780001}, {0xc78, 0x00790001}, 512 {0xc78, 0x007a0001}, {0xc78, 0x007b0001}, 513 {0xc78, 0x007c0001}, {0xc78, 0x007d0001}, 514 {0xc78, 0x007e0001}, {0xc78, 0x007f0001}, 515 {0xc78, 0x3800001e}, {0xc78, 0x3801001e}, 516 {0xc78, 0x3802001e}, {0xc78, 0x3803001e}, 517 {0xc78, 0x3804001e}, {0xc78, 0x3805001e}, 518 {0xc78, 0x3806001e}, {0xc78, 0x3807001e}, 519 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e}, 520 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e}, 521 {0xc78, 0x440c001e}, {0xc78, 0x480d001e}, 522 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e}, 523 {0xc78, 0x5210001e}, {0xc78, 0x5611001e}, 524 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e}, 525 {0xc78, 0x6014001e}, {0xc78, 0x6015001e}, 526 {0xc78, 0x6016001e}, {0xc78, 0x6217001e}, 527 {0xc78, 0x6218001e}, {0xc78, 0x6219001e}, 528 {0xc78, 0x621a001e}, {0xc78, 0x621b001e}, 529 {0xc78, 0x621c001e}, {0xc78, 0x621d001e}, 530 {0xc78, 0x621e001e}, {0xc78, 0x621f001e}, 531 {0xffff, 0xffffffff} 532 }; 533 534 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = { 535 {0xc78, 0x7b000001}, {0xc78, 0x7b010001}, 536 {0xc78, 0x7b020001}, {0xc78, 0x7b030001}, 537 {0xc78, 0x7b040001}, {0xc78, 0x7b050001}, 538 {0xc78, 0x7b060001}, {0xc78, 0x7b070001}, 539 {0xc78, 0x7b080001}, {0xc78, 0x7a090001}, 540 {0xc78, 0x790a0001}, {0xc78, 0x780b0001}, 541 {0xc78, 0x770c0001}, {0xc78, 0x760d0001}, 542 {0xc78, 0x750e0001}, {0xc78, 0x740f0001}, 543 {0xc78, 0x73100001}, {0xc78, 0x72110001}, 544 {0xc78, 0x71120001}, {0xc78, 0x70130001}, 545 {0xc78, 0x6f140001}, {0xc78, 0x6e150001}, 546 {0xc78, 0x6d160001}, {0xc78, 0x6c170001}, 547 {0xc78, 0x6b180001}, {0xc78, 0x6a190001}, 548 {0xc78, 0x691a0001}, {0xc78, 0x681b0001}, 549 {0xc78, 0x671c0001}, {0xc78, 0x661d0001}, 550 {0xc78, 0x651e0001}, {0xc78, 0x641f0001}, 551 {0xc78, 0x63200001}, {0xc78, 0x62210001}, 552 {0xc78, 0x61220001}, {0xc78, 0x60230001}, 553 {0xc78, 0x46240001}, {0xc78, 0x45250001}, 554 {0xc78, 0x44260001}, {0xc78, 0x43270001}, 555 {0xc78, 0x42280001}, {0xc78, 0x41290001}, 556 {0xc78, 0x402a0001}, {0xc78, 0x262b0001}, 557 {0xc78, 0x252c0001}, {0xc78, 0x242d0001}, 558 {0xc78, 0x232e0001}, {0xc78, 0x222f0001}, 559 {0xc78, 0x21300001}, {0xc78, 0x20310001}, 560 {0xc78, 0x06320001}, {0xc78, 0x05330001}, 561 {0xc78, 0x04340001}, {0xc78, 0x03350001}, 562 {0xc78, 0x02360001}, {0xc78, 0x01370001}, 563 {0xc78, 0x00380001}, {0xc78, 0x00390001}, 564 {0xc78, 0x003a0001}, {0xc78, 0x003b0001}, 565 {0xc78, 0x003c0001}, {0xc78, 0x003d0001}, 566 {0xc78, 0x003e0001}, {0xc78, 0x003f0001}, 567 {0xc78, 0x7b400001}, {0xc78, 0x7b410001}, 568 {0xc78, 0x7b420001}, {0xc78, 0x7b430001}, 569 {0xc78, 0x7b440001}, {0xc78, 0x7b450001}, 570 {0xc78, 0x7b460001}, {0xc78, 0x7b470001}, 571 {0xc78, 0x7b480001}, {0xc78, 0x7a490001}, 572 {0xc78, 0x794a0001}, {0xc78, 0x784b0001}, 573 {0xc78, 0x774c0001}, {0xc78, 0x764d0001}, 574 {0xc78, 0x754e0001}, {0xc78, 0x744f0001}, 575 {0xc78, 0x73500001}, {0xc78, 0x72510001}, 576 {0xc78, 0x71520001}, {0xc78, 0x70530001}, 577 {0xc78, 0x6f540001}, {0xc78, 0x6e550001}, 578 {0xc78, 0x6d560001}, {0xc78, 0x6c570001}, 579 {0xc78, 0x6b580001}, {0xc78, 0x6a590001}, 580 {0xc78, 0x695a0001}, {0xc78, 0x685b0001}, 581 {0xc78, 0x675c0001}, {0xc78, 0x665d0001}, 582 {0xc78, 0x655e0001}, {0xc78, 0x645f0001}, 583 {0xc78, 0x63600001}, {0xc78, 0x62610001}, 584 {0xc78, 0x61620001}, {0xc78, 0x60630001}, 585 {0xc78, 0x46640001}, {0xc78, 0x45650001}, 586 {0xc78, 0x44660001}, {0xc78, 0x43670001}, 587 {0xc78, 0x42680001}, {0xc78, 0x41690001}, 588 {0xc78, 0x406a0001}, {0xc78, 0x266b0001}, 589 {0xc78, 0x256c0001}, {0xc78, 0x246d0001}, 590 {0xc78, 0x236e0001}, {0xc78, 0x226f0001}, 591 {0xc78, 0x21700001}, {0xc78, 0x20710001}, 592 {0xc78, 0x06720001}, {0xc78, 0x05730001}, 593 {0xc78, 0x04740001}, {0xc78, 0x03750001}, 594 {0xc78, 0x02760001}, {0xc78, 0x01770001}, 595 {0xc78, 0x00780001}, {0xc78, 0x00790001}, 596 {0xc78, 0x007a0001}, {0xc78, 0x007b0001}, 597 {0xc78, 0x007c0001}, {0xc78, 0x007d0001}, 598 {0xc78, 0x007e0001}, {0xc78, 0x007f0001}, 599 {0xc78, 0x3800001e}, {0xc78, 0x3801001e}, 600 {0xc78, 0x3802001e}, {0xc78, 0x3803001e}, 601 {0xc78, 0x3804001e}, {0xc78, 0x3805001e}, 602 {0xc78, 0x3806001e}, {0xc78, 0x3807001e}, 603 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e}, 604 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e}, 605 {0xc78, 0x440c001e}, {0xc78, 0x480d001e}, 606 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e}, 607 {0xc78, 0x5210001e}, {0xc78, 0x5611001e}, 608 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e}, 609 {0xc78, 0x6014001e}, {0xc78, 0x6015001e}, 610 {0xc78, 0x6016001e}, {0xc78, 0x6217001e}, 611 {0xc78, 0x6218001e}, {0xc78, 0x6219001e}, 612 {0xc78, 0x621a001e}, {0xc78, 0x621b001e}, 613 {0xc78, 0x621c001e}, {0xc78, 0x621d001e}, 614 {0xc78, 0x621e001e}, {0xc78, 0x621f001e}, 615 {0xffff, 0xffffffff} 616 }; 617 618 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = { 619 { /* RF_A */ 620 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1, 621 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2, 622 .lssiparm = REG_FPGA0_XA_LSSI_PARM, 623 .hspiread = REG_HSPI_XA_READBACK, 624 .lssiread = REG_FPGA0_XA_LSSI_READBACK, 625 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL, 626 }, 627 { /* RF_B */ 628 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1, 629 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2, 630 .lssiparm = REG_FPGA0_XB_LSSI_PARM, 631 .hspiread = REG_HSPI_XB_READBACK, 632 .lssiread = REG_FPGA0_XB_LSSI_READBACK, 633 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL, 634 }, 635 }; 636 637 const u32 rtl8xxxu_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = { 638 REG_OFDM0_XA_RX_IQ_IMBALANCE, 639 REG_OFDM0_XB_RX_IQ_IMBALANCE, 640 REG_OFDM0_ENERGY_CCA_THRES, 641 REG_OFDM0_AGCR_SSI_TABLE, 642 REG_OFDM0_XA_TX_IQ_IMBALANCE, 643 REG_OFDM0_XB_TX_IQ_IMBALANCE, 644 REG_OFDM0_XC_TX_AFE, 645 REG_OFDM0_XD_TX_AFE, 646 REG_OFDM0_RX_IQ_EXT_ANTA 647 }; 648 649 u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr) 650 { 651 struct usb_device *udev = priv->udev; 652 int len; 653 u8 data; 654 655 mutex_lock(&priv->usb_buf_mutex); 656 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 657 REALTEK_USB_CMD_REQ, REALTEK_USB_READ, 658 addr, 0, &priv->usb_buf.val8, sizeof(u8), 659 RTW_USB_CONTROL_MSG_TIMEOUT); 660 data = priv->usb_buf.val8; 661 mutex_unlock(&priv->usb_buf_mutex); 662 663 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) 664 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n", 665 __func__, addr, data, len); 666 return data; 667 } 668 669 u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr) 670 { 671 struct usb_device *udev = priv->udev; 672 int len; 673 u16 data; 674 675 mutex_lock(&priv->usb_buf_mutex); 676 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 677 REALTEK_USB_CMD_REQ, REALTEK_USB_READ, 678 addr, 0, &priv->usb_buf.val16, sizeof(u16), 679 RTW_USB_CONTROL_MSG_TIMEOUT); 680 data = le16_to_cpu(priv->usb_buf.val16); 681 mutex_unlock(&priv->usb_buf_mutex); 682 683 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) 684 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n", 685 __func__, addr, data, len); 686 return data; 687 } 688 689 u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr) 690 { 691 struct usb_device *udev = priv->udev; 692 int len; 693 u32 data; 694 695 mutex_lock(&priv->usb_buf_mutex); 696 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 697 REALTEK_USB_CMD_REQ, REALTEK_USB_READ, 698 addr, 0, &priv->usb_buf.val32, sizeof(u32), 699 RTW_USB_CONTROL_MSG_TIMEOUT); 700 data = le32_to_cpu(priv->usb_buf.val32); 701 mutex_unlock(&priv->usb_buf_mutex); 702 703 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) 704 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n", 705 __func__, addr, data, len); 706 return data; 707 } 708 709 int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val) 710 { 711 struct usb_device *udev = priv->udev; 712 int ret; 713 714 mutex_lock(&priv->usb_buf_mutex); 715 priv->usb_buf.val8 = val; 716 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 717 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 718 addr, 0, &priv->usb_buf.val8, sizeof(u8), 719 RTW_USB_CONTROL_MSG_TIMEOUT); 720 721 mutex_unlock(&priv->usb_buf_mutex); 722 723 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) 724 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n", 725 __func__, addr, val); 726 return ret; 727 } 728 729 int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val) 730 { 731 struct usb_device *udev = priv->udev; 732 int ret; 733 734 mutex_lock(&priv->usb_buf_mutex); 735 priv->usb_buf.val16 = cpu_to_le16(val); 736 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 737 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 738 addr, 0, &priv->usb_buf.val16, sizeof(u16), 739 RTW_USB_CONTROL_MSG_TIMEOUT); 740 mutex_unlock(&priv->usb_buf_mutex); 741 742 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) 743 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n", 744 __func__, addr, val); 745 return ret; 746 } 747 748 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val) 749 { 750 struct usb_device *udev = priv->udev; 751 int ret; 752 753 mutex_lock(&priv->usb_buf_mutex); 754 priv->usb_buf.val32 = cpu_to_le32(val); 755 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 756 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 757 addr, 0, &priv->usb_buf.val32, sizeof(u32), 758 RTW_USB_CONTROL_MSG_TIMEOUT); 759 mutex_unlock(&priv->usb_buf_mutex); 760 761 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) 762 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n", 763 __func__, addr, val); 764 return ret; 765 } 766 767 static int 768 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len) 769 { 770 struct usb_device *udev = priv->udev; 771 int blocksize = priv->fops->writeN_block_size; 772 int ret, i, count, remainder; 773 774 count = len / blocksize; 775 remainder = len % blocksize; 776 777 for (i = 0; i < count; i++) { 778 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 779 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 780 addr, 0, buf, blocksize, 781 RTW_USB_CONTROL_MSG_TIMEOUT); 782 if (ret != blocksize) 783 goto write_error; 784 785 addr += blocksize; 786 buf += blocksize; 787 } 788 789 if (remainder) { 790 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 791 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 792 addr, 0, buf, remainder, 793 RTW_USB_CONTROL_MSG_TIMEOUT); 794 if (ret != remainder) 795 goto write_error; 796 } 797 798 return len; 799 800 write_error: 801 dev_info(&udev->dev, 802 "%s: Failed to write block at addr: %04x size: %04x\n", 803 __func__, addr, blocksize); 804 return -EAGAIN; 805 } 806 807 u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv, 808 enum rtl8xxxu_rfpath path, u8 reg) 809 { 810 u32 hssia, val32, retval; 811 812 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2); 813 if (path != RF_A) 814 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2); 815 else 816 val32 = hssia; 817 818 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK; 819 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT); 820 val32 |= FPGA0_HSSI_PARM2_EDGE_READ; 821 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ; 822 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); 823 824 udelay(10); 825 826 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32); 827 udelay(100); 828 829 hssia |= FPGA0_HSSI_PARM2_EDGE_READ; 830 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); 831 udelay(10); 832 833 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1); 834 if (val32 & FPGA0_HSSI_PARM1_PI) 835 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread); 836 else 837 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread); 838 839 retval &= 0xfffff; 840 841 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ) 842 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n", 843 __func__, reg, retval); 844 return retval; 845 } 846 847 /* 848 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can 849 * have write issues in high temperature conditions. We may have to 850 * retry writing them. 851 */ 852 int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv, 853 enum rtl8xxxu_rfpath path, u8 reg, u32 data) 854 { 855 int ret, retval; 856 u32 dataaddr, val32; 857 858 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE) 859 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n", 860 __func__, reg, data); 861 862 data &= FPGA0_LSSI_PARM_DATA_MASK; 863 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data; 864 865 if (priv->rtl_chip == RTL8192E) { 866 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 867 val32 &= ~0x20000; 868 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 869 } 870 871 /* Use XB for path B */ 872 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr); 873 if (ret != sizeof(dataaddr)) 874 retval = -EIO; 875 else 876 retval = 0; 877 878 udelay(1); 879 880 if (priv->rtl_chip == RTL8192E) { 881 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 882 val32 |= 0x20000; 883 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 884 } 885 886 return retval; 887 } 888 889 static int 890 rtl8xxxu_gen1_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len) 891 { 892 struct device *dev = &priv->udev->dev; 893 int mbox_nr, retry, retval = 0; 894 int mbox_reg, mbox_ext_reg; 895 u8 val8; 896 897 mutex_lock(&priv->h2c_mutex); 898 899 mbox_nr = priv->next_mbox; 900 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4); 901 mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2); 902 903 /* 904 * MBOX ready? 905 */ 906 retry = 100; 907 do { 908 val8 = rtl8xxxu_read8(priv, REG_HMTFR); 909 if (!(val8 & BIT(mbox_nr))) 910 break; 911 } while (retry--); 912 913 if (!retry) { 914 dev_info(dev, "%s: Mailbox busy\n", __func__); 915 retval = -EBUSY; 916 goto error; 917 } 918 919 /* 920 * Need to swap as it's being swapped again by rtl8xxxu_write16/32() 921 */ 922 if (len > sizeof(u32)) { 923 rtl8xxxu_write16(priv, mbox_ext_reg, le16_to_cpu(h2c->raw.ext)); 924 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 925 dev_info(dev, "H2C_EXT %04x\n", 926 le16_to_cpu(h2c->raw.ext)); 927 } 928 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data)); 929 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 930 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data)); 931 932 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX; 933 934 error: 935 mutex_unlock(&priv->h2c_mutex); 936 return retval; 937 } 938 939 int 940 rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len) 941 { 942 struct device *dev = &priv->udev->dev; 943 int mbox_nr, retry, retval = 0; 944 int mbox_reg, mbox_ext_reg; 945 u8 val8; 946 947 mutex_lock(&priv->h2c_mutex); 948 949 mbox_nr = priv->next_mbox; 950 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4); 951 mbox_ext_reg = REG_HMBOX_EXT0_8723B + (mbox_nr * 4); 952 953 /* 954 * MBOX ready? 955 */ 956 retry = 100; 957 do { 958 val8 = rtl8xxxu_read8(priv, REG_HMTFR); 959 if (!(val8 & BIT(mbox_nr))) 960 break; 961 } while (retry--); 962 963 if (!retry) { 964 dev_info(dev, "%s: Mailbox busy\n", __func__); 965 retval = -EBUSY; 966 goto error; 967 } 968 969 /* 970 * Need to swap as it's being swapped again by rtl8xxxu_write16/32() 971 */ 972 if (len > sizeof(u32)) { 973 rtl8xxxu_write32(priv, mbox_ext_reg, 974 le32_to_cpu(h2c->raw_wide.ext)); 975 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 976 dev_info(dev, "H2C_EXT %08x\n", 977 le32_to_cpu(h2c->raw_wide.ext)); 978 } 979 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data)); 980 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 981 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data)); 982 983 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX; 984 985 error: 986 mutex_unlock(&priv->h2c_mutex); 987 return retval; 988 } 989 990 void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv) 991 { 992 u8 val8; 993 u32 val32; 994 995 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL); 996 val8 |= BIT(0) | BIT(3); 997 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8); 998 999 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); 1000 val32 &= ~(BIT(4) | BIT(5)); 1001 val32 |= BIT(3); 1002 if (priv->rf_paths == 2) { 1003 val32 &= ~(BIT(20) | BIT(21)); 1004 val32 |= BIT(19); 1005 } 1006 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); 1007 1008 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1009 val32 &= ~OFDM_RF_PATH_TX_MASK; 1010 if (priv->tx_paths == 2) 1011 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B; 1012 else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C) 1013 val32 |= OFDM_RF_PATH_TX_B; 1014 else 1015 val32 |= OFDM_RF_PATH_TX_A; 1016 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1017 1018 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1019 val32 &= ~FPGA_RF_MODE_JAPAN; 1020 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1021 1022 if (priv->rf_paths == 2) 1023 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0); 1024 else 1025 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0); 1026 1027 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95); 1028 if (priv->rf_paths == 2) 1029 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95); 1030 1031 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); 1032 } 1033 1034 void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv) 1035 { 1036 u8 sps0; 1037 u32 val32; 1038 1039 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL); 1040 1041 /* RF RX code for preamble power saving */ 1042 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); 1043 val32 &= ~(BIT(3) | BIT(4) | BIT(5)); 1044 if (priv->rf_paths == 2) 1045 val32 &= ~(BIT(19) | BIT(20) | BIT(21)); 1046 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); 1047 1048 /* Disable TX for four paths */ 1049 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1050 val32 &= ~OFDM_RF_PATH_TX_MASK; 1051 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1052 1053 /* Enable power saving */ 1054 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1055 val32 |= FPGA_RF_MODE_JAPAN; 1056 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1057 1058 /* AFE control register to power down bits [30:22] */ 1059 if (priv->rf_paths == 2) 1060 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0); 1061 else 1062 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0); 1063 1064 /* Power down RF module */ 1065 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); 1066 if (priv->rf_paths == 2) 1067 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0); 1068 1069 sps0 &= ~(BIT(0) | BIT(3)); 1070 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0); 1071 } 1072 1073 static void rtl8xxxu_stop_tx_beacon(struct rtl8xxxu_priv *priv) 1074 { 1075 u8 val8; 1076 1077 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2); 1078 val8 &= ~BIT(6); 1079 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8); 1080 1081 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64); 1082 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2); 1083 val8 &= ~BIT(0); 1084 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8); 1085 } 1086 1087 1088 /* 1089 * The rtl8723a has 3 channel groups for it's efuse settings. It only 1090 * supports the 2.4GHz band, so channels 1 - 14: 1091 * group 0: channels 1 - 3 1092 * group 1: channels 4 - 9 1093 * group 2: channels 10 - 14 1094 * 1095 * Note: We index from 0 in the code 1096 */ 1097 static int rtl8xxxu_gen1_channel_to_group(int channel) 1098 { 1099 int group; 1100 1101 if (channel < 4) 1102 group = 0; 1103 else if (channel < 10) 1104 group = 1; 1105 else 1106 group = 2; 1107 1108 return group; 1109 } 1110 1111 /* 1112 * Valid for rtl8723bu and rtl8192eu 1113 */ 1114 int rtl8xxxu_gen2_channel_to_group(int channel) 1115 { 1116 int group; 1117 1118 if (channel < 3) 1119 group = 0; 1120 else if (channel < 6) 1121 group = 1; 1122 else if (channel < 9) 1123 group = 2; 1124 else if (channel < 12) 1125 group = 3; 1126 else 1127 group = 4; 1128 1129 return group; 1130 } 1131 1132 void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw) 1133 { 1134 struct rtl8xxxu_priv *priv = hw->priv; 1135 u32 val32, rsr; 1136 u8 val8, opmode; 1137 bool ht = true; 1138 int sec_ch_above, channel; 1139 int i; 1140 1141 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE); 1142 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 1143 channel = hw->conf.chandef.chan->hw_value; 1144 1145 switch (hw->conf.chandef.width) { 1146 case NL80211_CHAN_WIDTH_20_NOHT: 1147 ht = false; 1148 /* fall through */ 1149 case NL80211_CHAN_WIDTH_20: 1150 opmode |= BW_OPMODE_20MHZ; 1151 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); 1152 1153 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1154 val32 &= ~FPGA_RF_MODE; 1155 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1156 1157 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1158 val32 &= ~FPGA_RF_MODE; 1159 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1160 1161 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); 1162 val32 |= FPGA0_ANALOG2_20MHZ; 1163 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); 1164 break; 1165 case NL80211_CHAN_WIDTH_40: 1166 if (hw->conf.chandef.center_freq1 > 1167 hw->conf.chandef.chan->center_freq) { 1168 sec_ch_above = 1; 1169 channel += 2; 1170 } else { 1171 sec_ch_above = 0; 1172 channel -= 2; 1173 } 1174 1175 opmode &= ~BW_OPMODE_20MHZ; 1176 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); 1177 rsr &= ~RSR_RSC_BANDWIDTH_40M; 1178 if (sec_ch_above) 1179 rsr |= RSR_RSC_UPPER_SUB_CHANNEL; 1180 else 1181 rsr |= RSR_RSC_LOWER_SUB_CHANNEL; 1182 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr); 1183 1184 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1185 val32 |= FPGA_RF_MODE; 1186 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1187 1188 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1189 val32 |= FPGA_RF_MODE; 1190 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1191 1192 /* 1193 * Set Control channel to upper or lower. These settings 1194 * are required only for 40MHz 1195 */ 1196 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); 1197 val32 &= ~CCK0_SIDEBAND; 1198 if (!sec_ch_above) 1199 val32 |= CCK0_SIDEBAND; 1200 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); 1201 1202 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 1203 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ 1204 if (sec_ch_above) 1205 val32 |= OFDM_LSTF_PRIME_CH_LOW; 1206 else 1207 val32 |= OFDM_LSTF_PRIME_CH_HIGH; 1208 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 1209 1210 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); 1211 val32 &= ~FPGA0_ANALOG2_20MHZ; 1212 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); 1213 1214 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 1215 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); 1216 if (sec_ch_above) 1217 val32 |= FPGA0_PS_UPPER_CHANNEL; 1218 else 1219 val32 |= FPGA0_PS_LOWER_CHANNEL; 1220 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 1221 break; 1222 1223 default: 1224 break; 1225 } 1226 1227 for (i = RF_A; i < priv->rf_paths; i++) { 1228 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1229 val32 &= ~MODE_AG_CHANNEL_MASK; 1230 val32 |= channel; 1231 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1232 } 1233 1234 if (ht) 1235 val8 = 0x0e; 1236 else 1237 val8 = 0x0a; 1238 1239 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8); 1240 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8); 1241 1242 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808); 1243 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a); 1244 1245 for (i = RF_A; i < priv->rf_paths; i++) { 1246 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1247 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) 1248 val32 &= ~MODE_AG_CHANNEL_20MHZ; 1249 else 1250 val32 |= MODE_AG_CHANNEL_20MHZ; 1251 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1252 } 1253 } 1254 1255 void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw) 1256 { 1257 struct rtl8xxxu_priv *priv = hw->priv; 1258 u32 val32; 1259 u8 val8, subchannel; 1260 u16 rf_mode_bw; 1261 bool ht = true; 1262 int sec_ch_above, channel; 1263 int i; 1264 1265 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL); 1266 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK; 1267 channel = hw->conf.chandef.chan->hw_value; 1268 1269 /* Hack */ 1270 subchannel = 0; 1271 1272 switch (hw->conf.chandef.width) { 1273 case NL80211_CHAN_WIDTH_20_NOHT: 1274 ht = false; 1275 /* fall through */ 1276 case NL80211_CHAN_WIDTH_20: 1277 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20; 1278 subchannel = 0; 1279 1280 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1281 val32 &= ~FPGA_RF_MODE; 1282 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1283 1284 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1285 val32 &= ~FPGA_RF_MODE; 1286 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1287 1288 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); 1289 val32 &= ~(BIT(30) | BIT(31)); 1290 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); 1291 1292 break; 1293 case NL80211_CHAN_WIDTH_40: 1294 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40; 1295 1296 if (hw->conf.chandef.center_freq1 > 1297 hw->conf.chandef.chan->center_freq) { 1298 sec_ch_above = 1; 1299 channel += 2; 1300 } else { 1301 sec_ch_above = 0; 1302 channel -= 2; 1303 } 1304 1305 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1306 val32 |= FPGA_RF_MODE; 1307 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1308 1309 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1310 val32 |= FPGA_RF_MODE; 1311 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1312 1313 /* 1314 * Set Control channel to upper or lower. These settings 1315 * are required only for 40MHz 1316 */ 1317 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); 1318 val32 &= ~CCK0_SIDEBAND; 1319 if (!sec_ch_above) 1320 val32 |= CCK0_SIDEBAND; 1321 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); 1322 1323 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 1324 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ 1325 if (sec_ch_above) 1326 val32 |= OFDM_LSTF_PRIME_CH_LOW; 1327 else 1328 val32 |= OFDM_LSTF_PRIME_CH_HIGH; 1329 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 1330 1331 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 1332 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); 1333 if (sec_ch_above) 1334 val32 |= FPGA0_PS_UPPER_CHANNEL; 1335 else 1336 val32 |= FPGA0_PS_LOWER_CHANNEL; 1337 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 1338 break; 1339 case NL80211_CHAN_WIDTH_80: 1340 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80; 1341 break; 1342 default: 1343 break; 1344 } 1345 1346 for (i = RF_A; i < priv->rf_paths; i++) { 1347 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1348 val32 &= ~MODE_AG_CHANNEL_MASK; 1349 val32 |= channel; 1350 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1351 } 1352 1353 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw); 1354 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel); 1355 1356 if (ht) 1357 val8 = 0x0e; 1358 else 1359 val8 = 0x0a; 1360 1361 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8); 1362 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8); 1363 1364 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808); 1365 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a); 1366 1367 for (i = RF_A; i < priv->rf_paths; i++) { 1368 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1369 val32 &= ~MODE_AG_BW_MASK; 1370 switch(hw->conf.chandef.width) { 1371 case NL80211_CHAN_WIDTH_80: 1372 val32 |= MODE_AG_BW_80MHZ_8723B; 1373 break; 1374 case NL80211_CHAN_WIDTH_40: 1375 val32 |= MODE_AG_BW_40MHZ_8723B; 1376 break; 1377 default: 1378 val32 |= MODE_AG_BW_20MHZ_8723B; 1379 break; 1380 } 1381 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1382 } 1383 } 1384 1385 void 1386 rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) 1387 { 1388 struct rtl8xxxu_power_base *power_base = priv->power_base; 1389 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS]; 1390 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS]; 1391 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b; 1392 u8 val8; 1393 int group, i; 1394 1395 group = rtl8xxxu_gen1_channel_to_group(channel); 1396 1397 cck[0] = priv->cck_tx_power_index_A[group] - 1; 1398 cck[1] = priv->cck_tx_power_index_B[group] - 1; 1399 1400 if (priv->hi_pa) { 1401 if (cck[0] > 0x20) 1402 cck[0] = 0x20; 1403 if (cck[1] > 0x20) 1404 cck[1] = 0x20; 1405 } 1406 1407 ofdm[0] = priv->ht40_1s_tx_power_index_A[group]; 1408 ofdm[1] = priv->ht40_1s_tx_power_index_B[group]; 1409 if (ofdm[0]) 1410 ofdm[0] -= 1; 1411 if (ofdm[1]) 1412 ofdm[1] -= 1; 1413 1414 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a; 1415 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b; 1416 1417 mcsbase[0] = ofdm[0]; 1418 mcsbase[1] = ofdm[1]; 1419 if (!ht40) { 1420 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a; 1421 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b; 1422 } 1423 1424 if (priv->tx_paths > 1) { 1425 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a) 1426 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a; 1427 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b) 1428 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b; 1429 } 1430 1431 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL) 1432 dev_info(&priv->udev->dev, 1433 "%s: Setting TX power CCK A: %02x, " 1434 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n", 1435 __func__, cck[0], cck[1], ofdm[0], ofdm[1]); 1436 1437 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) { 1438 if (cck[i] > RF6052_MAX_TX_PWR) 1439 cck[i] = RF6052_MAX_TX_PWR; 1440 if (ofdm[i] > RF6052_MAX_TX_PWR) 1441 ofdm[i] = RF6052_MAX_TX_PWR; 1442 } 1443 1444 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); 1445 val32 &= 0xffff00ff; 1446 val32 |= (cck[0] << 8); 1447 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); 1448 1449 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); 1450 val32 &= 0xff; 1451 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24)); 1452 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); 1453 1454 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); 1455 val32 &= 0xffffff00; 1456 val32 |= cck[1]; 1457 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); 1458 1459 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32); 1460 val32 &= 0xff; 1461 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24)); 1462 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32); 1463 1464 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 | 1465 ofdmbase[0] << 16 | ofdmbase[0] << 24; 1466 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 | 1467 ofdmbase[1] << 16 | ofdmbase[1] << 24; 1468 1469 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, 1470 ofdm_a + power_base->reg_0e00); 1471 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, 1472 ofdm_b + power_base->reg_0830); 1473 1474 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, 1475 ofdm_a + power_base->reg_0e04); 1476 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, 1477 ofdm_b + power_base->reg_0834); 1478 1479 mcs_a = mcsbase[0] | mcsbase[0] << 8 | 1480 mcsbase[0] << 16 | mcsbase[0] << 24; 1481 mcs_b = mcsbase[1] | mcsbase[1] << 8 | 1482 mcsbase[1] << 16 | mcsbase[1] << 24; 1483 1484 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, 1485 mcs_a + power_base->reg_0e10); 1486 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, 1487 mcs_b + power_base->reg_083c); 1488 1489 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, 1490 mcs_a + power_base->reg_0e14); 1491 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, 1492 mcs_b + power_base->reg_0848); 1493 1494 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, 1495 mcs_a + power_base->reg_0e18); 1496 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, 1497 mcs_b + power_base->reg_084c); 1498 1499 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, 1500 mcs_a + power_base->reg_0e1c); 1501 for (i = 0; i < 3; i++) { 1502 if (i != 2) 1503 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0; 1504 else 1505 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0; 1506 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8); 1507 } 1508 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, 1509 mcs_b + power_base->reg_0868); 1510 for (i = 0; i < 3; i++) { 1511 if (i != 2) 1512 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0; 1513 else 1514 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0; 1515 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8); 1516 } 1517 } 1518 1519 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv, 1520 enum nl80211_iftype linktype) 1521 { 1522 u8 val8; 1523 1524 val8 = rtl8xxxu_read8(priv, REG_MSR); 1525 val8 &= ~MSR_LINKTYPE_MASK; 1526 1527 switch (linktype) { 1528 case NL80211_IFTYPE_UNSPECIFIED: 1529 val8 |= MSR_LINKTYPE_NONE; 1530 break; 1531 case NL80211_IFTYPE_ADHOC: 1532 val8 |= MSR_LINKTYPE_ADHOC; 1533 break; 1534 case NL80211_IFTYPE_STATION: 1535 val8 |= MSR_LINKTYPE_STATION; 1536 break; 1537 case NL80211_IFTYPE_AP: 1538 val8 |= MSR_LINKTYPE_AP; 1539 break; 1540 default: 1541 goto out; 1542 } 1543 1544 rtl8xxxu_write8(priv, REG_MSR, val8); 1545 out: 1546 return; 1547 } 1548 1549 static void 1550 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry) 1551 { 1552 u16 val16; 1553 1554 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) & 1555 RETRY_LIMIT_SHORT_MASK) | 1556 ((long_retry << RETRY_LIMIT_LONG_SHIFT) & 1557 RETRY_LIMIT_LONG_MASK); 1558 1559 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16); 1560 } 1561 1562 static void 1563 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm) 1564 { 1565 u16 val16; 1566 1567 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) | 1568 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK); 1569 1570 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16); 1571 } 1572 1573 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv) 1574 { 1575 struct device *dev = &priv->udev->dev; 1576 char *cut; 1577 1578 switch (priv->chip_cut) { 1579 case 0: 1580 cut = "A"; 1581 break; 1582 case 1: 1583 cut = "B"; 1584 break; 1585 case 2: 1586 cut = "C"; 1587 break; 1588 case 3: 1589 cut = "D"; 1590 break; 1591 case 4: 1592 cut = "E"; 1593 break; 1594 default: 1595 cut = "unknown"; 1596 } 1597 1598 dev_info(dev, 1599 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n", 1600 priv->chip_name, cut, priv->chip_vendor, priv->tx_paths, 1601 priv->rx_paths, priv->ep_tx_count, priv->has_wifi, 1602 priv->has_bluetooth, priv->has_gps, priv->hi_pa); 1603 1604 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr); 1605 } 1606 1607 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv) 1608 { 1609 struct device *dev = &priv->udev->dev; 1610 u32 val32, bonding; 1611 u16 val16; 1612 1613 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG); 1614 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >> 1615 SYS_CFG_CHIP_VERSION_SHIFT; 1616 if (val32 & SYS_CFG_TRP_VAUX_EN) { 1617 dev_info(dev, "Unsupported test chip\n"); 1618 return -ENOTSUPP; 1619 } 1620 1621 if (val32 & SYS_CFG_BT_FUNC) { 1622 if (priv->chip_cut >= 3) { 1623 sprintf(priv->chip_name, "8723BU"); 1624 priv->rtl_chip = RTL8723B; 1625 } else { 1626 sprintf(priv->chip_name, "8723AU"); 1627 priv->usb_interrupts = 1; 1628 priv->rtl_chip = RTL8723A; 1629 } 1630 1631 priv->rf_paths = 1; 1632 priv->rx_paths = 1; 1633 priv->tx_paths = 1; 1634 1635 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); 1636 if (val32 & MULTI_WIFI_FUNC_EN) 1637 priv->has_wifi = 1; 1638 if (val32 & MULTI_BT_FUNC_EN) 1639 priv->has_bluetooth = 1; 1640 if (val32 & MULTI_GPS_FUNC_EN) 1641 priv->has_gps = 1; 1642 priv->is_multi_func = 1; 1643 } else if (val32 & SYS_CFG_TYPE_ID) { 1644 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM); 1645 bonding &= HPON_FSM_BONDING_MASK; 1646 if (priv->fops->tx_desc_size == 1647 sizeof(struct rtl8xxxu_txdesc40)) { 1648 if (bonding == HPON_FSM_BONDING_1T2R) { 1649 sprintf(priv->chip_name, "8191EU"); 1650 priv->rf_paths = 2; 1651 priv->rx_paths = 2; 1652 priv->tx_paths = 1; 1653 priv->rtl_chip = RTL8191E; 1654 } else { 1655 sprintf(priv->chip_name, "8192EU"); 1656 priv->rf_paths = 2; 1657 priv->rx_paths = 2; 1658 priv->tx_paths = 2; 1659 priv->rtl_chip = RTL8192E; 1660 } 1661 } else if (bonding == HPON_FSM_BONDING_1T2R) { 1662 sprintf(priv->chip_name, "8191CU"); 1663 priv->rf_paths = 2; 1664 priv->rx_paths = 2; 1665 priv->tx_paths = 1; 1666 priv->usb_interrupts = 1; 1667 priv->rtl_chip = RTL8191C; 1668 } else { 1669 sprintf(priv->chip_name, "8192CU"); 1670 priv->rf_paths = 2; 1671 priv->rx_paths = 2; 1672 priv->tx_paths = 2; 1673 priv->usb_interrupts = 1; 1674 priv->rtl_chip = RTL8192C; 1675 } 1676 priv->has_wifi = 1; 1677 } else { 1678 sprintf(priv->chip_name, "8188CU"); 1679 priv->rf_paths = 1; 1680 priv->rx_paths = 1; 1681 priv->tx_paths = 1; 1682 priv->rtl_chip = RTL8188C; 1683 priv->usb_interrupts = 1; 1684 priv->has_wifi = 1; 1685 } 1686 1687 switch (priv->rtl_chip) { 1688 case RTL8188E: 1689 case RTL8192E: 1690 case RTL8723B: 1691 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) { 1692 case SYS_CFG_VENDOR_ID_TSMC: 1693 sprintf(priv->chip_vendor, "TSMC"); 1694 break; 1695 case SYS_CFG_VENDOR_ID_SMIC: 1696 sprintf(priv->chip_vendor, "SMIC"); 1697 priv->vendor_smic = 1; 1698 break; 1699 case SYS_CFG_VENDOR_ID_UMC: 1700 sprintf(priv->chip_vendor, "UMC"); 1701 priv->vendor_umc = 1; 1702 break; 1703 default: 1704 sprintf(priv->chip_vendor, "unknown"); 1705 } 1706 break; 1707 default: 1708 if (val32 & SYS_CFG_VENDOR_ID) { 1709 sprintf(priv->chip_vendor, "UMC"); 1710 priv->vendor_umc = 1; 1711 } else { 1712 sprintf(priv->chip_vendor, "TSMC"); 1713 } 1714 } 1715 1716 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); 1717 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28; 1718 1719 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX); 1720 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) { 1721 priv->ep_tx_high_queue = 1; 1722 priv->ep_tx_count++; 1723 } 1724 1725 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) { 1726 priv->ep_tx_normal_queue = 1; 1727 priv->ep_tx_count++; 1728 } 1729 1730 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) { 1731 priv->ep_tx_low_queue = 1; 1732 priv->ep_tx_count++; 1733 } 1734 1735 /* 1736 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX 1737 */ 1738 if (!priv->ep_tx_count) { 1739 switch (priv->nr_out_eps) { 1740 case 4: 1741 case 3: 1742 priv->ep_tx_low_queue = 1; 1743 priv->ep_tx_count++; 1744 /* fall through */ 1745 case 2: 1746 priv->ep_tx_normal_queue = 1; 1747 priv->ep_tx_count++; 1748 /* fall through */ 1749 case 1: 1750 priv->ep_tx_high_queue = 1; 1751 priv->ep_tx_count++; 1752 break; 1753 default: 1754 dev_info(dev, "Unsupported USB TX end-points\n"); 1755 return -ENOTSUPP; 1756 } 1757 } 1758 1759 return 0; 1760 } 1761 1762 static int 1763 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data) 1764 { 1765 int i; 1766 u8 val8; 1767 u32 val32; 1768 1769 /* Write Address */ 1770 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff); 1771 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2); 1772 val8 &= 0xfc; 1773 val8 |= (offset >> 8) & 0x03; 1774 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8); 1775 1776 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3); 1777 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f); 1778 1779 /* Poll for data read */ 1780 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); 1781 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) { 1782 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); 1783 if (val32 & BIT(31)) 1784 break; 1785 } 1786 1787 if (i == RTL8XXXU_MAX_REG_POLL) 1788 return -EIO; 1789 1790 udelay(50); 1791 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); 1792 1793 *data = val32 & 0xff; 1794 return 0; 1795 } 1796 1797 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv) 1798 { 1799 struct device *dev = &priv->udev->dev; 1800 int i, ret = 0; 1801 u8 val8, word_mask, header, extheader; 1802 u16 val16, efuse_addr, offset; 1803 u32 val32; 1804 1805 val16 = rtl8xxxu_read16(priv, REG_9346CR); 1806 if (val16 & EEPROM_ENABLE) 1807 priv->has_eeprom = 1; 1808 if (val16 & EEPROM_BOOT) 1809 priv->boot_eeprom = 1; 1810 1811 if (priv->is_multi_func) { 1812 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST); 1813 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT; 1814 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32); 1815 } 1816 1817 dev_dbg(dev, "Booting from %s\n", 1818 priv->boot_eeprom ? "EEPROM" : "EFUSE"); 1819 1820 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE); 1821 1822 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */ 1823 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL); 1824 if (!(val16 & SYS_ISO_PWC_EV12V)) { 1825 val16 |= SYS_ISO_PWC_EV12V; 1826 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16); 1827 } 1828 /* Reset: 0x0000[28], default valid */ 1829 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1830 if (!(val16 & SYS_FUNC_ELDR)) { 1831 val16 |= SYS_FUNC_ELDR; 1832 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 1833 } 1834 1835 /* 1836 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid 1837 */ 1838 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR); 1839 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) { 1840 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M); 1841 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16); 1842 } 1843 1844 /* Default value is 0xff */ 1845 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN); 1846 1847 efuse_addr = 0; 1848 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) { 1849 u16 map_addr; 1850 1851 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header); 1852 if (ret || header == 0xff) 1853 goto exit; 1854 1855 if ((header & 0x1f) == 0x0f) { /* extended header */ 1856 offset = (header & 0xe0) >> 5; 1857 1858 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, 1859 &extheader); 1860 if (ret) 1861 goto exit; 1862 /* All words disabled */ 1863 if ((extheader & 0x0f) == 0x0f) 1864 continue; 1865 1866 offset |= ((extheader & 0xf0) >> 1); 1867 word_mask = extheader & 0x0f; 1868 } else { 1869 offset = (header >> 4) & 0x0f; 1870 word_mask = header & 0x0f; 1871 } 1872 1873 /* Get word enable value from PG header */ 1874 1875 /* We have 8 bits to indicate validity */ 1876 map_addr = offset * 8; 1877 if (map_addr >= EFUSE_MAP_LEN) { 1878 dev_warn(dev, "%s: Illegal map_addr (%04x), " 1879 "efuse corrupt!\n", 1880 __func__, map_addr); 1881 ret = -EINVAL; 1882 goto exit; 1883 } 1884 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { 1885 /* Check word enable condition in the section */ 1886 if (word_mask & BIT(i)) { 1887 map_addr += 2; 1888 continue; 1889 } 1890 1891 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8); 1892 if (ret) 1893 goto exit; 1894 priv->efuse_wifi.raw[map_addr++] = val8; 1895 1896 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8); 1897 if (ret) 1898 goto exit; 1899 priv->efuse_wifi.raw[map_addr++] = val8; 1900 } 1901 } 1902 1903 exit: 1904 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE); 1905 1906 return ret; 1907 } 1908 1909 void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv) 1910 { 1911 u8 val8; 1912 u16 sys_func; 1913 1914 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 1915 val8 &= ~BIT(0); 1916 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 1917 1918 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1919 sys_func &= ~SYS_FUNC_CPU_ENABLE; 1920 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); 1921 1922 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 1923 val8 |= BIT(0); 1924 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 1925 1926 sys_func |= SYS_FUNC_CPU_ENABLE; 1927 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); 1928 } 1929 1930 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv) 1931 { 1932 struct device *dev = &priv->udev->dev; 1933 int ret = 0, i; 1934 u32 val32; 1935 1936 /* Poll checksum report */ 1937 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) { 1938 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); 1939 if (val32 & MCU_FW_DL_CSUM_REPORT) 1940 break; 1941 } 1942 1943 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) { 1944 dev_warn(dev, "Firmware checksum poll timed out\n"); 1945 ret = -EAGAIN; 1946 goto exit; 1947 } 1948 1949 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); 1950 val32 |= MCU_FW_DL_READY; 1951 val32 &= ~MCU_WINT_INIT_READY; 1952 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32); 1953 1954 /* 1955 * Reset the 8051 in order for the firmware to start running, 1956 * otherwise it won't come up on the 8192eu 1957 */ 1958 priv->fops->reset_8051(priv); 1959 1960 /* Wait for firmware to become ready */ 1961 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) { 1962 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); 1963 if (val32 & MCU_WINT_INIT_READY) 1964 break; 1965 1966 udelay(100); 1967 } 1968 1969 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) { 1970 dev_warn(dev, "Firmware failed to start\n"); 1971 ret = -EAGAIN; 1972 goto exit; 1973 } 1974 1975 /* 1976 * Init H2C command 1977 */ 1978 if (priv->rtl_chip == RTL8723B) 1979 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f); 1980 exit: 1981 return ret; 1982 } 1983 1984 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv) 1985 { 1986 int pages, remainder, i, ret; 1987 u8 val8; 1988 u16 val16; 1989 u32 val32; 1990 u8 *fwptr; 1991 1992 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1); 1993 val8 |= 4; 1994 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8); 1995 1996 /* 8051 enable */ 1997 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1998 val16 |= SYS_FUNC_CPU_ENABLE; 1999 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 2000 2001 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL); 2002 if (val8 & MCU_FW_RAM_SEL) { 2003 pr_info("do the RAM reset\n"); 2004 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); 2005 priv->fops->reset_8051(priv); 2006 } 2007 2008 /* MCU firmware download enable */ 2009 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL); 2010 val8 |= MCU_FW_DL_ENABLE; 2011 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8); 2012 2013 /* 8051 reset */ 2014 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); 2015 val32 &= ~BIT(19); 2016 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32); 2017 2018 /* Reset firmware download checksum */ 2019 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL); 2020 val8 |= MCU_FW_DL_CSUM_REPORT; 2021 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8); 2022 2023 pages = priv->fw_size / RTL_FW_PAGE_SIZE; 2024 remainder = priv->fw_size % RTL_FW_PAGE_SIZE; 2025 2026 fwptr = priv->fw_data->data; 2027 2028 for (i = 0; i < pages; i++) { 2029 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8; 2030 val8 |= i; 2031 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8); 2032 2033 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS, 2034 fwptr, RTL_FW_PAGE_SIZE); 2035 if (ret != RTL_FW_PAGE_SIZE) { 2036 ret = -EAGAIN; 2037 goto fw_abort; 2038 } 2039 2040 fwptr += RTL_FW_PAGE_SIZE; 2041 } 2042 2043 if (remainder) { 2044 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8; 2045 val8 |= i; 2046 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8); 2047 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS, 2048 fwptr, remainder); 2049 if (ret != remainder) { 2050 ret = -EAGAIN; 2051 goto fw_abort; 2052 } 2053 } 2054 2055 ret = 0; 2056 fw_abort: 2057 /* MCU firmware download disable */ 2058 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL); 2059 val16 &= ~MCU_FW_DL_ENABLE; 2060 rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16); 2061 2062 return ret; 2063 } 2064 2065 int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name) 2066 { 2067 struct device *dev = &priv->udev->dev; 2068 const struct firmware *fw; 2069 int ret = 0; 2070 u16 signature; 2071 2072 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name); 2073 if (request_firmware(&fw, fw_name, &priv->udev->dev)) { 2074 dev_warn(dev, "request_firmware(%s) failed\n", fw_name); 2075 ret = -EAGAIN; 2076 goto exit; 2077 } 2078 if (!fw) { 2079 dev_warn(dev, "Firmware data not available\n"); 2080 ret = -EINVAL; 2081 goto exit; 2082 } 2083 2084 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL); 2085 if (!priv->fw_data) { 2086 ret = -ENOMEM; 2087 goto exit; 2088 } 2089 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header); 2090 2091 signature = le16_to_cpu(priv->fw_data->signature); 2092 switch (signature & 0xfff0) { 2093 case 0x92e0: 2094 case 0x92c0: 2095 case 0x88c0: 2096 case 0x5300: 2097 case 0x2300: 2098 break; 2099 default: 2100 ret = -EINVAL; 2101 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n", 2102 __func__, signature); 2103 } 2104 2105 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n", 2106 le16_to_cpu(priv->fw_data->major_version), 2107 priv->fw_data->minor_version, signature); 2108 2109 exit: 2110 release_firmware(fw); 2111 return ret; 2112 } 2113 2114 void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv) 2115 { 2116 u16 val16; 2117 int i = 100; 2118 2119 /* Inform 8051 to perform reset */ 2120 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20); 2121 2122 for (i = 100; i > 0; i--) { 2123 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2124 2125 if (!(val16 & SYS_FUNC_CPU_ENABLE)) { 2126 dev_dbg(&priv->udev->dev, 2127 "%s: Firmware self reset success!\n", __func__); 2128 break; 2129 } 2130 udelay(50); 2131 } 2132 2133 if (!i) { 2134 /* Force firmware reset */ 2135 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2136 val16 &= ~SYS_FUNC_CPU_ENABLE; 2137 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 2138 } 2139 } 2140 2141 static int 2142 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv) 2143 { 2144 struct rtl8xxxu_reg8val *array = priv->fops->mactable; 2145 int i, ret; 2146 u16 reg; 2147 u8 val; 2148 2149 for (i = 0; ; i++) { 2150 reg = array[i].reg; 2151 val = array[i].val; 2152 2153 if (reg == 0xffff && val == 0xff) 2154 break; 2155 2156 ret = rtl8xxxu_write8(priv, reg, val); 2157 if (ret != 1) { 2158 dev_warn(&priv->udev->dev, 2159 "Failed to initialize MAC " 2160 "(reg: %04x, val %02x)\n", reg, val); 2161 return -EAGAIN; 2162 } 2163 } 2164 2165 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E) 2166 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a); 2167 2168 return 0; 2169 } 2170 2171 int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv, 2172 struct rtl8xxxu_reg32val *array) 2173 { 2174 int i, ret; 2175 u16 reg; 2176 u32 val; 2177 2178 for (i = 0; ; i++) { 2179 reg = array[i].reg; 2180 val = array[i].val; 2181 2182 if (reg == 0xffff && val == 0xffffffff) 2183 break; 2184 2185 ret = rtl8xxxu_write32(priv, reg, val); 2186 if (ret != sizeof(val)) { 2187 dev_warn(&priv->udev->dev, 2188 "Failed to initialize PHY\n"); 2189 return -EAGAIN; 2190 } 2191 udelay(1); 2192 } 2193 2194 return 0; 2195 } 2196 2197 void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv) 2198 { 2199 u8 val8, ldoa15, ldov12d, lpldo, ldohci12; 2200 u16 val16; 2201 u32 val32; 2202 2203 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); 2204 udelay(2); 2205 val8 |= AFE_PLL_320_ENABLE; 2206 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); 2207 udelay(2); 2208 2209 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff); 2210 udelay(2); 2211 2212 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2213 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB; 2214 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 2215 2216 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); 2217 val32 &= ~AFE_XTAL_RF_GATE; 2218 if (priv->has_bluetooth) 2219 val32 &= ~AFE_XTAL_BT_GATE; 2220 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); 2221 2222 /* 6. 0x1f[7:0] = 0x07 */ 2223 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; 2224 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); 2225 2226 if (priv->hi_pa) 2227 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table); 2228 else if (priv->tx_paths == 2) 2229 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table); 2230 else 2231 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table); 2232 2233 if (priv->rtl_chip == RTL8188R && priv->hi_pa && 2234 priv->vendor_umc && priv->chip_cut == 1) 2235 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50); 2236 2237 if (priv->hi_pa) 2238 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table); 2239 else 2240 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table); 2241 2242 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF; 2243 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT); 2244 ldohci12 = 0x57; 2245 lpldo = 1; 2246 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15; 2247 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32); 2248 } 2249 2250 /* 2251 * Most of this is black magic retrieved from the old rtl8723au driver 2252 */ 2253 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv) 2254 { 2255 u8 val8; 2256 u32 val32; 2257 2258 priv->fops->init_phy_bb(priv); 2259 2260 if (priv->tx_paths == 1 && priv->rx_paths == 2) { 2261 /* 2262 * For 1T2R boards, patch the registers. 2263 * 2264 * It looks like 8191/2 1T2R boards use path B for TX 2265 */ 2266 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO); 2267 val32 &= ~(BIT(0) | BIT(1)); 2268 val32 |= BIT(1); 2269 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32); 2270 2271 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO); 2272 val32 &= ~0x300033; 2273 val32 |= 0x200022; 2274 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32); 2275 2276 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); 2277 val32 &= ~CCK0_AFE_RX_MASK; 2278 val32 &= 0x00ffffff; 2279 val32 |= 0x40000000; 2280 val32 |= CCK0_AFE_RX_ANT_B; 2281 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); 2282 2283 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 2284 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); 2285 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B | 2286 OFDM_RF_PATH_TX_B); 2287 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 2288 2289 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1); 2290 val32 &= ~(BIT(4) | BIT(5)); 2291 val32 |= BIT(4); 2292 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32); 2293 2294 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON); 2295 val32 &= ~(BIT(27) | BIT(26)); 2296 val32 |= BIT(27); 2297 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32); 2298 2299 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON); 2300 val32 &= ~(BIT(27) | BIT(26)); 2301 val32 |= BIT(27); 2302 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32); 2303 2304 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON); 2305 val32 &= ~(BIT(27) | BIT(26)); 2306 val32 |= BIT(27); 2307 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32); 2308 2309 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON); 2310 val32 &= ~(BIT(27) | BIT(26)); 2311 val32 |= BIT(27); 2312 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32); 2313 2314 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX); 2315 val32 &= ~(BIT(27) | BIT(26)); 2316 val32 |= BIT(27); 2317 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32); 2318 } 2319 2320 if (priv->has_xtalk) { 2321 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL); 2322 2323 val8 = priv->xtalk; 2324 val32 &= 0xff000fff; 2325 val32 |= ((val8 | (val8 << 6)) << 12); 2326 2327 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32); 2328 } 2329 2330 if (priv->rtl_chip == RTL8192E) 2331 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x000f81fb); 2332 2333 return 0; 2334 } 2335 2336 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv, 2337 struct rtl8xxxu_rfregval *array, 2338 enum rtl8xxxu_rfpath path) 2339 { 2340 int i, ret; 2341 u8 reg; 2342 u32 val; 2343 2344 for (i = 0; ; i++) { 2345 reg = array[i].reg; 2346 val = array[i].val; 2347 2348 if (reg == 0xff && val == 0xffffffff) 2349 break; 2350 2351 switch (reg) { 2352 case 0xfe: 2353 msleep(50); 2354 continue; 2355 case 0xfd: 2356 mdelay(5); 2357 continue; 2358 case 0xfc: 2359 mdelay(1); 2360 continue; 2361 case 0xfb: 2362 udelay(50); 2363 continue; 2364 case 0xfa: 2365 udelay(5); 2366 continue; 2367 case 0xf9: 2368 udelay(1); 2369 continue; 2370 } 2371 2372 ret = rtl8xxxu_write_rfreg(priv, path, reg, val); 2373 if (ret) { 2374 dev_warn(&priv->udev->dev, 2375 "Failed to initialize RF\n"); 2376 return -EAGAIN; 2377 } 2378 udelay(1); 2379 } 2380 2381 return 0; 2382 } 2383 2384 int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv, 2385 struct rtl8xxxu_rfregval *table, 2386 enum rtl8xxxu_rfpath path) 2387 { 2388 u32 val32; 2389 u16 val16, rfsi_rfenv; 2390 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2; 2391 2392 switch (path) { 2393 case RF_A: 2394 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL; 2395 reg_int_oe = REG_FPGA0_XA_RF_INT_OE; 2396 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2; 2397 break; 2398 case RF_B: 2399 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL; 2400 reg_int_oe = REG_FPGA0_XB_RF_INT_OE; 2401 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2; 2402 break; 2403 default: 2404 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n", 2405 __func__, path + 'A'); 2406 return -EINVAL; 2407 } 2408 /* For path B, use XB */ 2409 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl); 2410 rfsi_rfenv &= FPGA0_RF_RFENV; 2411 2412 /* 2413 * These two we might be able to optimize into one 2414 */ 2415 val32 = rtl8xxxu_read32(priv, reg_int_oe); 2416 val32 |= BIT(20); /* 0x10 << 16 */ 2417 rtl8xxxu_write32(priv, reg_int_oe, val32); 2418 udelay(1); 2419 2420 val32 = rtl8xxxu_read32(priv, reg_int_oe); 2421 val32 |= BIT(4); 2422 rtl8xxxu_write32(priv, reg_int_oe, val32); 2423 udelay(1); 2424 2425 /* 2426 * These two we might be able to optimize into one 2427 */ 2428 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); 2429 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN; 2430 rtl8xxxu_write32(priv, reg_hssi_parm2, val32); 2431 udelay(1); 2432 2433 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); 2434 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN; 2435 rtl8xxxu_write32(priv, reg_hssi_parm2, val32); 2436 udelay(1); 2437 2438 rtl8xxxu_init_rf_regs(priv, table, path); 2439 2440 /* For path B, use XB */ 2441 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl); 2442 val16 &= ~FPGA0_RF_RFENV; 2443 val16 |= rfsi_rfenv; 2444 rtl8xxxu_write16(priv, reg_sw_ctrl, val16); 2445 2446 return 0; 2447 } 2448 2449 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data) 2450 { 2451 int ret = -EBUSY; 2452 int count = 0; 2453 u32 value; 2454 2455 value = LLT_OP_WRITE | address << 8 | data; 2456 2457 rtl8xxxu_write32(priv, REG_LLT_INIT, value); 2458 2459 do { 2460 value = rtl8xxxu_read32(priv, REG_LLT_INIT); 2461 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) { 2462 ret = 0; 2463 break; 2464 } 2465 } while (count++ < 20); 2466 2467 return ret; 2468 } 2469 2470 int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv) 2471 { 2472 int ret; 2473 int i; 2474 u8 last_tx_page; 2475 2476 last_tx_page = priv->fops->total_page_num; 2477 2478 for (i = 0; i < last_tx_page; i++) { 2479 ret = rtl8xxxu_llt_write(priv, i, i + 1); 2480 if (ret) 2481 goto exit; 2482 } 2483 2484 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff); 2485 if (ret) 2486 goto exit; 2487 2488 /* Mark remaining pages as a ring buffer */ 2489 for (i = last_tx_page + 1; i < 0xff; i++) { 2490 ret = rtl8xxxu_llt_write(priv, i, (i + 1)); 2491 if (ret) 2492 goto exit; 2493 } 2494 2495 /* Let last entry point to the start entry of ring buffer */ 2496 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1); 2497 if (ret) 2498 goto exit; 2499 2500 exit: 2501 return ret; 2502 } 2503 2504 int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv) 2505 { 2506 u32 val32; 2507 int ret = 0; 2508 int i; 2509 2510 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT); 2511 val32 |= AUTO_LLT_INIT_LLT; 2512 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32); 2513 2514 for (i = 500; i; i--) { 2515 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT); 2516 if (!(val32 & AUTO_LLT_INIT_LLT)) 2517 break; 2518 usleep_range(2, 4); 2519 } 2520 2521 if (!i) { 2522 ret = -EBUSY; 2523 dev_warn(&priv->udev->dev, "LLT table init failed\n"); 2524 } 2525 2526 return ret; 2527 } 2528 2529 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv) 2530 { 2531 u16 val16, hi, lo; 2532 u16 hiq, mgq, bkq, beq, viq, voq; 2533 int hip, mgp, bkp, bep, vip, vop; 2534 int ret = 0; 2535 2536 switch (priv->ep_tx_count) { 2537 case 1: 2538 if (priv->ep_tx_high_queue) { 2539 hi = TRXDMA_QUEUE_HIGH; 2540 } else if (priv->ep_tx_low_queue) { 2541 hi = TRXDMA_QUEUE_LOW; 2542 } else if (priv->ep_tx_normal_queue) { 2543 hi = TRXDMA_QUEUE_NORMAL; 2544 } else { 2545 hi = 0; 2546 ret = -EINVAL; 2547 } 2548 2549 hiq = hi; 2550 mgq = hi; 2551 bkq = hi; 2552 beq = hi; 2553 viq = hi; 2554 voq = hi; 2555 2556 hip = 0; 2557 mgp = 0; 2558 bkp = 0; 2559 bep = 0; 2560 vip = 0; 2561 vop = 0; 2562 break; 2563 case 2: 2564 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) { 2565 hi = TRXDMA_QUEUE_HIGH; 2566 lo = TRXDMA_QUEUE_LOW; 2567 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) { 2568 hi = TRXDMA_QUEUE_NORMAL; 2569 lo = TRXDMA_QUEUE_LOW; 2570 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) { 2571 hi = TRXDMA_QUEUE_HIGH; 2572 lo = TRXDMA_QUEUE_NORMAL; 2573 } else { 2574 ret = -EINVAL; 2575 hi = 0; 2576 lo = 0; 2577 } 2578 2579 hiq = hi; 2580 mgq = hi; 2581 bkq = lo; 2582 beq = lo; 2583 viq = hi; 2584 voq = hi; 2585 2586 hip = 0; 2587 mgp = 0; 2588 bkp = 1; 2589 bep = 1; 2590 vip = 0; 2591 vop = 0; 2592 break; 2593 case 3: 2594 beq = TRXDMA_QUEUE_LOW; 2595 bkq = TRXDMA_QUEUE_LOW; 2596 viq = TRXDMA_QUEUE_NORMAL; 2597 voq = TRXDMA_QUEUE_HIGH; 2598 mgq = TRXDMA_QUEUE_HIGH; 2599 hiq = TRXDMA_QUEUE_HIGH; 2600 2601 hip = hiq ^ 3; 2602 mgp = mgq ^ 3; 2603 bkp = bkq ^ 3; 2604 bep = beq ^ 3; 2605 vip = viq ^ 3; 2606 vop = viq ^ 3; 2607 break; 2608 default: 2609 ret = -EINVAL; 2610 } 2611 2612 /* 2613 * None of the vendor drivers are configuring the beacon 2614 * queue here .... why? 2615 */ 2616 if (!ret) { 2617 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL); 2618 val16 &= 0x7; 2619 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) | 2620 (viq << TRXDMA_CTRL_VIQ_SHIFT) | 2621 (beq << TRXDMA_CTRL_BEQ_SHIFT) | 2622 (bkq << TRXDMA_CTRL_BKQ_SHIFT) | 2623 (mgq << TRXDMA_CTRL_MGQ_SHIFT) | 2624 (hiq << TRXDMA_CTRL_HIQ_SHIFT); 2625 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16); 2626 2627 priv->pipe_out[TXDESC_QUEUE_VO] = 2628 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]); 2629 priv->pipe_out[TXDESC_QUEUE_VI] = 2630 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]); 2631 priv->pipe_out[TXDESC_QUEUE_BE] = 2632 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]); 2633 priv->pipe_out[TXDESC_QUEUE_BK] = 2634 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]); 2635 priv->pipe_out[TXDESC_QUEUE_BEACON] = 2636 usb_sndbulkpipe(priv->udev, priv->out_ep[0]); 2637 priv->pipe_out[TXDESC_QUEUE_MGNT] = 2638 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]); 2639 priv->pipe_out[TXDESC_QUEUE_HIGH] = 2640 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]); 2641 priv->pipe_out[TXDESC_QUEUE_CMD] = 2642 usb_sndbulkpipe(priv->udev, priv->out_ep[0]); 2643 } 2644 2645 return ret; 2646 } 2647 2648 void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok, 2649 int result[][8], int candidate, bool tx_only) 2650 { 2651 u32 oldval, x, tx0_a, reg; 2652 int y, tx0_c; 2653 u32 val32; 2654 2655 if (!iqk_ok) 2656 return; 2657 2658 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); 2659 oldval = val32 >> 22; 2660 2661 x = result[candidate][0]; 2662 if ((x & 0x00000200) != 0) 2663 x = x | 0xfffffc00; 2664 tx0_a = (x * oldval) >> 8; 2665 2666 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); 2667 val32 &= ~0x3ff; 2668 val32 |= tx0_a; 2669 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); 2670 2671 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2672 val32 &= ~BIT(31); 2673 if ((x * oldval >> 7) & 0x1) 2674 val32 |= BIT(31); 2675 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2676 2677 y = result[candidate][1]; 2678 if ((y & 0x00000200) != 0) 2679 y = y | 0xfffffc00; 2680 tx0_c = (y * oldval) >> 8; 2681 2682 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE); 2683 val32 &= ~0xf0000000; 2684 val32 |= (((tx0_c & 0x3c0) >> 6) << 28); 2685 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32); 2686 2687 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); 2688 val32 &= ~0x003f0000; 2689 val32 |= ((tx0_c & 0x3f) << 16); 2690 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); 2691 2692 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2693 val32 &= ~BIT(29); 2694 if ((y * oldval >> 7) & 0x1) 2695 val32 |= BIT(29); 2696 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2697 2698 if (tx_only) { 2699 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__); 2700 return; 2701 } 2702 2703 reg = result[candidate][2]; 2704 2705 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); 2706 val32 &= ~0x3ff; 2707 val32 |= (reg & 0x3ff); 2708 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); 2709 2710 reg = result[candidate][3] & 0x3F; 2711 2712 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); 2713 val32 &= ~0xfc00; 2714 val32 |= ((reg << 10) & 0xfc00); 2715 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); 2716 2717 reg = (result[candidate][3] >> 6) & 0xF; 2718 2719 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA); 2720 val32 &= ~0xf0000000; 2721 val32 |= (reg << 28); 2722 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32); 2723 } 2724 2725 void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok, 2726 int result[][8], int candidate, bool tx_only) 2727 { 2728 u32 oldval, x, tx1_a, reg; 2729 int y, tx1_c; 2730 u32 val32; 2731 2732 if (!iqk_ok) 2733 return; 2734 2735 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); 2736 oldval = val32 >> 22; 2737 2738 x = result[candidate][4]; 2739 if ((x & 0x00000200) != 0) 2740 x = x | 0xfffffc00; 2741 tx1_a = (x * oldval) >> 8; 2742 2743 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); 2744 val32 &= ~0x3ff; 2745 val32 |= tx1_a; 2746 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); 2747 2748 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2749 val32 &= ~BIT(27); 2750 if ((x * oldval >> 7) & 0x1) 2751 val32 |= BIT(27); 2752 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2753 2754 y = result[candidate][5]; 2755 if ((y & 0x00000200) != 0) 2756 y = y | 0xfffffc00; 2757 tx1_c = (y * oldval) >> 8; 2758 2759 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE); 2760 val32 &= ~0xf0000000; 2761 val32 |= (((tx1_c & 0x3c0) >> 6) << 28); 2762 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32); 2763 2764 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); 2765 val32 &= ~0x003f0000; 2766 val32 |= ((tx1_c & 0x3f) << 16); 2767 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); 2768 2769 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2770 val32 &= ~BIT(25); 2771 if ((y * oldval >> 7) & 0x1) 2772 val32 |= BIT(25); 2773 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2774 2775 if (tx_only) { 2776 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__); 2777 return; 2778 } 2779 2780 reg = result[candidate][6]; 2781 2782 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); 2783 val32 &= ~0x3ff; 2784 val32 |= (reg & 0x3ff); 2785 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); 2786 2787 reg = result[candidate][7] & 0x3f; 2788 2789 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); 2790 val32 &= ~0xfc00; 2791 val32 |= ((reg << 10) & 0xfc00); 2792 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); 2793 2794 reg = (result[candidate][7] >> 6) & 0xf; 2795 2796 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE); 2797 val32 &= ~0x0000f000; 2798 val32 |= (reg << 12); 2799 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32); 2800 } 2801 2802 #define MAX_TOLERANCE 5 2803 2804 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv, 2805 int result[][8], int c1, int c2) 2806 { 2807 u32 i, j, diff, simubitmap, bound = 0; 2808 int candidate[2] = {-1, -1}; /* for path A and path B */ 2809 bool retval = true; 2810 2811 if (priv->tx_paths > 1) 2812 bound = 8; 2813 else 2814 bound = 4; 2815 2816 simubitmap = 0; 2817 2818 for (i = 0; i < bound; i++) { 2819 diff = (result[c1][i] > result[c2][i]) ? 2820 (result[c1][i] - result[c2][i]) : 2821 (result[c2][i] - result[c1][i]); 2822 if (diff > MAX_TOLERANCE) { 2823 if ((i == 2 || i == 6) && !simubitmap) { 2824 if (result[c1][i] + result[c1][i + 1] == 0) 2825 candidate[(i / 4)] = c2; 2826 else if (result[c2][i] + result[c2][i + 1] == 0) 2827 candidate[(i / 4)] = c1; 2828 else 2829 simubitmap = simubitmap | (1 << i); 2830 } else { 2831 simubitmap = simubitmap | (1 << i); 2832 } 2833 } 2834 } 2835 2836 if (simubitmap == 0) { 2837 for (i = 0; i < (bound / 4); i++) { 2838 if (candidate[i] >= 0) { 2839 for (j = i * 4; j < (i + 1) * 4 - 2; j++) 2840 result[3][j] = result[candidate[i]][j]; 2841 retval = false; 2842 } 2843 } 2844 return retval; 2845 } else if (!(simubitmap & 0x0f)) { 2846 /* path A OK */ 2847 for (i = 0; i < 4; i++) 2848 result[3][i] = result[c1][i]; 2849 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) { 2850 /* path B OK */ 2851 for (i = 4; i < 8; i++) 2852 result[3][i] = result[c1][i]; 2853 } 2854 2855 return false; 2856 } 2857 2858 bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv, 2859 int result[][8], int c1, int c2) 2860 { 2861 u32 i, j, diff, simubitmap, bound = 0; 2862 int candidate[2] = {-1, -1}; /* for path A and path B */ 2863 int tmp1, tmp2; 2864 bool retval = true; 2865 2866 if (priv->tx_paths > 1) 2867 bound = 8; 2868 else 2869 bound = 4; 2870 2871 simubitmap = 0; 2872 2873 for (i = 0; i < bound; i++) { 2874 if (i & 1) { 2875 if ((result[c1][i] & 0x00000200)) 2876 tmp1 = result[c1][i] | 0xfffffc00; 2877 else 2878 tmp1 = result[c1][i]; 2879 2880 if ((result[c2][i]& 0x00000200)) 2881 tmp2 = result[c2][i] | 0xfffffc00; 2882 else 2883 tmp2 = result[c2][i]; 2884 } else { 2885 tmp1 = result[c1][i]; 2886 tmp2 = result[c2][i]; 2887 } 2888 2889 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); 2890 2891 if (diff > MAX_TOLERANCE) { 2892 if ((i == 2 || i == 6) && !simubitmap) { 2893 if (result[c1][i] + result[c1][i + 1] == 0) 2894 candidate[(i / 4)] = c2; 2895 else if (result[c2][i] + result[c2][i + 1] == 0) 2896 candidate[(i / 4)] = c1; 2897 else 2898 simubitmap = simubitmap | (1 << i); 2899 } else { 2900 simubitmap = simubitmap | (1 << i); 2901 } 2902 } 2903 } 2904 2905 if (simubitmap == 0) { 2906 for (i = 0; i < (bound / 4); i++) { 2907 if (candidate[i] >= 0) { 2908 for (j = i * 4; j < (i + 1) * 4 - 2; j++) 2909 result[3][j] = result[candidate[i]][j]; 2910 retval = false; 2911 } 2912 } 2913 return retval; 2914 } else { 2915 if (!(simubitmap & 0x03)) { 2916 /* path A TX OK */ 2917 for (i = 0; i < 2; i++) 2918 result[3][i] = result[c1][i]; 2919 } 2920 2921 if (!(simubitmap & 0x0c)) { 2922 /* path A RX OK */ 2923 for (i = 2; i < 4; i++) 2924 result[3][i] = result[c1][i]; 2925 } 2926 2927 if (!(simubitmap & 0x30) && priv->tx_paths > 1) { 2928 /* path B RX OK */ 2929 for (i = 4; i < 6; i++) 2930 result[3][i] = result[c1][i]; 2931 } 2932 2933 if (!(simubitmap & 0x30) && priv->tx_paths > 1) { 2934 /* path B RX OK */ 2935 for (i = 6; i < 8; i++) 2936 result[3][i] = result[c1][i]; 2937 } 2938 } 2939 2940 return false; 2941 } 2942 2943 void 2944 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup) 2945 { 2946 int i; 2947 2948 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++) 2949 backup[i] = rtl8xxxu_read8(priv, reg[i]); 2950 2951 backup[i] = rtl8xxxu_read32(priv, reg[i]); 2952 } 2953 2954 void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv, 2955 const u32 *reg, u32 *backup) 2956 { 2957 int i; 2958 2959 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++) 2960 rtl8xxxu_write8(priv, reg[i], backup[i]); 2961 2962 rtl8xxxu_write32(priv, reg[i], backup[i]); 2963 } 2964 2965 void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 2966 u32 *backup, int count) 2967 { 2968 int i; 2969 2970 for (i = 0; i < count; i++) 2971 backup[i] = rtl8xxxu_read32(priv, regs[i]); 2972 } 2973 2974 void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 2975 u32 *backup, int count) 2976 { 2977 int i; 2978 2979 for (i = 0; i < count; i++) 2980 rtl8xxxu_write32(priv, regs[i], backup[i]); 2981 } 2982 2983 2984 void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs, 2985 bool path_a_on) 2986 { 2987 u32 path_on; 2988 int i; 2989 2990 if (priv->tx_paths == 1) { 2991 path_on = priv->fops->adda_1t_path_on; 2992 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init); 2993 } else { 2994 path_on = path_a_on ? priv->fops->adda_2t_path_on_a : 2995 priv->fops->adda_2t_path_on_b; 2996 2997 rtl8xxxu_write32(priv, regs[0], path_on); 2998 } 2999 3000 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++) 3001 rtl8xxxu_write32(priv, regs[i], path_on); 3002 } 3003 3004 void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv, 3005 const u32 *regs, u32 *backup) 3006 { 3007 int i = 0; 3008 3009 rtl8xxxu_write8(priv, regs[i], 0x3f); 3010 3011 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++) 3012 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3))); 3013 3014 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5))); 3015 } 3016 3017 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv) 3018 { 3019 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32; 3020 int result = 0; 3021 3022 /* path-A IQK setting */ 3023 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f); 3024 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f); 3025 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102); 3026 3027 val32 = (priv->rf_paths > 1) ? 0x28160202 : 3028 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */ 3029 0x28160502; 3030 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32); 3031 3032 /* path-B IQK setting */ 3033 if (priv->rf_paths > 1) { 3034 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22); 3035 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22); 3036 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102); 3037 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202); 3038 } 3039 3040 /* LO calibration setting */ 3041 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1); 3042 3043 /* One shot, path A LOK & IQK */ 3044 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 3045 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 3046 3047 mdelay(1); 3048 3049 /* Check failed */ 3050 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 3051 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 3052 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 3053 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); 3054 3055 if (!(reg_eac & BIT(28)) && 3056 ((reg_e94 & 0x03ff0000) != 0x01420000) && 3057 ((reg_e9c & 0x03ff0000) != 0x00420000)) 3058 result |= 0x01; 3059 else /* If TX not OK, ignore RX */ 3060 goto out; 3061 3062 /* If TX is OK, check whether RX is OK */ 3063 if (!(reg_eac & BIT(27)) && 3064 ((reg_ea4 & 0x03ff0000) != 0x01320000) && 3065 ((reg_eac & 0x03ff0000) != 0x00360000)) 3066 result |= 0x02; 3067 else 3068 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n", 3069 __func__); 3070 out: 3071 return result; 3072 } 3073 3074 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv) 3075 { 3076 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc; 3077 int result = 0; 3078 3079 /* One shot, path B LOK & IQK */ 3080 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002); 3081 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000); 3082 3083 mdelay(1); 3084 3085 /* Check failed */ 3086 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 3087 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 3088 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 3089 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); 3090 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); 3091 3092 if (!(reg_eac & BIT(31)) && 3093 ((reg_eb4 & 0x03ff0000) != 0x01420000) && 3094 ((reg_ebc & 0x03ff0000) != 0x00420000)) 3095 result |= 0x01; 3096 else 3097 goto out; 3098 3099 if (!(reg_eac & BIT(30)) && 3100 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) && 3101 (((reg_ecc & 0x03ff0000) >> 16) != 0x36)) 3102 result |= 0x02; 3103 else 3104 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", 3105 __func__); 3106 out: 3107 return result; 3108 } 3109 3110 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, 3111 int result[][8], int t) 3112 { 3113 struct device *dev = &priv->udev->dev; 3114 u32 i, val32; 3115 int path_a_ok, path_b_ok; 3116 int retry = 2; 3117 static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { 3118 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, 3119 REG_RX_WAIT_CCA, REG_TX_CCK_RFON, 3120 REG_TX_CCK_BBON, REG_TX_OFDM_RFON, 3121 REG_TX_OFDM_BBON, REG_TX_TO_RX, 3122 REG_TX_TO_TX, REG_RX_CCK, 3123 REG_RX_OFDM, REG_RX_WAIT_RIFS, 3124 REG_RX_TO_RX, REG_STANDBY, 3125 REG_SLEEP, REG_PMPD_ANAEN 3126 }; 3127 static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { 3128 REG_TXPAUSE, REG_BEACON_CTRL, 3129 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG 3130 }; 3131 static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { 3132 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, 3133 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, 3134 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, 3135 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE 3136 }; 3137 3138 /* 3139 * Note: IQ calibration must be performed after loading 3140 * PHY_REG.txt , and radio_a, radio_b.txt 3141 */ 3142 3143 if (t == 0) { 3144 /* Save ADDA parameters, turn Path A ADDA on */ 3145 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, 3146 RTL8XXXU_ADDA_REGS); 3147 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 3148 rtl8xxxu_save_regs(priv, iqk_bb_regs, 3149 priv->bb_backup, RTL8XXXU_BB_REGS); 3150 } 3151 3152 rtl8xxxu_path_adda_on(priv, adda_regs, true); 3153 3154 if (t == 0) { 3155 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); 3156 if (val32 & FPGA0_HSSI_PARM1_PI) 3157 priv->pi_enabled = 1; 3158 } 3159 3160 if (!priv->pi_enabled) { 3161 /* Switch BB to PI mode to do IQ Calibration. */ 3162 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); 3163 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100); 3164 } 3165 3166 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 3167 val32 &= ~FPGA_RF_MODE_CCK; 3168 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 3169 3170 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); 3171 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); 3172 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); 3173 3174 if (!priv->no_pape) { 3175 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); 3176 val32 |= (FPGA0_RF_PAPE | 3177 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); 3178 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); 3179 } 3180 3181 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); 3182 val32 &= ~BIT(10); 3183 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); 3184 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); 3185 val32 &= ~BIT(10); 3186 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); 3187 3188 if (priv->tx_paths > 1) { 3189 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); 3190 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000); 3191 } 3192 3193 /* MAC settings */ 3194 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); 3195 3196 /* Page B init */ 3197 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000); 3198 3199 if (priv->tx_paths > 1) 3200 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000); 3201 3202 /* IQ calibration setting */ 3203 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); 3204 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 3205 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 3206 3207 for (i = 0; i < retry; i++) { 3208 path_a_ok = rtl8xxxu_iqk_path_a(priv); 3209 if (path_a_ok == 0x03) { 3210 val32 = rtl8xxxu_read32(priv, 3211 REG_TX_POWER_BEFORE_IQK_A); 3212 result[t][0] = (val32 >> 16) & 0x3ff; 3213 val32 = rtl8xxxu_read32(priv, 3214 REG_TX_POWER_AFTER_IQK_A); 3215 result[t][1] = (val32 >> 16) & 0x3ff; 3216 val32 = rtl8xxxu_read32(priv, 3217 REG_RX_POWER_BEFORE_IQK_A_2); 3218 result[t][2] = (val32 >> 16) & 0x3ff; 3219 val32 = rtl8xxxu_read32(priv, 3220 REG_RX_POWER_AFTER_IQK_A_2); 3221 result[t][3] = (val32 >> 16) & 0x3ff; 3222 break; 3223 } else if (i == (retry - 1) && path_a_ok == 0x01) { 3224 /* TX IQK OK */ 3225 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n", 3226 __func__); 3227 3228 val32 = rtl8xxxu_read32(priv, 3229 REG_TX_POWER_BEFORE_IQK_A); 3230 result[t][0] = (val32 >> 16) & 0x3ff; 3231 val32 = rtl8xxxu_read32(priv, 3232 REG_TX_POWER_AFTER_IQK_A); 3233 result[t][1] = (val32 >> 16) & 0x3ff; 3234 } 3235 } 3236 3237 if (!path_a_ok) 3238 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__); 3239 3240 if (priv->tx_paths > 1) { 3241 /* 3242 * Path A into standby 3243 */ 3244 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0); 3245 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); 3246 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); 3247 3248 /* Turn Path B ADDA on */ 3249 rtl8xxxu_path_adda_on(priv, adda_regs, false); 3250 3251 for (i = 0; i < retry; i++) { 3252 path_b_ok = rtl8xxxu_iqk_path_b(priv); 3253 if (path_b_ok == 0x03) { 3254 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 3255 result[t][4] = (val32 >> 16) & 0x3ff; 3256 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 3257 result[t][5] = (val32 >> 16) & 0x3ff; 3258 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); 3259 result[t][6] = (val32 >> 16) & 0x3ff; 3260 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); 3261 result[t][7] = (val32 >> 16) & 0x3ff; 3262 break; 3263 } else if (i == (retry - 1) && path_b_ok == 0x01) { 3264 /* TX IQK OK */ 3265 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 3266 result[t][4] = (val32 >> 16) & 0x3ff; 3267 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 3268 result[t][5] = (val32 >> 16) & 0x3ff; 3269 } 3270 } 3271 3272 if (!path_b_ok) 3273 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__); 3274 } 3275 3276 /* Back to BB mode, load original value */ 3277 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0); 3278 3279 if (t) { 3280 if (!priv->pi_enabled) { 3281 /* 3282 * Switch back BB to SI mode after finishing 3283 * IQ Calibration 3284 */ 3285 val32 = 0x01000000; 3286 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32); 3287 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32); 3288 } 3289 3290 /* Reload ADDA power saving parameters */ 3291 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, 3292 RTL8XXXU_ADDA_REGS); 3293 3294 /* Reload MAC parameters */ 3295 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 3296 3297 /* Reload BB parameters */ 3298 rtl8xxxu_restore_regs(priv, iqk_bb_regs, 3299 priv->bb_backup, RTL8XXXU_BB_REGS); 3300 3301 /* Restore RX initial gain */ 3302 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3); 3303 3304 if (priv->tx_paths > 1) { 3305 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 3306 0x00032ed3); 3307 } 3308 3309 /* Load 0xe30 IQC default value */ 3310 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); 3311 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); 3312 } 3313 } 3314 3315 void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start) 3316 { 3317 struct h2c_cmd h2c; 3318 3319 memset(&h2c, 0, sizeof(struct h2c_cmd)); 3320 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION; 3321 h2c.bt_wlan_calibration.data = start; 3322 3323 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration)); 3324 } 3325 3326 void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv) 3327 { 3328 struct device *dev = &priv->udev->dev; 3329 int result[4][8]; /* last is final result */ 3330 int i, candidate; 3331 bool path_a_ok, path_b_ok; 3332 u32 reg_e94, reg_e9c, reg_ea4, reg_eac; 3333 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; 3334 s32 reg_tmp = 0; 3335 bool simu; 3336 3337 memset(result, 0, sizeof(result)); 3338 candidate = -1; 3339 3340 path_a_ok = false; 3341 path_b_ok = false; 3342 3343 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 3344 3345 for (i = 0; i < 3; i++) { 3346 rtl8xxxu_phy_iqcalibrate(priv, result, i); 3347 3348 if (i == 1) { 3349 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1); 3350 if (simu) { 3351 candidate = 0; 3352 break; 3353 } 3354 } 3355 3356 if (i == 2) { 3357 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2); 3358 if (simu) { 3359 candidate = 0; 3360 break; 3361 } 3362 3363 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2); 3364 if (simu) { 3365 candidate = 1; 3366 } else { 3367 for (i = 0; i < 8; i++) 3368 reg_tmp += result[3][i]; 3369 3370 if (reg_tmp) 3371 candidate = 3; 3372 else 3373 candidate = -1; 3374 } 3375 } 3376 } 3377 3378 for (i = 0; i < 4; i++) { 3379 reg_e94 = result[i][0]; 3380 reg_e9c = result[i][1]; 3381 reg_ea4 = result[i][2]; 3382 reg_eac = result[i][3]; 3383 reg_eb4 = result[i][4]; 3384 reg_ebc = result[i][5]; 3385 reg_ec4 = result[i][6]; 3386 reg_ecc = result[i][7]; 3387 } 3388 3389 if (candidate >= 0) { 3390 reg_e94 = result[candidate][0]; 3391 priv->rege94 = reg_e94; 3392 reg_e9c = result[candidate][1]; 3393 priv->rege9c = reg_e9c; 3394 reg_ea4 = result[candidate][2]; 3395 reg_eac = result[candidate][3]; 3396 reg_eb4 = result[candidate][4]; 3397 priv->regeb4 = reg_eb4; 3398 reg_ebc = result[candidate][5]; 3399 priv->regebc = reg_ebc; 3400 reg_ec4 = result[candidate][6]; 3401 reg_ecc = result[candidate][7]; 3402 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); 3403 dev_dbg(dev, 3404 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n", 3405 __func__, reg_e94, reg_e9c, 3406 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); 3407 path_a_ok = true; 3408 path_b_ok = true; 3409 } else { 3410 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; 3411 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; 3412 } 3413 3414 if (reg_e94 && candidate >= 0) 3415 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, 3416 candidate, (reg_ea4 == 0)); 3417 3418 if (priv->tx_paths > 1 && reg_eb4) 3419 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, 3420 candidate, (reg_ec4 == 0)); 3421 3422 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, 3423 priv->bb_recovery_backup, RTL8XXXU_BB_REGS); 3424 } 3425 3426 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv) 3427 { 3428 u32 val32; 3429 u32 rf_amode, rf_bmode = 0, lstf; 3430 3431 /* Check continuous TX and Packet TX */ 3432 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 3433 3434 if (lstf & OFDM_LSTF_MASK) { 3435 /* Disable all continuous TX */ 3436 val32 = lstf & ~OFDM_LSTF_MASK; 3437 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 3438 3439 /* Read original RF mode Path A */ 3440 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC); 3441 3442 /* Set RF mode to standby Path A */ 3443 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 3444 (rf_amode & 0x8ffff) | 0x10000); 3445 3446 /* Path-B */ 3447 if (priv->tx_paths > 1) { 3448 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B, 3449 RF6052_REG_AC); 3450 3451 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 3452 (rf_bmode & 0x8ffff) | 0x10000); 3453 } 3454 } else { 3455 /* Deal with Packet TX case */ 3456 /* block all queues */ 3457 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 3458 } 3459 3460 /* Start LC calibration */ 3461 if (priv->fops->has_s0s1) 3462 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0); 3463 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); 3464 val32 |= 0x08000; 3465 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); 3466 3467 msleep(100); 3468 3469 if (priv->fops->has_s0s1) 3470 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0); 3471 3472 /* Restore original parameters */ 3473 if (lstf & OFDM_LSTF_MASK) { 3474 /* Path-A */ 3475 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf); 3476 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode); 3477 3478 /* Path-B */ 3479 if (priv->tx_paths > 1) 3480 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 3481 rf_bmode); 3482 } else /* Deal with Packet TX case */ 3483 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); 3484 } 3485 3486 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv) 3487 { 3488 int i; 3489 u16 reg; 3490 3491 reg = REG_MACID; 3492 3493 for (i = 0; i < ETH_ALEN; i++) 3494 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]); 3495 3496 return 0; 3497 } 3498 3499 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid) 3500 { 3501 int i; 3502 u16 reg; 3503 3504 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid); 3505 3506 reg = REG_BSSID; 3507 3508 for (i = 0; i < ETH_ALEN; i++) 3509 rtl8xxxu_write8(priv, reg + i, bssid[i]); 3510 3511 return 0; 3512 } 3513 3514 static void 3515 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor) 3516 { 3517 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 }; 3518 u8 max_agg = 0xf; 3519 int i; 3520 3521 ampdu_factor = 1 << (ampdu_factor + 2); 3522 if (ampdu_factor > max_agg) 3523 ampdu_factor = max_agg; 3524 3525 for (i = 0; i < 4; i++) { 3526 if ((vals[i] & 0xf0) > (ampdu_factor << 4)) 3527 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4); 3528 3529 if ((vals[i] & 0x0f) > ampdu_factor) 3530 vals[i] = (vals[i] & 0xf0) | ampdu_factor; 3531 3532 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]); 3533 } 3534 } 3535 3536 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density) 3537 { 3538 u8 val8; 3539 3540 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE); 3541 val8 &= 0xf8; 3542 val8 |= density; 3543 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8); 3544 } 3545 3546 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv) 3547 { 3548 u8 val8; 3549 int count, ret = 0; 3550 3551 /* Start of rtl8723AU_card_enable_flow */ 3552 /* Act to Cardemu sequence*/ 3553 /* Turn off RF */ 3554 rtl8xxxu_write8(priv, REG_RF_CTRL, 0); 3555 3556 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */ 3557 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); 3558 val8 &= ~LEDCFG2_DPDT_SELECT; 3559 rtl8xxxu_write8(priv, REG_LEDCFG2, val8); 3560 3561 /* 0x0005[1] = 1 turn off MAC by HW state machine*/ 3562 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3563 val8 |= BIT(1); 3564 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3565 3566 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 3567 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3568 if ((val8 & BIT(1)) == 0) 3569 break; 3570 udelay(10); 3571 } 3572 3573 if (!count) { 3574 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", 3575 __func__); 3576 ret = -EBUSY; 3577 goto exit; 3578 } 3579 3580 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */ 3581 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); 3582 val8 |= SYS_ISO_ANALOG_IPS; 3583 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); 3584 3585 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/ 3586 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); 3587 val8 &= ~LDOA15_ENABLE; 3588 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); 3589 3590 exit: 3591 return ret; 3592 } 3593 3594 int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv) 3595 { 3596 u8 val8; 3597 u8 val32; 3598 int count, ret = 0; 3599 3600 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 3601 3602 /* 3603 * Poll - wait for RX packet to complete 3604 */ 3605 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 3606 val32 = rtl8xxxu_read32(priv, 0x5f8); 3607 if (!val32) 3608 break; 3609 udelay(10); 3610 } 3611 3612 if (!count) { 3613 dev_warn(&priv->udev->dev, 3614 "%s: RX poll timed out (0x05f8)\n", __func__); 3615 ret = -EBUSY; 3616 goto exit; 3617 } 3618 3619 /* Disable CCK and OFDM, clock gated */ 3620 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 3621 val8 &= ~SYS_FUNC_BBRSTB; 3622 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 3623 3624 udelay(2); 3625 3626 /* Reset baseband */ 3627 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 3628 val8 &= ~SYS_FUNC_BB_GLB_RSTN; 3629 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 3630 3631 /* Reset MAC TRX */ 3632 val8 = rtl8xxxu_read8(priv, REG_CR); 3633 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE; 3634 rtl8xxxu_write8(priv, REG_CR, val8); 3635 3636 /* Reset MAC TRX */ 3637 val8 = rtl8xxxu_read8(priv, REG_CR + 1); 3638 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */ 3639 rtl8xxxu_write8(priv, REG_CR + 1, val8); 3640 3641 /* Respond TX OK to scheduler */ 3642 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); 3643 val8 |= DUAL_TSF_TX_OK; 3644 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); 3645 3646 exit: 3647 return ret; 3648 } 3649 3650 void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv) 3651 { 3652 u8 val8; 3653 3654 /* Clear suspend enable and power down enable*/ 3655 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3656 val8 &= ~(BIT(3) | BIT(7)); 3657 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3658 3659 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ 3660 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); 3661 val8 &= ~BIT(0); 3662 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); 3663 3664 /* 0x04[12:11] = 11 enable WL suspend*/ 3665 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3666 val8 &= ~(BIT(3) | BIT(4)); 3667 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3668 } 3669 3670 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv) 3671 { 3672 u8 val8; 3673 3674 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */ 3675 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20); 3676 3677 /* 0x04[12:11] = 01 enable WL suspend */ 3678 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3679 val8 &= ~BIT(4); 3680 val8 |= BIT(3); 3681 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3682 3683 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3684 val8 |= BIT(7); 3685 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3686 3687 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */ 3688 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); 3689 val8 |= BIT(0); 3690 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); 3691 3692 return 0; 3693 } 3694 3695 int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv) 3696 { 3697 struct device *dev = &priv->udev->dev; 3698 u32 val32; 3699 int retry, retval; 3700 3701 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 3702 3703 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM); 3704 val32 |= RXPKT_NUM_RW_RELEASE_EN; 3705 rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32); 3706 3707 retry = 100; 3708 retval = -EBUSY; 3709 3710 do { 3711 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM); 3712 if (val32 & RXPKT_NUM_RXDMA_IDLE) { 3713 retval = 0; 3714 break; 3715 } 3716 } while (retry--); 3717 3718 rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0); 3719 rtl8xxxu_write32(priv, REG_RQPN, 0x80000000); 3720 mdelay(2); 3721 3722 if (!retry) 3723 dev_warn(dev, "Failed to flush FIFO\n"); 3724 3725 return retval; 3726 } 3727 3728 void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv) 3729 { 3730 /* Fix USB interface interference issue */ 3731 rtl8xxxu_write8(priv, 0xfe40, 0xe0); 3732 rtl8xxxu_write8(priv, 0xfe41, 0x8d); 3733 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3734 /* 3735 * This sets TXDMA_OFFSET_DROP_DATA_EN (bit 9) as well as bits 3736 * 8 and 5, for which I have found no documentation. 3737 */ 3738 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320); 3739 3740 /* 3741 * Solve too many protocol error on USB bus. 3742 * Can't do this for 8188/8192 UMC A cut parts 3743 */ 3744 if (!(!priv->chip_cut && priv->vendor_umc)) { 3745 rtl8xxxu_write8(priv, 0xfe40, 0xe6); 3746 rtl8xxxu_write8(priv, 0xfe41, 0x94); 3747 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3748 3749 rtl8xxxu_write8(priv, 0xfe40, 0xe0); 3750 rtl8xxxu_write8(priv, 0xfe41, 0x19); 3751 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3752 3753 rtl8xxxu_write8(priv, 0xfe40, 0xe5); 3754 rtl8xxxu_write8(priv, 0xfe41, 0x91); 3755 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3756 3757 rtl8xxxu_write8(priv, 0xfe40, 0xe2); 3758 rtl8xxxu_write8(priv, 0xfe41, 0x81); 3759 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3760 } 3761 } 3762 3763 void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv) 3764 { 3765 u32 val32; 3766 3767 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK); 3768 val32 |= TXDMA_OFFSET_DROP_DATA_EN; 3769 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32); 3770 } 3771 3772 void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv) 3773 { 3774 u8 val8; 3775 u16 val16; 3776 u32 val32; 3777 3778 /* 3779 * Workaround for 8188RU LNA power leakage problem. 3780 */ 3781 if (priv->rtl_chip == RTL8188R) { 3782 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM); 3783 val32 |= BIT(1); 3784 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32); 3785 } 3786 3787 rtl8xxxu_flush_fifo(priv); 3788 3789 rtl8xxxu_active_to_lps(priv); 3790 3791 /* Turn off RF */ 3792 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); 3793 3794 /* Reset Firmware if running in RAM */ 3795 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) 3796 rtl8xxxu_firmware_self_reset(priv); 3797 3798 /* Reset MCU */ 3799 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 3800 val16 &= ~SYS_FUNC_CPU_ENABLE; 3801 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 3802 3803 /* Reset MCU ready status */ 3804 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); 3805 3806 rtl8xxxu_active_to_emu(priv); 3807 rtl8xxxu_emu_to_disabled(priv); 3808 3809 /* Reset MCU IO Wrapper */ 3810 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 3811 val8 &= ~BIT(0); 3812 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 3813 3814 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 3815 val8 |= BIT(0); 3816 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 3817 3818 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */ 3819 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e); 3820 } 3821 3822 void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv, 3823 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5) 3824 { 3825 struct h2c_cmd h2c; 3826 3827 memset(&h2c, 0, sizeof(struct h2c_cmd)); 3828 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA; 3829 h2c.b_type_dma.data1 = arg1; 3830 h2c.b_type_dma.data2 = arg2; 3831 h2c.b_type_dma.data3 = arg3; 3832 h2c.b_type_dma.data4 = arg4; 3833 h2c.b_type_dma.data5 = arg5; 3834 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma)); 3835 } 3836 3837 void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv) 3838 { 3839 u32 val32; 3840 3841 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); 3842 val32 &= ~(BIT(22) | BIT(23)); 3843 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); 3844 } 3845 3846 static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv *priv) 3847 { 3848 struct rtl8xxxu_fileops *fops = priv->fops; 3849 u32 hq, lq, nq, eq, pubq; 3850 u32 val32; 3851 3852 hq = 0; 3853 lq = 0; 3854 nq = 0; 3855 eq = 0; 3856 pubq = 0; 3857 3858 if (priv->ep_tx_high_queue) 3859 hq = fops->page_num_hi; 3860 if (priv->ep_tx_low_queue) 3861 lq = fops->page_num_lo; 3862 if (priv->ep_tx_normal_queue) 3863 nq = fops->page_num_norm; 3864 3865 val32 = (nq << RQPN_NPQ_SHIFT) | (eq << RQPN_EPQ_SHIFT); 3866 rtl8xxxu_write32(priv, REG_RQPN_NPQ, val32); 3867 3868 pubq = fops->total_page_num - hq - lq - nq - 1; 3869 3870 val32 = RQPN_LOAD; 3871 val32 |= (hq << RQPN_HI_PQ_SHIFT); 3872 val32 |= (lq << RQPN_LO_PQ_SHIFT); 3873 val32 |= (pubq << RQPN_PUB_PQ_SHIFT); 3874 3875 rtl8xxxu_write32(priv, REG_RQPN, val32); 3876 } 3877 3878 static int rtl8xxxu_init_device(struct ieee80211_hw *hw) 3879 { 3880 struct rtl8xxxu_priv *priv = hw->priv; 3881 struct device *dev = &priv->udev->dev; 3882 struct rtl8xxxu_fileops *fops = priv->fops; 3883 bool macpower; 3884 int ret; 3885 u8 val8; 3886 u16 val16; 3887 u32 val32; 3888 3889 /* Check if MAC is already powered on */ 3890 val8 = rtl8xxxu_read8(priv, REG_CR); 3891 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR); 3892 3893 /* 3894 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not 3895 * initialized. First MAC returns 0xea, second MAC returns 0x00 3896 */ 3897 if (val8 == 0xea || !(val16 & SYS_CLK_MAC_CLK_ENABLE)) 3898 macpower = false; 3899 else 3900 macpower = true; 3901 3902 if (fops->needs_full_init) 3903 macpower = false; 3904 3905 ret = fops->power_on(priv); 3906 if (ret < 0) { 3907 dev_warn(dev, "%s: Failed power on\n", __func__); 3908 goto exit; 3909 } 3910 3911 if (!macpower) 3912 rtl8xxxu_init_queue_reserved_page(priv); 3913 3914 ret = rtl8xxxu_init_queue_priority(priv); 3915 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret); 3916 if (ret) 3917 goto exit; 3918 3919 /* 3920 * Set RX page boundary 3921 */ 3922 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, fops->trxff_boundary); 3923 3924 ret = rtl8xxxu_download_firmware(priv); 3925 dev_dbg(dev, "%s: download_firmware %i\n", __func__, ret); 3926 if (ret) 3927 goto exit; 3928 ret = rtl8xxxu_start_firmware(priv); 3929 dev_dbg(dev, "%s: start_firmware %i\n", __func__, ret); 3930 if (ret) 3931 goto exit; 3932 3933 if (fops->phy_init_antenna_selection) 3934 fops->phy_init_antenna_selection(priv); 3935 3936 ret = rtl8xxxu_init_mac(priv); 3937 3938 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret); 3939 if (ret) 3940 goto exit; 3941 3942 ret = rtl8xxxu_init_phy_bb(priv); 3943 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret); 3944 if (ret) 3945 goto exit; 3946 3947 ret = fops->init_phy_rf(priv); 3948 if (ret) 3949 goto exit; 3950 3951 /* RFSW Control - clear bit 14 ?? */ 3952 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E) 3953 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003); 3954 3955 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW | 3956 FPGA0_RF_ANTSWB | 3957 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB) << FPGA0_RF_BD_CTRL_SHIFT); 3958 if (!priv->no_pape) { 3959 val32 |= (FPGA0_RF_PAPE | 3960 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); 3961 } 3962 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); 3963 3964 /* 0x860[6:5]= 00 - why? - this sets antenna B */ 3965 if (priv->rtl_chip != RTL8192E) 3966 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210); 3967 3968 if (!macpower) { 3969 /* 3970 * Set TX buffer boundary 3971 */ 3972 val8 = fops->total_page_num + 1; 3973 3974 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8); 3975 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8); 3976 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8); 3977 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8); 3978 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8); 3979 } 3980 3981 /* 3982 * The vendor drivers set PBP for all devices, except 8192e. 3983 * There is no explanation for this in any of the sources. 3984 */ 3985 val8 = (fops->pbp_rx << PBP_PAGE_SIZE_RX_SHIFT) | 3986 (fops->pbp_tx << PBP_PAGE_SIZE_TX_SHIFT); 3987 if (priv->rtl_chip != RTL8192E) 3988 rtl8xxxu_write8(priv, REG_PBP, val8); 3989 3990 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower); 3991 if (!macpower) { 3992 ret = fops->llt_init(priv); 3993 if (ret) { 3994 dev_warn(dev, "%s: LLT table init failed\n", __func__); 3995 goto exit; 3996 } 3997 3998 /* 3999 * Chip specific quirks 4000 */ 4001 fops->usb_quirks(priv); 4002 4003 /* 4004 * Enable TX report and TX report timer for 8723bu/8188eu/... 4005 */ 4006 if (fops->has_tx_report) { 4007 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); 4008 val8 |= TX_REPORT_CTRL_TIMER_ENABLE; 4009 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); 4010 /* Set MAX RPT MACID */ 4011 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02); 4012 /* TX report Timer. Unit: 32us */ 4013 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0); 4014 4015 /* tmp ps ? */ 4016 val8 = rtl8xxxu_read8(priv, 0xa3); 4017 val8 &= 0xf8; 4018 rtl8xxxu_write8(priv, 0xa3, val8); 4019 } 4020 } 4021 4022 /* 4023 * Unit in 8 bytes, not obvious what it is used for 4024 */ 4025 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4); 4026 4027 if (priv->rtl_chip == RTL8192E) { 4028 rtl8xxxu_write32(priv, REG_HIMR0, 0x00); 4029 rtl8xxxu_write32(priv, REG_HIMR1, 0x00); 4030 } else { 4031 /* 4032 * Enable all interrupts - not obvious USB needs to do this 4033 */ 4034 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff); 4035 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff); 4036 } 4037 4038 rtl8xxxu_set_mac(priv); 4039 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION); 4040 4041 /* 4042 * Configure initial WMAC settings 4043 */ 4044 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST | 4045 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL | 4046 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC; 4047 rtl8xxxu_write32(priv, REG_RCR, val32); 4048 4049 /* 4050 * Accept all multicast 4051 */ 4052 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff); 4053 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff); 4054 4055 /* 4056 * Init adaptive controls 4057 */ 4058 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 4059 val32 &= ~RESPONSE_RATE_BITMAP_ALL; 4060 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M; 4061 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 4062 4063 /* CCK = 0x0a, OFDM = 0x10 */ 4064 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10); 4065 rtl8xxxu_set_retry(priv, 0x30, 0x30); 4066 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10); 4067 4068 /* 4069 * Init EDCA 4070 */ 4071 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a); 4072 4073 /* Set CCK SIFS */ 4074 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a); 4075 4076 /* Set OFDM SIFS */ 4077 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a); 4078 4079 /* TXOP */ 4080 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b); 4081 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f); 4082 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324); 4083 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226); 4084 4085 /* Set data auto rate fallback retry count */ 4086 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000); 4087 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404); 4088 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201); 4089 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605); 4090 4091 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL); 4092 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY; 4093 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8); 4094 4095 /* Set ACK timeout */ 4096 rtl8xxxu_write8(priv, REG_ACKTO, 0x40); 4097 4098 /* 4099 * Initialize beacon parameters 4100 */ 4101 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8); 4102 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16); 4103 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404); 4104 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME); 4105 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME); 4106 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F); 4107 4108 /* 4109 * Initialize burst parameters 4110 */ 4111 if (priv->rtl_chip == RTL8723B) { 4112 /* 4113 * For USB high speed set 512B packets 4114 */ 4115 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B); 4116 val8 &= ~(BIT(4) | BIT(5)); 4117 val8 |= BIT(4); 4118 val8 |= BIT(1) | BIT(2) | BIT(3); 4119 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8); 4120 4121 /* 4122 * For USB high speed set 512B packets 4123 */ 4124 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B); 4125 val8 |= BIT(7); 4126 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8); 4127 4128 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14); 4129 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 0x5e); 4130 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff); 4131 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18); 4132 rtl8xxxu_write8(priv, REG_PIFS, 0x00); 4133 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, 0x50); 4134 rtl8xxxu_write8(priv, REG_USTIME_EDCA, 0x50); 4135 4136 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); 4137 val8 |= BIT(5) | BIT(6); 4138 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); 4139 } 4140 4141 if (fops->init_aggregation) 4142 fops->init_aggregation(priv); 4143 4144 /* 4145 * Enable CCK and OFDM block 4146 */ 4147 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 4148 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM); 4149 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 4150 4151 /* 4152 * Invalidate all CAM entries - bit 30 is undocumented 4153 */ 4154 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30)); 4155 4156 /* 4157 * Start out with default power levels for channel 6, 20MHz 4158 */ 4159 fops->set_tx_power(priv, 1, false); 4160 4161 /* Let the 8051 take control of antenna setting */ 4162 if (priv->rtl_chip != RTL8192E) { 4163 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); 4164 val8 |= LEDCFG2_DPDT_SELECT; 4165 rtl8xxxu_write8(priv, REG_LEDCFG2, val8); 4166 } 4167 4168 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff); 4169 4170 /* Disable BAR - not sure if this has any effect on USB */ 4171 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff); 4172 4173 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0); 4174 4175 if (fops->init_statistics) 4176 fops->init_statistics(priv); 4177 4178 if (priv->rtl_chip == RTL8192E) { 4179 /* 4180 * 0x4c6[3] 1: RTS BW = Data BW 4181 * 0: RTS BW depends on CCA / secondary CCA result. 4182 */ 4183 val8 = rtl8xxxu_read8(priv, REG_QUEUE_CTRL); 4184 val8 &= ~BIT(3); 4185 rtl8xxxu_write8(priv, REG_QUEUE_CTRL, val8); 4186 /* 4187 * Reset USB mode switch setting 4188 */ 4189 rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00); 4190 } 4191 4192 rtl8723a_phy_lc_calibrate(priv); 4193 4194 fops->phy_iq_calibrate(priv); 4195 4196 /* 4197 * This should enable thermal meter 4198 */ 4199 if (fops->gen2_thermal_meter) 4200 rtl8xxxu_write_rfreg(priv, 4201 RF_A, RF6052_REG_T_METER_8723B, 0x37cf8); 4202 else 4203 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60); 4204 4205 /* Set NAV_UPPER to 30000us */ 4206 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT); 4207 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8); 4208 4209 if (priv->rtl_chip == RTL8723A) { 4210 /* 4211 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test, 4212 * but we need to find root cause. 4213 * This is 8723au only. 4214 */ 4215 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 4216 if ((val32 & 0xff000000) != 0x83000000) { 4217 val32 |= FPGA_RF_MODE_CCK; 4218 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 4219 } 4220 } else if (priv->rtl_chip == RTL8192E) { 4221 rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00); 4222 } 4223 4224 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL); 4225 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK; 4226 /* ack for xmit mgmt frames. */ 4227 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32); 4228 4229 if (priv->rtl_chip == RTL8192E) { 4230 /* 4231 * Fix LDPC rx hang issue. 4232 */ 4233 val32 = rtl8xxxu_read32(priv, REG_AFE_MISC); 4234 rtl8xxxu_write8(priv, REG_8192E_LDOV12_CTRL, 0x75); 4235 val32 &= 0xfff00fff; 4236 val32 |= 0x0007e000; 4237 rtl8xxxu_write32(priv, REG_AFE_MISC, val32); 4238 } 4239 exit: 4240 return ret; 4241 } 4242 4243 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv, 4244 struct ieee80211_key_conf *key, const u8 *mac) 4245 { 4246 u32 cmd, val32, addr, ctrl; 4247 int j, i, tmp_debug; 4248 4249 tmp_debug = rtl8xxxu_debug; 4250 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY) 4251 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE; 4252 4253 /* 4254 * This is a bit of a hack - the lower bits of the cipher 4255 * suite selector happens to match the cipher index in the CAM 4256 */ 4257 addr = key->keyidx << CAM_CMD_KEY_SHIFT; 4258 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID; 4259 4260 for (j = 5; j >= 0; j--) { 4261 switch (j) { 4262 case 0: 4263 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24); 4264 break; 4265 case 1: 4266 val32 = mac[2] | (mac[3] << 8) | 4267 (mac[4] << 16) | (mac[5] << 24); 4268 break; 4269 default: 4270 i = (j - 2) << 2; 4271 val32 = key->key[i] | (key->key[i + 1] << 8) | 4272 key->key[i + 2] << 16 | key->key[i + 3] << 24; 4273 break; 4274 } 4275 4276 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32); 4277 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j); 4278 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd); 4279 udelay(100); 4280 } 4281 4282 rtl8xxxu_debug = tmp_debug; 4283 } 4284 4285 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw, 4286 struct ieee80211_vif *vif, const u8 *mac) 4287 { 4288 struct rtl8xxxu_priv *priv = hw->priv; 4289 u8 val8; 4290 4291 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 4292 val8 |= BEACON_DISABLE_TSF_UPDATE; 4293 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 4294 } 4295 4296 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw, 4297 struct ieee80211_vif *vif) 4298 { 4299 struct rtl8xxxu_priv *priv = hw->priv; 4300 u8 val8; 4301 4302 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 4303 val8 &= ~BEACON_DISABLE_TSF_UPDATE; 4304 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 4305 } 4306 4307 void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv, 4308 u32 ramask, u8 rateid, int sgi) 4309 { 4310 struct h2c_cmd h2c; 4311 4312 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4313 4314 h2c.ramask.cmd = H2C_SET_RATE_MASK; 4315 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff); 4316 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16); 4317 4318 h2c.ramask.arg = 0x80; 4319 if (sgi) 4320 h2c.ramask.arg |= 0x20; 4321 4322 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n", 4323 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask)); 4324 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.ramask)); 4325 } 4326 4327 void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv, 4328 u32 ramask, u8 rateid, int sgi) 4329 { 4330 struct h2c_cmd h2c; 4331 u8 bw = RTL8XXXU_CHANNEL_WIDTH_20; 4332 4333 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4334 4335 h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID; 4336 h2c.b_macid_cfg.ramask0 = ramask & 0xff; 4337 h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff; 4338 h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff; 4339 h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff; 4340 4341 h2c.ramask.arg = 0x80; 4342 h2c.b_macid_cfg.data1 = rateid; 4343 if (sgi) 4344 h2c.b_macid_cfg.data1 |= BIT(7); 4345 4346 h2c.b_macid_cfg.data2 = bw; 4347 4348 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n", 4349 __func__, ramask, h2c.ramask.arg, sizeof(h2c.b_macid_cfg)); 4350 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg)); 4351 } 4352 4353 void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv, 4354 u8 macid, bool connect) 4355 { 4356 struct h2c_cmd h2c; 4357 4358 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4359 4360 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT; 4361 4362 if (connect) 4363 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT; 4364 else 4365 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT; 4366 4367 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss)); 4368 } 4369 4370 void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv, 4371 u8 macid, bool connect) 4372 { 4373 #ifdef RTL8XXXU_GEN2_REPORT_CONNECT 4374 /* 4375 * Barry Day reports this causes issues with 8192eu and 8723bu 4376 * devices reconnecting. The reason for this is unclear, but 4377 * until it is better understood, leave the code in place but 4378 * disabled, so it is not lost. 4379 */ 4380 struct h2c_cmd h2c; 4381 4382 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4383 4384 h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT; 4385 if (connect) 4386 h2c.media_status_rpt.parm |= BIT(0); 4387 else 4388 h2c.media_status_rpt.parm &= ~BIT(0); 4389 4390 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt)); 4391 #endif 4392 } 4393 4394 void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv) 4395 { 4396 u8 agg_ctrl, usb_spec, page_thresh, timeout; 4397 4398 usb_spec = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION); 4399 usb_spec &= ~USB_SPEC_USB_AGG_ENABLE; 4400 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, usb_spec); 4401 4402 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); 4403 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; 4404 4405 if (!rtl8xxxu_dma_aggregation) { 4406 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); 4407 return; 4408 } 4409 4410 agg_ctrl |= TRXDMA_CTRL_RXDMA_AGG_EN; 4411 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); 4412 4413 /* 4414 * The number of packets we can take looks to be buffer size / 512 4415 * which matches the 512 byte rounding we have to do when de-muxing 4416 * the packets. 4417 * 4418 * Sample numbers from the vendor driver: 4419 * USB High-Speed mode values: 4420 * RxAggBlockCount = 8 : 512 byte unit 4421 * RxAggBlockTimeout = 6 4422 * RxAggPageCount = 48 : 128 byte unit 4423 * RxAggPageTimeout = 4 or 6 (absolute time 34ms/(2^6)) 4424 */ 4425 4426 page_thresh = (priv->fops->rx_agg_buf_size / 512); 4427 if (rtl8xxxu_dma_agg_pages >= 0) { 4428 if (rtl8xxxu_dma_agg_pages <= page_thresh) 4429 timeout = page_thresh; 4430 else if (rtl8xxxu_dma_agg_pages <= 6) 4431 dev_err(&priv->udev->dev, 4432 "%s: dma_agg_pages=%i too small, minimum is 6\n", 4433 __func__, rtl8xxxu_dma_agg_pages); 4434 else 4435 dev_err(&priv->udev->dev, 4436 "%s: dma_agg_pages=%i larger than limit %i\n", 4437 __func__, rtl8xxxu_dma_agg_pages, page_thresh); 4438 } 4439 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH, page_thresh); 4440 /* 4441 * REG_RXDMA_AGG_PG_TH + 1 seems to be the timeout register on 4442 * gen2 chips and rtl8188eu. The rtl8723au seems unhappy if we 4443 * don't set it, so better set both. 4444 */ 4445 timeout = 4; 4446 4447 if (rtl8xxxu_dma_agg_timeout >= 0) { 4448 if (rtl8xxxu_dma_agg_timeout <= 127) 4449 timeout = rtl8xxxu_dma_agg_timeout; 4450 else 4451 dev_err(&priv->udev->dev, 4452 "%s: Invalid dma_agg_timeout: %i\n", 4453 __func__, rtl8xxxu_dma_agg_timeout); 4454 } 4455 4456 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH + 1, timeout); 4457 rtl8xxxu_write8(priv, REG_USB_DMA_AGG_TO, timeout); 4458 priv->rx_buf_aggregation = 1; 4459 } 4460 4461 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg) 4462 { 4463 u32 val32; 4464 u8 rate_idx = 0; 4465 4466 rate_cfg &= RESPONSE_RATE_BITMAP_ALL; 4467 4468 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 4469 val32 &= ~RESPONSE_RATE_BITMAP_ALL; 4470 val32 |= rate_cfg; 4471 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 4472 4473 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg); 4474 4475 while (rate_cfg) { 4476 rate_cfg = (rate_cfg >> 1); 4477 rate_idx++; 4478 } 4479 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx); 4480 } 4481 4482 static u16 4483 rtl8xxxu_wireless_mode(struct ieee80211_hw *hw, struct ieee80211_sta *sta) 4484 { 4485 u16 network_type = WIRELESS_MODE_UNKNOWN; 4486 4487 if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ) { 4488 if (sta->vht_cap.vht_supported) 4489 network_type = WIRELESS_MODE_AC; 4490 else if (sta->ht_cap.ht_supported) 4491 network_type = WIRELESS_MODE_N_5G; 4492 4493 network_type |= WIRELESS_MODE_A; 4494 } else { 4495 if (sta->vht_cap.vht_supported) 4496 network_type = WIRELESS_MODE_AC; 4497 else if (sta->ht_cap.ht_supported) 4498 network_type = WIRELESS_MODE_N_24G; 4499 4500 if (sta->supp_rates[0] <= 0xf) 4501 network_type |= WIRELESS_MODE_B; 4502 else if (sta->supp_rates[0] & 0xf) 4503 network_type |= (WIRELESS_MODE_B | WIRELESS_MODE_G); 4504 else 4505 network_type |= WIRELESS_MODE_G; 4506 } 4507 4508 return network_type; 4509 } 4510 4511 static void 4512 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 4513 struct ieee80211_bss_conf *bss_conf, u32 changed) 4514 { 4515 struct rtl8xxxu_priv *priv = hw->priv; 4516 struct device *dev = &priv->udev->dev; 4517 struct ieee80211_sta *sta; 4518 u32 val32; 4519 u8 val8; 4520 4521 if (changed & BSS_CHANGED_ASSOC) { 4522 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc); 4523 4524 rtl8xxxu_set_linktype(priv, vif->type); 4525 4526 if (bss_conf->assoc) { 4527 u32 ramask; 4528 int sgi = 0; 4529 4530 rcu_read_lock(); 4531 sta = ieee80211_find_sta(vif, bss_conf->bssid); 4532 if (!sta) { 4533 dev_info(dev, "%s: ASSOC no sta found\n", 4534 __func__); 4535 rcu_read_unlock(); 4536 goto error; 4537 } 4538 4539 if (sta->ht_cap.ht_supported) 4540 dev_info(dev, "%s: HT supported\n", __func__); 4541 if (sta->vht_cap.vht_supported) 4542 dev_info(dev, "%s: VHT supported\n", __func__); 4543 4544 /* TODO: Set bits 28-31 for rate adaptive id */ 4545 ramask = (sta->supp_rates[0] & 0xfff) | 4546 sta->ht_cap.mcs.rx_mask[0] << 12 | 4547 sta->ht_cap.mcs.rx_mask[1] << 20; 4548 if (sta->ht_cap.cap & 4549 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)) 4550 sgi = 1; 4551 rcu_read_unlock(); 4552 4553 priv->vif = vif; 4554 priv->rssi_level = RTL8XXXU_RATR_STA_INIT; 4555 4556 priv->fops->update_rate_mask(priv, ramask, 0, sgi); 4557 4558 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff); 4559 4560 rtl8xxxu_stop_tx_beacon(priv); 4561 4562 /* joinbss sequence */ 4563 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT, 4564 0xc000 | bss_conf->aid); 4565 4566 priv->fops->report_connect(priv, 0, true); 4567 } else { 4568 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 4569 val8 |= BEACON_DISABLE_TSF_UPDATE; 4570 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 4571 4572 priv->fops->report_connect(priv, 0, false); 4573 } 4574 } 4575 4576 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 4577 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n", 4578 bss_conf->use_short_preamble); 4579 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 4580 if (bss_conf->use_short_preamble) 4581 val32 |= RSR_ACK_SHORT_PREAMBLE; 4582 else 4583 val32 &= ~RSR_ACK_SHORT_PREAMBLE; 4584 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 4585 } 4586 4587 if (changed & BSS_CHANGED_ERP_SLOT) { 4588 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n", 4589 bss_conf->use_short_slot); 4590 4591 if (bss_conf->use_short_slot) 4592 val8 = 9; 4593 else 4594 val8 = 20; 4595 rtl8xxxu_write8(priv, REG_SLOT, val8); 4596 } 4597 4598 if (changed & BSS_CHANGED_BSSID) { 4599 dev_dbg(dev, "Changed BSSID!\n"); 4600 rtl8xxxu_set_bssid(priv, bss_conf->bssid); 4601 } 4602 4603 if (changed & BSS_CHANGED_BASIC_RATES) { 4604 dev_dbg(dev, "Changed BASIC_RATES!\n"); 4605 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates); 4606 } 4607 error: 4608 return; 4609 } 4610 4611 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue) 4612 { 4613 u32 rtlqueue; 4614 4615 switch (queue) { 4616 case IEEE80211_AC_VO: 4617 rtlqueue = TXDESC_QUEUE_VO; 4618 break; 4619 case IEEE80211_AC_VI: 4620 rtlqueue = TXDESC_QUEUE_VI; 4621 break; 4622 case IEEE80211_AC_BE: 4623 rtlqueue = TXDESC_QUEUE_BE; 4624 break; 4625 case IEEE80211_AC_BK: 4626 rtlqueue = TXDESC_QUEUE_BK; 4627 break; 4628 default: 4629 rtlqueue = TXDESC_QUEUE_BE; 4630 } 4631 4632 return rtlqueue; 4633 } 4634 4635 static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb) 4636 { 4637 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 4638 u32 queue; 4639 4640 if (ieee80211_is_mgmt(hdr->frame_control)) 4641 queue = TXDESC_QUEUE_MGNT; 4642 else 4643 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb)); 4644 4645 return queue; 4646 } 4647 4648 /* 4649 * Despite newer chips 8723b/8812/8821 having a larger TX descriptor 4650 * format. The descriptor checksum is still only calculated over the 4651 * initial 32 bytes of the descriptor! 4652 */ 4653 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc) 4654 { 4655 __le16 *ptr = (__le16 *)tx_desc; 4656 u16 csum = 0; 4657 int i; 4658 4659 /* 4660 * Clear csum field before calculation, as the csum field is 4661 * in the middle of the struct. 4662 */ 4663 tx_desc->csum = cpu_to_le16(0); 4664 4665 for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++) 4666 csum = csum ^ le16_to_cpu(ptr[i]); 4667 4668 tx_desc->csum |= cpu_to_le16(csum); 4669 } 4670 4671 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv) 4672 { 4673 struct rtl8xxxu_tx_urb *tx_urb, *tmp; 4674 unsigned long flags; 4675 4676 spin_lock_irqsave(&priv->tx_urb_lock, flags); 4677 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) { 4678 list_del(&tx_urb->list); 4679 priv->tx_urb_free_count--; 4680 usb_free_urb(&tx_urb->urb); 4681 } 4682 spin_unlock_irqrestore(&priv->tx_urb_lock, flags); 4683 } 4684 4685 static struct rtl8xxxu_tx_urb * 4686 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv) 4687 { 4688 struct rtl8xxxu_tx_urb *tx_urb; 4689 unsigned long flags; 4690 4691 spin_lock_irqsave(&priv->tx_urb_lock, flags); 4692 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list, 4693 struct rtl8xxxu_tx_urb, list); 4694 if (tx_urb) { 4695 list_del(&tx_urb->list); 4696 priv->tx_urb_free_count--; 4697 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER && 4698 !priv->tx_stopped) { 4699 priv->tx_stopped = true; 4700 ieee80211_stop_queues(priv->hw); 4701 } 4702 } 4703 4704 spin_unlock_irqrestore(&priv->tx_urb_lock, flags); 4705 4706 return tx_urb; 4707 } 4708 4709 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv, 4710 struct rtl8xxxu_tx_urb *tx_urb) 4711 { 4712 unsigned long flags; 4713 4714 INIT_LIST_HEAD(&tx_urb->list); 4715 4716 spin_lock_irqsave(&priv->tx_urb_lock, flags); 4717 4718 list_add(&tx_urb->list, &priv->tx_urb_free_list); 4719 priv->tx_urb_free_count++; 4720 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER && 4721 priv->tx_stopped) { 4722 priv->tx_stopped = false; 4723 ieee80211_wake_queues(priv->hw); 4724 } 4725 4726 spin_unlock_irqrestore(&priv->tx_urb_lock, flags); 4727 } 4728 4729 static void rtl8xxxu_tx_complete(struct urb *urb) 4730 { 4731 struct sk_buff *skb = (struct sk_buff *)urb->context; 4732 struct ieee80211_tx_info *tx_info; 4733 struct ieee80211_hw *hw; 4734 struct rtl8xxxu_priv *priv; 4735 struct rtl8xxxu_tx_urb *tx_urb = 4736 container_of(urb, struct rtl8xxxu_tx_urb, urb); 4737 4738 tx_info = IEEE80211_SKB_CB(skb); 4739 hw = tx_info->rate_driver_data[0]; 4740 priv = hw->priv; 4741 4742 skb_pull(skb, priv->fops->tx_desc_size); 4743 4744 ieee80211_tx_info_clear_status(tx_info); 4745 tx_info->status.rates[0].idx = -1; 4746 tx_info->status.rates[0].count = 0; 4747 4748 if (!urb->status) 4749 tx_info->flags |= IEEE80211_TX_STAT_ACK; 4750 4751 ieee80211_tx_status_irqsafe(hw, skb); 4752 4753 rtl8xxxu_free_tx_urb(priv, tx_urb); 4754 } 4755 4756 static void rtl8xxxu_dump_action(struct device *dev, 4757 struct ieee80211_hdr *hdr) 4758 { 4759 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr; 4760 u16 cap, timeout; 4761 4762 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION)) 4763 return; 4764 4765 switch (mgmt->u.action.u.addba_resp.action_code) { 4766 case WLAN_ACTION_ADDBA_RESP: 4767 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab); 4768 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout); 4769 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: " 4770 "timeout %i, tid %02x, buf_size %02x, policy %02x, " 4771 "status %02x\n", 4772 timeout, 4773 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2, 4774 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6, 4775 (cap >> 1) & 0x1, 4776 le16_to_cpu(mgmt->u.action.u.addba_resp.status)); 4777 break; 4778 case WLAN_ACTION_ADDBA_REQ: 4779 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab); 4780 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout); 4781 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: " 4782 "timeout %i, tid %02x, buf_size %02x, policy %02x\n", 4783 timeout, 4784 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2, 4785 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6, 4786 (cap >> 1) & 0x1); 4787 break; 4788 default: 4789 dev_info(dev, "action frame %02x\n", 4790 mgmt->u.action.u.addba_resp.action_code); 4791 break; 4792 } 4793 } 4794 4795 /* 4796 * Fill in v1 (gen1) specific TX descriptor bits. 4797 * This format is used on 8188cu/8192cu/8723au 4798 */ 4799 void 4800 rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 4801 struct ieee80211_tx_info *tx_info, 4802 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 4803 bool short_preamble, bool ampdu_enable, u32 rts_rate) 4804 { 4805 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info); 4806 struct rtl8xxxu_priv *priv = hw->priv; 4807 struct device *dev = &priv->udev->dev; 4808 u32 rate; 4809 u16 rate_flags = tx_info->control.rates[0].flags; 4810 u16 seq_number; 4811 4812 if (rate_flags & IEEE80211_TX_RC_MCS && 4813 !ieee80211_is_mgmt(hdr->frame_control)) 4814 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0; 4815 else 4816 rate = tx_rate->hw_value; 4817 4818 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) 4819 dev_info(dev, "%s: TX rate: %d, pkt size %u\n", 4820 __func__, rate, le16_to_cpu(tx_desc->pkt_size)); 4821 4822 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 4823 4824 tx_desc->txdw5 = cpu_to_le32(rate); 4825 4826 if (ieee80211_is_data(hdr->frame_control)) 4827 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00); 4828 4829 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT); 4830 4831 if (ampdu_enable) 4832 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE); 4833 else 4834 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK); 4835 4836 if (ieee80211_is_mgmt(hdr->frame_control)) { 4837 tx_desc->txdw5 = cpu_to_le32(rate); 4838 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE); 4839 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT); 4840 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE); 4841 } 4842 4843 if (ieee80211_is_data_qos(hdr->frame_control)) 4844 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS); 4845 4846 if (short_preamble) 4847 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE); 4848 4849 if (sgi) 4850 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI); 4851 4852 /* 4853 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled 4854 */ 4855 tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT); 4856 if (rate_flags & IEEE80211_TX_RC_USE_RTS_CTS) { 4857 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE); 4858 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); 4859 } else if (rate_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 4860 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE); 4861 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); 4862 } 4863 } 4864 4865 /* 4866 * Fill in v2 (gen2) specific TX descriptor bits. 4867 * This format is used on 8192eu/8723bu 4868 */ 4869 void 4870 rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 4871 struct ieee80211_tx_info *tx_info, 4872 struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi, 4873 bool short_preamble, bool ampdu_enable, u32 rts_rate) 4874 { 4875 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info); 4876 struct rtl8xxxu_priv *priv = hw->priv; 4877 struct device *dev = &priv->udev->dev; 4878 struct rtl8xxxu_txdesc40 *tx_desc40; 4879 u32 rate; 4880 u16 rate_flags = tx_info->control.rates[0].flags; 4881 u16 seq_number; 4882 4883 tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc32; 4884 4885 if (rate_flags & IEEE80211_TX_RC_MCS && 4886 !ieee80211_is_mgmt(hdr->frame_control)) 4887 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0; 4888 else 4889 rate = tx_rate->hw_value; 4890 4891 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) 4892 dev_info(dev, "%s: TX rate: %d, pkt size %u\n", 4893 __func__, rate, le16_to_cpu(tx_desc40->pkt_size)); 4894 4895 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 4896 4897 tx_desc40->txdw4 = cpu_to_le32(rate); 4898 if (ieee80211_is_data(hdr->frame_control)) { 4899 tx_desc40->txdw4 |= cpu_to_le32(0x1f << 4900 TXDESC40_DATA_RATE_FB_SHIFT); 4901 } 4902 4903 tx_desc40->txdw9 = cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT); 4904 4905 if (ampdu_enable) 4906 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE); 4907 else 4908 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK); 4909 4910 if (ieee80211_is_mgmt(hdr->frame_control)) { 4911 tx_desc40->txdw4 = cpu_to_le32(rate); 4912 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_USE_DRIVER_RATE); 4913 tx_desc40->txdw4 |= 4914 cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT); 4915 tx_desc40->txdw4 |= cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE); 4916 } 4917 4918 if (short_preamble) 4919 tx_desc40->txdw5 |= cpu_to_le32(TXDESC40_SHORT_PREAMBLE); 4920 4921 tx_desc40->txdw4 |= cpu_to_le32(rts_rate << TXDESC40_RTS_RATE_SHIFT); 4922 /* 4923 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled 4924 */ 4925 if (rate_flags & IEEE80211_TX_RC_USE_RTS_CTS) { 4926 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE); 4927 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE); 4928 } else if (rate_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 4929 /* 4930 * For some reason the vendor driver doesn't set 4931 * TXDESC40_HW_RTS_ENABLE for CTS to SELF 4932 */ 4933 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_CTS_SELF_ENABLE); 4934 } 4935 } 4936 4937 static void rtl8xxxu_tx(struct ieee80211_hw *hw, 4938 struct ieee80211_tx_control *control, 4939 struct sk_buff *skb) 4940 { 4941 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 4942 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 4943 struct rtl8xxxu_priv *priv = hw->priv; 4944 struct rtl8xxxu_txdesc32 *tx_desc; 4945 struct rtl8xxxu_tx_urb *tx_urb; 4946 struct ieee80211_sta *sta = NULL; 4947 struct ieee80211_vif *vif = tx_info->control.vif; 4948 struct device *dev = &priv->udev->dev; 4949 u32 queue, rts_rate; 4950 u16 pktlen = skb->len; 4951 u16 rate_flag = tx_info->control.rates[0].flags; 4952 int tx_desc_size = priv->fops->tx_desc_size; 4953 int ret; 4954 bool ampdu_enable, sgi = false, short_preamble = false; 4955 4956 if (skb_headroom(skb) < tx_desc_size) { 4957 dev_warn(dev, 4958 "%s: Not enough headroom (%i) for tx descriptor\n", 4959 __func__, skb_headroom(skb)); 4960 goto error; 4961 } 4962 4963 if (unlikely(skb->len > (65535 - tx_desc_size))) { 4964 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n", 4965 __func__, skb->len); 4966 goto error; 4967 } 4968 4969 tx_urb = rtl8xxxu_alloc_tx_urb(priv); 4970 if (!tx_urb) { 4971 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__); 4972 goto error; 4973 } 4974 4975 if (ieee80211_is_action(hdr->frame_control)) 4976 rtl8xxxu_dump_action(dev, hdr); 4977 4978 tx_info->rate_driver_data[0] = hw; 4979 4980 if (control && control->sta) 4981 sta = control->sta; 4982 4983 tx_desc = skb_push(skb, tx_desc_size); 4984 4985 memset(tx_desc, 0, tx_desc_size); 4986 tx_desc->pkt_size = cpu_to_le16(pktlen); 4987 tx_desc->pkt_offset = tx_desc_size; 4988 4989 tx_desc->txdw0 = 4990 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT; 4991 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) || 4992 is_broadcast_ether_addr(ieee80211_get_DA(hdr))) 4993 tx_desc->txdw0 |= TXDESC_BROADMULTICAST; 4994 4995 queue = rtl8xxxu_queue_select(hw, skb); 4996 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT); 4997 4998 if (tx_info->control.hw_key) { 4999 switch (tx_info->control.hw_key->cipher) { 5000 case WLAN_CIPHER_SUITE_WEP40: 5001 case WLAN_CIPHER_SUITE_WEP104: 5002 case WLAN_CIPHER_SUITE_TKIP: 5003 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4); 5004 break; 5005 case WLAN_CIPHER_SUITE_CCMP: 5006 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES); 5007 break; 5008 default: 5009 break; 5010 } 5011 } 5012 5013 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */ 5014 ampdu_enable = false; 5015 if (ieee80211_is_data_qos(hdr->frame_control) && sta) { 5016 if (sta->ht_cap.ht_supported) { 5017 u32 ampdu, val32; 5018 5019 ampdu = (u32)sta->ht_cap.ampdu_density; 5020 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT; 5021 tx_desc->txdw2 |= cpu_to_le32(val32); 5022 5023 ampdu_enable = true; 5024 } 5025 } 5026 5027 if (rate_flag & IEEE80211_TX_RC_SHORT_GI || 5028 (ieee80211_is_data_qos(hdr->frame_control) && 5029 sta && sta->ht_cap.cap & 5030 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) 5031 sgi = true; 5032 5033 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE || 5034 (sta && vif && vif->bss_conf.use_short_preamble)) 5035 short_preamble = true; 5036 5037 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) 5038 rts_rate = ieee80211_get_rts_cts_rate(hw, tx_info)->hw_value; 5039 else if (rate_flag & IEEE80211_TX_RC_USE_CTS_PROTECT) 5040 rts_rate = ieee80211_get_rts_cts_rate(hw, tx_info)->hw_value; 5041 else 5042 rts_rate = 0; 5043 5044 5045 priv->fops->fill_txdesc(hw, hdr, tx_info, tx_desc, sgi, short_preamble, 5046 ampdu_enable, rts_rate); 5047 5048 rtl8xxxu_calc_tx_desc_csum(tx_desc); 5049 5050 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue], 5051 skb->data, skb->len, rtl8xxxu_tx_complete, skb); 5052 5053 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor); 5054 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC); 5055 if (ret) { 5056 usb_unanchor_urb(&tx_urb->urb); 5057 rtl8xxxu_free_tx_urb(priv, tx_urb); 5058 goto error; 5059 } 5060 return; 5061 error: 5062 dev_kfree_skb(skb); 5063 } 5064 5065 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv, 5066 struct ieee80211_rx_status *rx_status, 5067 struct rtl8723au_phy_stats *phy_stats, 5068 u32 rxmcs) 5069 { 5070 if (phy_stats->sgi_en) 5071 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 5072 5073 if (rxmcs < DESC_RATE_6M) { 5074 /* 5075 * Handle PHY stats for CCK rates 5076 */ 5077 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a; 5078 5079 switch (cck_agc_rpt & 0xc0) { 5080 case 0xc0: 5081 rx_status->signal = -46 - (cck_agc_rpt & 0x3e); 5082 break; 5083 case 0x80: 5084 rx_status->signal = -26 - (cck_agc_rpt & 0x3e); 5085 break; 5086 case 0x40: 5087 rx_status->signal = -12 - (cck_agc_rpt & 0x3e); 5088 break; 5089 case 0x00: 5090 rx_status->signal = 16 - (cck_agc_rpt & 0x3e); 5091 break; 5092 } 5093 } else { 5094 rx_status->signal = 5095 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110; 5096 } 5097 } 5098 5099 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv) 5100 { 5101 struct rtl8xxxu_rx_urb *rx_urb, *tmp; 5102 unsigned long flags; 5103 5104 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5105 5106 list_for_each_entry_safe(rx_urb, tmp, 5107 &priv->rx_urb_pending_list, list) { 5108 list_del(&rx_urb->list); 5109 priv->rx_urb_pending_count--; 5110 usb_free_urb(&rx_urb->urb); 5111 } 5112 5113 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5114 } 5115 5116 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv, 5117 struct rtl8xxxu_rx_urb *rx_urb) 5118 { 5119 struct sk_buff *skb; 5120 unsigned long flags; 5121 int pending = 0; 5122 5123 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5124 5125 if (!priv->shutdown) { 5126 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list); 5127 priv->rx_urb_pending_count++; 5128 pending = priv->rx_urb_pending_count; 5129 } else { 5130 skb = (struct sk_buff *)rx_urb->urb.context; 5131 dev_kfree_skb(skb); 5132 usb_free_urb(&rx_urb->urb); 5133 } 5134 5135 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5136 5137 if (pending > RTL8XXXU_RX_URB_PENDING_WATER) 5138 schedule_work(&priv->rx_urb_wq); 5139 } 5140 5141 static void rtl8xxxu_rx_urb_work(struct work_struct *work) 5142 { 5143 struct rtl8xxxu_priv *priv; 5144 struct rtl8xxxu_rx_urb *rx_urb, *tmp; 5145 struct list_head local; 5146 struct sk_buff *skb; 5147 unsigned long flags; 5148 int ret; 5149 5150 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq); 5151 INIT_LIST_HEAD(&local); 5152 5153 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5154 5155 list_splice_init(&priv->rx_urb_pending_list, &local); 5156 priv->rx_urb_pending_count = 0; 5157 5158 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5159 5160 list_for_each_entry_safe(rx_urb, tmp, &local, list) { 5161 list_del_init(&rx_urb->list); 5162 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb); 5163 /* 5164 * If out of memory or temporary error, put it back on the 5165 * queue and try again. Otherwise the device is dead/gone 5166 * and we should drop it. 5167 */ 5168 switch (ret) { 5169 case 0: 5170 break; 5171 case -ENOMEM: 5172 case -EAGAIN: 5173 rtl8xxxu_queue_rx_urb(priv, rx_urb); 5174 break; 5175 default: 5176 pr_info("failed to requeue urb %i\n", ret); 5177 skb = (struct sk_buff *)rx_urb->urb.context; 5178 dev_kfree_skb(skb); 5179 usb_free_urb(&rx_urb->urb); 5180 } 5181 } 5182 } 5183 5184 /* 5185 * The RTL8723BU/RTL8192EU vendor driver use coexistence table type 5186 * 0-7 to represent writing different combinations of register values 5187 * to REG_BT_COEX_TABLEs. It's for different kinds of coexistence use 5188 * cases which Realtek doesn't provide detail for these settings. Keep 5189 * this aligned with vendor driver for easier maintenance. 5190 */ 5191 static 5192 void rtl8723bu_set_coex_with_type(struct rtl8xxxu_priv *priv, u8 type) 5193 { 5194 switch (type) { 5195 case 0: 5196 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); 5197 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555); 5198 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5199 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5200 break; 5201 case 1: 5202 case 3: 5203 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); 5204 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a); 5205 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5206 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5207 break; 5208 case 2: 5209 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a); 5210 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a); 5211 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5212 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5213 break; 5214 case 4: 5215 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a); 5216 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaa5a5a); 5217 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5218 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5219 break; 5220 case 5: 5221 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a); 5222 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaa5a5a5a); 5223 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5224 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5225 break; 5226 case 6: 5227 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); 5228 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa); 5229 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5230 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5231 break; 5232 case 7: 5233 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0xaaaaaaaa); 5234 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa); 5235 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5236 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5237 break; 5238 default: 5239 break; 5240 } 5241 } 5242 5243 static 5244 void rtl8723bu_update_bt_link_info(struct rtl8xxxu_priv *priv, u8 bt_info) 5245 { 5246 struct rtl8xxxu_btcoex *btcoex = &priv->bt_coex; 5247 5248 if (bt_info & BT_INFO_8723B_1ANT_B_INQ_PAGE) 5249 btcoex->c2h_bt_inquiry = true; 5250 else 5251 btcoex->c2h_bt_inquiry = false; 5252 5253 if (!(bt_info & BT_INFO_8723B_1ANT_B_CONNECTION)) { 5254 btcoex->bt_status = BT_8723B_1ANT_STATUS_NON_CONNECTED_IDLE; 5255 btcoex->has_sco = false; 5256 btcoex->has_hid = false; 5257 btcoex->has_pan = false; 5258 btcoex->has_a2dp = false; 5259 } else { 5260 if ((bt_info & 0x1f) == BT_INFO_8723B_1ANT_B_CONNECTION) 5261 btcoex->bt_status = BT_8723B_1ANT_STATUS_CONNECTED_IDLE; 5262 else if ((bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) || 5263 (bt_info & BT_INFO_8723B_1ANT_B_SCO_BUSY)) 5264 btcoex->bt_status = BT_8723B_1ANT_STATUS_SCO_BUSY; 5265 else if (bt_info & BT_INFO_8723B_1ANT_B_ACL_BUSY) 5266 btcoex->bt_status = BT_8723B_1ANT_STATUS_ACL_BUSY; 5267 else 5268 btcoex->bt_status = BT_8723B_1ANT_STATUS_MAX; 5269 5270 if (bt_info & BT_INFO_8723B_1ANT_B_FTP) 5271 btcoex->has_pan = true; 5272 else 5273 btcoex->has_pan = false; 5274 5275 if (bt_info & BT_INFO_8723B_1ANT_B_A2DP) 5276 btcoex->has_a2dp = true; 5277 else 5278 btcoex->has_a2dp = false; 5279 5280 if (bt_info & BT_INFO_8723B_1ANT_B_HID) 5281 btcoex->has_hid = true; 5282 else 5283 btcoex->has_hid = false; 5284 5285 if (bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) 5286 btcoex->has_sco = true; 5287 else 5288 btcoex->has_sco = false; 5289 } 5290 5291 if (!btcoex->has_a2dp && !btcoex->has_sco && 5292 !btcoex->has_pan && btcoex->has_hid) 5293 btcoex->hid_only = true; 5294 else 5295 btcoex->hid_only = false; 5296 5297 if (!btcoex->has_sco && !btcoex->has_pan && 5298 !btcoex->has_hid && btcoex->has_a2dp) 5299 btcoex->has_a2dp = true; 5300 else 5301 btcoex->has_a2dp = false; 5302 5303 if (btcoex->bt_status == BT_8723B_1ANT_STATUS_SCO_BUSY || 5304 btcoex->bt_status == BT_8723B_1ANT_STATUS_ACL_BUSY) 5305 btcoex->bt_busy = true; 5306 else 5307 btcoex->bt_busy = false; 5308 } 5309 5310 static 5311 void rtl8723bu_handle_bt_inquiry(struct rtl8xxxu_priv *priv) 5312 { 5313 struct ieee80211_vif *vif; 5314 struct rtl8xxxu_btcoex *btcoex; 5315 bool wifi_connected; 5316 5317 vif = priv->vif; 5318 btcoex = &priv->bt_coex; 5319 wifi_connected = (vif && vif->bss_conf.assoc); 5320 5321 if (!wifi_connected) { 5322 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); 5323 rtl8723bu_set_coex_with_type(priv, 0); 5324 } else if (btcoex->has_sco || btcoex->has_hid || btcoex->has_a2dp) { 5325 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, 0x3, 0x11, 0x11); 5326 rtl8723bu_set_coex_with_type(priv, 4); 5327 } else if (btcoex->has_pan) { 5328 rtl8723bu_set_ps_tdma(priv, 0x61, 0x3f, 0x3, 0x11, 0x11); 5329 rtl8723bu_set_coex_with_type(priv, 4); 5330 } else { 5331 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); 5332 rtl8723bu_set_coex_with_type(priv, 7); 5333 } 5334 } 5335 5336 static 5337 void rtl8723bu_handle_bt_info(struct rtl8xxxu_priv *priv) 5338 { 5339 struct ieee80211_vif *vif; 5340 struct rtl8xxxu_btcoex *btcoex; 5341 bool wifi_connected; 5342 5343 vif = priv->vif; 5344 btcoex = &priv->bt_coex; 5345 wifi_connected = (vif && vif->bss_conf.assoc); 5346 5347 if (wifi_connected) { 5348 u32 val32 = 0; 5349 u32 high_prio_tx = 0, high_prio_rx = 0; 5350 5351 val32 = rtl8xxxu_read32(priv, 0x770); 5352 high_prio_tx = val32 & 0x0000ffff; 5353 high_prio_rx = (val32 & 0xffff0000) >> 16; 5354 5355 if (btcoex->bt_busy) { 5356 if (btcoex->hid_only) { 5357 rtl8723bu_set_ps_tdma(priv, 0x61, 0x20, 5358 0x3, 0x11, 0x11); 5359 rtl8723bu_set_coex_with_type(priv, 5); 5360 } else if (btcoex->a2dp_only) { 5361 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, 5362 0x3, 0x11, 0x11); 5363 rtl8723bu_set_coex_with_type(priv, 4); 5364 } else if ((btcoex->has_a2dp && btcoex->has_pan) || 5365 (btcoex->has_hid && btcoex->has_a2dp && 5366 btcoex->has_pan)) { 5367 rtl8723bu_set_ps_tdma(priv, 0x51, 0x21, 5368 0x3, 0x10, 0x10); 5369 rtl8723bu_set_coex_with_type(priv, 4); 5370 } else if (btcoex->has_hid && btcoex->has_a2dp) { 5371 rtl8723bu_set_ps_tdma(priv, 0x51, 0x21, 5372 0x3, 0x10, 0x10); 5373 rtl8723bu_set_coex_with_type(priv, 3); 5374 } else { 5375 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, 5376 0x3, 0x11, 0x11); 5377 rtl8723bu_set_coex_with_type(priv, 4); 5378 } 5379 } else { 5380 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); 5381 if (high_prio_tx + high_prio_rx <= 60) 5382 rtl8723bu_set_coex_with_type(priv, 2); 5383 else 5384 rtl8723bu_set_coex_with_type(priv, 7); 5385 } 5386 } else { 5387 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); 5388 rtl8723bu_set_coex_with_type(priv, 0); 5389 } 5390 } 5391 5392 static struct ieee80211_rate rtl8xxxu_legacy_ratetable[] = { 5393 {.bitrate = 10, .hw_value = 0x00,}, 5394 {.bitrate = 20, .hw_value = 0x01,}, 5395 {.bitrate = 55, .hw_value = 0x02,}, 5396 {.bitrate = 110, .hw_value = 0x03,}, 5397 {.bitrate = 60, .hw_value = 0x04,}, 5398 {.bitrate = 90, .hw_value = 0x05,}, 5399 {.bitrate = 120, .hw_value = 0x06,}, 5400 {.bitrate = 180, .hw_value = 0x07,}, 5401 {.bitrate = 240, .hw_value = 0x08,}, 5402 {.bitrate = 360, .hw_value = 0x09,}, 5403 {.bitrate = 480, .hw_value = 0x0a,}, 5404 {.bitrate = 540, .hw_value = 0x0b,}, 5405 }; 5406 5407 static void rtl8xxxu_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss) 5408 { 5409 if (rate <= DESC_RATE_54M) 5410 return; 5411 5412 if (rate >= DESC_RATE_MCS0 && rate <= DESC_RATE_MCS15) { 5413 if (rate < DESC_RATE_MCS8) 5414 *nss = 1; 5415 else 5416 *nss = 2; 5417 *mcs = rate - DESC_RATE_MCS0; 5418 } 5419 } 5420 5421 static void rtl8xxxu_c2hcmd_callback(struct work_struct *work) 5422 { 5423 struct rtl8xxxu_priv *priv; 5424 struct rtl8723bu_c2h *c2h; 5425 struct sk_buff *skb = NULL; 5426 unsigned long flags; 5427 u8 bt_info = 0; 5428 struct rtl8xxxu_btcoex *btcoex; 5429 struct rtl8xxxu_ra_report *rarpt; 5430 u8 rate, sgi, bw; 5431 u32 bit_rate; 5432 u8 mcs = 0, nss = 0; 5433 5434 priv = container_of(work, struct rtl8xxxu_priv, c2hcmd_work); 5435 btcoex = &priv->bt_coex; 5436 rarpt = &priv->ra_report; 5437 5438 if (priv->rf_paths > 1) 5439 goto out; 5440 5441 while (!skb_queue_empty(&priv->c2hcmd_queue)) { 5442 spin_lock_irqsave(&priv->c2hcmd_lock, flags); 5443 skb = __skb_dequeue(&priv->c2hcmd_queue); 5444 spin_unlock_irqrestore(&priv->c2hcmd_lock, flags); 5445 5446 c2h = (struct rtl8723bu_c2h *)skb->data; 5447 5448 switch (c2h->id) { 5449 case C2H_8723B_BT_INFO: 5450 bt_info = c2h->bt_info.bt_info; 5451 5452 rtl8723bu_update_bt_link_info(priv, bt_info); 5453 if (btcoex->c2h_bt_inquiry) { 5454 rtl8723bu_handle_bt_inquiry(priv); 5455 break; 5456 } 5457 rtl8723bu_handle_bt_info(priv); 5458 break; 5459 case C2H_8723B_RA_REPORT: 5460 rarpt->txrate.flags = 0; 5461 rate = c2h->ra_report.rate; 5462 sgi = c2h->ra_report.sgi; 5463 bw = c2h->ra_report.bw; 5464 5465 if (rate < DESC_RATE_MCS0) { 5466 rarpt->txrate.legacy = 5467 rtl8xxxu_legacy_ratetable[rate].bitrate; 5468 } else { 5469 rtl8xxxu_desc_to_mcsrate(rate, &mcs, &nss); 5470 rarpt->txrate.flags |= RATE_INFO_FLAGS_MCS; 5471 5472 rarpt->txrate.mcs = mcs; 5473 rarpt->txrate.nss = nss; 5474 5475 if (sgi) { 5476 rarpt->txrate.flags |= 5477 RATE_INFO_FLAGS_SHORT_GI; 5478 } 5479 5480 if (bw == RATE_INFO_BW_20) 5481 rarpt->txrate.bw |= RATE_INFO_BW_20; 5482 } 5483 bit_rate = cfg80211_calculate_bitrate(&rarpt->txrate); 5484 rarpt->bit_rate = bit_rate; 5485 rarpt->desc_rate = rate; 5486 break; 5487 default: 5488 break; 5489 } 5490 } 5491 5492 out: 5493 dev_kfree_skb(skb); 5494 } 5495 5496 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv, 5497 struct sk_buff *skb) 5498 { 5499 struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data; 5500 struct device *dev = &priv->udev->dev; 5501 int len; 5502 unsigned long flags; 5503 5504 len = skb->len - 2; 5505 5506 dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n", 5507 c2h->id, c2h->seq, len, c2h->bt_info.response_source); 5508 5509 switch(c2h->id) { 5510 case C2H_8723B_BT_INFO: 5511 if (c2h->bt_info.response_source > 5512 BT_INFO_SRC_8723B_BT_ACTIVE_SEND) 5513 dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n"); 5514 else 5515 dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n"); 5516 5517 if (c2h->bt_info.bt_has_reset) 5518 dev_dbg(dev, "BT has been reset\n"); 5519 if (c2h->bt_info.tx_rx_mask) 5520 dev_dbg(dev, "BT TRx mask\n"); 5521 5522 break; 5523 case C2H_8723B_BT_MP_INFO: 5524 dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n", 5525 c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status); 5526 break; 5527 case C2H_8723B_RA_REPORT: 5528 dev_dbg(dev, 5529 "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n", 5530 c2h->ra_report.rate, c2h->ra_report.sgi, 5531 c2h->ra_report.macid, c2h->ra_report.noisy_state); 5532 break; 5533 default: 5534 dev_info(dev, "Unhandled C2H event %02x seq %02x\n", 5535 c2h->id, c2h->seq); 5536 print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE, 5537 16, 1, c2h->raw.payload, len, false); 5538 break; 5539 } 5540 5541 spin_lock_irqsave(&priv->c2hcmd_lock, flags); 5542 __skb_queue_tail(&priv->c2hcmd_queue, skb); 5543 spin_unlock_irqrestore(&priv->c2hcmd_lock, flags); 5544 5545 schedule_work(&priv->c2hcmd_work); 5546 } 5547 5548 int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb) 5549 { 5550 struct ieee80211_hw *hw = priv->hw; 5551 struct ieee80211_rx_status *rx_status; 5552 struct rtl8xxxu_rxdesc16 *rx_desc; 5553 struct rtl8723au_phy_stats *phy_stats; 5554 struct sk_buff *next_skb = NULL; 5555 __le32 *_rx_desc_le; 5556 u32 *_rx_desc; 5557 int drvinfo_sz, desc_shift; 5558 int i, pkt_cnt, pkt_len, urb_len, pkt_offset; 5559 5560 urb_len = skb->len; 5561 pkt_cnt = 0; 5562 5563 do { 5564 rx_desc = (struct rtl8xxxu_rxdesc16 *)skb->data; 5565 _rx_desc_le = (__le32 *)skb->data; 5566 _rx_desc = (u32 *)skb->data; 5567 5568 for (i = 0; 5569 i < (sizeof(struct rtl8xxxu_rxdesc16) / sizeof(u32)); i++) 5570 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]); 5571 5572 /* 5573 * Only read pkt_cnt from the header if we're parsing the 5574 * first packet 5575 */ 5576 if (!pkt_cnt) 5577 pkt_cnt = rx_desc->pkt_cnt; 5578 pkt_len = rx_desc->pktlen; 5579 5580 drvinfo_sz = rx_desc->drvinfo_sz * 8; 5581 desc_shift = rx_desc->shift; 5582 pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift + 5583 sizeof(struct rtl8xxxu_rxdesc16), 128); 5584 5585 /* 5586 * Only clone the skb if there's enough data at the end to 5587 * at least cover the rx descriptor 5588 */ 5589 if (pkt_cnt > 1 && 5590 urb_len > (pkt_offset + sizeof(struct rtl8xxxu_rxdesc16))) 5591 next_skb = skb_clone(skb, GFP_ATOMIC); 5592 5593 rx_status = IEEE80211_SKB_RXCB(skb); 5594 memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); 5595 5596 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc16)); 5597 5598 phy_stats = (struct rtl8723au_phy_stats *)skb->data; 5599 5600 skb_pull(skb, drvinfo_sz + desc_shift); 5601 5602 skb_trim(skb, pkt_len); 5603 5604 if (rx_desc->phy_stats) 5605 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats, 5606 rx_desc->rxmcs); 5607 5608 rx_status->mactime = rx_desc->tsfl; 5609 rx_status->flag |= RX_FLAG_MACTIME_START; 5610 5611 if (!rx_desc->swdec) 5612 rx_status->flag |= RX_FLAG_DECRYPTED; 5613 if (rx_desc->crc32) 5614 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 5615 if (rx_desc->bw) 5616 rx_status->bw = RATE_INFO_BW_40; 5617 5618 if (rx_desc->rxht) { 5619 rx_status->encoding = RX_ENC_HT; 5620 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0; 5621 } else { 5622 rx_status->rate_idx = rx_desc->rxmcs; 5623 } 5624 5625 rx_status->freq = hw->conf.chandef.chan->center_freq; 5626 rx_status->band = hw->conf.chandef.chan->band; 5627 5628 ieee80211_rx_irqsafe(hw, skb); 5629 5630 skb = next_skb; 5631 if (skb) 5632 skb_pull(next_skb, pkt_offset); 5633 5634 pkt_cnt--; 5635 urb_len -= pkt_offset; 5636 } while (skb && urb_len > 0 && pkt_cnt > 0); 5637 5638 return RX_TYPE_DATA_PKT; 5639 } 5640 5641 int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb) 5642 { 5643 struct ieee80211_hw *hw = priv->hw; 5644 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 5645 struct rtl8xxxu_rxdesc24 *rx_desc = 5646 (struct rtl8xxxu_rxdesc24 *)skb->data; 5647 struct rtl8723au_phy_stats *phy_stats; 5648 __le32 *_rx_desc_le = (__le32 *)skb->data; 5649 u32 *_rx_desc = (u32 *)skb->data; 5650 int drvinfo_sz, desc_shift; 5651 int i; 5652 5653 for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++) 5654 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]); 5655 5656 memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); 5657 5658 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24)); 5659 5660 phy_stats = (struct rtl8723au_phy_stats *)skb->data; 5661 5662 drvinfo_sz = rx_desc->drvinfo_sz * 8; 5663 desc_shift = rx_desc->shift; 5664 skb_pull(skb, drvinfo_sz + desc_shift); 5665 5666 if (rx_desc->rpt_sel) { 5667 struct device *dev = &priv->udev->dev; 5668 dev_dbg(dev, "%s: C2H packet\n", __func__); 5669 rtl8723bu_handle_c2h(priv, skb); 5670 return RX_TYPE_C2H; 5671 } 5672 5673 if (rx_desc->phy_stats) 5674 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats, 5675 rx_desc->rxmcs); 5676 5677 rx_status->mactime = rx_desc->tsfl; 5678 rx_status->flag |= RX_FLAG_MACTIME_START; 5679 5680 if (!rx_desc->swdec) 5681 rx_status->flag |= RX_FLAG_DECRYPTED; 5682 if (rx_desc->crc32) 5683 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 5684 if (rx_desc->bw) 5685 rx_status->bw = RATE_INFO_BW_40; 5686 5687 if (rx_desc->rxmcs >= DESC_RATE_MCS0) { 5688 rx_status->encoding = RX_ENC_HT; 5689 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0; 5690 } else { 5691 rx_status->rate_idx = rx_desc->rxmcs; 5692 } 5693 5694 rx_status->freq = hw->conf.chandef.chan->center_freq; 5695 rx_status->band = hw->conf.chandef.chan->band; 5696 5697 ieee80211_rx_irqsafe(hw, skb); 5698 return RX_TYPE_DATA_PKT; 5699 } 5700 5701 static void rtl8xxxu_rx_complete(struct urb *urb) 5702 { 5703 struct rtl8xxxu_rx_urb *rx_urb = 5704 container_of(urb, struct rtl8xxxu_rx_urb, urb); 5705 struct ieee80211_hw *hw = rx_urb->hw; 5706 struct rtl8xxxu_priv *priv = hw->priv; 5707 struct sk_buff *skb = (struct sk_buff *)urb->context; 5708 struct device *dev = &priv->udev->dev; 5709 5710 skb_put(skb, urb->actual_length); 5711 5712 if (urb->status == 0) { 5713 priv->fops->parse_rx_desc(priv, skb); 5714 5715 skb = NULL; 5716 rx_urb->urb.context = NULL; 5717 rtl8xxxu_queue_rx_urb(priv, rx_urb); 5718 } else { 5719 dev_dbg(dev, "%s: status %i\n", __func__, urb->status); 5720 goto cleanup; 5721 } 5722 return; 5723 5724 cleanup: 5725 usb_free_urb(urb); 5726 dev_kfree_skb(skb); 5727 return; 5728 } 5729 5730 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv, 5731 struct rtl8xxxu_rx_urb *rx_urb) 5732 { 5733 struct rtl8xxxu_fileops *fops = priv->fops; 5734 struct sk_buff *skb; 5735 int skb_size; 5736 int ret, rx_desc_sz; 5737 5738 rx_desc_sz = fops->rx_desc_size; 5739 5740 if (priv->rx_buf_aggregation && fops->rx_agg_buf_size) { 5741 skb_size = fops->rx_agg_buf_size; 5742 skb_size += (rx_desc_sz + sizeof(struct rtl8723au_phy_stats)); 5743 } else { 5744 skb_size = IEEE80211_MAX_FRAME_LEN; 5745 } 5746 5747 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL); 5748 if (!skb) 5749 return -ENOMEM; 5750 5751 memset(skb->data, 0, rx_desc_sz); 5752 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data, 5753 skb_size, rtl8xxxu_rx_complete, skb); 5754 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor); 5755 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC); 5756 if (ret) 5757 usb_unanchor_urb(&rx_urb->urb); 5758 return ret; 5759 } 5760 5761 static void rtl8xxxu_int_complete(struct urb *urb) 5762 { 5763 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context; 5764 struct device *dev = &priv->udev->dev; 5765 int ret; 5766 5767 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_INTERRUPT) 5768 dev_dbg(dev, "%s: status %i\n", __func__, urb->status); 5769 if (urb->status == 0) { 5770 usb_anchor_urb(urb, &priv->int_anchor); 5771 ret = usb_submit_urb(urb, GFP_ATOMIC); 5772 if (ret) 5773 usb_unanchor_urb(urb); 5774 } else { 5775 dev_dbg(dev, "%s: Error %i\n", __func__, urb->status); 5776 } 5777 } 5778 5779 5780 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw) 5781 { 5782 struct rtl8xxxu_priv *priv = hw->priv; 5783 struct urb *urb; 5784 u32 val32; 5785 int ret; 5786 5787 urb = usb_alloc_urb(0, GFP_KERNEL); 5788 if (!urb) 5789 return -ENOMEM; 5790 5791 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt, 5792 priv->int_buf, USB_INTR_CONTENT_LENGTH, 5793 rtl8xxxu_int_complete, priv, 1); 5794 usb_anchor_urb(urb, &priv->int_anchor); 5795 ret = usb_submit_urb(urb, GFP_KERNEL); 5796 if (ret) { 5797 usb_unanchor_urb(urb); 5798 goto error; 5799 } 5800 5801 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR); 5802 val32 |= USB_HIMR_CPWM; 5803 rtl8xxxu_write32(priv, REG_USB_HIMR, val32); 5804 5805 error: 5806 usb_free_urb(urb); 5807 return ret; 5808 } 5809 5810 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw, 5811 struct ieee80211_vif *vif) 5812 { 5813 struct rtl8xxxu_priv *priv = hw->priv; 5814 int ret; 5815 u8 val8; 5816 5817 switch (vif->type) { 5818 case NL80211_IFTYPE_STATION: 5819 if (!priv->vif) 5820 priv->vif = vif; 5821 else 5822 return -EOPNOTSUPP; 5823 rtl8xxxu_stop_tx_beacon(priv); 5824 5825 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 5826 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE | 5827 BEACON_DISABLE_TSF_UPDATE; 5828 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 5829 ret = 0; 5830 break; 5831 default: 5832 ret = -EOPNOTSUPP; 5833 } 5834 5835 rtl8xxxu_set_linktype(priv, vif->type); 5836 5837 return ret; 5838 } 5839 5840 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw, 5841 struct ieee80211_vif *vif) 5842 { 5843 struct rtl8xxxu_priv *priv = hw->priv; 5844 5845 dev_dbg(&priv->udev->dev, "%s\n", __func__); 5846 5847 if (priv->vif) 5848 priv->vif = NULL; 5849 } 5850 5851 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed) 5852 { 5853 struct rtl8xxxu_priv *priv = hw->priv; 5854 struct device *dev = &priv->udev->dev; 5855 u16 val16; 5856 int ret = 0, channel; 5857 bool ht40; 5858 5859 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL) 5860 dev_info(dev, 5861 "%s: channel: %i (changed %08x chandef.width %02x)\n", 5862 __func__, hw->conf.chandef.chan->hw_value, 5863 changed, hw->conf.chandef.width); 5864 5865 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) { 5866 val16 = ((hw->conf.long_frame_max_tx_count << 5867 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) | 5868 ((hw->conf.short_frame_max_tx_count << 5869 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK); 5870 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16); 5871 } 5872 5873 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { 5874 switch (hw->conf.chandef.width) { 5875 case NL80211_CHAN_WIDTH_20_NOHT: 5876 case NL80211_CHAN_WIDTH_20: 5877 ht40 = false; 5878 break; 5879 case NL80211_CHAN_WIDTH_40: 5880 ht40 = true; 5881 break; 5882 default: 5883 ret = -ENOTSUPP; 5884 goto exit; 5885 } 5886 5887 channel = hw->conf.chandef.chan->hw_value; 5888 5889 priv->fops->set_tx_power(priv, channel, ht40); 5890 5891 priv->fops->config_channel(hw); 5892 } 5893 5894 exit: 5895 return ret; 5896 } 5897 5898 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw, 5899 struct ieee80211_vif *vif, u16 queue, 5900 const struct ieee80211_tx_queue_params *param) 5901 { 5902 struct rtl8xxxu_priv *priv = hw->priv; 5903 struct device *dev = &priv->udev->dev; 5904 u32 val32; 5905 u8 aifs, acm_ctrl, acm_bit; 5906 5907 aifs = param->aifs; 5908 5909 val32 = aifs | 5910 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT | 5911 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT | 5912 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT; 5913 5914 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL); 5915 dev_dbg(dev, 5916 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n", 5917 __func__, queue, val32, param->acm, acm_ctrl); 5918 5919 switch (queue) { 5920 case IEEE80211_AC_VO: 5921 acm_bit = ACM_HW_CTRL_VO; 5922 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32); 5923 break; 5924 case IEEE80211_AC_VI: 5925 acm_bit = ACM_HW_CTRL_VI; 5926 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32); 5927 break; 5928 case IEEE80211_AC_BE: 5929 acm_bit = ACM_HW_CTRL_BE; 5930 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32); 5931 break; 5932 case IEEE80211_AC_BK: 5933 acm_bit = ACM_HW_CTRL_BK; 5934 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32); 5935 break; 5936 default: 5937 acm_bit = 0; 5938 break; 5939 } 5940 5941 if (param->acm) 5942 acm_ctrl |= acm_bit; 5943 else 5944 acm_ctrl &= ~acm_bit; 5945 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl); 5946 5947 return 0; 5948 } 5949 5950 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw, 5951 unsigned int changed_flags, 5952 unsigned int *total_flags, u64 multicast) 5953 { 5954 struct rtl8xxxu_priv *priv = hw->priv; 5955 u32 rcr = rtl8xxxu_read32(priv, REG_RCR); 5956 5957 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n", 5958 __func__, changed_flags, *total_flags); 5959 5960 /* 5961 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR) 5962 */ 5963 5964 if (*total_flags & FIF_FCSFAIL) 5965 rcr |= RCR_ACCEPT_CRC32; 5966 else 5967 rcr &= ~RCR_ACCEPT_CRC32; 5968 5969 /* 5970 * FIF_PLCPFAIL not supported? 5971 */ 5972 5973 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) 5974 rcr &= ~RCR_CHECK_BSSID_BEACON; 5975 else 5976 rcr |= RCR_CHECK_BSSID_BEACON; 5977 5978 if (*total_flags & FIF_CONTROL) 5979 rcr |= RCR_ACCEPT_CTRL_FRAME; 5980 else 5981 rcr &= ~RCR_ACCEPT_CTRL_FRAME; 5982 5983 if (*total_flags & FIF_OTHER_BSS) { 5984 rcr |= RCR_ACCEPT_AP; 5985 rcr &= ~RCR_CHECK_BSSID_MATCH; 5986 } else { 5987 rcr &= ~RCR_ACCEPT_AP; 5988 rcr |= RCR_CHECK_BSSID_MATCH; 5989 } 5990 5991 if (*total_flags & FIF_PSPOLL) 5992 rcr |= RCR_ACCEPT_PM; 5993 else 5994 rcr &= ~RCR_ACCEPT_PM; 5995 5996 /* 5997 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted 5998 */ 5999 6000 rtl8xxxu_write32(priv, REG_RCR, rcr); 6001 6002 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC | 6003 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL | 6004 FIF_PROBE_REQ); 6005 } 6006 6007 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts) 6008 { 6009 if (rts > 2347) 6010 return -EINVAL; 6011 6012 return 0; 6013 } 6014 6015 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 6016 struct ieee80211_vif *vif, 6017 struct ieee80211_sta *sta, 6018 struct ieee80211_key_conf *key) 6019 { 6020 struct rtl8xxxu_priv *priv = hw->priv; 6021 struct device *dev = &priv->udev->dev; 6022 u8 mac_addr[ETH_ALEN]; 6023 u8 val8; 6024 u16 val16; 6025 u32 val32; 6026 int retval = -EOPNOTSUPP; 6027 6028 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n", 6029 __func__, cmd, key->cipher, key->keyidx); 6030 6031 if (vif->type != NL80211_IFTYPE_STATION) 6032 return -EOPNOTSUPP; 6033 6034 if (key->keyidx > 3) 6035 return -EOPNOTSUPP; 6036 6037 switch (key->cipher) { 6038 case WLAN_CIPHER_SUITE_WEP40: 6039 case WLAN_CIPHER_SUITE_WEP104: 6040 6041 break; 6042 case WLAN_CIPHER_SUITE_CCMP: 6043 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; 6044 break; 6045 case WLAN_CIPHER_SUITE_TKIP: 6046 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 6047 break; 6048 default: 6049 return -EOPNOTSUPP; 6050 } 6051 6052 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { 6053 dev_dbg(dev, "%s: pairwise key\n", __func__); 6054 ether_addr_copy(mac_addr, sta->addr); 6055 } else { 6056 dev_dbg(dev, "%s: group key\n", __func__); 6057 eth_broadcast_addr(mac_addr); 6058 } 6059 6060 val16 = rtl8xxxu_read16(priv, REG_CR); 6061 val16 |= CR_SECURITY_ENABLE; 6062 rtl8xxxu_write16(priv, REG_CR, val16); 6063 6064 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY | 6065 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY; 6066 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY; 6067 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8); 6068 6069 switch (cmd) { 6070 case SET_KEY: 6071 key->hw_key_idx = key->keyidx; 6072 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 6073 rtl8xxxu_cam_write(priv, key, mac_addr); 6074 retval = 0; 6075 break; 6076 case DISABLE_KEY: 6077 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000); 6078 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE | 6079 key->keyidx << CAM_CMD_KEY_SHIFT; 6080 rtl8xxxu_write32(priv, REG_CAM_CMD, val32); 6081 retval = 0; 6082 break; 6083 default: 6084 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd); 6085 } 6086 6087 return retval; 6088 } 6089 6090 static int 6091 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 6092 struct ieee80211_ampdu_params *params) 6093 { 6094 struct rtl8xxxu_priv *priv = hw->priv; 6095 struct device *dev = &priv->udev->dev; 6096 u8 ampdu_factor, ampdu_density; 6097 struct ieee80211_sta *sta = params->sta; 6098 enum ieee80211_ampdu_mlme_action action = params->action; 6099 6100 switch (action) { 6101 case IEEE80211_AMPDU_TX_START: 6102 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__); 6103 ampdu_factor = sta->ht_cap.ampdu_factor; 6104 ampdu_density = sta->ht_cap.ampdu_density; 6105 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor); 6106 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density); 6107 dev_dbg(dev, 6108 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n", 6109 ampdu_factor, ampdu_density); 6110 break; 6111 case IEEE80211_AMPDU_TX_STOP_FLUSH: 6112 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__); 6113 rtl8xxxu_set_ampdu_factor(priv, 0); 6114 rtl8xxxu_set_ampdu_min_space(priv, 0); 6115 break; 6116 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 6117 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n", 6118 __func__); 6119 rtl8xxxu_set_ampdu_factor(priv, 0); 6120 rtl8xxxu_set_ampdu_min_space(priv, 0); 6121 break; 6122 case IEEE80211_AMPDU_RX_START: 6123 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__); 6124 break; 6125 case IEEE80211_AMPDU_RX_STOP: 6126 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__); 6127 break; 6128 default: 6129 break; 6130 } 6131 return 0; 6132 } 6133 6134 static void 6135 rtl8xxxu_sta_statistics(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 6136 struct ieee80211_sta *sta, struct station_info *sinfo) 6137 { 6138 struct rtl8xxxu_priv *priv = hw->priv; 6139 6140 sinfo->txrate = priv->ra_report.txrate; 6141 sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE); 6142 } 6143 6144 static u8 rtl8xxxu_signal_to_snr(int signal) 6145 { 6146 if (signal < RTL8XXXU_NOISE_FLOOR_MIN) 6147 signal = RTL8XXXU_NOISE_FLOOR_MIN; 6148 else if (signal > 0) 6149 signal = 0; 6150 return (u8)(signal - RTL8XXXU_NOISE_FLOOR_MIN); 6151 } 6152 6153 static void rtl8xxxu_refresh_rate_mask(struct rtl8xxxu_priv *priv, 6154 int signal, struct ieee80211_sta *sta) 6155 { 6156 struct ieee80211_hw *hw = priv->hw; 6157 u16 wireless_mode; 6158 u8 rssi_level, ratr_idx; 6159 u8 txbw_40mhz; 6160 u8 snr, snr_thresh_high, snr_thresh_low; 6161 u8 go_up_gap = 5; 6162 6163 rssi_level = priv->rssi_level; 6164 snr = rtl8xxxu_signal_to_snr(signal); 6165 snr_thresh_high = RTL8XXXU_SNR_THRESH_HIGH; 6166 snr_thresh_low = RTL8XXXU_SNR_THRESH_LOW; 6167 txbw_40mhz = (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) ? 1 : 0; 6168 6169 switch (rssi_level) { 6170 case RTL8XXXU_RATR_STA_MID: 6171 snr_thresh_high += go_up_gap; 6172 break; 6173 case RTL8XXXU_RATR_STA_LOW: 6174 snr_thresh_high += go_up_gap; 6175 snr_thresh_low += go_up_gap; 6176 break; 6177 default: 6178 break; 6179 } 6180 6181 if (snr > snr_thresh_high) 6182 rssi_level = RTL8XXXU_RATR_STA_HIGH; 6183 else if (snr > snr_thresh_low) 6184 rssi_level = RTL8XXXU_RATR_STA_MID; 6185 else 6186 rssi_level = RTL8XXXU_RATR_STA_LOW; 6187 6188 if (rssi_level != priv->rssi_level) { 6189 int sgi = 0; 6190 u32 rate_bitmap = 0; 6191 6192 rcu_read_lock(); 6193 rate_bitmap = (sta->supp_rates[0] & 0xfff) | 6194 (sta->ht_cap.mcs.rx_mask[0] << 12) | 6195 (sta->ht_cap.mcs.rx_mask[1] << 20); 6196 if (sta->ht_cap.cap & 6197 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)) 6198 sgi = 1; 6199 rcu_read_unlock(); 6200 6201 wireless_mode = rtl8xxxu_wireless_mode(hw, sta); 6202 switch (wireless_mode) { 6203 case WIRELESS_MODE_B: 6204 ratr_idx = RATEID_IDX_B; 6205 if (rate_bitmap & 0x0000000c) 6206 rate_bitmap &= 0x0000000d; 6207 else 6208 rate_bitmap &= 0x0000000f; 6209 break; 6210 case WIRELESS_MODE_A: 6211 case WIRELESS_MODE_G: 6212 ratr_idx = RATEID_IDX_G; 6213 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) 6214 rate_bitmap &= 0x00000f00; 6215 else 6216 rate_bitmap &= 0x00000ff0; 6217 break; 6218 case (WIRELESS_MODE_B | WIRELESS_MODE_G): 6219 ratr_idx = RATEID_IDX_BG; 6220 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) 6221 rate_bitmap &= 0x00000f00; 6222 else if (rssi_level == RTL8XXXU_RATR_STA_MID) 6223 rate_bitmap &= 0x00000ff0; 6224 else 6225 rate_bitmap &= 0x00000ff5; 6226 break; 6227 case WIRELESS_MODE_N_24G: 6228 case WIRELESS_MODE_N_5G: 6229 case (WIRELESS_MODE_G | WIRELESS_MODE_N_24G): 6230 case (WIRELESS_MODE_A | WIRELESS_MODE_N_5G): 6231 if (priv->tx_paths == 2 && priv->rx_paths == 2) 6232 ratr_idx = RATEID_IDX_GN_N2SS; 6233 else 6234 ratr_idx = RATEID_IDX_GN_N1SS; 6235 break; 6236 case (WIRELESS_MODE_B | WIRELESS_MODE_G | WIRELESS_MODE_N_24G): 6237 case (WIRELESS_MODE_B | WIRELESS_MODE_N_24G): 6238 if (txbw_40mhz) { 6239 if (priv->tx_paths == 2 && priv->rx_paths == 2) 6240 ratr_idx = RATEID_IDX_BGN_40M_2SS; 6241 else 6242 ratr_idx = RATEID_IDX_BGN_40M_1SS; 6243 } else { 6244 if (priv->tx_paths == 2 && priv->rx_paths == 2) 6245 ratr_idx = RATEID_IDX_BGN_20M_2SS_BN; 6246 else 6247 ratr_idx = RATEID_IDX_BGN_20M_1SS_BN; 6248 } 6249 6250 if (priv->tx_paths == 2 && priv->rx_paths == 2) { 6251 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) { 6252 rate_bitmap &= 0x0f8f0000; 6253 } else if (rssi_level == RTL8XXXU_RATR_STA_MID) { 6254 rate_bitmap &= 0x0f8ff000; 6255 } else { 6256 if (txbw_40mhz) 6257 rate_bitmap &= 0x0f8ff015; 6258 else 6259 rate_bitmap &= 0x0f8ff005; 6260 } 6261 } else { 6262 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) { 6263 rate_bitmap &= 0x000f0000; 6264 } else if (rssi_level == RTL8XXXU_RATR_STA_MID) { 6265 rate_bitmap &= 0x000ff000; 6266 } else { 6267 if (txbw_40mhz) 6268 rate_bitmap &= 0x000ff015; 6269 else 6270 rate_bitmap &= 0x000ff005; 6271 } 6272 } 6273 break; 6274 default: 6275 ratr_idx = RATEID_IDX_BGN_40M_2SS; 6276 rate_bitmap &= 0x0fffffff; 6277 break; 6278 } 6279 6280 priv->rssi_level = rssi_level; 6281 priv->fops->update_rate_mask(priv, rate_bitmap, ratr_idx, sgi); 6282 } 6283 } 6284 6285 static void rtl8xxxu_watchdog_callback(struct work_struct *work) 6286 { 6287 struct ieee80211_vif *vif; 6288 struct rtl8xxxu_priv *priv; 6289 6290 priv = container_of(work, struct rtl8xxxu_priv, ra_watchdog.work); 6291 vif = priv->vif; 6292 6293 if (vif && vif->type == NL80211_IFTYPE_STATION) { 6294 int signal; 6295 struct ieee80211_sta *sta; 6296 6297 rcu_read_lock(); 6298 sta = ieee80211_find_sta(vif, vif->bss_conf.bssid); 6299 if (!sta) { 6300 struct device *dev = &priv->udev->dev; 6301 6302 dev_dbg(dev, "%s: no sta found\n", __func__); 6303 rcu_read_unlock(); 6304 goto out; 6305 } 6306 rcu_read_unlock(); 6307 6308 signal = ieee80211_ave_rssi(vif); 6309 rtl8xxxu_refresh_rate_mask(priv, signal, sta); 6310 } 6311 6312 out: 6313 schedule_delayed_work(&priv->ra_watchdog, 2 * HZ); 6314 } 6315 6316 static int rtl8xxxu_start(struct ieee80211_hw *hw) 6317 { 6318 struct rtl8xxxu_priv *priv = hw->priv; 6319 struct rtl8xxxu_rx_urb *rx_urb; 6320 struct rtl8xxxu_tx_urb *tx_urb; 6321 struct sk_buff *skb; 6322 unsigned long flags; 6323 int ret, i; 6324 6325 ret = 0; 6326 6327 init_usb_anchor(&priv->rx_anchor); 6328 init_usb_anchor(&priv->tx_anchor); 6329 init_usb_anchor(&priv->int_anchor); 6330 6331 priv->fops->enable_rf(priv); 6332 if (priv->usb_interrupts) { 6333 ret = rtl8xxxu_submit_int_urb(hw); 6334 if (ret) 6335 goto exit; 6336 } 6337 6338 for (i = 0; i < RTL8XXXU_TX_URBS; i++) { 6339 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL); 6340 if (!tx_urb) { 6341 if (!i) 6342 ret = -ENOMEM; 6343 6344 goto error_out; 6345 } 6346 usb_init_urb(&tx_urb->urb); 6347 INIT_LIST_HEAD(&tx_urb->list); 6348 tx_urb->hw = hw; 6349 list_add(&tx_urb->list, &priv->tx_urb_free_list); 6350 priv->tx_urb_free_count++; 6351 } 6352 6353 priv->tx_stopped = false; 6354 6355 spin_lock_irqsave(&priv->rx_urb_lock, flags); 6356 priv->shutdown = false; 6357 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 6358 6359 for (i = 0; i < RTL8XXXU_RX_URBS; i++) { 6360 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL); 6361 if (!rx_urb) { 6362 if (!i) 6363 ret = -ENOMEM; 6364 6365 goto error_out; 6366 } 6367 usb_init_urb(&rx_urb->urb); 6368 INIT_LIST_HEAD(&rx_urb->list); 6369 rx_urb->hw = hw; 6370 6371 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb); 6372 if (ret) { 6373 if (ret != -ENOMEM) { 6374 skb = (struct sk_buff *)rx_urb->urb.context; 6375 dev_kfree_skb(skb); 6376 } 6377 rtl8xxxu_queue_rx_urb(priv, rx_urb); 6378 } 6379 } 6380 6381 schedule_delayed_work(&priv->ra_watchdog, 2 * HZ); 6382 exit: 6383 /* 6384 * Accept all data and mgmt frames 6385 */ 6386 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff); 6387 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff); 6388 6389 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e); 6390 6391 return ret; 6392 6393 error_out: 6394 rtl8xxxu_free_tx_resources(priv); 6395 /* 6396 * Disable all data and mgmt frames 6397 */ 6398 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); 6399 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000); 6400 6401 return ret; 6402 } 6403 6404 static void rtl8xxxu_stop(struct ieee80211_hw *hw) 6405 { 6406 struct rtl8xxxu_priv *priv = hw->priv; 6407 unsigned long flags; 6408 6409 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 6410 6411 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000); 6412 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); 6413 6414 spin_lock_irqsave(&priv->rx_urb_lock, flags); 6415 priv->shutdown = true; 6416 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 6417 6418 usb_kill_anchored_urbs(&priv->rx_anchor); 6419 usb_kill_anchored_urbs(&priv->tx_anchor); 6420 if (priv->usb_interrupts) 6421 usb_kill_anchored_urbs(&priv->int_anchor); 6422 6423 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 6424 6425 priv->fops->disable_rf(priv); 6426 6427 /* 6428 * Disable interrupts 6429 */ 6430 if (priv->usb_interrupts) 6431 rtl8xxxu_write32(priv, REG_USB_HIMR, 0); 6432 6433 cancel_delayed_work_sync(&priv->ra_watchdog); 6434 6435 rtl8xxxu_free_rx_resources(priv); 6436 rtl8xxxu_free_tx_resources(priv); 6437 } 6438 6439 static const struct ieee80211_ops rtl8xxxu_ops = { 6440 .tx = rtl8xxxu_tx, 6441 .add_interface = rtl8xxxu_add_interface, 6442 .remove_interface = rtl8xxxu_remove_interface, 6443 .config = rtl8xxxu_config, 6444 .conf_tx = rtl8xxxu_conf_tx, 6445 .bss_info_changed = rtl8xxxu_bss_info_changed, 6446 .configure_filter = rtl8xxxu_configure_filter, 6447 .set_rts_threshold = rtl8xxxu_set_rts_threshold, 6448 .start = rtl8xxxu_start, 6449 .stop = rtl8xxxu_stop, 6450 .sw_scan_start = rtl8xxxu_sw_scan_start, 6451 .sw_scan_complete = rtl8xxxu_sw_scan_complete, 6452 .set_key = rtl8xxxu_set_key, 6453 .ampdu_action = rtl8xxxu_ampdu_action, 6454 .sta_statistics = rtl8xxxu_sta_statistics, 6455 }; 6456 6457 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv, 6458 struct usb_interface *interface) 6459 { 6460 struct usb_interface_descriptor *interface_desc; 6461 struct usb_host_interface *host_interface; 6462 struct usb_endpoint_descriptor *endpoint; 6463 struct device *dev = &priv->udev->dev; 6464 int i, j = 0, endpoints; 6465 u8 dir, xtype, num; 6466 int ret = 0; 6467 6468 host_interface = interface->cur_altsetting; 6469 interface_desc = &host_interface->desc; 6470 endpoints = interface_desc->bNumEndpoints; 6471 6472 for (i = 0; i < endpoints; i++) { 6473 endpoint = &host_interface->endpoint[i].desc; 6474 6475 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK; 6476 num = usb_endpoint_num(endpoint); 6477 xtype = usb_endpoint_type(endpoint); 6478 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 6479 dev_dbg(dev, 6480 "%s: endpoint: dir %02x, # %02x, type %02x\n", 6481 __func__, dir, num, xtype); 6482 if (usb_endpoint_dir_in(endpoint) && 6483 usb_endpoint_xfer_bulk(endpoint)) { 6484 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 6485 dev_dbg(dev, "%s: in endpoint num %i\n", 6486 __func__, num); 6487 6488 if (priv->pipe_in) { 6489 dev_warn(dev, 6490 "%s: Too many IN pipes\n", __func__); 6491 ret = -EINVAL; 6492 goto exit; 6493 } 6494 6495 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num); 6496 } 6497 6498 if (usb_endpoint_dir_in(endpoint) && 6499 usb_endpoint_xfer_int(endpoint)) { 6500 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 6501 dev_dbg(dev, "%s: interrupt endpoint num %i\n", 6502 __func__, num); 6503 6504 if (priv->pipe_interrupt) { 6505 dev_warn(dev, "%s: Too many INTERRUPT pipes\n", 6506 __func__); 6507 ret = -EINVAL; 6508 goto exit; 6509 } 6510 6511 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num); 6512 } 6513 6514 if (usb_endpoint_dir_out(endpoint) && 6515 usb_endpoint_xfer_bulk(endpoint)) { 6516 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 6517 dev_dbg(dev, "%s: out endpoint num %i\n", 6518 __func__, num); 6519 if (j >= RTL8XXXU_OUT_ENDPOINTS) { 6520 dev_warn(dev, 6521 "%s: Too many OUT pipes\n", __func__); 6522 ret = -EINVAL; 6523 goto exit; 6524 } 6525 priv->out_ep[j++] = num; 6526 } 6527 } 6528 exit: 6529 priv->nr_out_eps = j; 6530 return ret; 6531 } 6532 6533 static int rtl8xxxu_probe(struct usb_interface *interface, 6534 const struct usb_device_id *id) 6535 { 6536 struct rtl8xxxu_priv *priv; 6537 struct ieee80211_hw *hw; 6538 struct usb_device *udev; 6539 struct ieee80211_supported_band *sband; 6540 int ret; 6541 int untested = 1; 6542 6543 udev = usb_get_dev(interface_to_usbdev(interface)); 6544 6545 switch (id->idVendor) { 6546 case USB_VENDOR_ID_REALTEK: 6547 switch(id->idProduct) { 6548 case 0x1724: 6549 case 0x8176: 6550 case 0x8178: 6551 case 0x817f: 6552 case 0x818b: 6553 untested = 0; 6554 break; 6555 } 6556 break; 6557 case 0x7392: 6558 if (id->idProduct == 0x7811 || id->idProduct == 0xa611) 6559 untested = 0; 6560 break; 6561 case 0x050d: 6562 if (id->idProduct == 0x1004) 6563 untested = 0; 6564 break; 6565 case 0x20f4: 6566 if (id->idProduct == 0x648b) 6567 untested = 0; 6568 break; 6569 case 0x2001: 6570 if (id->idProduct == 0x3308) 6571 untested = 0; 6572 break; 6573 case 0x2357: 6574 if (id->idProduct == 0x0109) 6575 untested = 0; 6576 break; 6577 default: 6578 break; 6579 } 6580 6581 if (untested) { 6582 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE; 6583 dev_info(&udev->dev, 6584 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n", 6585 id->idVendor, id->idProduct); 6586 dev_info(&udev->dev, 6587 "Please report results to Jes.Sorensen@gmail.com\n"); 6588 } 6589 6590 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops); 6591 if (!hw) { 6592 ret = -ENOMEM; 6593 priv = NULL; 6594 goto exit; 6595 } 6596 6597 priv = hw->priv; 6598 priv->hw = hw; 6599 priv->udev = udev; 6600 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info; 6601 mutex_init(&priv->usb_buf_mutex); 6602 mutex_init(&priv->h2c_mutex); 6603 INIT_LIST_HEAD(&priv->tx_urb_free_list); 6604 spin_lock_init(&priv->tx_urb_lock); 6605 INIT_LIST_HEAD(&priv->rx_urb_pending_list); 6606 spin_lock_init(&priv->rx_urb_lock); 6607 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work); 6608 INIT_DELAYED_WORK(&priv->ra_watchdog, rtl8xxxu_watchdog_callback); 6609 spin_lock_init(&priv->c2hcmd_lock); 6610 INIT_WORK(&priv->c2hcmd_work, rtl8xxxu_c2hcmd_callback); 6611 skb_queue_head_init(&priv->c2hcmd_queue); 6612 6613 usb_set_intfdata(interface, hw); 6614 6615 ret = rtl8xxxu_parse_usb(priv, interface); 6616 if (ret) 6617 goto exit; 6618 6619 ret = rtl8xxxu_identify_chip(priv); 6620 if (ret) { 6621 dev_err(&udev->dev, "Fatal - failed to identify chip\n"); 6622 goto exit; 6623 } 6624 6625 ret = rtl8xxxu_read_efuse(priv); 6626 if (ret) { 6627 dev_err(&udev->dev, "Fatal - failed to read EFuse\n"); 6628 goto exit; 6629 } 6630 6631 ret = priv->fops->parse_efuse(priv); 6632 if (ret) { 6633 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n"); 6634 goto exit; 6635 } 6636 6637 rtl8xxxu_print_chipinfo(priv); 6638 6639 ret = priv->fops->load_firmware(priv); 6640 if (ret) { 6641 dev_err(&udev->dev, "Fatal - failed to load firmware\n"); 6642 goto exit; 6643 } 6644 6645 ret = rtl8xxxu_init_device(hw); 6646 if (ret) 6647 goto exit; 6648 6649 hw->wiphy->max_scan_ssids = 1; 6650 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; 6651 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); 6652 hw->queues = 4; 6653 6654 sband = &rtl8xxxu_supported_band; 6655 sband->ht_cap.ht_supported = true; 6656 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 6657 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16; 6658 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40; 6659 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs)); 6660 sband->ht_cap.mcs.rx_mask[0] = 0xff; 6661 sband->ht_cap.mcs.rx_mask[4] = 0x01; 6662 if (priv->rf_paths > 1) { 6663 sband->ht_cap.mcs.rx_mask[1] = 0xff; 6664 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40; 6665 } 6666 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 6667 /* 6668 * Some APs will negotiate HT20_40 in a noisy environment leading 6669 * to miserable performance. Rather than defaulting to this, only 6670 * enable it if explicitly requested at module load time. 6671 */ 6672 if (rtl8xxxu_ht40_2g) { 6673 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n"); 6674 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; 6675 } 6676 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 6677 6678 hw->wiphy->rts_threshold = 2347; 6679 6680 SET_IEEE80211_DEV(priv->hw, &interface->dev); 6681 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr); 6682 6683 hw->extra_tx_headroom = priv->fops->tx_desc_size; 6684 ieee80211_hw_set(hw, SIGNAL_DBM); 6685 /* 6686 * The firmware handles rate control 6687 */ 6688 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 6689 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 6690 6691 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); 6692 6693 ret = ieee80211_register_hw(priv->hw); 6694 if (ret) { 6695 dev_err(&udev->dev, "%s: Failed to register: %i\n", 6696 __func__, ret); 6697 goto exit; 6698 } 6699 6700 return 0; 6701 6702 exit: 6703 usb_set_intfdata(interface, NULL); 6704 6705 if (priv) { 6706 kfree(priv->fw_data); 6707 mutex_destroy(&priv->usb_buf_mutex); 6708 mutex_destroy(&priv->h2c_mutex); 6709 } 6710 usb_put_dev(udev); 6711 6712 ieee80211_free_hw(hw); 6713 6714 return ret; 6715 } 6716 6717 static void rtl8xxxu_disconnect(struct usb_interface *interface) 6718 { 6719 struct rtl8xxxu_priv *priv; 6720 struct ieee80211_hw *hw; 6721 6722 hw = usb_get_intfdata(interface); 6723 priv = hw->priv; 6724 6725 ieee80211_unregister_hw(hw); 6726 6727 priv->fops->power_off(priv); 6728 6729 usb_set_intfdata(interface, NULL); 6730 6731 dev_info(&priv->udev->dev, "disconnecting\n"); 6732 6733 kfree(priv->fw_data); 6734 mutex_destroy(&priv->usb_buf_mutex); 6735 mutex_destroy(&priv->h2c_mutex); 6736 6737 if (priv->udev->state != USB_STATE_NOTATTACHED) { 6738 dev_info(&priv->udev->dev, 6739 "Device still attached, trying to reset\n"); 6740 usb_reset_device(priv->udev); 6741 } 6742 usb_put_dev(priv->udev); 6743 ieee80211_free_hw(hw); 6744 } 6745 6746 static const struct usb_device_id dev_table[] = { 6747 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff), 6748 .driver_info = (unsigned long)&rtl8723au_fops}, 6749 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff), 6750 .driver_info = (unsigned long)&rtl8723au_fops}, 6751 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff), 6752 .driver_info = (unsigned long)&rtl8723au_fops}, 6753 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff), 6754 .driver_info = (unsigned long)&rtl8192eu_fops}, 6755 /* TP-Link TL-WN822N v4 */ 6756 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0108, 0xff, 0xff, 0xff), 6757 .driver_info = (unsigned long)&rtl8192eu_fops}, 6758 /* D-Link DWA-131 rev E1, tested by David Patiño */ 6759 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3319, 0xff, 0xff, 0xff), 6760 .driver_info = (unsigned long)&rtl8192eu_fops}, 6761 /* Tested by Myckel Habets */ 6762 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0109, 0xff, 0xff, 0xff), 6763 .driver_info = (unsigned long)&rtl8192eu_fops}, 6764 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff), 6765 .driver_info = (unsigned long)&rtl8723bu_fops}, 6766 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xa611, 0xff, 0xff, 0xff), 6767 .driver_info = (unsigned long)&rtl8723bu_fops}, 6768 #ifdef CONFIG_RTL8XXXU_UNTESTED 6769 /* Still supported by rtlwifi */ 6770 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff), 6771 .driver_info = (unsigned long)&rtl8192cu_fops}, 6772 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff), 6773 .driver_info = (unsigned long)&rtl8192cu_fops}, 6774 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff), 6775 .driver_info = (unsigned long)&rtl8192cu_fops}, 6776 /* Tested by Larry Finger */ 6777 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff), 6778 .driver_info = (unsigned long)&rtl8192cu_fops}, 6779 /* Tested by Andrea Merello */ 6780 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff), 6781 .driver_info = (unsigned long)&rtl8192cu_fops}, 6782 /* Tested by Jocelyn Mayer */ 6783 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff), 6784 .driver_info = (unsigned long)&rtl8192cu_fops}, 6785 /* Tested by Stefano Bravi */ 6786 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff), 6787 .driver_info = (unsigned long)&rtl8192cu_fops}, 6788 /* Currently untested 8188 series devices */ 6789 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x018a, 0xff, 0xff, 0xff), 6790 .driver_info = (unsigned long)&rtl8192cu_fops}, 6791 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff), 6792 .driver_info = (unsigned long)&rtl8192cu_fops}, 6793 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff), 6794 .driver_info = (unsigned long)&rtl8192cu_fops}, 6795 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff), 6796 .driver_info = (unsigned long)&rtl8192cu_fops}, 6797 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff), 6798 .driver_info = (unsigned long)&rtl8192cu_fops}, 6799 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff), 6800 .driver_info = (unsigned long)&rtl8192cu_fops}, 6801 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff), 6802 .driver_info = (unsigned long)&rtl8192cu_fops}, 6803 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff), 6804 .driver_info = (unsigned long)&rtl8192cu_fops}, 6805 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff), 6806 .driver_info = (unsigned long)&rtl8192cu_fops}, 6807 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff), 6808 .driver_info = (unsigned long)&rtl8192cu_fops}, 6809 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff), 6810 .driver_info = (unsigned long)&rtl8192cu_fops}, 6811 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff), 6812 .driver_info = (unsigned long)&rtl8192cu_fops}, 6813 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff), 6814 .driver_info = (unsigned long)&rtl8192cu_fops}, 6815 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff), 6816 .driver_info = (unsigned long)&rtl8192cu_fops}, 6817 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff), 6818 .driver_info = (unsigned long)&rtl8192cu_fops}, 6819 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff), 6820 .driver_info = (unsigned long)&rtl8192cu_fops}, 6821 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff), 6822 .driver_info = (unsigned long)&rtl8192cu_fops}, 6823 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff), 6824 .driver_info = (unsigned long)&rtl8192cu_fops}, 6825 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff), 6826 .driver_info = (unsigned long)&rtl8192cu_fops}, 6827 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff), 6828 .driver_info = (unsigned long)&rtl8192cu_fops}, 6829 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff), 6830 .driver_info = (unsigned long)&rtl8192cu_fops}, 6831 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff), 6832 .driver_info = (unsigned long)&rtl8192cu_fops}, 6833 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff), 6834 .driver_info = (unsigned long)&rtl8192cu_fops}, 6835 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff), 6836 .driver_info = (unsigned long)&rtl8192cu_fops}, 6837 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff), 6838 .driver_info = (unsigned long)&rtl8192cu_fops}, 6839 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff), 6840 .driver_info = (unsigned long)&rtl8192cu_fops}, 6841 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff), 6842 .driver_info = (unsigned long)&rtl8192cu_fops}, 6843 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff), 6844 .driver_info = (unsigned long)&rtl8192cu_fops}, 6845 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff), 6846 .driver_info = (unsigned long)&rtl8192cu_fops}, 6847 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff), 6848 .driver_info = (unsigned long)&rtl8192cu_fops}, 6849 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff), 6850 .driver_info = (unsigned long)&rtl8192cu_fops}, 6851 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff), 6852 .driver_info = (unsigned long)&rtl8192cu_fops}, 6853 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff), 6854 .driver_info = (unsigned long)&rtl8192cu_fops}, 6855 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff), 6856 .driver_info = (unsigned long)&rtl8192cu_fops}, 6857 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff), 6858 .driver_info = (unsigned long)&rtl8192cu_fops}, 6859 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff), 6860 .driver_info = (unsigned long)&rtl8192cu_fops}, 6861 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff), 6862 .driver_info = (unsigned long)&rtl8192cu_fops}, 6863 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff), 6864 .driver_info = (unsigned long)&rtl8192cu_fops}, 6865 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff), 6866 .driver_info = (unsigned long)&rtl8192cu_fops}, 6867 /* Currently untested 8192 series devices */ 6868 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff), 6869 .driver_info = (unsigned long)&rtl8192cu_fops}, 6870 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff), 6871 .driver_info = (unsigned long)&rtl8192cu_fops}, 6872 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff), 6873 .driver_info = (unsigned long)&rtl8192cu_fops}, 6874 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff), 6875 .driver_info = (unsigned long)&rtl8192cu_fops}, 6876 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff), 6877 .driver_info = (unsigned long)&rtl8192cu_fops}, 6878 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff), 6879 .driver_info = (unsigned long)&rtl8192cu_fops}, 6880 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff), 6881 .driver_info = (unsigned long)&rtl8192cu_fops}, 6882 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff), 6883 .driver_info = (unsigned long)&rtl8192cu_fops}, 6884 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff), 6885 .driver_info = (unsigned long)&rtl8192cu_fops}, 6886 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff), 6887 .driver_info = (unsigned long)&rtl8192cu_fops}, 6888 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff), 6889 .driver_info = (unsigned long)&rtl8192cu_fops}, 6890 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff), 6891 .driver_info = (unsigned long)&rtl8192cu_fops}, 6892 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff), 6893 .driver_info = (unsigned long)&rtl8192cu_fops}, 6894 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff), 6895 .driver_info = (unsigned long)&rtl8192cu_fops}, 6896 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff), 6897 .driver_info = (unsigned long)&rtl8192cu_fops}, 6898 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff), 6899 .driver_info = (unsigned long)&rtl8192cu_fops}, 6900 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff), 6901 .driver_info = (unsigned long)&rtl8192cu_fops}, 6902 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff), 6903 .driver_info = (unsigned long)&rtl8192cu_fops}, 6904 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff), 6905 .driver_info = (unsigned long)&rtl8192cu_fops}, 6906 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff), 6907 .driver_info = (unsigned long)&rtl8192cu_fops}, 6908 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff), 6909 .driver_info = (unsigned long)&rtl8192cu_fops}, 6910 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff), 6911 .driver_info = (unsigned long)&rtl8192cu_fops}, 6912 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff), 6913 .driver_info = (unsigned long)&rtl8192cu_fops}, 6914 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff), 6915 .driver_info = (unsigned long)&rtl8192cu_fops}, 6916 /* found in rtl8192eu vendor driver */ 6917 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0107, 0xff, 0xff, 0xff), 6918 .driver_info = (unsigned long)&rtl8192eu_fops}, 6919 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab33, 0xff, 0xff, 0xff), 6920 .driver_info = (unsigned long)&rtl8192eu_fops}, 6921 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818c, 0xff, 0xff, 0xff), 6922 .driver_info = (unsigned long)&rtl8192eu_fops}, 6923 #endif 6924 { } 6925 }; 6926 6927 static struct usb_driver rtl8xxxu_driver = { 6928 .name = DRIVER_NAME, 6929 .probe = rtl8xxxu_probe, 6930 .disconnect = rtl8xxxu_disconnect, 6931 .id_table = dev_table, 6932 .no_dynamic_id = 1, 6933 .disable_hub_initiated_lpm = 1, 6934 }; 6935 6936 static int __init rtl8xxxu_module_init(void) 6937 { 6938 int res; 6939 6940 res = usb_register(&rtl8xxxu_driver); 6941 if (res < 0) 6942 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res); 6943 6944 return res; 6945 } 6946 6947 static void __exit rtl8xxxu_module_exit(void) 6948 { 6949 usb_deregister(&rtl8xxxu_driver); 6950 } 6951 6952 6953 MODULE_DEVICE_TABLE(usb, dev_table); 6954 6955 module_init(rtl8xxxu_module_init); 6956 module_exit(rtl8xxxu_module_exit); 6957