1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * RTL8XXXU mac80211 USB driver
4 *
5 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
6 *
7 * Portions, notably calibration code:
8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
9 *
10 * This driver was written as a replacement for the vendor provided
11 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
12 * their programming interface, I have started adding support for
13 * additional 8xxx chips like the 8192cu, 8188cus, etc.
14 */
15
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <linux/sched.h>
19 #include <linux/errno.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/list.h>
24 #include <linux/usb.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/ethtool.h>
28 #include <linux/wireless.h>
29 #include <linux/firmware.h>
30 #include <linux/moduleparam.h>
31 #include <net/mac80211.h>
32 #include "rtl8xxxu.h"
33 #include "rtl8xxxu_regs.h"
34
35 #define DRIVER_NAME "rtl8xxxu"
36
37 int rtl8xxxu_debug;
38 static bool rtl8xxxu_ht40_2g;
39 static bool rtl8xxxu_dma_aggregation;
40 static int rtl8xxxu_dma_agg_timeout = -1;
41 static int rtl8xxxu_dma_agg_pages = -1;
42
43 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@gmail.com>");
44 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
45 MODULE_LICENSE("GPL");
46 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
47 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
48 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
49 MODULE_FIRMWARE("rtlwifi/rtl8188eufw.bin");
50 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
51 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
52 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
53 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
54 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
55 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
56 MODULE_FIRMWARE("rtlwifi/rtl8188fufw.bin");
57 MODULE_FIRMWARE("rtlwifi/rtl8710bufw_SMIC.bin");
58 MODULE_FIRMWARE("rtlwifi/rtl8710bufw_UMC.bin");
59 MODULE_FIRMWARE("rtlwifi/rtl8192fufw.bin");
60
61 module_param_named(debug, rtl8xxxu_debug, int, 0600);
62 MODULE_PARM_DESC(debug, "Set debug mask");
63 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
64 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
65 module_param_named(dma_aggregation, rtl8xxxu_dma_aggregation, bool, 0600);
66 MODULE_PARM_DESC(dma_aggregation, "Enable DMA packet aggregation");
67 module_param_named(dma_agg_timeout, rtl8xxxu_dma_agg_timeout, int, 0600);
68 MODULE_PARM_DESC(dma_agg_timeout, "Set DMA aggregation timeout (range 1-127)");
69 module_param_named(dma_agg_pages, rtl8xxxu_dma_agg_pages, int, 0600);
70 MODULE_PARM_DESC(dma_agg_pages, "Set DMA aggregation pages (range 1-127, 0 to disable)");
71
72 #define USB_VENDOR_ID_REALTEK 0x0bda
73 #define RTL8XXXU_RX_URBS 32
74 #define RTL8XXXU_RX_URB_PENDING_WATER 8
75 #define RTL8XXXU_TX_URBS 64
76 #define RTL8XXXU_TX_URB_LOW_WATER 25
77 #define RTL8XXXU_TX_URB_HIGH_WATER 32
78
79 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
80 struct rtl8xxxu_rx_urb *rx_urb);
81
82 static struct ieee80211_rate rtl8xxxu_rates[] = {
83 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
84 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
85 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
86 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
87 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
88 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
89 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
90 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
91 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
92 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
93 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
94 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
95 };
96
97 static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
98 { .band = NL80211_BAND_2GHZ, .center_freq = 2412,
99 .hw_value = 1, .max_power = 30 },
100 { .band = NL80211_BAND_2GHZ, .center_freq = 2417,
101 .hw_value = 2, .max_power = 30 },
102 { .band = NL80211_BAND_2GHZ, .center_freq = 2422,
103 .hw_value = 3, .max_power = 30 },
104 { .band = NL80211_BAND_2GHZ, .center_freq = 2427,
105 .hw_value = 4, .max_power = 30 },
106 { .band = NL80211_BAND_2GHZ, .center_freq = 2432,
107 .hw_value = 5, .max_power = 30 },
108 { .band = NL80211_BAND_2GHZ, .center_freq = 2437,
109 .hw_value = 6, .max_power = 30 },
110 { .band = NL80211_BAND_2GHZ, .center_freq = 2442,
111 .hw_value = 7, .max_power = 30 },
112 { .band = NL80211_BAND_2GHZ, .center_freq = 2447,
113 .hw_value = 8, .max_power = 30 },
114 { .band = NL80211_BAND_2GHZ, .center_freq = 2452,
115 .hw_value = 9, .max_power = 30 },
116 { .band = NL80211_BAND_2GHZ, .center_freq = 2457,
117 .hw_value = 10, .max_power = 30 },
118 { .band = NL80211_BAND_2GHZ, .center_freq = 2462,
119 .hw_value = 11, .max_power = 30 },
120 { .band = NL80211_BAND_2GHZ, .center_freq = 2467,
121 .hw_value = 12, .max_power = 30 },
122 { .band = NL80211_BAND_2GHZ, .center_freq = 2472,
123 .hw_value = 13, .max_power = 30 },
124 { .band = NL80211_BAND_2GHZ, .center_freq = 2484,
125 .hw_value = 14, .max_power = 30 }
126 };
127
128 static struct ieee80211_supported_band rtl8xxxu_supported_band = {
129 .channels = rtl8xxxu_channels_2g,
130 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
131 .bitrates = rtl8xxxu_rates,
132 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
133 };
134
135 const struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[] = {
136 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
137 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
138 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
139 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
140 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
141 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
142 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
143 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
144 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
145 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
146 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
147 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
148 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
149 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
150 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
151 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
152 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
153 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
154 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
155 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
156 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
157 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
158 };
159
160 static const struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
161 {0x800, 0x80040000}, {0x804, 0x00000003},
162 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
163 {0x810, 0x10001331}, {0x814, 0x020c3d10},
164 {0x818, 0x02200385}, {0x81c, 0x00000000},
165 {0x820, 0x01000100}, {0x824, 0x00390004},
166 {0x828, 0x00000000}, {0x82c, 0x00000000},
167 {0x830, 0x00000000}, {0x834, 0x00000000},
168 {0x838, 0x00000000}, {0x83c, 0x00000000},
169 {0x840, 0x00010000}, {0x844, 0x00000000},
170 {0x848, 0x00000000}, {0x84c, 0x00000000},
171 {0x850, 0x00000000}, {0x854, 0x00000000},
172 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
173 {0x860, 0x66f60110}, {0x864, 0x061f0130},
174 {0x868, 0x00000000}, {0x86c, 0x32323200},
175 {0x870, 0x07000760}, {0x874, 0x22004000},
176 {0x878, 0x00000808}, {0x87c, 0x00000000},
177 {0x880, 0xc0083070}, {0x884, 0x000004d5},
178 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
179 {0x890, 0x00000800}, {0x894, 0xfffffffe},
180 {0x898, 0x40302010}, {0x89c, 0x00706050},
181 {0x900, 0x00000000}, {0x904, 0x00000023},
182 {0x908, 0x00000000}, {0x90c, 0x81121111},
183 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
184 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
185 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
186 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
187 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
188 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
189 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
190 {0xa78, 0x00000900},
191 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
192 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
193 {0xc10, 0x08800000}, {0xc14, 0x40000100},
194 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
195 {0xc20, 0x00000000}, {0xc24, 0x00000000},
196 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
197 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
198 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
199 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
200 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
201 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
202 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
203 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
204 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
205 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
206 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
207 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
208 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
209 {0xc90, 0x00121820}, {0xc94, 0x00000000},
210 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
211 {0xca0, 0x00000000}, {0xca4, 0x00000080},
212 {0xca8, 0x00000000}, {0xcac, 0x00000000},
213 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
214 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
215 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
216 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
217 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
218 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
219 {0xce0, 0x00222222}, {0xce4, 0x00000000},
220 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
221 {0xd00, 0x00080740}, {0xd04, 0x00020401},
222 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
223 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
224 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
225 {0xd30, 0x00000000}, {0xd34, 0x80608000},
226 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
227 {0xd40, 0x00000000}, {0xd44, 0x00000000},
228 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
229 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
230 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
231 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
232 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
233 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
234 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
235 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
236 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
237 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
238 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
239 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
240 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
241 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
242 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
243 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
244 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
245 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
246 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
247 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
248 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
249 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
250 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
251 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
252 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
253 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
254 {0xf00, 0x00000300},
255 {0xffff, 0xffffffff},
256 };
257
258 static const struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
259 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
260 {0x800, 0x80040002}, {0x804, 0x00000003},
261 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
262 {0x810, 0x10000330}, {0x814, 0x020c3d10},
263 {0x818, 0x02200385}, {0x81c, 0x00000000},
264 {0x820, 0x01000100}, {0x824, 0x00390004},
265 {0x828, 0x01000100}, {0x82c, 0x00390004},
266 {0x830, 0x27272727}, {0x834, 0x27272727},
267 {0x838, 0x27272727}, {0x83c, 0x27272727},
268 {0x840, 0x00010000}, {0x844, 0x00010000},
269 {0x848, 0x27272727}, {0x84c, 0x27272727},
270 {0x850, 0x00000000}, {0x854, 0x00000000},
271 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
272 {0x860, 0x66e60230}, {0x864, 0x061f0130},
273 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
274 {0x870, 0x07000700}, {0x874, 0x22184000},
275 {0x878, 0x08080808}, {0x87c, 0x00000000},
276 {0x880, 0xc0083070}, {0x884, 0x000004d5},
277 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
278 {0x890, 0x00000800}, {0x894, 0xfffffffe},
279 {0x898, 0x40302010}, {0x89c, 0x00706050},
280 {0x900, 0x00000000}, {0x904, 0x00000023},
281 {0x908, 0x00000000}, {0x90c, 0x81121313},
282 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
283 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
284 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
285 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
286 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
287 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
288 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
289 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
290 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
291 {0xc10, 0x08800000}, {0xc14, 0x40000100},
292 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
293 {0xc20, 0x00000000}, {0xc24, 0x00000000},
294 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
295 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
296 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
297 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
298 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
299 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
300 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
301 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
302 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
303 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
304 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
305 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
306 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
307 {0xc90, 0x00121820}, {0xc94, 0x00000000},
308 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
309 {0xca0, 0x00000000}, {0xca4, 0x00000080},
310 {0xca8, 0x00000000}, {0xcac, 0x00000000},
311 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
312 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
313 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
314 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
315 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
316 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
317 {0xce0, 0x00222222}, {0xce4, 0x00000000},
318 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
319 {0xd00, 0x00080740}, {0xd04, 0x00020403},
320 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
321 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
322 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
323 {0xd30, 0x00000000}, {0xd34, 0x80608000},
324 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
325 {0xd40, 0x00000000}, {0xd44, 0x00000000},
326 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
327 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
328 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
329 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
330 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
331 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
332 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
333 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
334 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
335 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
336 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
337 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
338 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
339 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
340 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
341 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
342 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
343 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
344 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
345 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
346 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
347 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
348 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
349 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
350 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
351 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
352 {0xf00, 0x00000300},
353 {0xffff, 0xffffffff},
354 };
355
356 static const struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
357 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
358 {0x040, 0x000c0004}, {0x800, 0x80040000},
359 {0x804, 0x00000001}, {0x808, 0x0000fc00},
360 {0x80c, 0x0000000a}, {0x810, 0x10005388},
361 {0x814, 0x020c3d10}, {0x818, 0x02200385},
362 {0x81c, 0x00000000}, {0x820, 0x01000100},
363 {0x824, 0x00390204}, {0x828, 0x00000000},
364 {0x82c, 0x00000000}, {0x830, 0x00000000},
365 {0x834, 0x00000000}, {0x838, 0x00000000},
366 {0x83c, 0x00000000}, {0x840, 0x00010000},
367 {0x844, 0x00000000}, {0x848, 0x00000000},
368 {0x84c, 0x00000000}, {0x850, 0x00000000},
369 {0x854, 0x00000000}, {0x858, 0x569a569a},
370 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
371 {0x864, 0x061f0130}, {0x868, 0x00000000},
372 {0x86c, 0x20202000}, {0x870, 0x03000300},
373 {0x874, 0x22004000}, {0x878, 0x00000808},
374 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
375 {0x884, 0x000004d5}, {0x888, 0x00000000},
376 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
377 {0x894, 0xfffffffe}, {0x898, 0x40302010},
378 {0x89c, 0x00706050}, {0x900, 0x00000000},
379 {0x904, 0x00000023}, {0x908, 0x00000000},
380 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
381 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
382 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
383 {0xa14, 0x11144028}, {0xa18, 0x00881117},
384 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
385 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
386 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
387 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
388 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
389 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
390 {0xc14, 0x40000100}, {0xc18, 0x08800000},
391 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
392 {0xc24, 0x00000000}, {0xc28, 0x00000000},
393 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
394 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
395 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
396 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
397 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
398 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
399 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
400 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
401 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
402 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
403 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
404 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
405 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
406 {0xc94, 0x00000000}, {0xc98, 0x00121820},
407 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
408 {0xca4, 0x00000080}, {0xca8, 0x00000000},
409 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
410 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
411 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
412 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
413 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
414 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
415 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
416 {0xce4, 0x00000000}, {0xce8, 0x37644302},
417 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
418 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
419 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
420 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
421 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
422 {0xd34, 0x80608000}, {0xd38, 0x00000000},
423 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
424 {0xd44, 0x00000000}, {0xd48, 0x00000000},
425 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
426 {0xd54, 0x00000000}, {0xd58, 0x00000000},
427 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
428 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
429 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
430 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
431 {0xe00, 0x24242424}, {0xe04, 0x24242424},
432 {0xe08, 0x03902024}, {0xe10, 0x24242424},
433 {0xe14, 0x24242424}, {0xe18, 0x24242424},
434 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
435 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
436 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
437 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
438 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
439 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
440 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
441 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
442 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
443 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
444 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
445 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
446 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
447 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
448 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
449 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
450 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
451 {0xf00, 0x00000300},
452 {0xffff, 0xffffffff},
453 };
454
455 static const struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
456 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
457 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
458 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
459 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
460 {0xc78, 0x78080001}, {0xc78, 0x77090001},
461 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
462 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
463 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
464 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
465 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
466 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
467 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
468 {0xc78, 0x68180001}, {0xc78, 0x67190001},
469 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
470 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
471 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
472 {0xc78, 0x60200001}, {0xc78, 0x49210001},
473 {0xc78, 0x48220001}, {0xc78, 0x47230001},
474 {0xc78, 0x46240001}, {0xc78, 0x45250001},
475 {0xc78, 0x44260001}, {0xc78, 0x43270001},
476 {0xc78, 0x42280001}, {0xc78, 0x41290001},
477 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
478 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
479 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
480 {0xc78, 0x21300001}, {0xc78, 0x20310001},
481 {0xc78, 0x06320001}, {0xc78, 0x05330001},
482 {0xc78, 0x04340001}, {0xc78, 0x03350001},
483 {0xc78, 0x02360001}, {0xc78, 0x01370001},
484 {0xc78, 0x00380001}, {0xc78, 0x00390001},
485 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
486 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
487 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
488 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
489 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
490 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
491 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
492 {0xc78, 0x78480001}, {0xc78, 0x77490001},
493 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
494 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
495 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
496 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
497 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
498 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
499 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
500 {0xc78, 0x68580001}, {0xc78, 0x67590001},
501 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
502 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
503 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
504 {0xc78, 0x60600001}, {0xc78, 0x49610001},
505 {0xc78, 0x48620001}, {0xc78, 0x47630001},
506 {0xc78, 0x46640001}, {0xc78, 0x45650001},
507 {0xc78, 0x44660001}, {0xc78, 0x43670001},
508 {0xc78, 0x42680001}, {0xc78, 0x41690001},
509 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
510 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
511 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
512 {0xc78, 0x21700001}, {0xc78, 0x20710001},
513 {0xc78, 0x06720001}, {0xc78, 0x05730001},
514 {0xc78, 0x04740001}, {0xc78, 0x03750001},
515 {0xc78, 0x02760001}, {0xc78, 0x01770001},
516 {0xc78, 0x00780001}, {0xc78, 0x00790001},
517 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
518 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
519 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
520 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
521 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
522 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
523 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
524 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
525 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
526 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
527 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
528 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
529 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
530 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
531 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
532 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
533 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
534 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
535 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
536 {0xffff, 0xffffffff}
537 };
538
539 static const struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
540 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
541 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
542 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
543 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
544 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
545 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
546 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
547 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
548 {0xc78, 0x73100001}, {0xc78, 0x72110001},
549 {0xc78, 0x71120001}, {0xc78, 0x70130001},
550 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
551 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
552 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
553 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
554 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
555 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
556 {0xc78, 0x63200001}, {0xc78, 0x62210001},
557 {0xc78, 0x61220001}, {0xc78, 0x60230001},
558 {0xc78, 0x46240001}, {0xc78, 0x45250001},
559 {0xc78, 0x44260001}, {0xc78, 0x43270001},
560 {0xc78, 0x42280001}, {0xc78, 0x41290001},
561 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
562 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
563 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
564 {0xc78, 0x21300001}, {0xc78, 0x20310001},
565 {0xc78, 0x06320001}, {0xc78, 0x05330001},
566 {0xc78, 0x04340001}, {0xc78, 0x03350001},
567 {0xc78, 0x02360001}, {0xc78, 0x01370001},
568 {0xc78, 0x00380001}, {0xc78, 0x00390001},
569 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
570 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
571 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
572 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
573 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
574 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
575 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
576 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
577 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
578 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
579 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
580 {0xc78, 0x73500001}, {0xc78, 0x72510001},
581 {0xc78, 0x71520001}, {0xc78, 0x70530001},
582 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
583 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
584 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
585 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
586 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
587 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
588 {0xc78, 0x63600001}, {0xc78, 0x62610001},
589 {0xc78, 0x61620001}, {0xc78, 0x60630001},
590 {0xc78, 0x46640001}, {0xc78, 0x45650001},
591 {0xc78, 0x44660001}, {0xc78, 0x43670001},
592 {0xc78, 0x42680001}, {0xc78, 0x41690001},
593 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
594 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
595 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
596 {0xc78, 0x21700001}, {0xc78, 0x20710001},
597 {0xc78, 0x06720001}, {0xc78, 0x05730001},
598 {0xc78, 0x04740001}, {0xc78, 0x03750001},
599 {0xc78, 0x02760001}, {0xc78, 0x01770001},
600 {0xc78, 0x00780001}, {0xc78, 0x00790001},
601 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
602 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
603 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
604 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
605 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
606 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
607 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
608 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
609 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
610 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
611 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
612 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
613 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
614 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
615 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
616 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
617 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
618 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
619 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
620 {0xffff, 0xffffffff}
621 };
622
623 static const struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
624 { /* RF_A */
625 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
626 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
627 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
628 .hspiread = REG_HSPI_XA_READBACK,
629 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
630 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
631 },
632 { /* RF_B */
633 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
634 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
635 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
636 .hspiread = REG_HSPI_XB_READBACK,
637 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
638 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
639 },
640 };
641
642 const u32 rtl8xxxu_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
643 REG_OFDM0_XA_RX_IQ_IMBALANCE,
644 REG_OFDM0_XB_RX_IQ_IMBALANCE,
645 REG_OFDM0_ENERGY_CCA_THRES,
646 REG_OFDM0_AGC_RSSI_TABLE,
647 REG_OFDM0_XA_TX_IQ_IMBALANCE,
648 REG_OFDM0_XB_TX_IQ_IMBALANCE,
649 REG_OFDM0_XC_TX_AFE,
650 REG_OFDM0_XD_TX_AFE,
651 REG_OFDM0_RX_IQ_EXT_ANTA
652 };
653
rtl8xxxu_read8(struct rtl8xxxu_priv * priv,u16 addr)654 u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
655 {
656 struct usb_device *udev = priv->udev;
657 int len;
658 u8 data;
659
660 if (priv->rtl_chip == RTL8710B && addr <= 0xff)
661 addr |= 0x8000;
662
663 mutex_lock(&priv->usb_buf_mutex);
664 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
665 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
666 addr, 0, &priv->usb_buf.val8, sizeof(u8),
667 RTW_USB_CONTROL_MSG_TIMEOUT);
668 data = priv->usb_buf.val8;
669 mutex_unlock(&priv->usb_buf_mutex);
670
671 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
672 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",
673 __func__, addr, data, len);
674 return data;
675 }
676
rtl8xxxu_read16(struct rtl8xxxu_priv * priv,u16 addr)677 u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
678 {
679 struct usb_device *udev = priv->udev;
680 int len;
681 u16 data;
682
683 if (priv->rtl_chip == RTL8710B && addr <= 0xff)
684 addr |= 0x8000;
685
686 mutex_lock(&priv->usb_buf_mutex);
687 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
688 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
689 addr, 0, &priv->usb_buf.val16, sizeof(u16),
690 RTW_USB_CONTROL_MSG_TIMEOUT);
691 data = le16_to_cpu(priv->usb_buf.val16);
692 mutex_unlock(&priv->usb_buf_mutex);
693
694 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
695 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",
696 __func__, addr, data, len);
697 return data;
698 }
699
rtl8xxxu_read32(struct rtl8xxxu_priv * priv,u16 addr)700 u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
701 {
702 struct usb_device *udev = priv->udev;
703 int len;
704 u32 data;
705
706 if (priv->rtl_chip == RTL8710B && addr <= 0xff)
707 addr |= 0x8000;
708
709 mutex_lock(&priv->usb_buf_mutex);
710 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
711 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
712 addr, 0, &priv->usb_buf.val32, sizeof(u32),
713 RTW_USB_CONTROL_MSG_TIMEOUT);
714 data = le32_to_cpu(priv->usb_buf.val32);
715 mutex_unlock(&priv->usb_buf_mutex);
716
717 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
718 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",
719 __func__, addr, data, len);
720 return data;
721 }
722
rtl8xxxu_write8(struct rtl8xxxu_priv * priv,u16 addr,u8 val)723 int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
724 {
725 struct usb_device *udev = priv->udev;
726 int ret;
727
728 if (priv->rtl_chip == RTL8710B && addr <= 0xff)
729 addr |= 0x8000;
730
731 mutex_lock(&priv->usb_buf_mutex);
732 priv->usb_buf.val8 = val;
733 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
734 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
735 addr, 0, &priv->usb_buf.val8, sizeof(u8),
736 RTW_USB_CONTROL_MSG_TIMEOUT);
737
738 mutex_unlock(&priv->usb_buf_mutex);
739
740 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
741 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
742 __func__, addr, val);
743 return ret;
744 }
745
rtl8xxxu_write16(struct rtl8xxxu_priv * priv,u16 addr,u16 val)746 int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
747 {
748 struct usb_device *udev = priv->udev;
749 int ret;
750
751 if (priv->rtl_chip == RTL8710B && addr <= 0xff)
752 addr |= 0x8000;
753
754 mutex_lock(&priv->usb_buf_mutex);
755 priv->usb_buf.val16 = cpu_to_le16(val);
756 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
757 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
758 addr, 0, &priv->usb_buf.val16, sizeof(u16),
759 RTW_USB_CONTROL_MSG_TIMEOUT);
760 mutex_unlock(&priv->usb_buf_mutex);
761
762 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
763 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
764 __func__, addr, val);
765 return ret;
766 }
767
rtl8xxxu_write32(struct rtl8xxxu_priv * priv,u16 addr,u32 val)768 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
769 {
770 struct usb_device *udev = priv->udev;
771 int ret;
772
773 if (priv->rtl_chip == RTL8710B && addr <= 0xff)
774 addr |= 0x8000;
775
776 mutex_lock(&priv->usb_buf_mutex);
777 priv->usb_buf.val32 = cpu_to_le32(val);
778 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
779 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
780 addr, 0, &priv->usb_buf.val32, sizeof(u32),
781 RTW_USB_CONTROL_MSG_TIMEOUT);
782 mutex_unlock(&priv->usb_buf_mutex);
783
784 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
785 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
786 __func__, addr, val);
787 return ret;
788 }
789
rtl8xxxu_write8_set(struct rtl8xxxu_priv * priv,u16 addr,u8 bits)790 int rtl8xxxu_write8_set(struct rtl8xxxu_priv *priv, u16 addr, u8 bits)
791 {
792 u8 val8;
793
794 val8 = rtl8xxxu_read8(priv, addr);
795 val8 |= bits;
796 return rtl8xxxu_write8(priv, addr, val8);
797 }
798
rtl8xxxu_write8_clear(struct rtl8xxxu_priv * priv,u16 addr,u8 bits)799 int rtl8xxxu_write8_clear(struct rtl8xxxu_priv *priv, u16 addr, u8 bits)
800 {
801 u8 val8;
802
803 val8 = rtl8xxxu_read8(priv, addr);
804 val8 &= ~bits;
805 return rtl8xxxu_write8(priv, addr, val8);
806 }
807
rtl8xxxu_write16_set(struct rtl8xxxu_priv * priv,u16 addr,u16 bits)808 int rtl8xxxu_write16_set(struct rtl8xxxu_priv *priv, u16 addr, u16 bits)
809 {
810 u16 val16;
811
812 val16 = rtl8xxxu_read16(priv, addr);
813 val16 |= bits;
814 return rtl8xxxu_write16(priv, addr, val16);
815 }
816
rtl8xxxu_write16_clear(struct rtl8xxxu_priv * priv,u16 addr,u16 bits)817 int rtl8xxxu_write16_clear(struct rtl8xxxu_priv *priv, u16 addr, u16 bits)
818 {
819 u16 val16;
820
821 val16 = rtl8xxxu_read16(priv, addr);
822 val16 &= ~bits;
823 return rtl8xxxu_write16(priv, addr, val16);
824 }
825
rtl8xxxu_write32_set(struct rtl8xxxu_priv * priv,u16 addr,u32 bits)826 int rtl8xxxu_write32_set(struct rtl8xxxu_priv *priv, u16 addr, u32 bits)
827 {
828 u32 val32;
829
830 val32 = rtl8xxxu_read32(priv, addr);
831 val32 |= bits;
832 return rtl8xxxu_write32(priv, addr, val32);
833 }
834
rtl8xxxu_write32_clear(struct rtl8xxxu_priv * priv,u16 addr,u32 bits)835 int rtl8xxxu_write32_clear(struct rtl8xxxu_priv *priv, u16 addr, u32 bits)
836 {
837 u32 val32;
838
839 val32 = rtl8xxxu_read32(priv, addr);
840 val32 &= ~bits;
841 return rtl8xxxu_write32(priv, addr, val32);
842 }
843
rtl8xxxu_write32_mask(struct rtl8xxxu_priv * priv,u16 addr,u32 mask,u32 val)844 int rtl8xxxu_write32_mask(struct rtl8xxxu_priv *priv, u16 addr,
845 u32 mask, u32 val)
846 {
847 u32 orig, new, shift;
848
849 shift = __ffs(mask);
850
851 orig = rtl8xxxu_read32(priv, addr);
852 new = (orig & ~mask) | ((val << shift) & mask);
853 return rtl8xxxu_write32(priv, addr, new);
854 }
855
rtl8xxxu_write_rfreg_mask(struct rtl8xxxu_priv * priv,enum rtl8xxxu_rfpath path,u8 reg,u32 mask,u32 val)856 int rtl8xxxu_write_rfreg_mask(struct rtl8xxxu_priv *priv,
857 enum rtl8xxxu_rfpath path, u8 reg,
858 u32 mask, u32 val)
859 {
860 u32 orig, new, shift;
861
862 shift = __ffs(mask);
863
864 orig = rtl8xxxu_read_rfreg(priv, path, reg);
865 new = (orig & ~mask) | ((val << shift) & mask);
866 return rtl8xxxu_write_rfreg(priv, path, reg, new);
867 }
868
869 static int
rtl8xxxu_writeN(struct rtl8xxxu_priv * priv,u16 addr,u8 * buf,u16 len)870 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
871 {
872 struct usb_device *udev = priv->udev;
873 int blocksize = priv->fops->writeN_block_size;
874 int ret, i, count, remainder;
875
876 count = len / blocksize;
877 remainder = len % blocksize;
878
879 for (i = 0; i < count; i++) {
880 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
881 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
882 addr, 0, buf, blocksize,
883 RTW_USB_CONTROL_MSG_TIMEOUT);
884 if (ret != blocksize)
885 goto write_error;
886
887 addr += blocksize;
888 buf += blocksize;
889 }
890
891 if (remainder) {
892 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
893 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
894 addr, 0, buf, remainder,
895 RTW_USB_CONTROL_MSG_TIMEOUT);
896 if (ret != remainder)
897 goto write_error;
898 }
899
900 return len;
901
902 write_error:
903 dev_info(&udev->dev,
904 "%s: Failed to write block at addr: %04x size: %04x\n",
905 __func__, addr, blocksize);
906 return -EAGAIN;
907 }
908
rtl8xxxu_read_rfreg(struct rtl8xxxu_priv * priv,enum rtl8xxxu_rfpath path,u8 reg)909 u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
910 enum rtl8xxxu_rfpath path, u8 reg)
911 {
912 u32 hssia, val32, retval;
913
914 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
915 if (path != RF_A)
916 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
917 else
918 val32 = hssia;
919
920 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
921 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
922 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
923 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
924 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
925
926 udelay(10);
927
928 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
929 udelay(100);
930
931 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
932 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
933 udelay(10);
934
935 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
936 if (val32 & FPGA0_HSSI_PARM1_PI)
937 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
938 else
939 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
940
941 retval &= 0xfffff;
942
943 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
944 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
945 __func__, reg, retval);
946 return retval;
947 }
948
949 /*
950 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
951 * have write issues in high temperature conditions. We may have to
952 * retry writing them.
953 */
rtl8xxxu_write_rfreg(struct rtl8xxxu_priv * priv,enum rtl8xxxu_rfpath path,u8 reg,u32 data)954 int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
955 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
956 {
957 int ret, retval;
958 u32 dataaddr, val32;
959
960 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
961 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
962 __func__, reg, data);
963
964 data &= FPGA0_LSSI_PARM_DATA_MASK;
965 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
966
967 if (priv->rtl_chip == RTL8192E) {
968 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
969 val32 &= ~0x20000;
970 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
971 }
972
973 /* Use XB for path B */
974 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
975 if (ret != sizeof(dataaddr))
976 retval = -EIO;
977 else
978 retval = 0;
979
980 udelay(1);
981
982 if (priv->rtl_chip == RTL8192E) {
983 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
984 val32 |= 0x20000;
985 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
986 }
987
988 return retval;
989 }
990
991 static int
rtl8xxxu_gen1_h2c_cmd(struct rtl8xxxu_priv * priv,struct h2c_cmd * h2c,int len)992 rtl8xxxu_gen1_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len)
993 {
994 struct device *dev = &priv->udev->dev;
995 int mbox_nr, retry, retval = 0;
996 int mbox_reg, mbox_ext_reg;
997 u8 val8;
998
999 mutex_lock(&priv->h2c_mutex);
1000
1001 mbox_nr = priv->next_mbox;
1002 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1003 mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2);
1004
1005 /*
1006 * MBOX ready?
1007 */
1008 retry = 100;
1009 do {
1010 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1011 if (!(val8 & BIT(mbox_nr)))
1012 break;
1013 } while (retry--);
1014
1015 if (!retry) {
1016 dev_info(dev, "%s: Mailbox busy\n", __func__);
1017 retval = -EBUSY;
1018 goto error;
1019 }
1020
1021 /*
1022 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1023 */
1024 if (len > sizeof(u32)) {
1025 rtl8xxxu_write16(priv, mbox_ext_reg, le16_to_cpu(h2c->raw.ext));
1026 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1027 dev_info(dev, "H2C_EXT %04x\n",
1028 le16_to_cpu(h2c->raw.ext));
1029 }
1030 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1031 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1032 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1033
1034 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1035
1036 error:
1037 mutex_unlock(&priv->h2c_mutex);
1038 return retval;
1039 }
1040
1041 int
rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv * priv,struct h2c_cmd * h2c,int len)1042 rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len)
1043 {
1044 struct device *dev = &priv->udev->dev;
1045 int mbox_nr, retry, retval = 0;
1046 int mbox_reg, mbox_ext_reg;
1047 u8 val8;
1048
1049 mutex_lock(&priv->h2c_mutex);
1050
1051 mbox_nr = priv->next_mbox;
1052 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1053 mbox_ext_reg = REG_HMBOX_EXT0_8723B + (mbox_nr * 4);
1054
1055 /*
1056 * MBOX ready?
1057 */
1058 retry = 100;
1059 do {
1060 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1061 if (!(val8 & BIT(mbox_nr)))
1062 break;
1063 } while (retry--);
1064
1065 if (!retry) {
1066 dev_info(dev, "%s: Mailbox busy\n", __func__);
1067 retval = -EBUSY;
1068 goto error;
1069 }
1070
1071 /*
1072 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1073 */
1074 if (len > sizeof(u32)) {
1075 rtl8xxxu_write32(priv, mbox_ext_reg,
1076 le32_to_cpu(h2c->raw_wide.ext));
1077 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1078 dev_info(dev, "H2C_EXT %08x\n",
1079 le32_to_cpu(h2c->raw_wide.ext));
1080 }
1081 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1082 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1083 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1084
1085 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1086
1087 error:
1088 mutex_unlock(&priv->h2c_mutex);
1089 return retval;
1090 }
1091
rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv * priv)1092 void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv)
1093 {
1094 u8 val8;
1095 u32 val32;
1096
1097 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1098 val8 |= BIT(0) | BIT(3);
1099 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1100
1101 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1102 val32 &= ~(BIT(4) | BIT(5));
1103 val32 |= BIT(3);
1104 if (priv->rf_paths == 2) {
1105 val32 &= ~(BIT(20) | BIT(21));
1106 val32 |= BIT(19);
1107 }
1108 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1109
1110 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1111 val32 &= ~OFDM_RF_PATH_TX_MASK;
1112 if (priv->tx_paths == 2)
1113 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1114 else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C)
1115 val32 |= OFDM_RF_PATH_TX_B;
1116 else
1117 val32 |= OFDM_RF_PATH_TX_A;
1118 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1119
1120 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1121 val32 &= ~FPGA_RF_MODE_JAPAN;
1122 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1123
1124 if (priv->rf_paths == 2)
1125 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1126 else
1127 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1128
1129 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1130 if (priv->rf_paths == 2)
1131 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1132
1133 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1134 }
1135
rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv * priv)1136 void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv)
1137 {
1138 u8 sps0;
1139 u32 val32;
1140
1141 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1142
1143 /* RF RX code for preamble power saving */
1144 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1145 val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1146 if (priv->rf_paths == 2)
1147 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1148 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1149
1150 /* Disable TX for four paths */
1151 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1152 val32 &= ~OFDM_RF_PATH_TX_MASK;
1153 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1154
1155 /* Enable power saving */
1156 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1157 val32 |= FPGA_RF_MODE_JAPAN;
1158 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1159
1160 /* AFE control register to power down bits [30:22] */
1161 if (priv->rf_paths == 2)
1162 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1163 else
1164 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1165
1166 /* Power down RF module */
1167 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1168 if (priv->rf_paths == 2)
1169 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1170
1171 sps0 &= ~(BIT(0) | BIT(3));
1172 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1173 }
1174
rtl8xxxu_stop_tx_beacon(struct rtl8xxxu_priv * priv)1175 static void rtl8xxxu_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1176 {
1177 u8 val8;
1178
1179 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1180 val8 &= ~BIT(6);
1181 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1182
1183 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1184 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1185 val8 &= ~BIT(0);
1186 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1187 }
1188
rtl8xxxu_start_tx_beacon(struct rtl8xxxu_priv * priv)1189 static void rtl8xxxu_start_tx_beacon(struct rtl8xxxu_priv *priv)
1190 {
1191 u8 val8;
1192
1193 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1194 val8 |= EN_BCNQ_DL >> 16;
1195 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1196
1197 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x80);
1198 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1199 val8 &= 0xF0;
1200 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1201 }
1202
1203
1204 /*
1205 * The rtl8723a has 3 channel groups for it's efuse settings. It only
1206 * supports the 2.4GHz band, so channels 1 - 14:
1207 * group 0: channels 1 - 3
1208 * group 1: channels 4 - 9
1209 * group 2: channels 10 - 14
1210 *
1211 * Note: We index from 0 in the code
1212 */
rtl8xxxu_gen1_channel_to_group(int channel)1213 static int rtl8xxxu_gen1_channel_to_group(int channel)
1214 {
1215 int group;
1216
1217 if (channel < 4)
1218 group = 0;
1219 else if (channel < 10)
1220 group = 1;
1221 else
1222 group = 2;
1223
1224 return group;
1225 }
1226
1227 /*
1228 * Valid for rtl8723bu and rtl8192eu
1229 */
rtl8xxxu_gen2_channel_to_group(int channel)1230 int rtl8xxxu_gen2_channel_to_group(int channel)
1231 {
1232 int group;
1233
1234 if (channel < 3)
1235 group = 0;
1236 else if (channel < 6)
1237 group = 1;
1238 else if (channel < 9)
1239 group = 2;
1240 else if (channel < 12)
1241 group = 3;
1242 else
1243 group = 4;
1244
1245 return group;
1246 }
1247
rtl8xxxu_gen1_config_channel(struct ieee80211_hw * hw)1248 void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw)
1249 {
1250 struct rtl8xxxu_priv *priv = hw->priv;
1251 u32 val32, rsr;
1252 u8 val8, opmode;
1253 bool ht = true;
1254 int sec_ch_above, channel;
1255 int i;
1256
1257 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1258 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1259 channel = hw->conf.chandef.chan->hw_value;
1260
1261 switch (hw->conf.chandef.width) {
1262 case NL80211_CHAN_WIDTH_20_NOHT:
1263 ht = false;
1264 fallthrough;
1265 case NL80211_CHAN_WIDTH_20:
1266 opmode |= BW_OPMODE_20MHZ;
1267 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1268
1269 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1270 val32 &= ~FPGA_RF_MODE;
1271 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1272
1273 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1274 val32 &= ~FPGA_RF_MODE;
1275 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1276
1277 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1278 val32 |= FPGA0_ANALOG2_20MHZ;
1279 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1280 break;
1281 case NL80211_CHAN_WIDTH_40:
1282 if (hw->conf.chandef.center_freq1 >
1283 hw->conf.chandef.chan->center_freq) {
1284 sec_ch_above = 1;
1285 channel += 2;
1286 } else {
1287 sec_ch_above = 0;
1288 channel -= 2;
1289 }
1290
1291 opmode &= ~BW_OPMODE_20MHZ;
1292 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1293 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1294 if (sec_ch_above)
1295 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1296 else
1297 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1298 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1299
1300 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1301 val32 |= FPGA_RF_MODE;
1302 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1303
1304 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1305 val32 |= FPGA_RF_MODE;
1306 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1307
1308 /*
1309 * Set Control channel to upper or lower. These settings
1310 * are required only for 40MHz
1311 */
1312 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1313 val32 &= ~CCK0_SIDEBAND;
1314 if (!sec_ch_above)
1315 val32 |= CCK0_SIDEBAND;
1316 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1317
1318 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1319 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1320 if (sec_ch_above)
1321 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1322 else
1323 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1324 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1325
1326 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1327 val32 &= ~FPGA0_ANALOG2_20MHZ;
1328 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1329
1330 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1331 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1332 if (sec_ch_above)
1333 val32 |= FPGA0_PS_UPPER_CHANNEL;
1334 else
1335 val32 |= FPGA0_PS_LOWER_CHANNEL;
1336 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1337 break;
1338
1339 default:
1340 break;
1341 }
1342
1343 for (i = RF_A; i < priv->rf_paths; i++) {
1344 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1345 val32 &= ~MODE_AG_CHANNEL_MASK;
1346 val32 |= channel;
1347 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1348 }
1349
1350 if (ht)
1351 val8 = 0x0e;
1352 else
1353 val8 = 0x0a;
1354
1355 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1356 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1357
1358 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1359 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1360
1361 for (i = RF_A; i < priv->rf_paths; i++) {
1362 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1363 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1364 val32 &= ~MODE_AG_CHANNEL_20MHZ;
1365 else
1366 val32 |= MODE_AG_CHANNEL_20MHZ;
1367 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1368 }
1369 }
1370
rtl8xxxu_gen2_config_channel(struct ieee80211_hw * hw)1371 void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw)
1372 {
1373 struct rtl8xxxu_priv *priv = hw->priv;
1374 u32 val32;
1375 u8 val8, subchannel;
1376 u16 rf_mode_bw;
1377 bool ht = true;
1378 int sec_ch_above, channel;
1379 int i;
1380
1381 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);
1382 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK;
1383 channel = hw->conf.chandef.chan->hw_value;
1384
1385 /* Hack */
1386 subchannel = 0;
1387
1388 switch (hw->conf.chandef.width) {
1389 case NL80211_CHAN_WIDTH_20_NOHT:
1390 ht = false;
1391 fallthrough;
1392 case NL80211_CHAN_WIDTH_20:
1393 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20;
1394 subchannel = 0;
1395
1396 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1397 val32 &= ~FPGA_RF_MODE;
1398 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1399
1400 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1401 val32 &= ~FPGA_RF_MODE;
1402 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1403
1404 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
1405 val32 &= ~(BIT(30) | BIT(31));
1406 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
1407
1408 break;
1409 case NL80211_CHAN_WIDTH_40:
1410 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40;
1411
1412 if (hw->conf.chandef.center_freq1 >
1413 hw->conf.chandef.chan->center_freq) {
1414 sec_ch_above = 1;
1415 channel += 2;
1416 } else {
1417 sec_ch_above = 0;
1418 channel -= 2;
1419 }
1420
1421 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1422 val32 |= FPGA_RF_MODE;
1423 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1424
1425 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1426 val32 |= FPGA_RF_MODE;
1427 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1428
1429 /*
1430 * Set Control channel to upper or lower. These settings
1431 * are required only for 40MHz
1432 */
1433 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1434 val32 &= ~CCK0_SIDEBAND;
1435 if (!sec_ch_above)
1436 val32 |= CCK0_SIDEBAND;
1437 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1438
1439 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1440 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1441 if (sec_ch_above)
1442 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1443 else
1444 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1445 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1446
1447 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1448 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1449 if (sec_ch_above)
1450 val32 |= FPGA0_PS_UPPER_CHANNEL;
1451 else
1452 val32 |= FPGA0_PS_LOWER_CHANNEL;
1453 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1454 break;
1455 case NL80211_CHAN_WIDTH_80:
1456 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80;
1457 break;
1458 default:
1459 break;
1460 }
1461
1462 for (i = RF_A; i < priv->rf_paths; i++) {
1463 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1464 val32 &= ~MODE_AG_CHANNEL_MASK;
1465 val32 |= channel;
1466 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1467 }
1468
1469 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw);
1470 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);
1471
1472 if (ht)
1473 val8 = 0x0e;
1474 else
1475 val8 = 0x0a;
1476
1477 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1478 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1479
1480 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1481 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1482
1483 for (i = RF_A; i < priv->rf_paths; i++) {
1484 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1485 val32 &= ~MODE_AG_BW_MASK;
1486 switch(hw->conf.chandef.width) {
1487 case NL80211_CHAN_WIDTH_80:
1488 val32 |= MODE_AG_BW_80MHZ_8723B;
1489 break;
1490 case NL80211_CHAN_WIDTH_40:
1491 val32 |= MODE_AG_BW_40MHZ_8723B;
1492 break;
1493 default:
1494 val32 |= MODE_AG_BW_20MHZ_8723B;
1495 break;
1496 }
1497 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1498 }
1499 }
1500
1501 void
rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv * priv,int channel,bool ht40)1502 rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1503 {
1504 struct rtl8xxxu_power_base *power_base = priv->power_base;
1505 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1506 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1507 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1508 u8 val8, base;
1509 int group, i;
1510
1511 group = rtl8xxxu_gen1_channel_to_group(channel);
1512
1513 cck[0] = priv->cck_tx_power_index_A[group];
1514 cck[1] = priv->cck_tx_power_index_B[group];
1515
1516 if (priv->hi_pa) {
1517 if (cck[0] > 0x20)
1518 cck[0] = 0x20;
1519 if (cck[1] > 0x20)
1520 cck[1] = 0x20;
1521 }
1522
1523 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1524 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1525
1526 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1527 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1528
1529 mcsbase[0] = ofdm[0];
1530 mcsbase[1] = ofdm[1];
1531 if (!ht40) {
1532 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1533 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1534 }
1535
1536 if (priv->tx_paths > 1) {
1537 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1538 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;
1539 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1540 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;
1541 }
1542
1543 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1544 dev_info(&priv->udev->dev,
1545 "%s: Setting TX power CCK A: %02x, "
1546 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1547 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1548
1549 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1550 if (cck[i] > RF6052_MAX_TX_PWR)
1551 cck[i] = RF6052_MAX_TX_PWR;
1552 if (ofdm[i] > RF6052_MAX_TX_PWR)
1553 ofdm[i] = RF6052_MAX_TX_PWR;
1554 }
1555
1556 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1557 val32 &= 0xffff00ff;
1558 val32 |= (cck[0] << 8);
1559 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1560
1561 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1562 val32 &= 0xff;
1563 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1564 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1565
1566 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1567 val32 &= 0xffffff00;
1568 val32 |= cck[1];
1569 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1570
1571 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1572 val32 &= 0xff;
1573 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1574 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1575
1576 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1577 ofdmbase[0] << 16 | ofdmbase[0] << 24;
1578 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
1579 ofdmbase[1] << 16 | ofdmbase[1] << 24;
1580
1581 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06,
1582 ofdm_a + power_base->reg_0e00);
1583 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06,
1584 ofdm_b + power_base->reg_0830);
1585
1586 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24,
1587 ofdm_a + power_base->reg_0e04);
1588 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24,
1589 ofdm_b + power_base->reg_0834);
1590
1591 mcs_a = mcsbase[0] | mcsbase[0] << 8 |
1592 mcsbase[0] << 16 | mcsbase[0] << 24;
1593 mcs_b = mcsbase[1] | mcsbase[1] << 8 |
1594 mcsbase[1] << 16 | mcsbase[1] << 24;
1595
1596 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00,
1597 mcs_a + power_base->reg_0e10);
1598 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00,
1599 mcs_b + power_base->reg_083c);
1600
1601 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04,
1602 mcs_a + power_base->reg_0e14);
1603 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04,
1604 mcs_b + power_base->reg_0848);
1605
1606 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08,
1607 mcs_a + power_base->reg_0e18);
1608 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08,
1609 mcs_b + power_base->reg_084c);
1610
1611 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12,
1612 mcs_a + power_base->reg_0e1c);
1613 val8 = u32_get_bits(mcs_a + power_base->reg_0e1c, 0xff000000);
1614 for (i = 0; i < 3; i++) {
1615 base = i != 2 ? 8 : 6;
1616 val8 = max_t(int, val8 - base, 0);
1617 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
1618 }
1619
1620 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12,
1621 mcs_b + power_base->reg_0868);
1622 val8 = u32_get_bits(mcs_b + power_base->reg_0868, 0xff000000);
1623 for (i = 0; i < 3; i++) {
1624 base = i != 2 ? 8 : 6;
1625 val8 = max_t(int, val8 - base, 0);
1626 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
1627 }
1628 }
1629
rtl8xxxu_set_linktype(struct rtl8xxxu_priv * priv,enum nl80211_iftype linktype)1630 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
1631 enum nl80211_iftype linktype)
1632 {
1633 u8 val8;
1634
1635 val8 = rtl8xxxu_read8(priv, REG_MSR);
1636 val8 &= ~MSR_LINKTYPE_MASK;
1637
1638 switch (linktype) {
1639 case NL80211_IFTYPE_UNSPECIFIED:
1640 val8 |= MSR_LINKTYPE_NONE;
1641 break;
1642 case NL80211_IFTYPE_ADHOC:
1643 val8 |= MSR_LINKTYPE_ADHOC;
1644 break;
1645 case NL80211_IFTYPE_STATION:
1646 val8 |= MSR_LINKTYPE_STATION;
1647 break;
1648 case NL80211_IFTYPE_AP:
1649 val8 |= MSR_LINKTYPE_AP;
1650 break;
1651 default:
1652 goto out;
1653 }
1654
1655 rtl8xxxu_write8(priv, REG_MSR, val8);
1656 out:
1657 return;
1658 }
1659
1660 static void
rtl8xxxu_set_retry(struct rtl8xxxu_priv * priv,u16 short_retry,u16 long_retry)1661 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
1662 {
1663 u16 val16;
1664
1665 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
1666 RETRY_LIMIT_SHORT_MASK) |
1667 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
1668 RETRY_LIMIT_LONG_MASK);
1669
1670 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
1671 }
1672
1673 static void
rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv * priv,u16 cck,u16 ofdm)1674 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
1675 {
1676 u16 val16;
1677
1678 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
1679 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
1680
1681 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
1682 }
1683
rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv * priv)1684 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
1685 {
1686 struct device *dev = &priv->udev->dev;
1687 char cut = 'A' + priv->chip_cut;
1688
1689 dev_info(dev,
1690 "RTL%s rev %c (%s) romver %d, %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
1691 priv->chip_name, cut, priv->chip_vendor, priv->rom_rev,
1692 priv->tx_paths, priv->rx_paths, priv->ep_tx_count,
1693 priv->has_wifi, priv->has_bluetooth, priv->has_gps,
1694 priv->hi_pa);
1695
1696 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
1697 }
1698
rtl8xxxu_identify_vendor_1bit(struct rtl8xxxu_priv * priv,u32 vendor)1699 void rtl8xxxu_identify_vendor_1bit(struct rtl8xxxu_priv *priv, u32 vendor)
1700 {
1701 if (vendor) {
1702 strscpy(priv->chip_vendor, "UMC", sizeof(priv->chip_vendor));
1703 priv->vendor_umc = 1;
1704 } else {
1705 strscpy(priv->chip_vendor, "TSMC", sizeof(priv->chip_vendor));
1706 }
1707 }
1708
rtl8xxxu_identify_vendor_2bits(struct rtl8xxxu_priv * priv,u32 vendor)1709 void rtl8xxxu_identify_vendor_2bits(struct rtl8xxxu_priv *priv, u32 vendor)
1710 {
1711 switch (vendor) {
1712 case SYS_CFG_VENDOR_ID_TSMC:
1713 strscpy(priv->chip_vendor, "TSMC", sizeof(priv->chip_vendor));
1714 break;
1715 case SYS_CFG_VENDOR_ID_SMIC:
1716 strscpy(priv->chip_vendor, "SMIC", sizeof(priv->chip_vendor));
1717 priv->vendor_smic = 1;
1718 break;
1719 case SYS_CFG_VENDOR_ID_UMC:
1720 strscpy(priv->chip_vendor, "UMC", sizeof(priv->chip_vendor));
1721 priv->vendor_umc = 1;
1722 break;
1723 default:
1724 strscpy(priv->chip_vendor, "unknown", sizeof(priv->chip_vendor));
1725 }
1726 }
1727
rtl8xxxu_config_endpoints_sie(struct rtl8xxxu_priv * priv)1728 void rtl8xxxu_config_endpoints_sie(struct rtl8xxxu_priv *priv)
1729 {
1730 u16 val16;
1731
1732 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
1733
1734 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
1735 priv->ep_tx_high_queue = 1;
1736 priv->ep_tx_count++;
1737 }
1738
1739 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
1740 priv->ep_tx_normal_queue = 1;
1741 priv->ep_tx_count++;
1742 }
1743
1744 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
1745 priv->ep_tx_low_queue = 1;
1746 priv->ep_tx_count++;
1747 }
1748 }
1749
rtl8xxxu_config_endpoints_no_sie(struct rtl8xxxu_priv * priv)1750 int rtl8xxxu_config_endpoints_no_sie(struct rtl8xxxu_priv *priv)
1751 {
1752 struct device *dev = &priv->udev->dev;
1753
1754 switch (priv->nr_out_eps) {
1755 case 6:
1756 case 5:
1757 case 4:
1758 case 3:
1759 priv->ep_tx_low_queue = 1;
1760 priv->ep_tx_count++;
1761 fallthrough;
1762 case 2:
1763 priv->ep_tx_normal_queue = 1;
1764 priv->ep_tx_count++;
1765 fallthrough;
1766 case 1:
1767 priv->ep_tx_high_queue = 1;
1768 priv->ep_tx_count++;
1769 break;
1770 default:
1771 dev_info(dev, "Unsupported USB TX end-points\n");
1772 return -ENOTSUPP;
1773 }
1774
1775 return 0;
1776 }
1777
1778 int
rtl8xxxu_read_efuse8(struct rtl8xxxu_priv * priv,u16 offset,u8 * data)1779 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
1780 {
1781 int i;
1782 u8 val8;
1783 u32 val32;
1784
1785 /* Write Address */
1786 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
1787 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
1788 val8 &= 0xfc;
1789 val8 |= (offset >> 8) & 0x03;
1790 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
1791
1792 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
1793 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
1794
1795 /* Poll for data read */
1796 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1797 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
1798 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1799 if (val32 & BIT(31))
1800 break;
1801 }
1802
1803 if (i == RTL8XXXU_MAX_REG_POLL)
1804 return -EIO;
1805
1806 udelay(50);
1807 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1808
1809 *data = val32 & 0xff;
1810 return 0;
1811 }
1812
rtl8xxxu_read_efuse(struct rtl8xxxu_priv * priv)1813 int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
1814 {
1815 struct device *dev = &priv->udev->dev;
1816 int i, ret = 0;
1817 u8 val8, word_mask, header, extheader;
1818 u16 val16, efuse_addr, offset;
1819 u32 val32;
1820
1821 val16 = rtl8xxxu_read16(priv, REG_9346CR);
1822 if (val16 & EEPROM_ENABLE)
1823 priv->has_eeprom = 1;
1824 if (val16 & EEPROM_BOOT)
1825 priv->boot_eeprom = 1;
1826
1827 if (priv->is_multi_func) {
1828 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
1829 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
1830 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
1831 }
1832
1833 dev_dbg(dev, "Booting from %s\n",
1834 priv->boot_eeprom ? "EEPROM" : "EFUSE");
1835
1836 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
1837
1838 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
1839 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
1840 if (!(val16 & SYS_ISO_PWC_EV12V)) {
1841 val16 |= SYS_ISO_PWC_EV12V;
1842 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
1843 }
1844 /* Reset: 0x0000[28], default valid */
1845 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1846 if (!(val16 & SYS_FUNC_ELDR)) {
1847 val16 |= SYS_FUNC_ELDR;
1848 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1849 }
1850
1851 /*
1852 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
1853 */
1854 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
1855 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
1856 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
1857 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
1858 }
1859
1860 /* Default value is 0xff */
1861 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
1862
1863 efuse_addr = 0;
1864 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
1865 u16 map_addr;
1866
1867 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
1868 if (ret || header == 0xff)
1869 goto exit;
1870
1871 if ((header & 0x1f) == 0x0f) { /* extended header */
1872 offset = (header & 0xe0) >> 5;
1873
1874 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
1875 &extheader);
1876 if (ret)
1877 goto exit;
1878 /* All words disabled */
1879 if ((extheader & 0x0f) == 0x0f)
1880 continue;
1881
1882 offset |= ((extheader & 0xf0) >> 1);
1883 word_mask = extheader & 0x0f;
1884 } else {
1885 offset = (header >> 4) & 0x0f;
1886 word_mask = header & 0x0f;
1887 }
1888
1889 /* Get word enable value from PG header */
1890
1891 /* We have 8 bits to indicate validity */
1892 map_addr = offset * 8;
1893 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
1894 /* Check word enable condition in the section */
1895 if (word_mask & BIT(i)) {
1896 map_addr += 2;
1897 continue;
1898 }
1899
1900 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
1901 if (ret)
1902 goto exit;
1903 if (map_addr >= EFUSE_MAP_LEN - 1) {
1904 dev_warn(dev, "%s: Illegal map_addr (%04x), "
1905 "efuse corrupt!\n",
1906 __func__, map_addr);
1907 ret = -EINVAL;
1908 goto exit;
1909 }
1910 priv->efuse_wifi.raw[map_addr++] = val8;
1911
1912 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
1913 if (ret)
1914 goto exit;
1915 priv->efuse_wifi.raw[map_addr++] = val8;
1916 }
1917 }
1918
1919 exit:
1920 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
1921
1922 return ret;
1923 }
1924
rtl8xxxu_dump_efuse(struct rtl8xxxu_priv * priv)1925 static void rtl8xxxu_dump_efuse(struct rtl8xxxu_priv *priv)
1926 {
1927 dev_info(&priv->udev->dev,
1928 "Dumping efuse for RTL%s (0x%02x bytes):\n",
1929 priv->chip_name, EFUSE_MAP_LEN);
1930
1931 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
1932 priv->efuse_wifi.raw, EFUSE_MAP_LEN, true);
1933 }
1934
rtl8xxxu_reset_8051(struct rtl8xxxu_priv * priv)1935 void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
1936 {
1937 u8 val8;
1938 u16 sys_func;
1939
1940 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
1941 val8 &= ~BIT(0);
1942 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
1943
1944 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1945 sys_func &= ~SYS_FUNC_CPU_ENABLE;
1946 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
1947
1948 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
1949 val8 |= BIT(0);
1950 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
1951
1952 sys_func |= SYS_FUNC_CPU_ENABLE;
1953 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
1954 }
1955
rtl8xxxu_start_firmware(struct rtl8xxxu_priv * priv)1956 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
1957 {
1958 struct device *dev = &priv->udev->dev;
1959 u16 reg_mcu_fw_dl;
1960 int ret = 0, i;
1961 u32 val32;
1962
1963 if (priv->rtl_chip == RTL8710B)
1964 reg_mcu_fw_dl = REG_8051FW_CTRL_V1_8710B;
1965 else
1966 reg_mcu_fw_dl = REG_MCU_FW_DL;
1967
1968 /* Poll checksum report */
1969 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
1970 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl);
1971 if (val32 & MCU_FW_DL_CSUM_REPORT)
1972 break;
1973 }
1974
1975 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
1976 dev_warn(dev, "Firmware checksum poll timed out\n");
1977 ret = -EAGAIN;
1978 goto exit;
1979 }
1980
1981 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl);
1982 val32 |= MCU_FW_DL_READY;
1983 val32 &= ~MCU_WINT_INIT_READY;
1984 rtl8xxxu_write32(priv, reg_mcu_fw_dl, val32);
1985
1986 /*
1987 * Reset the 8051 in order for the firmware to start running,
1988 * otherwise it won't come up on the 8192eu
1989 */
1990 priv->fops->reset_8051(priv);
1991
1992 /* Wait for firmware to become ready */
1993 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
1994 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl);
1995 if (val32 & MCU_WINT_INIT_READY)
1996 break;
1997
1998 udelay(100);
1999 }
2000
2001 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2002 dev_warn(dev, "Firmware failed to start\n");
2003 ret = -EAGAIN;
2004 goto exit;
2005 }
2006
2007 /*
2008 * Init H2C command
2009 */
2010 if (priv->fops->init_reg_hmtfr)
2011 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f);
2012 exit:
2013 return ret;
2014 }
2015
rtl8xxxu_download_firmware(struct rtl8xxxu_priv * priv)2016 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2017 {
2018 int pages, remainder, i, ret;
2019 u16 reg_fw_start_address;
2020 u16 reg_mcu_fw_dl;
2021 u8 val8;
2022 u16 val16;
2023 u32 val32;
2024 u8 *fwptr;
2025
2026 if (priv->rtl_chip == RTL8192F)
2027 reg_fw_start_address = REG_FW_START_ADDRESS_8192F;
2028 else
2029 reg_fw_start_address = REG_FW_START_ADDRESS;
2030
2031 if (priv->rtl_chip == RTL8710B) {
2032 reg_mcu_fw_dl = REG_8051FW_CTRL_V1_8710B;
2033 } else {
2034 reg_mcu_fw_dl = REG_MCU_FW_DL;
2035
2036 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2037 val8 |= 4;
2038 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2039
2040 /* 8051 enable */
2041 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2042 val16 |= SYS_FUNC_CPU_ENABLE;
2043 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2044 }
2045
2046 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl);
2047 if (val8 & MCU_FW_RAM_SEL) {
2048 dev_info(&priv->udev->dev,
2049 "Firmware is already running, resetting the MCU.\n");
2050 rtl8xxxu_write8(priv, reg_mcu_fw_dl, 0x00);
2051 priv->fops->reset_8051(priv);
2052 }
2053
2054 /* MCU firmware download enable */
2055 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl);
2056 val8 |= MCU_FW_DL_ENABLE;
2057 rtl8xxxu_write8(priv, reg_mcu_fw_dl, val8);
2058
2059 /* 8051 reset */
2060 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl);
2061 val32 &= ~BIT(19);
2062 rtl8xxxu_write32(priv, reg_mcu_fw_dl, val32);
2063
2064 if (priv->rtl_chip == RTL8710B) {
2065 /* We must set 0x8090[8]=1 before download FW. */
2066 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 1);
2067 val8 |= BIT(0);
2068 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 1, val8);
2069 }
2070
2071 /* Reset firmware download checksum */
2072 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl);
2073 val8 |= MCU_FW_DL_CSUM_REPORT;
2074 rtl8xxxu_write8(priv, reg_mcu_fw_dl, val8);
2075
2076 pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2077 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2078
2079 fwptr = priv->fw_data->data;
2080
2081 for (i = 0; i < pages; i++) {
2082 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 2) & 0xF8;
2083 val8 |= i;
2084 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 2, val8);
2085
2086 ret = rtl8xxxu_writeN(priv, reg_fw_start_address,
2087 fwptr, RTL_FW_PAGE_SIZE);
2088 if (ret != RTL_FW_PAGE_SIZE) {
2089 ret = -EAGAIN;
2090 goto fw_abort;
2091 }
2092
2093 fwptr += RTL_FW_PAGE_SIZE;
2094 }
2095
2096 if (remainder) {
2097 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 2) & 0xF8;
2098 val8 |= i;
2099 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 2, val8);
2100 ret = rtl8xxxu_writeN(priv, reg_fw_start_address,
2101 fwptr, remainder);
2102 if (ret != remainder) {
2103 ret = -EAGAIN;
2104 goto fw_abort;
2105 }
2106 }
2107
2108 ret = 0;
2109 fw_abort:
2110 /* MCU firmware download disable */
2111 val16 = rtl8xxxu_read16(priv, reg_mcu_fw_dl);
2112 val16 &= ~MCU_FW_DL_ENABLE;
2113 rtl8xxxu_write16(priv, reg_mcu_fw_dl, val16);
2114
2115 return ret;
2116 }
2117
rtl8xxxu_load_firmware(struct rtl8xxxu_priv * priv,const char * fw_name)2118 int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, const char *fw_name)
2119 {
2120 struct device *dev = &priv->udev->dev;
2121 const struct firmware *fw;
2122 int ret = 0;
2123 u16 signature;
2124
2125 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2126 if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2127 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2128 ret = -EAGAIN;
2129 goto exit;
2130 }
2131 if (!fw) {
2132 dev_warn(dev, "Firmware data not available\n");
2133 ret = -EINVAL;
2134 goto exit;
2135 }
2136
2137 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
2138 if (!priv->fw_data) {
2139 ret = -ENOMEM;
2140 goto exit;
2141 }
2142 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2143
2144 signature = le16_to_cpu(priv->fw_data->signature);
2145 switch (signature & 0xfff0) {
2146 case 0x92e0:
2147 case 0x92c0:
2148 case 0x88e0:
2149 case 0x88c0:
2150 case 0x5300:
2151 case 0x2300:
2152 case 0x88f0:
2153 case 0x10b0:
2154 case 0x92f0:
2155 break;
2156 default:
2157 ret = -EINVAL;
2158 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2159 __func__, signature);
2160 }
2161
2162 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2163 le16_to_cpu(priv->fw_data->major_version),
2164 priv->fw_data->minor_version, signature);
2165
2166 exit:
2167 release_firmware(fw);
2168 return ret;
2169 }
2170
rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv * priv)2171 void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2172 {
2173 u16 val16;
2174 int i = 100;
2175
2176 /* Inform 8051 to perform reset */
2177 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2178
2179 for (i = 100; i > 0; i--) {
2180 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2181
2182 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2183 dev_dbg(&priv->udev->dev,
2184 "%s: Firmware self reset success!\n", __func__);
2185 break;
2186 }
2187 udelay(50);
2188 }
2189
2190 if (!i) {
2191 /* Force firmware reset */
2192 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2193 val16 &= ~SYS_FUNC_CPU_ENABLE;
2194 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2195 }
2196 }
2197
2198 static int
rtl8xxxu_init_mac(struct rtl8xxxu_priv * priv)2199 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv)
2200 {
2201 const struct rtl8xxxu_reg8val *array = priv->fops->mactable;
2202 int i, ret;
2203 u16 reg;
2204 u8 val;
2205
2206 for (i = 0; ; i++) {
2207 reg = array[i].reg;
2208 val = array[i].val;
2209
2210 if (reg == 0xffff && val == 0xff)
2211 break;
2212
2213 ret = rtl8xxxu_write8(priv, reg, val);
2214 if (ret != 1) {
2215 dev_warn(&priv->udev->dev,
2216 "Failed to initialize MAC "
2217 "(reg: %04x, val %02x)\n", reg, val);
2218 return -EAGAIN;
2219 }
2220 }
2221
2222 switch (priv->rtl_chip) {
2223 case RTL8188C:
2224 case RTL8188R:
2225 case RTL8191C:
2226 case RTL8192C:
2227 case RTL8723A:
2228 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2229 break;
2230 case RTL8188E:
2231 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0707);
2232 break;
2233 default:
2234 break;
2235 }
2236
2237 return 0;
2238 }
2239
rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv * priv,const struct rtl8xxxu_reg32val * array)2240 int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2241 const struct rtl8xxxu_reg32val *array)
2242 {
2243 int i, ret;
2244 u16 reg;
2245 u32 val;
2246
2247 for (i = 0; ; i++) {
2248 reg = array[i].reg;
2249 val = array[i].val;
2250
2251 if (reg == 0xffff && val == 0xffffffff)
2252 break;
2253
2254 ret = rtl8xxxu_write32(priv, reg, val);
2255 if (ret != sizeof(val)) {
2256 dev_warn(&priv->udev->dev,
2257 "Failed to initialize PHY\n");
2258 return -EAGAIN;
2259 }
2260 udelay(1);
2261 }
2262
2263 return 0;
2264 }
2265
rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv * priv)2266 void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv)
2267 {
2268 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
2269 u16 val16;
2270 u32 val32;
2271
2272 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
2273 udelay(2);
2274 val8 |= AFE_PLL_320_ENABLE;
2275 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
2276 udelay(2);
2277
2278 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
2279 udelay(2);
2280
2281 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2282 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
2283 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2284
2285 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
2286 val32 &= ~AFE_XTAL_RF_GATE;
2287 if (priv->has_bluetooth)
2288 val32 &= ~AFE_XTAL_BT_GATE;
2289 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
2290
2291 /* 6. 0x1f[7:0] = 0x07 */
2292 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
2293 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
2294
2295 if (priv->hi_pa)
2296 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
2297 else if (priv->tx_paths == 2)
2298 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
2299 else
2300 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
2301
2302 if (priv->rtl_chip == RTL8188R && priv->hi_pa &&
2303 priv->vendor_umc && priv->chip_cut == 1)
2304 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
2305
2306 if (priv->hi_pa)
2307 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
2308 else
2309 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
2310
2311 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
2312 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
2313 ldohci12 = 0x57;
2314 lpldo = 1;
2315 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
2316 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
2317 }
2318
2319 /*
2320 * Most of this is black magic retrieved from the old rtl8723au driver
2321 */
rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv * priv)2322 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2323 {
2324 u32 val32;
2325
2326 priv->fops->init_phy_bb(priv);
2327
2328 if (priv->tx_paths == 1 && priv->rx_paths == 2) {
2329 /*
2330 * For 1T2R boards, patch the registers.
2331 *
2332 * It looks like 8191/2 1T2R boards use path B for TX
2333 */
2334 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
2335 val32 &= ~(BIT(0) | BIT(1));
2336 val32 |= BIT(1);
2337 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
2338
2339 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
2340 val32 &= ~0x300033;
2341 val32 |= 0x200022;
2342 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
2343
2344 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
2345 val32 &= ~CCK0_AFE_RX_MASK;
2346 val32 &= 0x00ffffff;
2347 val32 |= 0x40000000;
2348 val32 |= CCK0_AFE_RX_ANT_B;
2349 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
2350
2351 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2352 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
2353 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
2354 OFDM_RF_PATH_TX_B);
2355 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2356
2357 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
2358 val32 &= ~(BIT(4) | BIT(5));
2359 val32 |= BIT(4);
2360 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
2361
2362 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
2363 val32 &= ~(BIT(27) | BIT(26));
2364 val32 |= BIT(27);
2365 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
2366
2367 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
2368 val32 &= ~(BIT(27) | BIT(26));
2369 val32 |= BIT(27);
2370 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
2371
2372 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
2373 val32 &= ~(BIT(27) | BIT(26));
2374 val32 |= BIT(27);
2375 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
2376
2377 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
2378 val32 &= ~(BIT(27) | BIT(26));
2379 val32 |= BIT(27);
2380 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
2381
2382 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
2383 val32 &= ~(BIT(27) | BIT(26));
2384 val32 |= BIT(27);
2385 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
2386 }
2387
2388 if (priv->fops->set_crystal_cap)
2389 priv->fops->set_crystal_cap(priv, priv->default_crystal_cap);
2390
2391 if (priv->rtl_chip == RTL8192E)
2392 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x000f81fb);
2393
2394 return 0;
2395 }
2396
rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv * priv,const struct rtl8xxxu_rfregval * array,enum rtl8xxxu_rfpath path)2397 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
2398 const struct rtl8xxxu_rfregval *array,
2399 enum rtl8xxxu_rfpath path)
2400 {
2401 int i, ret;
2402 u8 reg;
2403 u32 val;
2404
2405 for (i = 0; ; i++) {
2406 reg = array[i].reg;
2407 val = array[i].val;
2408
2409 if (reg == 0xff && val == 0xffffffff)
2410 break;
2411
2412 switch (reg) {
2413 case 0xfe:
2414 msleep(50);
2415 continue;
2416 case 0xfd:
2417 mdelay(5);
2418 continue;
2419 case 0xfc:
2420 mdelay(1);
2421 continue;
2422 case 0xfb:
2423 udelay(50);
2424 continue;
2425 case 0xfa:
2426 udelay(5);
2427 continue;
2428 case 0xf9:
2429 udelay(1);
2430 continue;
2431 }
2432
2433 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
2434 if (ret) {
2435 dev_warn(&priv->udev->dev,
2436 "Failed to initialize RF\n");
2437 return -EAGAIN;
2438 }
2439 udelay(1);
2440 }
2441
2442 return 0;
2443 }
2444
rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv * priv,const struct rtl8xxxu_rfregval * table,enum rtl8xxxu_rfpath path)2445 int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
2446 const struct rtl8xxxu_rfregval *table,
2447 enum rtl8xxxu_rfpath path)
2448 {
2449 u32 val32;
2450 u16 val16, rfsi_rfenv;
2451 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
2452
2453 switch (path) {
2454 case RF_A:
2455 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
2456 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
2457 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
2458 break;
2459 case RF_B:
2460 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
2461 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
2462 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
2463 break;
2464 default:
2465 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
2466 __func__, path + 'A');
2467 return -EINVAL;
2468 }
2469 /* For path B, use XB */
2470 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
2471 rfsi_rfenv &= FPGA0_RF_RFENV;
2472
2473 /*
2474 * These two we might be able to optimize into one
2475 */
2476 val32 = rtl8xxxu_read32(priv, reg_int_oe);
2477 val32 |= BIT(20); /* 0x10 << 16 */
2478 rtl8xxxu_write32(priv, reg_int_oe, val32);
2479 udelay(1);
2480
2481 val32 = rtl8xxxu_read32(priv, reg_int_oe);
2482 val32 |= BIT(4);
2483 rtl8xxxu_write32(priv, reg_int_oe, val32);
2484 udelay(1);
2485
2486 /*
2487 * These two we might be able to optimize into one
2488 */
2489 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2490 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
2491 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2492 udelay(1);
2493
2494 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2495 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
2496 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2497 udelay(1);
2498
2499 rtl8xxxu_init_rf_regs(priv, table, path);
2500
2501 /* For path B, use XB */
2502 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
2503 val16 &= ~FPGA0_RF_RFENV;
2504 val16 |= rfsi_rfenv;
2505 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
2506
2507 return 0;
2508 }
2509
rtl8xxxu_llt_write(struct rtl8xxxu_priv * priv,u8 address,u8 data)2510 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
2511 {
2512 int ret = -EBUSY;
2513 int count = 0;
2514 u32 value;
2515
2516 value = LLT_OP_WRITE | address << 8 | data;
2517
2518 rtl8xxxu_write32(priv, REG_LLT_INIT, value);
2519
2520 do {
2521 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
2522 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
2523 ret = 0;
2524 break;
2525 }
2526 } while (count++ < 20);
2527
2528 return ret;
2529 }
2530
rtl8xxxu_init_llt_table(struct rtl8xxxu_priv * priv)2531 int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv)
2532 {
2533 int ret;
2534 int i, last_entry;
2535 u8 last_tx_page;
2536
2537 last_tx_page = priv->fops->total_page_num;
2538
2539 if (priv->fops->last_llt_entry)
2540 last_entry = priv->fops->last_llt_entry;
2541 else
2542 last_entry = 255;
2543
2544 for (i = 0; i < last_tx_page; i++) {
2545 ret = rtl8xxxu_llt_write(priv, i, i + 1);
2546 if (ret)
2547 goto exit;
2548 }
2549
2550 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
2551 if (ret)
2552 goto exit;
2553
2554 /* Mark remaining pages as a ring buffer */
2555 for (i = last_tx_page + 1; i < last_entry; i++) {
2556 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
2557 if (ret)
2558 goto exit;
2559 }
2560
2561 /* Let last entry point to the start entry of ring buffer */
2562 ret = rtl8xxxu_llt_write(priv, last_entry, last_tx_page + 1);
2563 if (ret)
2564 goto exit;
2565
2566 exit:
2567 return ret;
2568 }
2569
rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv * priv)2570 int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv)
2571 {
2572 u32 val32;
2573 int ret = 0;
2574 int i;
2575
2576 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
2577 val32 |= AUTO_LLT_INIT_LLT;
2578 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
2579
2580 for (i = 500; i; i--) {
2581 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
2582 if (!(val32 & AUTO_LLT_INIT_LLT))
2583 break;
2584 usleep_range(2, 4);
2585 }
2586
2587 if (!i) {
2588 ret = -EBUSY;
2589 dev_warn(&priv->udev->dev, "LLT table init failed\n");
2590 }
2591
2592 return ret;
2593 }
2594
rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv * priv)2595 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
2596 {
2597 u16 val16, hi, lo;
2598 u16 hiq, mgq, bkq, beq, viq, voq;
2599 int hip, mgp, bkp, bep, vip, vop;
2600 int ret = 0;
2601 u32 val32;
2602
2603 switch (priv->ep_tx_count) {
2604 case 1:
2605 if (priv->ep_tx_high_queue) {
2606 hi = TRXDMA_QUEUE_HIGH;
2607 } else if (priv->ep_tx_low_queue) {
2608 hi = TRXDMA_QUEUE_LOW;
2609 } else if (priv->ep_tx_normal_queue) {
2610 hi = TRXDMA_QUEUE_NORMAL;
2611 } else {
2612 hi = 0;
2613 ret = -EINVAL;
2614 }
2615
2616 hiq = hi;
2617 mgq = hi;
2618 bkq = hi;
2619 beq = hi;
2620 viq = hi;
2621 voq = hi;
2622
2623 hip = 0;
2624 mgp = 0;
2625 bkp = 0;
2626 bep = 0;
2627 vip = 0;
2628 vop = 0;
2629 break;
2630 case 2:
2631 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
2632 hi = TRXDMA_QUEUE_HIGH;
2633 lo = TRXDMA_QUEUE_LOW;
2634 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
2635 hi = TRXDMA_QUEUE_NORMAL;
2636 lo = TRXDMA_QUEUE_LOW;
2637 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
2638 hi = TRXDMA_QUEUE_HIGH;
2639 lo = TRXDMA_QUEUE_NORMAL;
2640 } else {
2641 ret = -EINVAL;
2642 hi = 0;
2643 lo = 0;
2644 }
2645
2646 hiq = hi;
2647 mgq = hi;
2648 bkq = lo;
2649 beq = lo;
2650 viq = hi;
2651 voq = hi;
2652
2653 hip = 0;
2654 mgp = 0;
2655 bkp = 1;
2656 bep = 1;
2657 vip = 0;
2658 vop = 0;
2659 break;
2660 case 3:
2661 beq = TRXDMA_QUEUE_LOW;
2662 bkq = TRXDMA_QUEUE_LOW;
2663 viq = TRXDMA_QUEUE_NORMAL;
2664 voq = TRXDMA_QUEUE_HIGH;
2665 mgq = TRXDMA_QUEUE_HIGH;
2666 hiq = TRXDMA_QUEUE_HIGH;
2667
2668 hip = hiq ^ 3;
2669 mgp = mgq ^ 3;
2670 bkp = bkq ^ 3;
2671 bep = beq ^ 3;
2672 vip = viq ^ 3;
2673 vop = viq ^ 3;
2674 break;
2675 default:
2676 ret = -EINVAL;
2677 }
2678
2679 /*
2680 * None of the vendor drivers are configuring the beacon
2681 * queue here .... why?
2682 */
2683 if (!ret) {
2684 /* Only RTL8192F seems to do it like this. */
2685 if (priv->rtl_chip == RTL8192F) {
2686 val32 = rtl8xxxu_read32(priv, REG_TRXDMA_CTRL);
2687 val32 &= 0x7;
2688 val32 |= (voq << TRXDMA_CTRL_VOQ_SHIFT_8192F) |
2689 (viq << TRXDMA_CTRL_VIQ_SHIFT_8192F) |
2690 (beq << TRXDMA_CTRL_BEQ_SHIFT_8192F) |
2691 (bkq << TRXDMA_CTRL_BKQ_SHIFT_8192F) |
2692 (mgq << TRXDMA_CTRL_MGQ_SHIFT_8192F) |
2693 (hiq << TRXDMA_CTRL_HIQ_SHIFT_8192F);
2694 rtl8xxxu_write32(priv, REG_TRXDMA_CTRL, val32);
2695 } else {
2696 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
2697 val16 &= 0x7;
2698 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
2699 (viq << TRXDMA_CTRL_VIQ_SHIFT) |
2700 (beq << TRXDMA_CTRL_BEQ_SHIFT) |
2701 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
2702 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
2703 (hiq << TRXDMA_CTRL_HIQ_SHIFT);
2704 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
2705 }
2706
2707 priv->pipe_out[TXDESC_QUEUE_VO] =
2708 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
2709 priv->pipe_out[TXDESC_QUEUE_VI] =
2710 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
2711 priv->pipe_out[TXDESC_QUEUE_BE] =
2712 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
2713 priv->pipe_out[TXDESC_QUEUE_BK] =
2714 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
2715 priv->pipe_out[TXDESC_QUEUE_BEACON] =
2716 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2717 priv->pipe_out[TXDESC_QUEUE_MGNT] =
2718 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
2719 priv->pipe_out[TXDESC_QUEUE_HIGH] =
2720 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
2721 priv->pipe_out[TXDESC_QUEUE_CMD] =
2722 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2723 }
2724
2725 return ret;
2726 }
2727
rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv * priv,bool iqk_ok,int result[][8],int candidate,bool tx_only)2728 void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok,
2729 int result[][8], int candidate, bool tx_only)
2730 {
2731 u32 oldval, x, tx0_a, reg;
2732 int y, tx0_c;
2733 u32 val32;
2734
2735 if (!iqk_ok)
2736 return;
2737
2738 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2739 oldval = val32 >> 22;
2740
2741 x = result[candidate][0];
2742 if ((x & 0x00000200) != 0)
2743 x = x | 0xfffffc00;
2744 tx0_a = (x * oldval) >> 8;
2745
2746 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2747 val32 &= ~0x3ff;
2748 val32 |= tx0_a;
2749 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2750
2751 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2752 val32 &= ~BIT(31);
2753 if ((x * oldval >> 7) & 0x1)
2754 val32 |= BIT(31);
2755 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2756
2757 y = result[candidate][1];
2758 if ((y & 0x00000200) != 0)
2759 y = y | 0xfffffc00;
2760 tx0_c = (y * oldval) >> 8;
2761
2762 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
2763 val32 &= ~0xf0000000;
2764 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
2765 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
2766
2767 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2768 val32 &= ~0x003f0000;
2769 val32 |= ((tx0_c & 0x3f) << 16);
2770 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2771
2772 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2773 val32 &= ~BIT(29);
2774 if ((y * oldval >> 7) & 0x1)
2775 val32 |= BIT(29);
2776 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2777
2778 if (tx_only) {
2779 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2780 return;
2781 }
2782
2783 reg = result[candidate][2];
2784
2785 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2786 val32 &= ~0x3ff;
2787 val32 |= (reg & 0x3ff);
2788 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2789
2790 reg = result[candidate][3] & 0x3F;
2791
2792 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2793 val32 &= ~0xfc00;
2794 val32 |= ((reg << 10) & 0xfc00);
2795 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2796
2797 reg = (result[candidate][3] >> 6) & 0xF;
2798
2799 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
2800 val32 &= ~0xf0000000;
2801 val32 |= (reg << 28);
2802 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
2803 }
2804
rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv * priv,bool iqk_ok,int result[][8],int candidate,bool tx_only)2805 void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok,
2806 int result[][8], int candidate, bool tx_only)
2807 {
2808 u32 oldval, x, tx1_a, reg;
2809 int y, tx1_c;
2810 u32 val32;
2811
2812 if (!iqk_ok)
2813 return;
2814
2815 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2816 oldval = val32 >> 22;
2817
2818 x = result[candidate][4];
2819 if ((x & 0x00000200) != 0)
2820 x = x | 0xfffffc00;
2821 tx1_a = (x * oldval) >> 8;
2822
2823 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2824 val32 &= ~0x3ff;
2825 val32 |= tx1_a;
2826 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2827
2828 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2829 val32 &= ~BIT(27);
2830 if ((x * oldval >> 7) & 0x1)
2831 val32 |= BIT(27);
2832 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2833
2834 y = result[candidate][5];
2835 if ((y & 0x00000200) != 0)
2836 y = y | 0xfffffc00;
2837 tx1_c = (y * oldval) >> 8;
2838
2839 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
2840 val32 &= ~0xf0000000;
2841 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
2842 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
2843
2844 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2845 val32 &= ~0x003f0000;
2846 val32 |= ((tx1_c & 0x3f) << 16);
2847 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2848
2849 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2850 val32 &= ~BIT(25);
2851 if ((y * oldval >> 7) & 0x1)
2852 val32 |= BIT(25);
2853 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2854
2855 if (tx_only) {
2856 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2857 return;
2858 }
2859
2860 reg = result[candidate][6];
2861
2862 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2863 val32 &= ~0x3ff;
2864 val32 |= (reg & 0x3ff);
2865 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2866
2867 reg = result[candidate][7] & 0x3f;
2868
2869 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2870 val32 &= ~0xfc00;
2871 val32 |= ((reg << 10) & 0xfc00);
2872 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2873
2874 reg = (result[candidate][7] >> 6) & 0xf;
2875
2876 if (priv->rtl_chip == RTL8192F) {
2877 rtl8xxxu_write32_mask(priv, REG_RXIQB_EXT, 0x000000f0, reg);
2878 } else {
2879 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_RSSI_TABLE);
2880 val32 &= ~0x0000f000;
2881 val32 |= (reg << 12);
2882 rtl8xxxu_write32(priv, REG_OFDM0_AGC_RSSI_TABLE, val32);
2883 }
2884 }
2885
2886 #define MAX_TOLERANCE 5
2887
rtl8xxxu_simularity_compare(struct rtl8xxxu_priv * priv,int result[][8],int c1,int c2)2888 bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
2889 int result[][8], int c1, int c2)
2890 {
2891 u32 i, j, diff, simubitmap, bound = 0;
2892 int candidate[2] = {-1, -1}; /* for path A and path B */
2893 bool retval = true;
2894
2895 if (priv->tx_paths > 1)
2896 bound = 8;
2897 else
2898 bound = 4;
2899
2900 simubitmap = 0;
2901
2902 for (i = 0; i < bound; i++) {
2903 diff = (result[c1][i] > result[c2][i]) ?
2904 (result[c1][i] - result[c2][i]) :
2905 (result[c2][i] - result[c1][i]);
2906 if (diff > MAX_TOLERANCE) {
2907 if ((i == 2 || i == 6) && !simubitmap) {
2908 if (result[c1][i] + result[c1][i + 1] == 0)
2909 candidate[(i / 4)] = c2;
2910 else if (result[c2][i] + result[c2][i + 1] == 0)
2911 candidate[(i / 4)] = c1;
2912 else
2913 simubitmap = simubitmap | (1 << i);
2914 } else {
2915 simubitmap = simubitmap | (1 << i);
2916 }
2917 }
2918 }
2919
2920 if (simubitmap == 0) {
2921 for (i = 0; i < (bound / 4); i++) {
2922 if (candidate[i] >= 0) {
2923 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2924 result[3][j] = result[candidate[i]][j];
2925 retval = false;
2926 }
2927 }
2928 return retval;
2929 } else if (!(simubitmap & 0x0f)) {
2930 /* path A OK */
2931 for (i = 0; i < 4; i++)
2932 result[3][i] = result[c1][i];
2933 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
2934 /* path B OK */
2935 for (i = 4; i < 8; i++)
2936 result[3][i] = result[c1][i];
2937 }
2938
2939 return false;
2940 }
2941
rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv * priv,int result[][8],int c1,int c2)2942 bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv,
2943 int result[][8], int c1, int c2)
2944 {
2945 u32 i, j, diff, simubitmap, bound = 0;
2946 int candidate[2] = {-1, -1}; /* for path A and path B */
2947 int tmp1, tmp2;
2948 bool retval = true;
2949
2950 if (priv->tx_paths > 1)
2951 bound = 8;
2952 else
2953 bound = 4;
2954
2955 simubitmap = 0;
2956
2957 for (i = 0; i < bound; i++) {
2958 if (i & 1) {
2959 if ((result[c1][i] & 0x00000200))
2960 tmp1 = result[c1][i] | 0xfffffc00;
2961 else
2962 tmp1 = result[c1][i];
2963
2964 if ((result[c2][i]& 0x00000200))
2965 tmp2 = result[c2][i] | 0xfffffc00;
2966 else
2967 tmp2 = result[c2][i];
2968 } else {
2969 tmp1 = result[c1][i];
2970 tmp2 = result[c2][i];
2971 }
2972
2973 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
2974
2975 if (diff > MAX_TOLERANCE) {
2976 if ((i == 2 || i == 6) && !simubitmap) {
2977 if (result[c1][i] + result[c1][i + 1] == 0)
2978 candidate[(i / 4)] = c2;
2979 else if (result[c2][i] + result[c2][i + 1] == 0)
2980 candidate[(i / 4)] = c1;
2981 else
2982 simubitmap = simubitmap | (1 << i);
2983 } else {
2984 simubitmap = simubitmap | (1 << i);
2985 }
2986 }
2987 }
2988
2989 if (simubitmap == 0) {
2990 for (i = 0; i < (bound / 4); i++) {
2991 if (candidate[i] >= 0) {
2992 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2993 result[3][j] = result[candidate[i]][j];
2994 retval = false;
2995 }
2996 }
2997 return retval;
2998 } else {
2999 if (!(simubitmap & 0x03)) {
3000 /* path A TX OK */
3001 for (i = 0; i < 2; i++)
3002 result[3][i] = result[c1][i];
3003 }
3004
3005 if (!(simubitmap & 0x0c)) {
3006 /* path A RX OK */
3007 for (i = 2; i < 4; i++)
3008 result[3][i] = result[c1][i];
3009 }
3010
3011 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
3012 /* path B TX OK */
3013 for (i = 4; i < 6; i++)
3014 result[3][i] = result[c1][i];
3015 }
3016
3017 if (!(simubitmap & 0xc0) && priv->tx_paths > 1) {
3018 /* path B RX OK */
3019 for (i = 6; i < 8; i++)
3020 result[3][i] = result[c1][i];
3021 }
3022 }
3023
3024 return false;
3025 }
3026
3027 void
rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv * priv,const u32 * reg,u32 * backup)3028 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
3029 {
3030 int i;
3031
3032 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3033 backup[i] = rtl8xxxu_read8(priv, reg[i]);
3034
3035 backup[i] = rtl8xxxu_read32(priv, reg[i]);
3036 }
3037
rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv * priv,const u32 * reg,u32 * backup)3038 void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
3039 const u32 *reg, u32 *backup)
3040 {
3041 int i;
3042
3043 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3044 rtl8xxxu_write8(priv, reg[i], backup[i]);
3045
3046 rtl8xxxu_write32(priv, reg[i], backup[i]);
3047 }
3048
rtl8xxxu_save_regs(struct rtl8xxxu_priv * priv,const u32 * regs,u32 * backup,int count)3049 void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3050 u32 *backup, int count)
3051 {
3052 int i;
3053
3054 for (i = 0; i < count; i++)
3055 backup[i] = rtl8xxxu_read32(priv, regs[i]);
3056 }
3057
rtl8xxxu_restore_regs(struct rtl8xxxu_priv * priv,const u32 * regs,u32 * backup,int count)3058 void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3059 u32 *backup, int count)
3060 {
3061 int i;
3062
3063 for (i = 0; i < count; i++)
3064 rtl8xxxu_write32(priv, regs[i], backup[i]);
3065 }
3066
3067
rtl8xxxu_path_adda_on(struct rtl8xxxu_priv * priv,const u32 * regs,bool path_a_on)3068 void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
3069 bool path_a_on)
3070 {
3071 u32 path_on;
3072 int i;
3073
3074 if (priv->tx_paths == 1) {
3075 path_on = priv->fops->adda_1t_path_on;
3076 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init);
3077 } else {
3078 path_on = path_a_on ? priv->fops->adda_2t_path_on_a :
3079 priv->fops->adda_2t_path_on_b;
3080
3081 rtl8xxxu_write32(priv, regs[0], path_on);
3082 }
3083
3084 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3085 rtl8xxxu_write32(priv, regs[i], path_on);
3086 }
3087
rtl8xxxu_mac_calibration(struct rtl8xxxu_priv * priv,const u32 * regs,u32 * backup)3088 void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3089 const u32 *regs, u32 *backup)
3090 {
3091 int i = 0;
3092
3093 rtl8xxxu_write8(priv, regs[i], 0x3f);
3094
3095 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3096 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3097
3098 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3099 }
3100
rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv * priv)3101 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3102 {
3103 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3104 int result = 0;
3105
3106 /* path-A IQK setting */
3107 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3108 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3109 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3110
3111 val32 = (priv->rf_paths > 1) ? 0x28160202 :
3112 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3113 0x28160502;
3114 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3115
3116 /* path-B IQK setting */
3117 if (priv->rf_paths > 1) {
3118 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3119 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3120 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3121 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3122 }
3123
3124 /* LO calibration setting */
3125 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3126
3127 /* One shot, path A LOK & IQK */
3128 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3129 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3130
3131 mdelay(1);
3132
3133 /* Check failed */
3134 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3135 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3136 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3137 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3138
3139 if (!(reg_eac & BIT(28)) &&
3140 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3141 ((reg_e9c & 0x03ff0000) != 0x00420000))
3142 result |= 0x01;
3143 else /* If TX not OK, ignore RX */
3144 goto out;
3145
3146 /* If TX is OK, check whether RX is OK */
3147 if (!(reg_eac & BIT(27)) &&
3148 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3149 ((reg_eac & 0x03ff0000) != 0x00360000))
3150 result |= 0x02;
3151 else
3152 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3153 __func__);
3154 out:
3155 return result;
3156 }
3157
rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv * priv)3158 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3159 {
3160 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3161 int result = 0;
3162
3163 /* One shot, path B LOK & IQK */
3164 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3165 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3166
3167 mdelay(1);
3168
3169 /* Check failed */
3170 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3171 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3172 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3173 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3174 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3175
3176 if (!(reg_eac & BIT(31)) &&
3177 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3178 ((reg_ebc & 0x03ff0000) != 0x00420000))
3179 result |= 0x01;
3180 else
3181 goto out;
3182
3183 if (!(reg_eac & BIT(30)) &&
3184 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3185 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3186 result |= 0x02;
3187 else
3188 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3189 __func__);
3190 out:
3191 return result;
3192 }
3193
rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv * priv,int result[][8],int t)3194 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
3195 int result[][8], int t)
3196 {
3197 struct device *dev = &priv->udev->dev;
3198 u32 i, val32;
3199 int path_a_ok, path_b_ok;
3200 int retry = 2;
3201 static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
3202 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
3203 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
3204 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
3205 REG_TX_OFDM_BBON, REG_TX_TO_RX,
3206 REG_TX_TO_TX, REG_RX_CCK,
3207 REG_RX_OFDM, REG_RX_WAIT_RIFS,
3208 REG_RX_TO_RX, REG_STANDBY,
3209 REG_SLEEP, REG_PMPD_ANAEN
3210 };
3211 static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
3212 REG_TXPAUSE, REG_BEACON_CTRL,
3213 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
3214 };
3215 static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
3216 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
3217 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
3218 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
3219 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
3220 };
3221
3222 /*
3223 * Note: IQ calibration must be performed after loading
3224 * PHY_REG.txt , and radio_a, radio_b.txt
3225 */
3226
3227 if (t == 0) {
3228 /* Save ADDA parameters, turn Path A ADDA on */
3229 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
3230 RTL8XXXU_ADDA_REGS);
3231 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3232 rtl8xxxu_save_regs(priv, iqk_bb_regs,
3233 priv->bb_backup, RTL8XXXU_BB_REGS);
3234 }
3235
3236 rtl8xxxu_path_adda_on(priv, adda_regs, true);
3237
3238 if (t == 0) {
3239 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
3240 if (val32 & FPGA0_HSSI_PARM1_PI)
3241 priv->pi_enabled = 1;
3242 }
3243
3244 if (!priv->pi_enabled) {
3245 /* Switch BB to PI mode to do IQ Calibration. */
3246 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
3247 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
3248 }
3249
3250 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3251 val32 &= ~FPGA_RF_MODE_CCK;
3252 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
3253
3254 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
3255 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
3256 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
3257
3258 if (!priv->no_pape) {
3259 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
3260 val32 |= (FPGA0_RF_PAPE |
3261 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3262 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3263 }
3264
3265 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
3266 val32 &= ~BIT(10);
3267 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
3268 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
3269 val32 &= ~BIT(10);
3270 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
3271
3272 if (priv->tx_paths > 1) {
3273 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3274 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
3275 }
3276
3277 /* MAC settings */
3278 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
3279
3280 /* Page B init */
3281 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
3282
3283 if (priv->tx_paths > 1)
3284 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
3285
3286 /* IQ calibration setting */
3287 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3288 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3289 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3290
3291 for (i = 0; i < retry; i++) {
3292 path_a_ok = rtl8xxxu_iqk_path_a(priv);
3293 if (path_a_ok == 0x03) {
3294 val32 = rtl8xxxu_read32(priv,
3295 REG_TX_POWER_BEFORE_IQK_A);
3296 result[t][0] = (val32 >> 16) & 0x3ff;
3297 val32 = rtl8xxxu_read32(priv,
3298 REG_TX_POWER_AFTER_IQK_A);
3299 result[t][1] = (val32 >> 16) & 0x3ff;
3300 val32 = rtl8xxxu_read32(priv,
3301 REG_RX_POWER_BEFORE_IQK_A_2);
3302 result[t][2] = (val32 >> 16) & 0x3ff;
3303 val32 = rtl8xxxu_read32(priv,
3304 REG_RX_POWER_AFTER_IQK_A_2);
3305 result[t][3] = (val32 >> 16) & 0x3ff;
3306 break;
3307 } else if (i == (retry - 1) && path_a_ok == 0x01) {
3308 /* TX IQK OK */
3309 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
3310 __func__);
3311
3312 val32 = rtl8xxxu_read32(priv,
3313 REG_TX_POWER_BEFORE_IQK_A);
3314 result[t][0] = (val32 >> 16) & 0x3ff;
3315 val32 = rtl8xxxu_read32(priv,
3316 REG_TX_POWER_AFTER_IQK_A);
3317 result[t][1] = (val32 >> 16) & 0x3ff;
3318 }
3319 }
3320
3321 if (!path_a_ok)
3322 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
3323
3324 if (priv->tx_paths > 1) {
3325 /*
3326 * Path A into standby
3327 */
3328 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
3329 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3330 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3331
3332 /* Turn Path B ADDA on */
3333 rtl8xxxu_path_adda_on(priv, adda_regs, false);
3334
3335 for (i = 0; i < retry; i++) {
3336 path_b_ok = rtl8xxxu_iqk_path_b(priv);
3337 if (path_b_ok == 0x03) {
3338 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3339 result[t][4] = (val32 >> 16) & 0x3ff;
3340 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3341 result[t][5] = (val32 >> 16) & 0x3ff;
3342 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3343 result[t][6] = (val32 >> 16) & 0x3ff;
3344 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3345 result[t][7] = (val32 >> 16) & 0x3ff;
3346 break;
3347 } else if (i == (retry - 1) && path_b_ok == 0x01) {
3348 /* TX IQK OK */
3349 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3350 result[t][4] = (val32 >> 16) & 0x3ff;
3351 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3352 result[t][5] = (val32 >> 16) & 0x3ff;
3353 }
3354 }
3355
3356 if (!path_b_ok)
3357 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
3358 }
3359
3360 /* Back to BB mode, load original value */
3361 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
3362
3363 if (t) {
3364 if (!priv->pi_enabled) {
3365 /*
3366 * Switch back BB to SI mode after finishing
3367 * IQ Calibration
3368 */
3369 val32 = 0x01000000;
3370 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
3371 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
3372 }
3373
3374 /* Reload ADDA power saving parameters */
3375 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
3376 RTL8XXXU_ADDA_REGS);
3377
3378 /* Reload MAC parameters */
3379 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3380
3381 /* Reload BB parameters */
3382 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
3383 priv->bb_backup, RTL8XXXU_BB_REGS);
3384
3385 /* Restore RX initial gain */
3386 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
3387
3388 if (priv->tx_paths > 1) {
3389 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
3390 0x00032ed3);
3391 }
3392
3393 /* Load 0xe30 IQC default value */
3394 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
3395 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
3396 }
3397 }
3398
rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv * priv,u8 start)3399 void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start)
3400 {
3401 struct h2c_cmd h2c;
3402
3403 memset(&h2c, 0, sizeof(struct h2c_cmd));
3404 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION;
3405 h2c.bt_wlan_calibration.data = start;
3406
3407 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration));
3408 }
3409
rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv * priv)3410 void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
3411 {
3412 struct device *dev = &priv->udev->dev;
3413 int result[4][8]; /* last is final result */
3414 int i, candidate;
3415 bool path_a_ok, path_b_ok;
3416 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
3417 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3418 s32 reg_tmp = 0;
3419 bool simu;
3420
3421 memset(result, 0, sizeof(result));
3422 candidate = -1;
3423
3424 path_a_ok = false;
3425 path_b_ok = false;
3426
3427 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3428
3429 for (i = 0; i < 3; i++) {
3430 rtl8xxxu_phy_iqcalibrate(priv, result, i);
3431
3432 if (i == 1) {
3433 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
3434 if (simu) {
3435 candidate = 0;
3436 break;
3437 }
3438 }
3439
3440 if (i == 2) {
3441 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
3442 if (simu) {
3443 candidate = 0;
3444 break;
3445 }
3446
3447 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
3448 if (simu) {
3449 candidate = 1;
3450 } else {
3451 for (i = 0; i < 8; i++)
3452 reg_tmp += result[3][i];
3453
3454 if (reg_tmp)
3455 candidate = 3;
3456 else
3457 candidate = -1;
3458 }
3459 }
3460 }
3461
3462 for (i = 0; i < 4; i++) {
3463 reg_e94 = result[i][0];
3464 reg_e9c = result[i][1];
3465 reg_ea4 = result[i][2];
3466 reg_eac = result[i][3];
3467 reg_eb4 = result[i][4];
3468 reg_ebc = result[i][5];
3469 reg_ec4 = result[i][6];
3470 reg_ecc = result[i][7];
3471 }
3472
3473 if (candidate >= 0) {
3474 reg_e94 = result[candidate][0];
3475 priv->rege94 = reg_e94;
3476 reg_e9c = result[candidate][1];
3477 priv->rege9c = reg_e9c;
3478 reg_ea4 = result[candidate][2];
3479 reg_eac = result[candidate][3];
3480 reg_eb4 = result[candidate][4];
3481 priv->regeb4 = reg_eb4;
3482 reg_ebc = result[candidate][5];
3483 priv->regebc = reg_ebc;
3484 reg_ec4 = result[candidate][6];
3485 reg_ecc = result[candidate][7];
3486 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
3487 dev_dbg(dev,
3488 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n",
3489 __func__, reg_e94, reg_e9c,
3490 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
3491 path_a_ok = true;
3492 path_b_ok = true;
3493 } else {
3494 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
3495 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
3496 }
3497
3498 if (reg_e94 && candidate >= 0)
3499 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
3500 candidate, (reg_ea4 == 0));
3501
3502 if (priv->tx_paths > 1 && reg_eb4)
3503 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
3504 candidate, (reg_ec4 == 0));
3505
3506 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,
3507 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
3508 }
3509
rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv * priv)3510 void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
3511 {
3512 u32 val32;
3513 u32 rf_amode, rf_bmode = 0, lstf;
3514
3515 /* Check continuous TX and Packet TX */
3516 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
3517
3518 if (lstf & OFDM_LSTF_MASK) {
3519 /* Disable all continuous TX */
3520 val32 = lstf & ~OFDM_LSTF_MASK;
3521 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
3522
3523 /* Read original RF mode Path A */
3524 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
3525
3526 /* Set RF mode to standby Path A */
3527 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
3528 (rf_amode & 0x8ffff) | 0x10000);
3529
3530 /* Path-B */
3531 if (priv->tx_paths > 1) {
3532 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
3533 RF6052_REG_AC);
3534
3535 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3536 (rf_bmode & 0x8ffff) | 0x10000);
3537 }
3538 } else {
3539 /* Deal with Packet TX case */
3540 /* block all queues */
3541 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3542 }
3543
3544 /* Start LC calibration */
3545 if (priv->fops->has_s0s1)
3546 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0);
3547 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
3548 val32 |= 0x08000;
3549 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
3550
3551 msleep(100);
3552
3553 if (priv->fops->has_s0s1)
3554 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0);
3555
3556 /* Restore original parameters */
3557 if (lstf & OFDM_LSTF_MASK) {
3558 /* Path-A */
3559 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
3560 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
3561
3562 /* Path-B */
3563 if (priv->tx_paths > 1)
3564 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3565 rf_bmode);
3566 } else /* Deal with Packet TX case */
3567 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
3568 }
3569
rtl8xxxu_set_mac(struct rtl8xxxu_priv * priv)3570 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
3571 {
3572 int i;
3573 u16 reg;
3574
3575 reg = REG_MACID;
3576
3577 for (i = 0; i < ETH_ALEN; i++)
3578 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
3579
3580 return 0;
3581 }
3582
rtl8xxxu_set_bssid(struct rtl8xxxu_priv * priv,const u8 * bssid)3583 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
3584 {
3585 int i;
3586 u16 reg;
3587
3588 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
3589
3590 reg = REG_BSSID;
3591
3592 for (i = 0; i < ETH_ALEN; i++)
3593 rtl8xxxu_write8(priv, reg + i, bssid[i]);
3594
3595 return 0;
3596 }
3597
3598 static void
rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv * priv,u8 ampdu_factor)3599 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
3600 {
3601 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
3602 u8 max_agg = 0xf;
3603 int i;
3604
3605 ampdu_factor = 1 << (ampdu_factor + 2);
3606 if (ampdu_factor > max_agg)
3607 ampdu_factor = max_agg;
3608
3609 for (i = 0; i < 4; i++) {
3610 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
3611 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
3612
3613 if ((vals[i] & 0x0f) > ampdu_factor)
3614 vals[i] = (vals[i] & 0xf0) | ampdu_factor;
3615
3616 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
3617 }
3618 }
3619
rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv * priv,u8 density)3620 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
3621 {
3622 u8 val8;
3623
3624 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
3625 val8 &= 0xf8;
3626 val8 |= density;
3627 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
3628 }
3629
rtl8xxxu_active_to_emu(struct rtl8xxxu_priv * priv)3630 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
3631 {
3632 u8 val8;
3633 int count, ret = 0;
3634
3635 /* Start of rtl8723AU_card_enable_flow */
3636 /* Act to Cardemu sequence*/
3637 /* Turn off RF */
3638 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
3639
3640 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
3641 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3642 val8 &= ~LEDCFG2_DPDT_SELECT;
3643 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3644
3645 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
3646 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3647 val8 |= BIT(1);
3648 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3649
3650 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3651 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3652 if ((val8 & BIT(1)) == 0)
3653 break;
3654 udelay(10);
3655 }
3656
3657 if (!count) {
3658 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
3659 __func__);
3660 ret = -EBUSY;
3661 goto exit;
3662 }
3663
3664 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
3665 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3666 val8 |= SYS_ISO_ANALOG_IPS;
3667 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3668
3669 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
3670 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3671 val8 &= ~LDOA15_ENABLE;
3672 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3673
3674 exit:
3675 return ret;
3676 }
3677
rtl8xxxu_active_to_lps(struct rtl8xxxu_priv * priv)3678 int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
3679 {
3680 u8 val8;
3681 u8 val32;
3682 int count, ret = 0;
3683
3684 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3685
3686 /*
3687 * Poll - wait for RX packet to complete
3688 */
3689 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3690 val32 = rtl8xxxu_read32(priv, 0x5f8);
3691 if (!val32)
3692 break;
3693 udelay(10);
3694 }
3695
3696 if (!count) {
3697 dev_warn(&priv->udev->dev,
3698 "%s: RX poll timed out (0x05f8)\n", __func__);
3699 ret = -EBUSY;
3700 goto exit;
3701 }
3702
3703 /* Disable CCK and OFDM, clock gated */
3704 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3705 val8 &= ~SYS_FUNC_BBRSTB;
3706 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3707
3708 udelay(2);
3709
3710 /* Reset baseband */
3711 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3712 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
3713 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3714
3715 /* Reset MAC TRX */
3716 val8 = rtl8xxxu_read8(priv, REG_CR);
3717 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
3718 rtl8xxxu_write8(priv, REG_CR, val8);
3719
3720 /* Reset MAC TRX */
3721 val8 = rtl8xxxu_read8(priv, REG_CR + 1);
3722 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
3723 rtl8xxxu_write8(priv, REG_CR + 1, val8);
3724
3725 /* Respond TX OK to scheduler */
3726 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
3727 val8 |= DUAL_TSF_TX_OK;
3728 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
3729
3730 exit:
3731 return ret;
3732 }
3733
rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv * priv)3734 void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv)
3735 {
3736 u8 val8;
3737
3738 /* Clear suspend enable and power down enable*/
3739 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3740 val8 &= ~(BIT(3) | BIT(7));
3741 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3742
3743 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
3744 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3745 val8 &= ~BIT(0);
3746 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3747
3748 /* 0x04[12:11] = 11 enable WL suspend*/
3749 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3750 val8 &= ~(BIT(3) | BIT(4));
3751 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3752 }
3753
rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv * priv)3754 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
3755 {
3756 u8 val8;
3757
3758 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
3759 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
3760
3761 /* 0x04[12:11] = 01 enable WL suspend */
3762 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3763 val8 &= ~BIT(4);
3764 val8 |= BIT(3);
3765 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3766
3767 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3768 val8 |= BIT(7);
3769 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3770
3771 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
3772 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3773 val8 |= BIT(0);
3774 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3775
3776 return 0;
3777 }
3778
rtl8xxxu_flush_fifo(struct rtl8xxxu_priv * priv)3779 int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv)
3780 {
3781 struct device *dev = &priv->udev->dev;
3782 u32 val32;
3783 int retry, retval;
3784
3785 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3786
3787 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
3788 val32 |= RXPKT_NUM_RW_RELEASE_EN;
3789 rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32);
3790
3791 retry = 100;
3792 retval = -EBUSY;
3793
3794 do {
3795 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
3796 if (val32 & RXPKT_NUM_RXDMA_IDLE) {
3797 retval = 0;
3798 break;
3799 }
3800 } while (retry--);
3801
3802 rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0);
3803 rtl8xxxu_write32(priv, REG_RQPN, 0x80000000);
3804 mdelay(2);
3805
3806 if (!retry)
3807 dev_warn(dev, "Failed to flush FIFO\n");
3808
3809 return retval;
3810 }
3811
rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv * priv)3812 void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv)
3813 {
3814 /* Fix USB interface interference issue */
3815 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
3816 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
3817 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3818 /*
3819 * This sets TXDMA_OFFSET_DROP_DATA_EN (bit 9) as well as bits
3820 * 8 and 5, for which I have found no documentation.
3821 */
3822 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
3823
3824 /*
3825 * Solve too many protocol error on USB bus.
3826 * Can't do this for 8188/8192 UMC A cut parts
3827 */
3828 if (!(!priv->chip_cut && priv->vendor_umc)) {
3829 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
3830 rtl8xxxu_write8(priv, 0xfe41, 0x94);
3831 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3832
3833 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
3834 rtl8xxxu_write8(priv, 0xfe41, 0x19);
3835 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3836
3837 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
3838 rtl8xxxu_write8(priv, 0xfe41, 0x91);
3839 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3840
3841 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
3842 rtl8xxxu_write8(priv, 0xfe41, 0x81);
3843 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3844 }
3845 }
3846
rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv * priv)3847 void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv)
3848 {
3849 u32 val32;
3850
3851 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
3852 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
3853 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
3854 }
3855
rtl8xxxu_power_off(struct rtl8xxxu_priv * priv)3856 void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
3857 {
3858 u8 val8;
3859 u16 val16;
3860 u32 val32;
3861
3862 /*
3863 * Workaround for 8188RU LNA power leakage problem.
3864 */
3865 if (priv->rtl_chip == RTL8188R) {
3866 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
3867 val32 |= BIT(1);
3868 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
3869 }
3870
3871 rtl8xxxu_flush_fifo(priv);
3872
3873 rtl8xxxu_active_to_lps(priv);
3874
3875 /* Turn off RF */
3876 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
3877
3878 /* Reset Firmware if running in RAM */
3879 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
3880 rtl8xxxu_firmware_self_reset(priv);
3881
3882 /* Reset MCU */
3883 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3884 val16 &= ~SYS_FUNC_CPU_ENABLE;
3885 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3886
3887 /* Reset MCU ready status */
3888 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
3889
3890 rtl8xxxu_active_to_emu(priv);
3891 rtl8xxxu_emu_to_disabled(priv);
3892
3893 /* Reset MCU IO Wrapper */
3894 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3895 val8 &= ~BIT(0);
3896 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3897
3898 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3899 val8 |= BIT(0);
3900 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3901
3902 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
3903 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
3904 }
3905
rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv * priv,u8 arg1,u8 arg2,u8 arg3,u8 arg4,u8 arg5)3906 void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
3907 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5)
3908 {
3909 struct h2c_cmd h2c;
3910
3911 memset(&h2c, 0, sizeof(struct h2c_cmd));
3912 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA;
3913 h2c.b_type_dma.data1 = arg1;
3914 h2c.b_type_dma.data2 = arg2;
3915 h2c.b_type_dma.data3 = arg3;
3916 h2c.b_type_dma.data4 = arg4;
3917 h2c.b_type_dma.data5 = arg5;
3918 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma));
3919 }
3920
rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv * priv)3921 void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv)
3922 {
3923 u32 val32;
3924
3925 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);
3926 val32 &= ~(BIT(22) | BIT(23));
3927 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);
3928 }
3929
rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv * priv)3930 static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv *priv)
3931 {
3932 struct rtl8xxxu_fileops *fops = priv->fops;
3933 u32 hq, lq, nq, eq, pubq;
3934 u32 val32;
3935
3936 hq = 0;
3937 lq = 0;
3938 nq = 0;
3939 eq = 0;
3940 pubq = 0;
3941
3942 if (priv->ep_tx_high_queue)
3943 hq = fops->page_num_hi;
3944 if (priv->ep_tx_low_queue)
3945 lq = fops->page_num_lo;
3946 if (priv->ep_tx_normal_queue)
3947 nq = fops->page_num_norm;
3948
3949 val32 = (nq << RQPN_NPQ_SHIFT) | (eq << RQPN_EPQ_SHIFT);
3950 rtl8xxxu_write32(priv, REG_RQPN_NPQ, val32);
3951
3952 pubq = fops->total_page_num - hq - lq - nq - 1;
3953
3954 val32 = RQPN_LOAD;
3955 val32 |= (hq << RQPN_HI_PQ_SHIFT);
3956 val32 |= (lq << RQPN_LO_PQ_SHIFT);
3957 val32 |= (pubq << RQPN_PUB_PQ_SHIFT);
3958
3959 rtl8xxxu_write32(priv, REG_RQPN, val32);
3960 }
3961
rtl8xxxu_init_burst(struct rtl8xxxu_priv * priv)3962 void rtl8xxxu_init_burst(struct rtl8xxxu_priv *priv)
3963 {
3964 u8 val8;
3965
3966 /*
3967 * For USB high speed set 512B packets
3968 */
3969 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B);
3970 u8p_replace_bits(&val8, 1, RXDMA_PRO_DMA_BURST_SIZE);
3971 u8p_replace_bits(&val8, 3, RXDMA_PRO_DMA_BURST_CNT);
3972 val8 |= RXDMA_PRO_DMA_MODE;
3973 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8);
3974
3975 /*
3976 * Enable single packet AMPDU
3977 */
3978 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B);
3979 val8 |= HT_SINGLE_AMPDU_ENABLE;
3980 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);
3981
3982 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, priv->fops->max_aggr_num);
3983 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B,
3984 priv->fops->ampdu_max_time);
3985 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff);
3986 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18);
3987 rtl8xxxu_write8(priv, REG_PIFS, 0x00);
3988 if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8710B ||
3989 priv->rtl_chip == RTL8192F) {
3990 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, FWHW_TXQ_CTRL_AMPDU_RETRY);
3991 rtl8xxxu_write32(priv, REG_FAST_EDCA_CTRL, 0x03086666);
3992 }
3993 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, priv->fops->ustime_tsf_edca);
3994 rtl8xxxu_write8(priv, REG_USTIME_EDCA, priv->fops->ustime_tsf_edca);
3995
3996 /* to prevent mac is reseted by bus. */
3997 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
3998 val8 |= RSV_CTRL_WLOCK_1C | RSV_CTRL_DIS_PRST;
3999 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
4000 }
4001
rtl8xxxu_acquire_macid(struct rtl8xxxu_priv * priv)4002 static u8 rtl8xxxu_acquire_macid(struct rtl8xxxu_priv *priv)
4003 {
4004 u8 macid;
4005
4006 macid = find_first_zero_bit(priv->mac_id_map, RTL8XXXU_MAX_MAC_ID_NUM);
4007 if (macid < RTL8XXXU_MAX_MAC_ID_NUM)
4008 set_bit(macid, priv->mac_id_map);
4009
4010 return macid;
4011 }
4012
rtl8xxxu_release_macid(struct rtl8xxxu_priv * priv,u8 macid)4013 static void rtl8xxxu_release_macid(struct rtl8xxxu_priv *priv, u8 macid)
4014 {
4015 clear_bit(macid, priv->mac_id_map);
4016 }
4017
rtl8xxxu_get_macid(struct rtl8xxxu_priv * priv,struct ieee80211_sta * sta)4018 static inline u8 rtl8xxxu_get_macid(struct rtl8xxxu_priv *priv,
4019 struct ieee80211_sta *sta)
4020 {
4021 struct rtl8xxxu_sta_info *sta_info;
4022
4023 if (!priv->vif || priv->vif->type == NL80211_IFTYPE_STATION || !sta)
4024 return 0;
4025
4026 sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv;
4027 return sta_info->macid;
4028 }
4029
rtl8xxxu_init_device(struct ieee80211_hw * hw)4030 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
4031 {
4032 struct rtl8xxxu_priv *priv = hw->priv;
4033 struct device *dev = &priv->udev->dev;
4034 struct rtl8xxxu_fileops *fops = priv->fops;
4035 bool macpower;
4036 int ret;
4037 u8 val8;
4038 u16 val16;
4039 u32 val32;
4040
4041 /* Check if MAC is already powered on */
4042 val8 = rtl8xxxu_read8(priv, REG_CR);
4043 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
4044
4045 /*
4046 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
4047 * initialized. First MAC returns 0xea, second MAC returns 0x00
4048 */
4049 if (val8 == 0xea || !(val16 & SYS_CLK_MAC_CLK_ENABLE))
4050 macpower = false;
4051 else
4052 macpower = true;
4053
4054 if (fops->needs_full_init)
4055 macpower = false;
4056
4057 ret = fops->power_on(priv);
4058 if (ret < 0) {
4059 dev_warn(dev, "%s: Failed power on\n", __func__);
4060 goto exit;
4061 }
4062
4063 if (!macpower)
4064 rtl8xxxu_init_queue_reserved_page(priv);
4065
4066 ret = rtl8xxxu_init_queue_priority(priv);
4067 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
4068 if (ret)
4069 goto exit;
4070
4071 /*
4072 * Set RX page boundary
4073 */
4074 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, fops->trxff_boundary);
4075
4076 ret = rtl8xxxu_download_firmware(priv);
4077 dev_dbg(dev, "%s: download_firmware %i\n", __func__, ret);
4078 if (ret)
4079 goto exit;
4080 ret = rtl8xxxu_start_firmware(priv);
4081 dev_dbg(dev, "%s: start_firmware %i\n", __func__, ret);
4082 if (ret)
4083 goto exit;
4084
4085 if (fops->phy_init_antenna_selection)
4086 fops->phy_init_antenna_selection(priv);
4087
4088 ret = rtl8xxxu_init_mac(priv);
4089
4090 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
4091 if (ret)
4092 goto exit;
4093
4094 ret = rtl8xxxu_init_phy_bb(priv);
4095 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
4096 if (ret)
4097 goto exit;
4098
4099 ret = fops->init_phy_rf(priv);
4100 if (ret)
4101 goto exit;
4102
4103 /* Mac APLL Setting */
4104 if (priv->rtl_chip == RTL8192F)
4105 rtl8xxxu_write16_set(priv, REG_AFE_CTRL4, BIT(4) | BIT(15));
4106
4107 /* RFSW Control - clear bit 14 ?? */
4108 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E &&
4109 priv->rtl_chip != RTL8188E && priv->rtl_chip != RTL8710B &&
4110 priv->rtl_chip != RTL8192F)
4111 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
4112
4113 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
4114 FPGA0_RF_ANTSWB |
4115 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB) << FPGA0_RF_BD_CTRL_SHIFT);
4116 if (!priv->no_pape) {
4117 val32 |= (FPGA0_RF_PAPE |
4118 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
4119 }
4120 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4121
4122 /* 0x860[6:5]= 00 - why? - this sets antenna B */
4123 if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188E &&
4124 priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192F)
4125 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210);
4126
4127 if (!macpower) {
4128 /*
4129 * Set TX buffer boundary
4130 */
4131 val8 = fops->total_page_num + 1;
4132
4133 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
4134 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
4135 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
4136 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
4137 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
4138 }
4139
4140 /*
4141 * The vendor drivers set PBP for all devices, except 8192e.
4142 * There is no explanation for this in any of the sources.
4143 */
4144 val8 = (fops->pbp_rx << PBP_PAGE_SIZE_RX_SHIFT) |
4145 (fops->pbp_tx << PBP_PAGE_SIZE_TX_SHIFT);
4146 if (priv->rtl_chip != RTL8192E)
4147 rtl8xxxu_write8(priv, REG_PBP, val8);
4148
4149 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4150 if (!macpower) {
4151 ret = fops->llt_init(priv);
4152 if (ret) {
4153 dev_warn(dev, "%s: LLT table init failed\n", __func__);
4154 goto exit;
4155 }
4156
4157 /*
4158 * Chip specific quirks
4159 */
4160 fops->usb_quirks(priv);
4161
4162 /*
4163 * Enable TX report and TX report timer for 8723bu/8188eu/...
4164 */
4165 if (fops->has_tx_report) {
4166 /*
4167 * The RTL8188EU has two types of TX reports:
4168 * rpt_sel=1:
4169 * One report for one frame. We can use this for frames
4170 * with IEEE80211_TX_CTL_REQ_TX_STATUS.
4171 * rpt_sel=2:
4172 * One report for many frames transmitted over a period
4173 * of time. (This is what REG_TX_REPORT_TIME is for.) The
4174 * report includes the number of frames transmitted
4175 * successfully, and the number of unsuccessful
4176 * transmissions. We use this for software rate control.
4177 *
4178 * Bit 0 of REG_TX_REPORT_CTRL is required for both types.
4179 * Bit 1 (TX_REPORT_CTRL_TIMER_ENABLE) is required for
4180 * type 2.
4181 */
4182 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
4183 if (priv->rtl_chip == RTL8188E)
4184 val8 |= BIT(0);
4185 val8 |= TX_REPORT_CTRL_TIMER_ENABLE;
4186 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
4187 /* Set MAX RPT MACID */
4188 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02);
4189 /* TX report Timer. Unit: 32us */
4190 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0);
4191
4192 /* tmp ps ? */
4193 val8 = rtl8xxxu_read8(priv, 0xa3);
4194 val8 &= 0xf8;
4195 rtl8xxxu_write8(priv, 0xa3, val8);
4196 }
4197
4198 if (priv->rtl_chip == RTL8710B || priv->rtl_chip == RTL8192F)
4199 rtl8xxxu_write8(priv, REG_EARLY_MODE_CONTROL_8710B, 0);
4200 }
4201
4202 /*
4203 * Unit in 8 bytes.
4204 * Get Rx PHY status in order to report RSSI and others.
4205 */
4206 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
4207
4208 if (priv->rtl_chip == RTL8192E) {
4209 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
4210 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
4211 } else if (priv->rtl_chip == RTL8188F) {
4212 rtl8xxxu_write32(priv, REG_HISR0, 0xffffffff);
4213 rtl8xxxu_write32(priv, REG_HISR1, 0xffffffff);
4214 } else if (priv->rtl_chip == RTL8188E) {
4215 rtl8xxxu_write32(priv, REG_HISR0, 0xffffffff);
4216 val32 = IMR0_PSTIMEOUT | IMR0_TBDER | IMR0_CPWM | IMR0_CPWM2;
4217 rtl8xxxu_write32(priv, REG_HIMR0, val32);
4218 val32 = IMR1_TXERR | IMR1_RXERR | IMR1_TXFOVW | IMR1_RXFOVW;
4219 rtl8xxxu_write32(priv, REG_HIMR1, val32);
4220 val8 = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION);
4221 val8 |= USB_SPEC_INT_BULK_SELECT;
4222 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, val8);
4223 } else if (priv->rtl_chip == RTL8710B) {
4224 rtl8xxxu_write32(priv, REG_HIMR0_8710B, 0);
4225 } else if (priv->rtl_chip != RTL8192F) {
4226 /*
4227 * Enable all interrupts - not obvious USB needs to do this
4228 */
4229 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
4230 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
4231 }
4232
4233 rtl8xxxu_set_mac(priv);
4234 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
4235
4236 /*
4237 * Configure initial WMAC settings
4238 */
4239 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
4240 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
4241 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
4242 rtl8xxxu_write32(priv, REG_RCR, val32);
4243 priv->regrcr = val32;
4244
4245 if (fops->init_reg_rxfltmap) {
4246 /* Accept all data frames */
4247 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
4248
4249 /*
4250 * Since ADF is removed from RCR, ps-poll will not be indicate to driver,
4251 * RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll.
4252 */
4253 rtl8xxxu_write16(priv, REG_RXFLTMAP1, 0x400);
4254
4255 /* Accept all management frames */
4256 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
4257 } else {
4258 /*
4259 * Accept all multicast
4260 */
4261 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
4262 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
4263 }
4264
4265 /*
4266 * Init adaptive controls
4267 */
4268 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4269 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4270 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
4271 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4272
4273 /* CCK = 0x0a, OFDM = 0x10 */
4274 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
4275 rtl8xxxu_set_retry(priv, 0x30, 0x30);
4276 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
4277
4278 /*
4279 * Init EDCA
4280 */
4281 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
4282
4283 /* Set CCK SIFS */
4284 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
4285
4286 /* Set OFDM SIFS */
4287 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
4288
4289 /* TXOP */
4290 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
4291 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
4292 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
4293 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
4294
4295 /* Set data auto rate fallback retry count */
4296 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
4297 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
4298 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
4299 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
4300
4301 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
4302 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
4303 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
4304
4305 /* Set ACK timeout */
4306 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
4307
4308 /*
4309 * Initialize beacon parameters
4310 */
4311 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
4312 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
4313 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
4314 if (priv->rtl_chip != RTL8188F && priv->rtl_chip != RTL8710B &&
4315 priv->rtl_chip != RTL8192F)
4316 /* Firmware will control REG_DRVERLYINT when power saving is enable, */
4317 /* so don't set this register on STA mode. */
4318 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
4319 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
4320 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
4321
4322 /*
4323 * Initialize burst parameters
4324 */
4325 if (priv->fops->init_burst)
4326 priv->fops->init_burst(priv);
4327
4328 if (fops->init_aggregation)
4329 fops->init_aggregation(priv);
4330
4331 if (fops->init_reg_pkt_life_time) {
4332 rtl8xxxu_write16(priv, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
4333 rtl8xxxu_write16(priv, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
4334 }
4335
4336 /*
4337 * Enable CCK and OFDM block
4338 */
4339 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4340 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
4341 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4342
4343 /*
4344 * Invalidate all CAM entries - bit 30 is undocumented
4345 */
4346 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
4347
4348 /*
4349 * Start out with default power levels for channel 6, 20MHz
4350 */
4351 fops->set_tx_power(priv, 1, false);
4352
4353 /* Let the 8051 take control of antenna setting */
4354 if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188F &&
4355 priv->rtl_chip != RTL8710B) {
4356 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4357 val8 |= LEDCFG2_DPDT_SELECT;
4358 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4359 }
4360
4361 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
4362
4363 /* Disable BAR - not sure if this has any effect on USB */
4364 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
4365
4366 if (priv->rtl_chip != RTL8188F && priv->rtl_chip != RTL8188E &&
4367 priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192F)
4368 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
4369
4370 if (fops->init_statistics)
4371 fops->init_statistics(priv);
4372
4373 if (priv->rtl_chip == RTL8192E) {
4374 /*
4375 * 0x4c6[3] 1: RTS BW = Data BW
4376 * 0: RTS BW depends on CCA / secondary CCA result.
4377 */
4378 val8 = rtl8xxxu_read8(priv, REG_QUEUE_CTRL);
4379 val8 &= ~BIT(3);
4380 rtl8xxxu_write8(priv, REG_QUEUE_CTRL, val8);
4381 /*
4382 * Reset USB mode switch setting
4383 */
4384 rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00);
4385 } else if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8188E ||
4386 priv->rtl_chip == RTL8192F) {
4387 /*
4388 * Init GPIO settings for 8188f, 8188e, 8192f
4389 */
4390 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
4391 val8 &= ~GPIO_MUXCFG_IO_SEL_ENBT;
4392 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
4393 }
4394
4395 if (priv->rtl_chip == RTL8188F)
4396 /* CCK PD */
4397 rtl8xxxu_write8(priv, REG_CCK_PD_THRESH, CCK_PD_TYPE1_LV1_TH);
4398
4399 fops->phy_lc_calibrate(priv);
4400
4401 fops->phy_iq_calibrate(priv);
4402
4403 /*
4404 * This should enable thermal meter
4405 */
4406 if (fops->gen2_thermal_meter) {
4407 if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8710B) {
4408 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B);
4409 val32 |= 0x30000;
4410 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B, val32);
4411 } else {
4412 rtl8xxxu_write_rfreg(priv,
4413 RF_A, RF6052_REG_T_METER_8723B, 0x37cf8);
4414 }
4415 } else {
4416 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
4417 }
4418
4419 /* Set NAV_UPPER to 30000us */
4420 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
4421 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
4422
4423 if (priv->rtl_chip == RTL8723A) {
4424 /*
4425 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
4426 * but we need to find root cause.
4427 * This is 8723au only.
4428 */
4429 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4430 if ((val32 & 0xff000000) != 0x83000000) {
4431 val32 |= FPGA_RF_MODE_CCK;
4432 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4433 }
4434 } else if (priv->rtl_chip == RTL8192E || priv->rtl_chip == RTL8188E) {
4435 rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00);
4436 }
4437
4438 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
4439 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
4440 /* ack for xmit mgmt frames. */
4441 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
4442
4443 if (priv->rtl_chip == RTL8192E) {
4444 /*
4445 * Fix LDPC rx hang issue.
4446 */
4447 val32 = rtl8xxxu_read32(priv, REG_AFE_MISC);
4448 rtl8xxxu_write8(priv, REG_8192E_LDOV12_CTRL, 0x75);
4449 val32 &= 0xfff00fff;
4450 val32 |= 0x0007e000;
4451 rtl8xxxu_write32(priv, REG_AFE_MISC, val32);
4452
4453 /*
4454 * 0x824[9] = 0x82C[9] = 0xA80[7] those registers setting
4455 * should be equal or CCK RSSI report may be incorrect
4456 */
4457 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
4458 priv->cck_agc_report_type =
4459 u32_get_bits(val32, FPGA0_HSSI_PARM2_CCK_HIGH_PWR);
4460
4461 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_HSSI_PARM2);
4462 if (priv->cck_agc_report_type !=
4463 u32_get_bits(val32, FPGA0_HSSI_PARM2_CCK_HIGH_PWR)) {
4464 if (priv->cck_agc_report_type)
4465 val32 |= FPGA0_HSSI_PARM2_CCK_HIGH_PWR;
4466 else
4467 val32 &= ~FPGA0_HSSI_PARM2_CCK_HIGH_PWR;
4468 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM2, val32);
4469 }
4470
4471 val32 = rtl8xxxu_read32(priv, REG_AGC_RPT);
4472 if (priv->cck_agc_report_type)
4473 val32 |= AGC_RPT_CCK;
4474 else
4475 val32 &= ~AGC_RPT_CCK;
4476 rtl8xxxu_write32(priv, REG_AGC_RPT, val32);
4477 }
4478
4479 if (priv->rtl_chip == RTL8710B) {
4480 /*
4481 * 0x76D[5:4] is Port0,Port1 Enable Bit.
4482 * This is only for 8710B, 2b'00 for MP and 2b'11 for Normal Driver
4483 */
4484 val8 = rtl8xxxu_read8(priv, REG_PORT_CONTROL_8710B);
4485 val8 |= BIT(5) | BIT(4);
4486 rtl8xxxu_write8(priv, REG_PORT_CONTROL_8710B, val8);
4487
4488 /* Set 0x5c[8] and [2:0] = 1, LDO mode */
4489 val32 = rtl8xxxu_read32(priv, REG_WL_RF_PSS_8710B);
4490 val32 |= 0x107;
4491 rtl8xxxu_write32(priv, REG_WL_RF_PSS_8710B, val32);
4492 }
4493
4494 val32 = rtl8xxxu_read32(priv, 0xa9c);
4495 priv->cck_new_agc = u32_get_bits(val32, BIT(17));
4496
4497 /* Initialise the center frequency offset tracking */
4498 if (priv->fops->set_crystal_cap) {
4499 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING);
4500 priv->cfo_tracking.atc_status = val32 & CFO_TRACKING_ATC_STATUS;
4501 priv->cfo_tracking.adjust = true;
4502 priv->cfo_tracking.crystal_cap = priv->default_crystal_cap;
4503 }
4504
4505 if (priv->rtl_chip == RTL8188E)
4506 rtl8188e_ra_info_init_all(&priv->ra_info);
4507
4508 set_bit(RTL8XXXU_BC_MC_MACID, priv->mac_id_map);
4509
4510 exit:
4511 return ret;
4512 }
4513
rtl8xxxu_cam_write(struct rtl8xxxu_priv * priv,struct ieee80211_key_conf * key,const u8 * mac)4514 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
4515 struct ieee80211_key_conf *key, const u8 *mac)
4516 {
4517 u32 cmd, val32, addr, ctrl;
4518 int j, i, tmp_debug;
4519
4520 tmp_debug = rtl8xxxu_debug;
4521 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
4522 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
4523
4524 /*
4525 * This is a bit of a hack - the lower bits of the cipher
4526 * suite selector happens to match the cipher index in the CAM
4527 */
4528 addr = key->keyidx << CAM_CMD_KEY_SHIFT;
4529 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
4530
4531 for (j = 5; j >= 0; j--) {
4532 switch (j) {
4533 case 0:
4534 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
4535 break;
4536 case 1:
4537 val32 = mac[2] | (mac[3] << 8) |
4538 (mac[4] << 16) | (mac[5] << 24);
4539 break;
4540 default:
4541 i = (j - 2) << 2;
4542 val32 = key->key[i] | (key->key[i + 1] << 8) |
4543 key->key[i + 2] << 16 | key->key[i + 3] << 24;
4544 break;
4545 }
4546
4547 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
4548 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
4549 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
4550 udelay(100);
4551 }
4552
4553 rtl8xxxu_debug = tmp_debug;
4554 }
4555
4556 static
rtl8xxxu_get_antenna(struct ieee80211_hw * hw,u32 * tx_ant,u32 * rx_ant)4557 int rtl8xxxu_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
4558 {
4559 struct rtl8xxxu_priv *priv = hw->priv;
4560
4561 *tx_ant = BIT(priv->tx_paths) - 1;
4562 *rx_ant = BIT(priv->rx_paths) - 1;
4563
4564 return 0;
4565 }
4566
rtl8xxxu_set_tim(struct ieee80211_hw * hw,struct ieee80211_sta * sta,bool set)4567 static int rtl8xxxu_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
4568 bool set)
4569 {
4570 struct rtl8xxxu_priv *priv = hw->priv;
4571
4572 schedule_work(&priv->update_beacon_work);
4573
4574 return 0;
4575 }
4576
rtl8xxxu_sw_scan_start(struct ieee80211_hw * hw,struct ieee80211_vif * vif,const u8 * mac)4577 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
4578 struct ieee80211_vif *vif, const u8 *mac)
4579 {
4580 struct rtl8xxxu_priv *priv = hw->priv;
4581 u8 val8;
4582
4583 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4584 val8 |= BEACON_DISABLE_TSF_UPDATE;
4585 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4586 }
4587
rtl8xxxu_sw_scan_complete(struct ieee80211_hw * hw,struct ieee80211_vif * vif)4588 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
4589 struct ieee80211_vif *vif)
4590 {
4591 struct rtl8xxxu_priv *priv = hw->priv;
4592 u8 val8;
4593
4594 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4595 val8 &= ~BEACON_DISABLE_TSF_UPDATE;
4596 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4597 }
4598
rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv * priv,u32 ramask,u8 rateid,int sgi,int txbw_40mhz,u8 macid)4599 void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
4600 u32 ramask, u8 rateid, int sgi, int txbw_40mhz,
4601 u8 macid)
4602 {
4603 struct h2c_cmd h2c;
4604
4605 memset(&h2c, 0, sizeof(struct h2c_cmd));
4606
4607 h2c.ramask.cmd = H2C_SET_RATE_MASK;
4608 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
4609 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
4610
4611 h2c.ramask.arg = 0x80;
4612 if (sgi)
4613 h2c.ramask.arg |= 0x20;
4614
4615 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
4616 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));
4617 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));
4618 }
4619
rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv * priv,u32 ramask,u8 rateid,int sgi,int txbw_40mhz,u8 macid)4620 void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv,
4621 u32 ramask, u8 rateid, int sgi, int txbw_40mhz,
4622 u8 macid)
4623 {
4624 struct h2c_cmd h2c;
4625 u8 bw;
4626
4627 if (txbw_40mhz)
4628 bw = RTL8XXXU_CHANNEL_WIDTH_40;
4629 else
4630 bw = RTL8XXXU_CHANNEL_WIDTH_20;
4631
4632 memset(&h2c, 0, sizeof(struct h2c_cmd));
4633
4634 h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID;
4635 h2c.b_macid_cfg.ramask0 = ramask & 0xff;
4636 h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff;
4637 h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff;
4638 h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff;
4639 h2c.b_macid_cfg.macid = macid;
4640
4641 h2c.b_macid_cfg.data1 = rateid;
4642 if (sgi)
4643 h2c.b_macid_cfg.data1 |= BIT(7);
4644
4645 h2c.b_macid_cfg.data2 = bw;
4646
4647 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, rateid %02x, sgi %d, size %zi\n",
4648 __func__, ramask, rateid, sgi, sizeof(h2c.b_macid_cfg));
4649 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg));
4650 }
4651
rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv * priv,u8 macid,u8 role,bool connect)4652 void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv,
4653 u8 macid, u8 role, bool connect)
4654 {
4655 struct h2c_cmd h2c;
4656
4657 memset(&h2c, 0, sizeof(struct h2c_cmd));
4658
4659 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
4660
4661 if (connect)
4662 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
4663 else
4664 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
4665
4666 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));
4667 }
4668
rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv * priv,u8 macid,u8 role,bool connect)4669 void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv,
4670 u8 macid, u8 role, bool connect)
4671 {
4672 /*
4673 * The firmware turns on the rate control when it knows it's
4674 * connected to a network.
4675 */
4676 struct h2c_cmd h2c;
4677
4678 memset(&h2c, 0, sizeof(struct h2c_cmd));
4679
4680 h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT;
4681 if (connect)
4682 h2c.media_status_rpt.parm |= BIT(0);
4683 else
4684 h2c.media_status_rpt.parm &= ~BIT(0);
4685
4686 h2c.media_status_rpt.parm |= ((role << 4) & 0xf0);
4687 h2c.media_status_rpt.macid = macid;
4688
4689 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt));
4690 }
4691
rtl8xxxu_gen1_report_rssi(struct rtl8xxxu_priv * priv,u8 macid,u8 rssi)4692 void rtl8xxxu_gen1_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi)
4693 {
4694 struct h2c_cmd h2c;
4695 const int h2c_size = 4;
4696
4697 memset(&h2c, 0, sizeof(struct h2c_cmd));
4698
4699 h2c.rssi_report.cmd = H2C_SET_RSSI;
4700 h2c.rssi_report.macid = macid;
4701 h2c.rssi_report.rssi = rssi;
4702
4703 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, h2c_size);
4704 }
4705
rtl8xxxu_gen2_report_rssi(struct rtl8xxxu_priv * priv,u8 macid,u8 rssi)4706 void rtl8xxxu_gen2_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi)
4707 {
4708 struct h2c_cmd h2c;
4709 int h2c_size = sizeof(h2c.rssi_report);
4710
4711 if (priv->rtl_chip == RTL8723B)
4712 h2c_size = 4;
4713
4714 memset(&h2c, 0, sizeof(struct h2c_cmd));
4715
4716 h2c.rssi_report.cmd = H2C_8723B_RSSI_SETTING;
4717 h2c.rssi_report.macid = macid;
4718 h2c.rssi_report.rssi = rssi;
4719
4720 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, h2c_size);
4721 }
4722
rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv * priv)4723 void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv)
4724 {
4725 u8 agg_ctrl, usb_spec, page_thresh, timeout;
4726
4727 usb_spec = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION);
4728 usb_spec &= ~USB_SPEC_USB_AGG_ENABLE;
4729 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, usb_spec);
4730
4731 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
4732 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
4733
4734 if (!rtl8xxxu_dma_aggregation) {
4735 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
4736 return;
4737 }
4738
4739 agg_ctrl |= TRXDMA_CTRL_RXDMA_AGG_EN;
4740 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
4741
4742 /*
4743 * The number of packets we can take looks to be buffer size / 512
4744 * which matches the 512 byte rounding we have to do when de-muxing
4745 * the packets.
4746 *
4747 * Sample numbers from the vendor driver:
4748 * USB High-Speed mode values:
4749 * RxAggBlockCount = 8 : 512 byte unit
4750 * RxAggBlockTimeout = 6
4751 * RxAggPageCount = 48 : 128 byte unit
4752 * RxAggPageTimeout = 4 or 6 (absolute time 34ms/(2^6))
4753 */
4754
4755 page_thresh = (priv->fops->rx_agg_buf_size / 512);
4756 if (rtl8xxxu_dma_agg_pages >= 0) {
4757 if (rtl8xxxu_dma_agg_pages <= page_thresh)
4758 timeout = page_thresh;
4759 else if (rtl8xxxu_dma_agg_pages <= 6)
4760 dev_err(&priv->udev->dev,
4761 "%s: dma_agg_pages=%i too small, minimum is 6\n",
4762 __func__, rtl8xxxu_dma_agg_pages);
4763 else
4764 dev_err(&priv->udev->dev,
4765 "%s: dma_agg_pages=%i larger than limit %i\n",
4766 __func__, rtl8xxxu_dma_agg_pages, page_thresh);
4767 }
4768 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH, page_thresh);
4769 /*
4770 * REG_RXDMA_AGG_PG_TH + 1 seems to be the timeout register on
4771 * gen2 chips and rtl8188eu. The rtl8723au seems unhappy if we
4772 * don't set it, so better set both.
4773 */
4774 timeout = 4;
4775
4776 if (rtl8xxxu_dma_agg_timeout >= 0) {
4777 if (rtl8xxxu_dma_agg_timeout <= 127)
4778 timeout = rtl8xxxu_dma_agg_timeout;
4779 else
4780 dev_err(&priv->udev->dev,
4781 "%s: Invalid dma_agg_timeout: %i\n",
4782 __func__, rtl8xxxu_dma_agg_timeout);
4783 }
4784
4785 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH + 1, timeout);
4786 rtl8xxxu_write8(priv, REG_USB_DMA_AGG_TO, timeout);
4787 priv->rx_buf_aggregation = 1;
4788 }
4789
4790 static const struct ieee80211_rate rtl8xxxu_legacy_ratetable[] = {
4791 {.bitrate = 10, .hw_value = 0x00,},
4792 {.bitrate = 20, .hw_value = 0x01,},
4793 {.bitrate = 55, .hw_value = 0x02,},
4794 {.bitrate = 110, .hw_value = 0x03,},
4795 {.bitrate = 60, .hw_value = 0x04,},
4796 {.bitrate = 90, .hw_value = 0x05,},
4797 {.bitrate = 120, .hw_value = 0x06,},
4798 {.bitrate = 180, .hw_value = 0x07,},
4799 {.bitrate = 240, .hw_value = 0x08,},
4800 {.bitrate = 360, .hw_value = 0x09,},
4801 {.bitrate = 480, .hw_value = 0x0a,},
4802 {.bitrate = 540, .hw_value = 0x0b,},
4803 };
4804
rtl8xxxu_desc_to_mcsrate(u16 rate,u8 * mcs,u8 * nss)4805 static void rtl8xxxu_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss)
4806 {
4807 if (rate <= DESC_RATE_54M)
4808 return;
4809
4810 if (rate >= DESC_RATE_MCS0 && rate <= DESC_RATE_MCS15) {
4811 if (rate < DESC_RATE_MCS8)
4812 *nss = 1;
4813 else
4814 *nss = 2;
4815 *mcs = rate - DESC_RATE_MCS0;
4816 }
4817 }
4818
rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv * priv,u32 rate_cfg)4819 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
4820 {
4821 struct ieee80211_hw *hw = priv->hw;
4822 u32 val32;
4823 u8 rate_idx = 0;
4824
4825 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
4826
4827 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4828 if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ)
4829 val32 &= RESPONSE_RATE_RRSR_INIT_5G;
4830 else
4831 val32 &= RESPONSE_RATE_RRSR_INIT_2G;
4832 val32 |= rate_cfg;
4833 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4834
4835 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
4836
4837 while (rate_cfg) {
4838 rate_cfg = (rate_cfg >> 1);
4839 rate_idx++;
4840 }
4841 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
4842 }
4843
4844 static u16
rtl8xxxu_wireless_mode(struct ieee80211_hw * hw,struct ieee80211_sta * sta)4845 rtl8xxxu_wireless_mode(struct ieee80211_hw *hw, struct ieee80211_sta *sta)
4846 {
4847 u16 network_type = WIRELESS_MODE_UNKNOWN;
4848
4849 if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ) {
4850 if (sta->deflink.vht_cap.vht_supported)
4851 network_type = WIRELESS_MODE_AC;
4852 else if (sta->deflink.ht_cap.ht_supported)
4853 network_type = WIRELESS_MODE_N_5G;
4854
4855 network_type |= WIRELESS_MODE_A;
4856 } else {
4857 if (sta->deflink.vht_cap.vht_supported)
4858 network_type = WIRELESS_MODE_AC;
4859 else if (sta->deflink.ht_cap.ht_supported)
4860 network_type = WIRELESS_MODE_N_24G;
4861
4862 if (sta->deflink.supp_rates[0] <= 0xf)
4863 network_type |= WIRELESS_MODE_B;
4864 else if (sta->deflink.supp_rates[0] & 0xf)
4865 network_type |= (WIRELESS_MODE_B | WIRELESS_MODE_G);
4866 else
4867 network_type |= WIRELESS_MODE_G;
4868 }
4869
4870 return network_type;
4871 }
4872
rtl8xxxu_set_aifs(struct rtl8xxxu_priv * priv,u8 slot_time)4873 static void rtl8xxxu_set_aifs(struct rtl8xxxu_priv *priv, u8 slot_time)
4874 {
4875 u32 reg_edca_param[IEEE80211_NUM_ACS] = {
4876 [IEEE80211_AC_VO] = REG_EDCA_VO_PARAM,
4877 [IEEE80211_AC_VI] = REG_EDCA_VI_PARAM,
4878 [IEEE80211_AC_BE] = REG_EDCA_BE_PARAM,
4879 [IEEE80211_AC_BK] = REG_EDCA_BK_PARAM,
4880 };
4881 u32 val32;
4882 u16 wireless_mode = 0;
4883 u8 aifs, aifsn, sifs;
4884 int i;
4885
4886 if (priv->vif) {
4887 struct ieee80211_sta *sta;
4888
4889 rcu_read_lock();
4890 sta = ieee80211_find_sta(priv->vif, priv->vif->bss_conf.bssid);
4891 if (sta)
4892 wireless_mode = rtl8xxxu_wireless_mode(priv->hw, sta);
4893 rcu_read_unlock();
4894 }
4895
4896 if (priv->hw->conf.chandef.chan->band == NL80211_BAND_5GHZ ||
4897 (wireless_mode & WIRELESS_MODE_N_24G))
4898 sifs = 16;
4899 else
4900 sifs = 10;
4901
4902 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
4903 val32 = rtl8xxxu_read32(priv, reg_edca_param[i]);
4904
4905 /* It was set in conf_tx. */
4906 aifsn = val32 & 0xff;
4907
4908 /* aifsn not set yet or already fixed */
4909 if (aifsn < 2 || aifsn > 15)
4910 continue;
4911
4912 aifs = aifsn * slot_time + sifs;
4913
4914 val32 &= ~0xff;
4915 val32 |= aifs;
4916 rtl8xxxu_write32(priv, reg_edca_param[i], val32);
4917 }
4918 }
4919
rtl8xxxu_update_ra_report(struct rtl8xxxu_ra_report * rarpt,u8 rate,u8 sgi,u8 bw)4920 void rtl8xxxu_update_ra_report(struct rtl8xxxu_ra_report *rarpt,
4921 u8 rate, u8 sgi, u8 bw)
4922 {
4923 u8 mcs, nss;
4924
4925 rarpt->txrate.flags = 0;
4926
4927 if (rate <= DESC_RATE_54M) {
4928 rarpt->txrate.legacy = rtl8xxxu_legacy_ratetable[rate].bitrate;
4929 } else {
4930 rtl8xxxu_desc_to_mcsrate(rate, &mcs, &nss);
4931 rarpt->txrate.flags |= RATE_INFO_FLAGS_MCS;
4932
4933 rarpt->txrate.mcs = mcs;
4934 rarpt->txrate.nss = nss;
4935
4936 if (sgi)
4937 rarpt->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
4938
4939 rarpt->txrate.bw = bw;
4940 }
4941
4942 rarpt->bit_rate = cfg80211_calculate_bitrate(&rarpt->txrate);
4943 rarpt->desc_rate = rate;
4944 }
4945
4946 static void
rtl8xxxu_bss_info_changed(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_bss_conf * bss_conf,u64 changed)4947 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4948 struct ieee80211_bss_conf *bss_conf, u64 changed)
4949 {
4950 struct rtl8xxxu_priv *priv = hw->priv;
4951 struct device *dev = &priv->udev->dev;
4952 struct ieee80211_sta *sta;
4953 struct rtl8xxxu_ra_report *rarpt;
4954 u32 val32;
4955 u8 val8;
4956
4957 rarpt = &priv->ra_report;
4958
4959 if (changed & BSS_CHANGED_ASSOC) {
4960 dev_dbg(dev, "Changed ASSOC: %i!\n", vif->cfg.assoc);
4961
4962 rtl8xxxu_set_linktype(priv, vif->type);
4963
4964 if (vif->cfg.assoc) {
4965 u32 ramask;
4966 int sgi = 0;
4967 u8 highest_rate;
4968 u8 bw;
4969
4970 rcu_read_lock();
4971 sta = ieee80211_find_sta(vif, bss_conf->bssid);
4972 if (!sta) {
4973 dev_info(dev, "%s: ASSOC no sta found\n",
4974 __func__);
4975 rcu_read_unlock();
4976 goto error;
4977 }
4978
4979 if (sta->deflink.ht_cap.ht_supported)
4980 dev_info(dev, "%s: HT supported\n", __func__);
4981 if (sta->deflink.vht_cap.vht_supported)
4982 dev_info(dev, "%s: VHT supported\n", __func__);
4983
4984 /* TODO: Set bits 28-31 for rate adaptive id */
4985 ramask = (sta->deflink.supp_rates[0] & 0xfff) |
4986 sta->deflink.ht_cap.mcs.rx_mask[0] << 12 |
4987 sta->deflink.ht_cap.mcs.rx_mask[1] << 20;
4988 if (sta->deflink.ht_cap.cap &
4989 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
4990 sgi = 1;
4991
4992 highest_rate = fls(ramask) - 1;
4993 if (rtl8xxxu_ht40_2g &&
4994 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40))
4995 bw = RATE_INFO_BW_40;
4996 else
4997 bw = RATE_INFO_BW_20;
4998 rcu_read_unlock();
4999
5000 rtl8xxxu_update_ra_report(rarpt, highest_rate, sgi, bw);
5001
5002 priv->vif = vif;
5003 priv->rssi_level = RTL8XXXU_RATR_STA_INIT;
5004
5005 priv->fops->update_rate_mask(priv, ramask, 0, sgi,
5006 bw == RATE_INFO_BW_40, 0);
5007
5008 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
5009
5010 rtl8xxxu_stop_tx_beacon(priv);
5011
5012 /* joinbss sequence */
5013 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
5014 0xc000 | vif->cfg.aid);
5015
5016 priv->fops->report_connect(priv, 0, H2C_MACID_ROLE_AP, true);
5017 } else {
5018 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5019 val8 |= BEACON_DISABLE_TSF_UPDATE;
5020 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5021
5022 priv->fops->report_connect(priv, 0, H2C_MACID_ROLE_AP, false);
5023 }
5024 }
5025
5026 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
5027 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
5028 bss_conf->use_short_preamble);
5029 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
5030 if (bss_conf->use_short_preamble)
5031 val32 |= RSR_ACK_SHORT_PREAMBLE;
5032 else
5033 val32 &= ~RSR_ACK_SHORT_PREAMBLE;
5034 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
5035 }
5036
5037 if (changed & BSS_CHANGED_ERP_SLOT) {
5038 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
5039 bss_conf->use_short_slot);
5040
5041 if (bss_conf->use_short_slot)
5042 val8 = 9;
5043 else
5044 val8 = 20;
5045 rtl8xxxu_write8(priv, REG_SLOT, val8);
5046
5047 rtl8xxxu_set_aifs(priv, val8);
5048 }
5049
5050 if (changed & BSS_CHANGED_BSSID) {
5051 dev_dbg(dev, "Changed BSSID!\n");
5052 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
5053 }
5054
5055 if (changed & BSS_CHANGED_BASIC_RATES) {
5056 dev_dbg(dev, "Changed BASIC_RATES!\n");
5057 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
5058 }
5059
5060 if (changed & BSS_CHANGED_BEACON_ENABLED) {
5061 if (bss_conf->enable_beacon)
5062 rtl8xxxu_start_tx_beacon(priv);
5063 else
5064 rtl8xxxu_stop_tx_beacon(priv);
5065 }
5066
5067 if (changed & BSS_CHANGED_BEACON)
5068 schedule_work(&priv->update_beacon_work);
5069
5070 error:
5071 return;
5072 }
5073
rtl8xxxu_start_ap(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_bss_conf * link_conf)5074 static int rtl8xxxu_start_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5075 struct ieee80211_bss_conf *link_conf)
5076 {
5077 struct rtl8xxxu_priv *priv = hw->priv;
5078 struct device *dev = &priv->udev->dev;
5079
5080 dev_dbg(dev, "Start AP mode\n");
5081 rtl8xxxu_set_bssid(priv, vif->bss_conf.bssid);
5082 rtl8xxxu_write16(priv, REG_BCN_INTERVAL, vif->bss_conf.beacon_int);
5083 priv->fops->report_connect(priv, RTL8XXXU_BC_MC_MACID, 0, true);
5084
5085 return 0;
5086 }
5087
rtl8xxxu_80211_to_rtl_queue(u32 queue)5088 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
5089 {
5090 u32 rtlqueue;
5091
5092 switch (queue) {
5093 case IEEE80211_AC_VO:
5094 rtlqueue = TXDESC_QUEUE_VO;
5095 break;
5096 case IEEE80211_AC_VI:
5097 rtlqueue = TXDESC_QUEUE_VI;
5098 break;
5099 case IEEE80211_AC_BE:
5100 rtlqueue = TXDESC_QUEUE_BE;
5101 break;
5102 case IEEE80211_AC_BK:
5103 rtlqueue = TXDESC_QUEUE_BK;
5104 break;
5105 default:
5106 rtlqueue = TXDESC_QUEUE_BE;
5107 }
5108
5109 return rtlqueue;
5110 }
5111
rtl8xxxu_queue_select(struct ieee80211_hdr * hdr,struct sk_buff * skb)5112 static u32 rtl8xxxu_queue_select(struct ieee80211_hdr *hdr, struct sk_buff *skb)
5113 {
5114 u32 queue;
5115
5116 if (unlikely(ieee80211_is_beacon(hdr->frame_control)))
5117 queue = TXDESC_QUEUE_BEACON;
5118 else if (ieee80211_is_mgmt(hdr->frame_control))
5119 queue = TXDESC_QUEUE_MGNT;
5120 else
5121 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
5122
5123 return queue;
5124 }
5125
5126 /*
5127 * Despite newer chips 8723b/8812/8821 having a larger TX descriptor
5128 * format. The descriptor checksum is still only calculated over the
5129 * initial 32 bytes of the descriptor!
5130 */
rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 * tx_desc)5131 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc)
5132 {
5133 __le16 *ptr = (__le16 *)tx_desc;
5134 u16 csum = 0;
5135 int i;
5136
5137 /*
5138 * Clear csum field before calculation, as the csum field is
5139 * in the middle of the struct.
5140 */
5141 tx_desc->csum = cpu_to_le16(0);
5142
5143 for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++)
5144 csum = csum ^ le16_to_cpu(ptr[i]);
5145
5146 tx_desc->csum |= cpu_to_le16(csum);
5147 }
5148
rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv * priv)5149 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
5150 {
5151 struct rtl8xxxu_tx_urb *tx_urb, *tmp;
5152 unsigned long flags;
5153
5154 spin_lock_irqsave(&priv->tx_urb_lock, flags);
5155 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
5156 list_del(&tx_urb->list);
5157 priv->tx_urb_free_count--;
5158 usb_free_urb(&tx_urb->urb);
5159 }
5160 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5161 }
5162
5163 static struct rtl8xxxu_tx_urb *
rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv * priv)5164 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
5165 {
5166 struct rtl8xxxu_tx_urb *tx_urb;
5167 unsigned long flags;
5168
5169 spin_lock_irqsave(&priv->tx_urb_lock, flags);
5170 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
5171 struct rtl8xxxu_tx_urb, list);
5172 if (tx_urb) {
5173 list_del(&tx_urb->list);
5174 priv->tx_urb_free_count--;
5175 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
5176 !priv->tx_stopped) {
5177 priv->tx_stopped = true;
5178 ieee80211_stop_queues(priv->hw);
5179 }
5180 }
5181
5182 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5183
5184 return tx_urb;
5185 }
5186
rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv * priv,struct rtl8xxxu_tx_urb * tx_urb)5187 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
5188 struct rtl8xxxu_tx_urb *tx_urb)
5189 {
5190 unsigned long flags;
5191
5192 INIT_LIST_HEAD(&tx_urb->list);
5193
5194 spin_lock_irqsave(&priv->tx_urb_lock, flags);
5195
5196 list_add(&tx_urb->list, &priv->tx_urb_free_list);
5197 priv->tx_urb_free_count++;
5198 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
5199 priv->tx_stopped) {
5200 priv->tx_stopped = false;
5201 ieee80211_wake_queues(priv->hw);
5202 }
5203
5204 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5205 }
5206
rtl8xxxu_tx_complete(struct urb * urb)5207 static void rtl8xxxu_tx_complete(struct urb *urb)
5208 {
5209 struct sk_buff *skb = (struct sk_buff *)urb->context;
5210 struct ieee80211_tx_info *tx_info;
5211 struct ieee80211_hw *hw;
5212 struct rtl8xxxu_priv *priv;
5213 struct rtl8xxxu_tx_urb *tx_urb =
5214 container_of(urb, struct rtl8xxxu_tx_urb, urb);
5215
5216 tx_info = IEEE80211_SKB_CB(skb);
5217 hw = tx_info->rate_driver_data[0];
5218 priv = hw->priv;
5219
5220 skb_pull(skb, priv->fops->tx_desc_size);
5221
5222 ieee80211_tx_info_clear_status(tx_info);
5223 tx_info->status.rates[0].idx = -1;
5224 tx_info->status.rates[0].count = 0;
5225
5226 if (!urb->status)
5227 tx_info->flags |= IEEE80211_TX_STAT_ACK;
5228
5229 ieee80211_tx_status_irqsafe(hw, skb);
5230
5231 rtl8xxxu_free_tx_urb(priv, tx_urb);
5232 }
5233
rtl8xxxu_dump_action(struct device * dev,struct ieee80211_hdr * hdr)5234 static void rtl8xxxu_dump_action(struct device *dev,
5235 struct ieee80211_hdr *hdr)
5236 {
5237 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
5238 u16 cap, timeout;
5239
5240 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
5241 return;
5242
5243 switch (mgmt->u.action.u.addba_resp.action_code) {
5244 case WLAN_ACTION_ADDBA_RESP:
5245 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
5246 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
5247 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
5248 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
5249 "status %02x\n",
5250 timeout,
5251 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
5252 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
5253 (cap >> 1) & 0x1,
5254 le16_to_cpu(mgmt->u.action.u.addba_resp.status));
5255 break;
5256 case WLAN_ACTION_ADDBA_REQ:
5257 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
5258 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
5259 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
5260 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
5261 timeout,
5262 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
5263 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
5264 (cap >> 1) & 0x1);
5265 break;
5266 default:
5267 dev_info(dev, "action frame %02x\n",
5268 mgmt->u.action.u.addba_resp.action_code);
5269 break;
5270 }
5271 }
5272
5273 /*
5274 * Fill in v1 (gen1) specific TX descriptor bits.
5275 * This format is used on 8188cu/8192cu/8723au
5276 */
5277 void
rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw * hw,struct ieee80211_hdr * hdr,struct ieee80211_tx_info * tx_info,struct rtl8xxxu_txdesc32 * tx_desc,bool sgi,bool short_preamble,bool ampdu_enable,u32 rts_rate,u8 macid)5278 rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
5279 struct ieee80211_tx_info *tx_info,
5280 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi,
5281 bool short_preamble, bool ampdu_enable, u32 rts_rate,
5282 u8 macid)
5283 {
5284 struct rtl8xxxu_priv *priv = hw->priv;
5285 struct device *dev = &priv->udev->dev;
5286 u8 *qc = ieee80211_get_qos_ctl(hdr);
5287 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
5288 u32 rate = 0;
5289 u16 seq_number;
5290
5291 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
5292 dev_info(dev, "%s: TX rate: %d, pkt size %u\n",
5293 __func__, rate, le16_to_cpu(tx_desc->pkt_size));
5294
5295 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
5296
5297 tx_desc->txdw5 = cpu_to_le32(rate);
5298
5299 if (ieee80211_is_data(hdr->frame_control))
5300 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
5301
5302 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT);
5303
5304 if (ampdu_enable && test_bit(tid, priv->tid_tx_operational))
5305 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE);
5306 else
5307 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK);
5308
5309 if (ieee80211_is_mgmt(hdr->frame_control)) {
5310 tx_desc->txdw5 = cpu_to_le32(rate);
5311 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
5312 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT);
5313 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE);
5314 }
5315
5316 if (ieee80211_is_data_qos(hdr->frame_control))
5317 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS);
5318
5319 if (short_preamble)
5320 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE);
5321
5322 if (sgi)
5323 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI);
5324
5325 /*
5326 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled
5327 */
5328 tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT);
5329 if (ampdu_enable || tx_info->control.use_rts) {
5330 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE);
5331 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
5332 } else if (tx_info->control.use_cts_prot) {
5333 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE);
5334 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
5335 }
5336 }
5337
5338 /*
5339 * Fill in v2 (gen2) specific TX descriptor bits.
5340 * This format is used on 8192eu/8723bu
5341 */
5342 void
rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw * hw,struct ieee80211_hdr * hdr,struct ieee80211_tx_info * tx_info,struct rtl8xxxu_txdesc32 * tx_desc32,bool sgi,bool short_preamble,bool ampdu_enable,u32 rts_rate,u8 macid)5343 rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
5344 struct ieee80211_tx_info *tx_info,
5345 struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi,
5346 bool short_preamble, bool ampdu_enable, u32 rts_rate,
5347 u8 macid)
5348 {
5349 struct rtl8xxxu_priv *priv = hw->priv;
5350 struct device *dev = &priv->udev->dev;
5351 struct rtl8xxxu_txdesc40 *tx_desc40;
5352 u8 *qc = ieee80211_get_qos_ctl(hdr);
5353 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
5354 u32 rate = 0;
5355 u16 seq_number;
5356
5357 tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc32;
5358
5359 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
5360 dev_info(dev, "%s: TX rate: %d, pkt size %u\n",
5361 __func__, rate, le16_to_cpu(tx_desc40->pkt_size));
5362
5363 tx_desc40->txdw1 |= cpu_to_le32(macid << TXDESC40_MACID_SHIFT);
5364
5365 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
5366
5367 tx_desc40->txdw4 = cpu_to_le32(rate);
5368 if (ieee80211_is_data(hdr->frame_control)) {
5369 tx_desc40->txdw4 |= cpu_to_le32(0x1f <<
5370 TXDESC40_DATA_RATE_FB_SHIFT);
5371 }
5372
5373 tx_desc40->txdw9 = cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT);
5374
5375 if (ampdu_enable && test_bit(tid, priv->tid_tx_operational))
5376 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE);
5377 else
5378 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK);
5379
5380 if (ieee80211_is_mgmt(hdr->frame_control)) {
5381 tx_desc40->txdw4 = cpu_to_le32(rate);
5382 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_USE_DRIVER_RATE);
5383 tx_desc40->txdw4 |=
5384 cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT);
5385 tx_desc40->txdw4 |= cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE);
5386 }
5387
5388 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)
5389 tx_desc40->txdw8 |= cpu_to_le32(TXDESC40_HW_SEQ_ENABLE);
5390
5391 if (short_preamble)
5392 tx_desc40->txdw5 |= cpu_to_le32(TXDESC40_SHORT_PREAMBLE);
5393
5394 tx_desc40->txdw4 |= cpu_to_le32(rts_rate << TXDESC40_RTS_RATE_SHIFT);
5395
5396 /*
5397 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled
5398 */
5399 if (ampdu_enable || tx_info->control.use_rts) {
5400 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE);
5401 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE);
5402 } else if (tx_info->control.use_cts_prot) {
5403 /*
5404 * For some reason the vendor driver doesn't set
5405 * TXDESC40_HW_RTS_ENABLE for CTS to SELF
5406 */
5407 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_CTS_SELF_ENABLE);
5408 }
5409 }
5410
5411 /*
5412 * Fill in v3 (gen1) specific TX descriptor bits.
5413 * This format is a hybrid between the v1 and v2 formats, only seen
5414 * on 8188eu devices so far.
5415 */
5416 void
rtl8xxxu_fill_txdesc_v3(struct ieee80211_hw * hw,struct ieee80211_hdr * hdr,struct ieee80211_tx_info * tx_info,struct rtl8xxxu_txdesc32 * tx_desc,bool sgi,bool short_preamble,bool ampdu_enable,u32 rts_rate,u8 macid)5417 rtl8xxxu_fill_txdesc_v3(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
5418 struct ieee80211_tx_info *tx_info,
5419 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi,
5420 bool short_preamble, bool ampdu_enable, u32 rts_rate,
5421 u8 macid)
5422 {
5423 struct rtl8xxxu_priv *priv = hw->priv;
5424 struct device *dev = &priv->udev->dev;
5425 struct rtl8xxxu_ra_info *ra = &priv->ra_info;
5426 u8 *qc = ieee80211_get_qos_ctl(hdr);
5427 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
5428 u32 rate = 0;
5429 u16 seq_number;
5430
5431 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
5432
5433 if (ieee80211_is_data(hdr->frame_control)) {
5434 rate = ra->decision_rate;
5435 tx_desc->txdw5 = cpu_to_le32(rate);
5436 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
5437 tx_desc->txdw4 |= le32_encode_bits(ra->pt_stage, TXDESC32_PT_STAGE_MASK);
5438 /* Data/RTS rate FB limit */
5439 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
5440 }
5441
5442 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
5443 dev_info(dev, "%s: TX rate: %d, pkt size %d\n",
5444 __func__, rate, le16_to_cpu(tx_desc->pkt_size));
5445
5446 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT);
5447
5448 if (ampdu_enable && test_bit(tid, priv->tid_tx_operational))
5449 tx_desc->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE);
5450 else
5451 tx_desc->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK);
5452
5453 if (ieee80211_is_mgmt(hdr->frame_control)) {
5454 tx_desc->txdw5 = cpu_to_le32(rate);
5455 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
5456 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT);
5457 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE);
5458 }
5459
5460 if (ieee80211_is_data_qos(hdr->frame_control)) {
5461 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS);
5462
5463 if (conf_is_ht40(&hw->conf)) {
5464 tx_desc->txdw4 |= cpu_to_le32(TXDESC_DATA_BW);
5465
5466 if (conf_is_ht40_minus(&hw->conf))
5467 tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_UPPER);
5468 else
5469 tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_LOWER);
5470 }
5471 }
5472
5473 if (short_preamble)
5474 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE);
5475
5476 if (sgi && ra->rate_sgi)
5477 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI);
5478
5479 /*
5480 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled
5481 */
5482 tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT);
5483 if (ampdu_enable || tx_info->control.use_rts) {
5484 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE);
5485 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
5486 } else if (tx_info->control.use_cts_prot) {
5487 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE);
5488 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
5489 }
5490
5491 tx_desc->txdw2 |= cpu_to_le32(TXDESC_ANTENNA_SELECT_A |
5492 TXDESC_ANTENNA_SELECT_B);
5493 tx_desc->txdw7 |= cpu_to_le16(TXDESC_ANTENNA_SELECT_C >> 16);
5494 }
5495
rtl8xxxu_tx(struct ieee80211_hw * hw,struct ieee80211_tx_control * control,struct sk_buff * skb)5496 static void rtl8xxxu_tx(struct ieee80211_hw *hw,
5497 struct ieee80211_tx_control *control,
5498 struct sk_buff *skb)
5499 {
5500 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
5501 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
5502 struct rtl8xxxu_priv *priv = hw->priv;
5503 struct rtl8xxxu_txdesc32 *tx_desc;
5504 struct rtl8xxxu_tx_urb *tx_urb;
5505 struct ieee80211_sta *sta = NULL;
5506 struct ieee80211_vif *vif = tx_info->control.vif;
5507 struct device *dev = &priv->udev->dev;
5508 u32 queue, rts_rate;
5509 u16 pktlen = skb->len;
5510 int tx_desc_size = priv->fops->tx_desc_size;
5511 u8 macid;
5512 int ret;
5513 bool ampdu_enable, sgi = false, short_preamble = false;
5514
5515 if (skb_headroom(skb) < tx_desc_size) {
5516 dev_warn(dev,
5517 "%s: Not enough headroom (%i) for tx descriptor\n",
5518 __func__, skb_headroom(skb));
5519 goto error;
5520 }
5521
5522 if (unlikely(skb->len > (65535 - tx_desc_size))) {
5523 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
5524 __func__, skb->len);
5525 goto error;
5526 }
5527
5528 tx_urb = rtl8xxxu_alloc_tx_urb(priv);
5529 if (!tx_urb) {
5530 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
5531 goto error;
5532 }
5533
5534 if (ieee80211_is_action(hdr->frame_control))
5535 rtl8xxxu_dump_action(dev, hdr);
5536
5537 tx_info->rate_driver_data[0] = hw;
5538
5539 if (control && control->sta)
5540 sta = control->sta;
5541
5542 queue = rtl8xxxu_queue_select(hdr, skb);
5543
5544 tx_desc = skb_push(skb, tx_desc_size);
5545
5546 memset(tx_desc, 0, tx_desc_size);
5547 tx_desc->pkt_size = cpu_to_le16(pktlen);
5548 tx_desc->pkt_offset = tx_desc_size;
5549
5550 /* These bits mean different things to the RTL8192F. */
5551 if (priv->rtl_chip != RTL8192F)
5552 tx_desc->txdw0 =
5553 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
5554 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
5555 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
5556 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
5557
5558 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
5559
5560 if (tx_info->control.hw_key) {
5561 switch (tx_info->control.hw_key->cipher) {
5562 case WLAN_CIPHER_SUITE_WEP40:
5563 case WLAN_CIPHER_SUITE_WEP104:
5564 case WLAN_CIPHER_SUITE_TKIP:
5565 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
5566 break;
5567 case WLAN_CIPHER_SUITE_CCMP:
5568 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
5569 break;
5570 default:
5571 break;
5572 }
5573 }
5574
5575 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
5576 ampdu_enable = false;
5577 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
5578 if (sta->deflink.ht_cap.ht_supported) {
5579 u32 ampdu, val32;
5580 u8 *qc = ieee80211_get_qos_ctl(hdr);
5581 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
5582
5583 ampdu = (u32)sta->deflink.ht_cap.ampdu_density;
5584 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
5585 tx_desc->txdw2 |= cpu_to_le32(val32);
5586
5587 ampdu_enable = true;
5588
5589 if (!test_bit(tid, priv->tx_aggr_started) &&
5590 !(skb->protocol == cpu_to_be16(ETH_P_PAE)))
5591 if (!ieee80211_start_tx_ba_session(sta, tid, 0))
5592 set_bit(tid, priv->tx_aggr_started);
5593 }
5594 }
5595
5596 if (ieee80211_is_data_qos(hdr->frame_control) &&
5597 sta && sta->deflink.ht_cap.cap &
5598 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
5599 sgi = true;
5600
5601 if (sta && vif && vif->bss_conf.use_short_preamble)
5602 short_preamble = true;
5603
5604 if (skb->len > hw->wiphy->rts_threshold)
5605 tx_info->control.use_rts = true;
5606
5607 if (sta && vif && vif->bss_conf.use_cts_prot)
5608 tx_info->control.use_cts_prot = true;
5609
5610 if (ampdu_enable || tx_info->control.use_rts ||
5611 tx_info->control.use_cts_prot)
5612 rts_rate = DESC_RATE_24M;
5613 else
5614 rts_rate = 0;
5615
5616 macid = rtl8xxxu_get_macid(priv, sta);
5617 priv->fops->fill_txdesc(hw, hdr, tx_info, tx_desc, sgi, short_preamble,
5618 ampdu_enable, rts_rate, macid);
5619
5620 rtl8xxxu_calc_tx_desc_csum(tx_desc);
5621
5622 /* avoid zero checksum make tx hang */
5623 if (priv->rtl_chip == RTL8710B || priv->rtl_chip == RTL8192F)
5624 tx_desc->csum = ~tx_desc->csum;
5625
5626 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
5627 skb->data, skb->len, rtl8xxxu_tx_complete, skb);
5628
5629 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
5630 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
5631 if (ret) {
5632 usb_unanchor_urb(&tx_urb->urb);
5633 rtl8xxxu_free_tx_urb(priv, tx_urb);
5634 goto error;
5635 }
5636 return;
5637 error:
5638 dev_kfree_skb(skb);
5639 }
5640
rtl8xxxu_send_beacon_frame(struct ieee80211_hw * hw,struct ieee80211_vif * vif)5641 static void rtl8xxxu_send_beacon_frame(struct ieee80211_hw *hw,
5642 struct ieee80211_vif *vif)
5643 {
5644 struct rtl8xxxu_priv *priv = hw->priv;
5645 struct sk_buff *skb = ieee80211_beacon_get(hw, vif, 0);
5646 struct device *dev = &priv->udev->dev;
5647 int retry;
5648 u8 val8;
5649
5650 /* BCN_VALID, write 1 to clear, cleared by SW */
5651 val8 = rtl8xxxu_read8(priv, REG_TDECTRL + 2);
5652 val8 |= BIT_BCN_VALID >> 16;
5653 rtl8xxxu_write8(priv, REG_TDECTRL + 2, val8);
5654
5655 /* SW_BCN_SEL - Port0 */
5656 val8 = rtl8xxxu_read8(priv, REG_DWBCN1_CTRL_8723B + 2);
5657 val8 &= ~(BIT_SW_BCN_SEL >> 16);
5658 rtl8xxxu_write8(priv, REG_DWBCN1_CTRL_8723B + 2, val8);
5659
5660 if (skb)
5661 rtl8xxxu_tx(hw, NULL, skb);
5662
5663 retry = 100;
5664 do {
5665 val8 = rtl8xxxu_read8(priv, REG_TDECTRL + 2);
5666 if (val8 & (BIT_BCN_VALID >> 16))
5667 break;
5668 usleep_range(10, 20);
5669 } while (--retry);
5670
5671 if (!retry)
5672 dev_err(dev, "%s: Failed to read beacon valid bit\n", __func__);
5673 }
5674
rtl8xxxu_update_beacon_work_callback(struct work_struct * work)5675 static void rtl8xxxu_update_beacon_work_callback(struct work_struct *work)
5676 {
5677 struct rtl8xxxu_priv *priv =
5678 container_of(work, struct rtl8xxxu_priv, update_beacon_work);
5679 struct ieee80211_hw *hw = priv->hw;
5680 struct ieee80211_vif *vif = priv->vif;
5681
5682 if (!vif) {
5683 WARN_ONCE(true, "no vif to update beacon\n");
5684 return;
5685 }
5686
5687 rtl8xxxu_send_beacon_frame(hw, vif);
5688 }
5689
rtl8723au_rx_parse_phystats(struct rtl8xxxu_priv * priv,struct ieee80211_rx_status * rx_status,struct rtl8723au_phy_stats * phy_stats,u32 rxmcs,struct ieee80211_hdr * hdr,bool crc_icv_err)5690 void rtl8723au_rx_parse_phystats(struct rtl8xxxu_priv *priv,
5691 struct ieee80211_rx_status *rx_status,
5692 struct rtl8723au_phy_stats *phy_stats,
5693 u32 rxmcs, struct ieee80211_hdr *hdr,
5694 bool crc_icv_err)
5695 {
5696 if (phy_stats->sgi_en)
5697 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
5698
5699 if (rxmcs < DESC_RATE_6M) {
5700 /*
5701 * Handle PHY stats for CCK rates
5702 */
5703 rx_status->signal = priv->fops->cck_rssi(priv, phy_stats);
5704 } else {
5705 bool parse_cfo = priv->fops->set_crystal_cap &&
5706 priv->vif &&
5707 priv->vif->type == NL80211_IFTYPE_STATION &&
5708 priv->vif->cfg.assoc &&
5709 !crc_icv_err &&
5710 !ieee80211_is_ctl(hdr->frame_control) &&
5711 ether_addr_equal(priv->vif->bss_conf.bssid, hdr->addr2);
5712
5713 if (parse_cfo) {
5714 priv->cfo_tracking.cfo_tail[0] = phy_stats->path_cfotail[0];
5715 priv->cfo_tracking.cfo_tail[1] = phy_stats->path_cfotail[1];
5716
5717 priv->cfo_tracking.packet_count++;
5718 }
5719
5720 rx_status->signal =
5721 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
5722 }
5723 }
5724
jaguar2_rx_parse_phystats_type0(struct rtl8xxxu_priv * priv,struct ieee80211_rx_status * rx_status,struct jaguar2_phy_stats_type0 * phy_stats0,u32 rxmcs,struct ieee80211_hdr * hdr,bool crc_icv_err)5725 static void jaguar2_rx_parse_phystats_type0(struct rtl8xxxu_priv *priv,
5726 struct ieee80211_rx_status *rx_status,
5727 struct jaguar2_phy_stats_type0 *phy_stats0,
5728 u32 rxmcs, struct ieee80211_hdr *hdr,
5729 bool crc_icv_err)
5730 {
5731 s8 rx_power = phy_stats0->pwdb - 110;
5732
5733 if (!priv->cck_new_agc)
5734 rx_power = priv->fops->cck_rssi(priv, (struct rtl8723au_phy_stats *)phy_stats0);
5735
5736 rx_status->signal = rx_power;
5737 }
5738
jaguar2_rx_parse_phystats_type1(struct rtl8xxxu_priv * priv,struct ieee80211_rx_status * rx_status,struct jaguar2_phy_stats_type1 * phy_stats1,u32 rxmcs,struct ieee80211_hdr * hdr,bool crc_icv_err)5739 static void jaguar2_rx_parse_phystats_type1(struct rtl8xxxu_priv *priv,
5740 struct ieee80211_rx_status *rx_status,
5741 struct jaguar2_phy_stats_type1 *phy_stats1,
5742 u32 rxmcs, struct ieee80211_hdr *hdr,
5743 bool crc_icv_err)
5744 {
5745 bool parse_cfo = priv->fops->set_crystal_cap &&
5746 priv->vif &&
5747 priv->vif->type == NL80211_IFTYPE_STATION &&
5748 priv->vif->cfg.assoc &&
5749 !crc_icv_err &&
5750 !ieee80211_is_ctl(hdr->frame_control) &&
5751 ether_addr_equal(priv->vif->bss_conf.bssid, hdr->addr2);
5752 u8 pwdb_max = 0;
5753 int rx_path;
5754
5755 if (parse_cfo) {
5756 /* Only path-A and path-B have CFO tail and short CFO */
5757 priv->cfo_tracking.cfo_tail[RF_A] = phy_stats1->cfo_tail[RF_A];
5758 priv->cfo_tracking.cfo_tail[RF_B] = phy_stats1->cfo_tail[RF_B];
5759
5760 priv->cfo_tracking.packet_count++;
5761 }
5762
5763 for (rx_path = 0; rx_path < priv->rx_paths; rx_path++)
5764 pwdb_max = max(pwdb_max, phy_stats1->pwdb[rx_path]);
5765
5766 rx_status->signal = pwdb_max - 110;
5767 }
5768
jaguar2_rx_parse_phystats_type2(struct rtl8xxxu_priv * priv,struct ieee80211_rx_status * rx_status,struct jaguar2_phy_stats_type2 * phy_stats2,u32 rxmcs,struct ieee80211_hdr * hdr,bool crc_icv_err)5769 static void jaguar2_rx_parse_phystats_type2(struct rtl8xxxu_priv *priv,
5770 struct ieee80211_rx_status *rx_status,
5771 struct jaguar2_phy_stats_type2 *phy_stats2,
5772 u32 rxmcs, struct ieee80211_hdr *hdr,
5773 bool crc_icv_err)
5774 {
5775 u8 pwdb_max = 0;
5776 int rx_path;
5777
5778 for (rx_path = 0; rx_path < priv->rx_paths; rx_path++)
5779 pwdb_max = max(pwdb_max, phy_stats2->pwdb[rx_path]);
5780
5781 rx_status->signal = pwdb_max - 110;
5782 }
5783
jaguar2_rx_parse_phystats(struct rtl8xxxu_priv * priv,struct ieee80211_rx_status * rx_status,struct rtl8723au_phy_stats * phy_stats,u32 rxmcs,struct ieee80211_hdr * hdr,bool crc_icv_err)5784 void jaguar2_rx_parse_phystats(struct rtl8xxxu_priv *priv,
5785 struct ieee80211_rx_status *rx_status,
5786 struct rtl8723au_phy_stats *phy_stats,
5787 u32 rxmcs, struct ieee80211_hdr *hdr,
5788 bool crc_icv_err)
5789 {
5790 struct jaguar2_phy_stats_type0 *phy_stats0 = (struct jaguar2_phy_stats_type0 *)phy_stats;
5791 struct jaguar2_phy_stats_type1 *phy_stats1 = (struct jaguar2_phy_stats_type1 *)phy_stats;
5792 struct jaguar2_phy_stats_type2 *phy_stats2 = (struct jaguar2_phy_stats_type2 *)phy_stats;
5793
5794 switch (phy_stats0->page_num) {
5795 case 0:
5796 /* CCK */
5797 jaguar2_rx_parse_phystats_type0(priv, rx_status, phy_stats0,
5798 rxmcs, hdr, crc_icv_err);
5799 break;
5800 case 1:
5801 /* OFDM */
5802 jaguar2_rx_parse_phystats_type1(priv, rx_status, phy_stats1,
5803 rxmcs, hdr, crc_icv_err);
5804 break;
5805 case 2:
5806 /* Also OFDM but different (how?) */
5807 jaguar2_rx_parse_phystats_type2(priv, rx_status, phy_stats2,
5808 rxmcs, hdr, crc_icv_err);
5809 break;
5810 default:
5811 return;
5812 }
5813 }
5814
rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv * priv)5815 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
5816 {
5817 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5818 unsigned long flags;
5819
5820 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5821
5822 list_for_each_entry_safe(rx_urb, tmp,
5823 &priv->rx_urb_pending_list, list) {
5824 list_del(&rx_urb->list);
5825 priv->rx_urb_pending_count--;
5826 usb_free_urb(&rx_urb->urb);
5827 }
5828
5829 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5830 }
5831
rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv * priv,struct rtl8xxxu_rx_urb * rx_urb)5832 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
5833 struct rtl8xxxu_rx_urb *rx_urb)
5834 {
5835 struct sk_buff *skb;
5836 unsigned long flags;
5837 int pending = 0;
5838
5839 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5840
5841 if (!priv->shutdown) {
5842 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
5843 priv->rx_urb_pending_count++;
5844 pending = priv->rx_urb_pending_count;
5845 } else {
5846 skb = (struct sk_buff *)rx_urb->urb.context;
5847 dev_kfree_skb_irq(skb);
5848 usb_free_urb(&rx_urb->urb);
5849 }
5850
5851 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5852
5853 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
5854 schedule_work(&priv->rx_urb_wq);
5855 }
5856
rtl8xxxu_rx_urb_work(struct work_struct * work)5857 static void rtl8xxxu_rx_urb_work(struct work_struct *work)
5858 {
5859 struct rtl8xxxu_priv *priv;
5860 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5861 struct list_head local;
5862 struct sk_buff *skb;
5863 unsigned long flags;
5864 int ret;
5865
5866 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
5867 INIT_LIST_HEAD(&local);
5868
5869 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5870
5871 list_splice_init(&priv->rx_urb_pending_list, &local);
5872 priv->rx_urb_pending_count = 0;
5873
5874 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5875
5876 list_for_each_entry_safe(rx_urb, tmp, &local, list) {
5877 list_del_init(&rx_urb->list);
5878 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5879 /*
5880 * If out of memory or temporary error, put it back on the
5881 * queue and try again. Otherwise the device is dead/gone
5882 * and we should drop it.
5883 */
5884 switch (ret) {
5885 case 0:
5886 break;
5887 case -ENOMEM:
5888 case -EAGAIN:
5889 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5890 break;
5891 default:
5892 dev_warn(&priv->udev->dev,
5893 "failed to requeue urb with error %i\n", ret);
5894 skb = (struct sk_buff *)rx_urb->urb.context;
5895 dev_kfree_skb(skb);
5896 usb_free_urb(&rx_urb->urb);
5897 }
5898 }
5899 }
5900
5901 /*
5902 * The RTL8723BU/RTL8192EU vendor driver use coexistence table type
5903 * 0-7 to represent writing different combinations of register values
5904 * to REG_BT_COEX_TABLEs. It's for different kinds of coexistence use
5905 * cases which Realtek doesn't provide detail for these settings. Keep
5906 * this aligned with vendor driver for easier maintenance.
5907 */
5908 static
rtl8723bu_set_coex_with_type(struct rtl8xxxu_priv * priv,u8 type)5909 void rtl8723bu_set_coex_with_type(struct rtl8xxxu_priv *priv, u8 type)
5910 {
5911 switch (type) {
5912 case 0:
5913 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
5914 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555);
5915 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5916 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5917 break;
5918 case 1:
5919 case 3:
5920 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
5921 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a);
5922 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5923 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5924 break;
5925 case 2:
5926 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a);
5927 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a);
5928 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5929 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5930 break;
5931 case 4:
5932 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a);
5933 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaa5a5a);
5934 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5935 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5936 break;
5937 case 5:
5938 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a);
5939 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaa5a5a5a);
5940 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5941 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5942 break;
5943 case 6:
5944 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
5945 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa);
5946 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5947 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5948 break;
5949 case 7:
5950 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0xaaaaaaaa);
5951 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa);
5952 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5953 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5954 break;
5955 default:
5956 break;
5957 }
5958 }
5959
5960 static
rtl8723bu_update_bt_link_info(struct rtl8xxxu_priv * priv,u8 bt_info)5961 void rtl8723bu_update_bt_link_info(struct rtl8xxxu_priv *priv, u8 bt_info)
5962 {
5963 struct rtl8xxxu_btcoex *btcoex = &priv->bt_coex;
5964
5965 if (bt_info & BT_INFO_8723B_1ANT_B_INQ_PAGE)
5966 btcoex->c2h_bt_inquiry = true;
5967 else
5968 btcoex->c2h_bt_inquiry = false;
5969
5970 if (!(bt_info & BT_INFO_8723B_1ANT_B_CONNECTION)) {
5971 btcoex->bt_status = BT_8723B_1ANT_STATUS_NON_CONNECTED_IDLE;
5972 btcoex->has_sco = false;
5973 btcoex->has_hid = false;
5974 btcoex->has_pan = false;
5975 btcoex->has_a2dp = false;
5976 } else {
5977 if ((bt_info & 0x1f) == BT_INFO_8723B_1ANT_B_CONNECTION)
5978 btcoex->bt_status = BT_8723B_1ANT_STATUS_CONNECTED_IDLE;
5979 else if ((bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) ||
5980 (bt_info & BT_INFO_8723B_1ANT_B_SCO_BUSY))
5981 btcoex->bt_status = BT_8723B_1ANT_STATUS_SCO_BUSY;
5982 else if (bt_info & BT_INFO_8723B_1ANT_B_ACL_BUSY)
5983 btcoex->bt_status = BT_8723B_1ANT_STATUS_ACL_BUSY;
5984 else
5985 btcoex->bt_status = BT_8723B_1ANT_STATUS_MAX;
5986
5987 if (bt_info & BT_INFO_8723B_1ANT_B_FTP)
5988 btcoex->has_pan = true;
5989 else
5990 btcoex->has_pan = false;
5991
5992 if (bt_info & BT_INFO_8723B_1ANT_B_A2DP)
5993 btcoex->has_a2dp = true;
5994 else
5995 btcoex->has_a2dp = false;
5996
5997 if (bt_info & BT_INFO_8723B_1ANT_B_HID)
5998 btcoex->has_hid = true;
5999 else
6000 btcoex->has_hid = false;
6001
6002 if (bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO)
6003 btcoex->has_sco = true;
6004 else
6005 btcoex->has_sco = false;
6006 }
6007
6008 if (!btcoex->has_a2dp && !btcoex->has_sco &&
6009 !btcoex->has_pan && btcoex->has_hid)
6010 btcoex->hid_only = true;
6011 else
6012 btcoex->hid_only = false;
6013
6014 if (!btcoex->has_sco && !btcoex->has_pan &&
6015 !btcoex->has_hid && btcoex->has_a2dp)
6016 btcoex->has_a2dp = true;
6017 else
6018 btcoex->has_a2dp = false;
6019
6020 if (btcoex->bt_status == BT_8723B_1ANT_STATUS_SCO_BUSY ||
6021 btcoex->bt_status == BT_8723B_1ANT_STATUS_ACL_BUSY)
6022 btcoex->bt_busy = true;
6023 else
6024 btcoex->bt_busy = false;
6025 }
6026
6027 static
rtl8723bu_handle_bt_inquiry(struct rtl8xxxu_priv * priv)6028 void rtl8723bu_handle_bt_inquiry(struct rtl8xxxu_priv *priv)
6029 {
6030 struct ieee80211_vif *vif;
6031 struct rtl8xxxu_btcoex *btcoex;
6032 bool wifi_connected;
6033
6034 vif = priv->vif;
6035 btcoex = &priv->bt_coex;
6036 wifi_connected = (vif && vif->cfg.assoc);
6037
6038 if (!wifi_connected) {
6039 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0);
6040 rtl8723bu_set_coex_with_type(priv, 0);
6041 } else if (btcoex->has_sco || btcoex->has_hid || btcoex->has_a2dp) {
6042 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, 0x3, 0x11, 0x11);
6043 rtl8723bu_set_coex_with_type(priv, 4);
6044 } else if (btcoex->has_pan) {
6045 rtl8723bu_set_ps_tdma(priv, 0x61, 0x3f, 0x3, 0x11, 0x11);
6046 rtl8723bu_set_coex_with_type(priv, 4);
6047 } else {
6048 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0);
6049 rtl8723bu_set_coex_with_type(priv, 7);
6050 }
6051 }
6052
6053 static
rtl8723bu_handle_bt_info(struct rtl8xxxu_priv * priv)6054 void rtl8723bu_handle_bt_info(struct rtl8xxxu_priv *priv)
6055 {
6056 struct ieee80211_vif *vif;
6057 struct rtl8xxxu_btcoex *btcoex;
6058 bool wifi_connected;
6059
6060 vif = priv->vif;
6061 btcoex = &priv->bt_coex;
6062 wifi_connected = (vif && vif->cfg.assoc);
6063
6064 if (wifi_connected) {
6065 u32 val32 = 0;
6066 u32 high_prio_tx = 0, high_prio_rx = 0;
6067
6068 val32 = rtl8xxxu_read32(priv, 0x770);
6069 high_prio_tx = val32 & 0x0000ffff;
6070 high_prio_rx = (val32 & 0xffff0000) >> 16;
6071
6072 if (btcoex->bt_busy) {
6073 if (btcoex->hid_only) {
6074 rtl8723bu_set_ps_tdma(priv, 0x61, 0x20,
6075 0x3, 0x11, 0x11);
6076 rtl8723bu_set_coex_with_type(priv, 5);
6077 } else if (btcoex->a2dp_only) {
6078 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35,
6079 0x3, 0x11, 0x11);
6080 rtl8723bu_set_coex_with_type(priv, 4);
6081 } else if ((btcoex->has_a2dp && btcoex->has_pan) ||
6082 (btcoex->has_hid && btcoex->has_a2dp &&
6083 btcoex->has_pan)) {
6084 rtl8723bu_set_ps_tdma(priv, 0x51, 0x21,
6085 0x3, 0x10, 0x10);
6086 rtl8723bu_set_coex_with_type(priv, 4);
6087 } else if (btcoex->has_hid && btcoex->has_a2dp) {
6088 rtl8723bu_set_ps_tdma(priv, 0x51, 0x21,
6089 0x3, 0x10, 0x10);
6090 rtl8723bu_set_coex_with_type(priv, 3);
6091 } else {
6092 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35,
6093 0x3, 0x11, 0x11);
6094 rtl8723bu_set_coex_with_type(priv, 4);
6095 }
6096 } else {
6097 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0);
6098 if (high_prio_tx + high_prio_rx <= 60)
6099 rtl8723bu_set_coex_with_type(priv, 2);
6100 else
6101 rtl8723bu_set_coex_with_type(priv, 7);
6102 }
6103 } else {
6104 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0);
6105 rtl8723bu_set_coex_with_type(priv, 0);
6106 }
6107 }
6108
rtl8xxxu_c2hcmd_callback(struct work_struct * work)6109 static void rtl8xxxu_c2hcmd_callback(struct work_struct *work)
6110 {
6111 struct rtl8xxxu_priv *priv;
6112 struct rtl8723bu_c2h *c2h;
6113 struct sk_buff *skb = NULL;
6114 u8 bt_info = 0;
6115 struct rtl8xxxu_btcoex *btcoex;
6116 struct rtl8xxxu_ra_report *rarpt;
6117 u8 bw;
6118
6119 priv = container_of(work, struct rtl8xxxu_priv, c2hcmd_work);
6120 btcoex = &priv->bt_coex;
6121 rarpt = &priv->ra_report;
6122
6123 while (!skb_queue_empty(&priv->c2hcmd_queue)) {
6124 skb = skb_dequeue(&priv->c2hcmd_queue);
6125
6126 c2h = (struct rtl8723bu_c2h *)skb->data;
6127
6128 switch (c2h->id) {
6129 case C2H_8723B_BT_INFO:
6130 bt_info = c2h->bt_info.bt_info;
6131
6132 rtl8723bu_update_bt_link_info(priv, bt_info);
6133 if (btcoex->c2h_bt_inquiry) {
6134 rtl8723bu_handle_bt_inquiry(priv);
6135 break;
6136 }
6137 rtl8723bu_handle_bt_info(priv);
6138 break;
6139 case C2H_8723B_RA_REPORT:
6140 bw = rarpt->txrate.bw;
6141
6142 if (skb->len >= offsetofend(typeof(*c2h), ra_report.bw)) {
6143 if (c2h->ra_report.bw == RTL8XXXU_CHANNEL_WIDTH_40)
6144 bw = RATE_INFO_BW_40;
6145 else
6146 bw = RATE_INFO_BW_20;
6147 }
6148
6149 rtl8xxxu_update_ra_report(rarpt, c2h->ra_report.rate,
6150 c2h->ra_report.sgi, bw);
6151 break;
6152 default:
6153 break;
6154 }
6155
6156 dev_kfree_skb(skb);
6157 }
6158 }
6159
rtl8723bu_handle_c2h(struct rtl8xxxu_priv * priv,struct sk_buff * skb)6160 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv,
6161 struct sk_buff *skb)
6162 {
6163 struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data;
6164 struct device *dev = &priv->udev->dev;
6165 int len;
6166
6167 len = skb->len - 2;
6168
6169 dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n",
6170 c2h->id, c2h->seq, len, c2h->bt_info.response_source);
6171
6172 switch(c2h->id) {
6173 case C2H_8723B_BT_INFO:
6174 if (c2h->bt_info.response_source >
6175 BT_INFO_SRC_8723B_BT_ACTIVE_SEND)
6176 dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n");
6177 else
6178 dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n");
6179
6180 if (c2h->bt_info.bt_has_reset)
6181 dev_dbg(dev, "BT has been reset\n");
6182 if (c2h->bt_info.tx_rx_mask)
6183 dev_dbg(dev, "BT TRx mask\n");
6184
6185 break;
6186 case C2H_8723B_BT_MP_INFO:
6187 dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n",
6188 c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status);
6189 break;
6190 case C2H_8723B_RA_REPORT:
6191 dev_dbg(dev,
6192 "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n",
6193 c2h->ra_report.rate, c2h->ra_report.sgi,
6194 c2h->ra_report.macid, c2h->ra_report.noisy_state);
6195 break;
6196 default:
6197 dev_info(dev, "Unhandled C2H event %02x seq %02x\n",
6198 c2h->id, c2h->seq);
6199 print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE,
6200 16, 1, c2h->raw.payload, len, false);
6201 break;
6202 }
6203
6204 skb_queue_tail(&priv->c2hcmd_queue, skb);
6205
6206 schedule_work(&priv->c2hcmd_work);
6207 }
6208
rtl8188e_c2hcmd_callback(struct work_struct * work)6209 static void rtl8188e_c2hcmd_callback(struct work_struct *work)
6210 {
6211 struct rtl8xxxu_priv *priv = container_of(work, struct rtl8xxxu_priv, c2hcmd_work);
6212 struct device *dev = &priv->udev->dev;
6213 struct sk_buff *skb = NULL;
6214 struct rtl8xxxu_rxdesc16 *rx_desc;
6215
6216 while (!skb_queue_empty(&priv->c2hcmd_queue)) {
6217 skb = skb_dequeue(&priv->c2hcmd_queue);
6218
6219 rx_desc = (struct rtl8xxxu_rxdesc16 *)(skb->data - sizeof(struct rtl8xxxu_rxdesc16));
6220
6221 switch (rx_desc->rpt_sel) {
6222 case 1:
6223 dev_dbg(dev, "C2H TX report type 1\n");
6224
6225 break;
6226 case 2:
6227 dev_dbg(dev, "C2H TX report type 2\n");
6228
6229 rtl8188e_handle_ra_tx_report2(priv, skb);
6230
6231 break;
6232 case 3:
6233 dev_dbg(dev, "C2H USB interrupt report\n");
6234
6235 break;
6236 default:
6237 dev_warn(dev, "%s: rpt_sel should not be %d\n",
6238 __func__, rx_desc->rpt_sel);
6239
6240 break;
6241 }
6242
6243 dev_kfree_skb(skb);
6244 }
6245 }
6246
rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv * priv,struct sk_buff * skb)6247 int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb)
6248 {
6249 struct ieee80211_hw *hw = priv->hw;
6250 struct ieee80211_rx_status *rx_status;
6251 struct rtl8xxxu_rxdesc16 *rx_desc;
6252 struct rtl8723au_phy_stats *phy_stats;
6253 struct sk_buff *next_skb = NULL;
6254 __le32 *_rx_desc_le;
6255 u32 *_rx_desc;
6256 int drvinfo_sz, desc_shift;
6257 int i, pkt_cnt, pkt_len, urb_len, pkt_offset;
6258
6259 urb_len = skb->len;
6260 pkt_cnt = 0;
6261
6262 if (urb_len < sizeof(struct rtl8xxxu_rxdesc16)) {
6263 kfree_skb(skb);
6264 return RX_TYPE_ERROR;
6265 }
6266
6267 do {
6268 rx_desc = (struct rtl8xxxu_rxdesc16 *)skb->data;
6269 _rx_desc_le = (__le32 *)skb->data;
6270 _rx_desc = (u32 *)skb->data;
6271
6272 for (i = 0;
6273 i < (sizeof(struct rtl8xxxu_rxdesc16) / sizeof(u32)); i++)
6274 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
6275
6276 /*
6277 * Only read pkt_cnt from the header if we're parsing the
6278 * first packet
6279 */
6280 if (!pkt_cnt)
6281 pkt_cnt = rx_desc->pkt_cnt;
6282 pkt_len = rx_desc->pktlen;
6283
6284 drvinfo_sz = rx_desc->drvinfo_sz * 8;
6285 desc_shift = rx_desc->shift;
6286 pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift +
6287 sizeof(struct rtl8xxxu_rxdesc16), 128);
6288
6289 /*
6290 * Only clone the skb if there's enough data at the end to
6291 * at least cover the rx descriptor
6292 */
6293 if (pkt_cnt > 1 &&
6294 urb_len >= (pkt_offset + sizeof(struct rtl8xxxu_rxdesc16)))
6295 next_skb = skb_clone(skb, GFP_ATOMIC);
6296
6297 rx_status = IEEE80211_SKB_RXCB(skb);
6298 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
6299
6300 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc16));
6301
6302 if (rx_desc->rpt_sel) {
6303 skb_queue_tail(&priv->c2hcmd_queue, skb);
6304 schedule_work(&priv->c2hcmd_work);
6305 } else {
6306 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
6307
6308 skb_pull(skb, drvinfo_sz + desc_shift);
6309
6310 skb_trim(skb, pkt_len);
6311
6312 if (rx_desc->phy_stats)
6313 priv->fops->parse_phystats(
6314 priv, rx_status, phy_stats,
6315 rx_desc->rxmcs,
6316 (struct ieee80211_hdr *)skb->data,
6317 rx_desc->crc32 || rx_desc->icverr);
6318
6319 rx_status->mactime = rx_desc->tsfl;
6320 rx_status->flag |= RX_FLAG_MACTIME_START;
6321
6322 if (!rx_desc->swdec &&
6323 rx_desc->security != RX_DESC_ENC_NONE)
6324 rx_status->flag |= RX_FLAG_DECRYPTED;
6325 if (rx_desc->crc32)
6326 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
6327 if (rx_desc->bw)
6328 rx_status->bw = RATE_INFO_BW_40;
6329
6330 if (rx_desc->rxht) {
6331 rx_status->encoding = RX_ENC_HT;
6332 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
6333 } else {
6334 rx_status->rate_idx = rx_desc->rxmcs;
6335 }
6336
6337 rx_status->freq = hw->conf.chandef.chan->center_freq;
6338 rx_status->band = hw->conf.chandef.chan->band;
6339
6340 ieee80211_rx_irqsafe(hw, skb);
6341 }
6342
6343 skb = next_skb;
6344 if (skb)
6345 skb_pull(next_skb, pkt_offset);
6346
6347 pkt_cnt--;
6348 urb_len -= pkt_offset;
6349 next_skb = NULL;
6350 } while (skb && pkt_cnt > 0 &&
6351 urb_len >= sizeof(struct rtl8xxxu_rxdesc16));
6352
6353 return RX_TYPE_DATA_PKT;
6354 }
6355
rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv * priv,struct sk_buff * skb)6356 int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb)
6357 {
6358 struct ieee80211_hw *hw = priv->hw;
6359 struct ieee80211_rx_status *rx_status;
6360 struct rtl8xxxu_rxdesc24 *rx_desc;
6361 struct rtl8723au_phy_stats *phy_stats;
6362 struct sk_buff *next_skb = NULL;
6363 __le32 *_rx_desc_le;
6364 u32 *_rx_desc;
6365 int drvinfo_sz, desc_shift;
6366 int i, pkt_len, urb_len, pkt_offset;
6367
6368 urb_len = skb->len;
6369
6370 if (urb_len < sizeof(struct rtl8xxxu_rxdesc24)) {
6371 kfree_skb(skb);
6372 return RX_TYPE_ERROR;
6373 }
6374
6375 do {
6376 rx_desc = (struct rtl8xxxu_rxdesc24 *)skb->data;
6377 _rx_desc_le = (__le32 *)skb->data;
6378 _rx_desc = (u32 *)skb->data;
6379
6380 for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++)
6381 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
6382
6383 pkt_len = rx_desc->pktlen;
6384
6385 drvinfo_sz = rx_desc->drvinfo_sz * 8;
6386 desc_shift = rx_desc->shift;
6387 pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift +
6388 sizeof(struct rtl8xxxu_rxdesc24), 8);
6389
6390 /*
6391 * Only clone the skb if there's enough data at the end to
6392 * at least cover the rx descriptor
6393 */
6394 if (urb_len >= (pkt_offset + sizeof(struct rtl8xxxu_rxdesc24)))
6395 next_skb = skb_clone(skb, GFP_ATOMIC);
6396
6397 rx_status = IEEE80211_SKB_RXCB(skb);
6398 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
6399
6400 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24));
6401
6402 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
6403
6404 skb_pull(skb, drvinfo_sz + desc_shift);
6405
6406 skb_trim(skb, pkt_len);
6407
6408 if (rx_desc->rpt_sel) {
6409 struct device *dev = &priv->udev->dev;
6410 dev_dbg(dev, "%s: C2H packet\n", __func__);
6411 rtl8723bu_handle_c2h(priv, skb);
6412 } else {
6413 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
6414
6415 if (rx_desc->phy_stats)
6416 priv->fops->parse_phystats(priv, rx_status, phy_stats,
6417 rx_desc->rxmcs, hdr,
6418 rx_desc->crc32 || rx_desc->icverr);
6419
6420 rx_status->mactime = rx_desc->tsfl;
6421 rx_status->flag |= RX_FLAG_MACTIME_START;
6422
6423 if (!rx_desc->swdec &&
6424 rx_desc->security != RX_DESC_ENC_NONE)
6425 rx_status->flag |= RX_FLAG_DECRYPTED;
6426 if (rx_desc->crc32)
6427 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
6428 if (rx_desc->bw)
6429 rx_status->bw = RATE_INFO_BW_40;
6430
6431 if (rx_desc->rxmcs >= DESC_RATE_MCS0) {
6432 rx_status->encoding = RX_ENC_HT;
6433 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
6434 } else {
6435 rx_status->rate_idx = rx_desc->rxmcs;
6436 }
6437
6438 rx_status->freq = hw->conf.chandef.chan->center_freq;
6439 rx_status->band = hw->conf.chandef.chan->band;
6440
6441 ieee80211_rx_irqsafe(hw, skb);
6442 }
6443
6444 skb = next_skb;
6445 if (skb)
6446 skb_pull(next_skb, pkt_offset);
6447
6448 urb_len -= pkt_offset;
6449 next_skb = NULL;
6450 } while (skb && urb_len >= sizeof(struct rtl8xxxu_rxdesc24));
6451
6452 return RX_TYPE_DATA_PKT;
6453 }
6454
rtl8xxxu_rx_complete(struct urb * urb)6455 static void rtl8xxxu_rx_complete(struct urb *urb)
6456 {
6457 struct rtl8xxxu_rx_urb *rx_urb =
6458 container_of(urb, struct rtl8xxxu_rx_urb, urb);
6459 struct ieee80211_hw *hw = rx_urb->hw;
6460 struct rtl8xxxu_priv *priv = hw->priv;
6461 struct sk_buff *skb = (struct sk_buff *)urb->context;
6462 struct device *dev = &priv->udev->dev;
6463
6464 skb_put(skb, urb->actual_length);
6465
6466 if (urb->status == 0) {
6467 priv->fops->parse_rx_desc(priv, skb);
6468
6469 skb = NULL;
6470 rx_urb->urb.context = NULL;
6471 rtl8xxxu_queue_rx_urb(priv, rx_urb);
6472 } else {
6473 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
6474 goto cleanup;
6475 }
6476 return;
6477
6478 cleanup:
6479 usb_free_urb(urb);
6480 dev_kfree_skb(skb);
6481 }
6482
rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv * priv,struct rtl8xxxu_rx_urb * rx_urb)6483 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
6484 struct rtl8xxxu_rx_urb *rx_urb)
6485 {
6486 struct rtl8xxxu_fileops *fops = priv->fops;
6487 struct sk_buff *skb;
6488 int skb_size;
6489 int ret, rx_desc_sz;
6490
6491 rx_desc_sz = fops->rx_desc_size;
6492
6493 if (priv->rx_buf_aggregation && fops->rx_agg_buf_size) {
6494 skb_size = fops->rx_agg_buf_size;
6495 skb_size += (rx_desc_sz + sizeof(struct rtl8723au_phy_stats));
6496 } else {
6497 skb_size = IEEE80211_MAX_FRAME_LEN;
6498 }
6499
6500 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
6501 if (!skb)
6502 return -ENOMEM;
6503
6504 memset(skb->data, 0, rx_desc_sz);
6505 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
6506 skb_size, rtl8xxxu_rx_complete, skb);
6507 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
6508 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
6509 if (ret)
6510 usb_unanchor_urb(&rx_urb->urb);
6511 return ret;
6512 }
6513
rtl8xxxu_int_complete(struct urb * urb)6514 static void rtl8xxxu_int_complete(struct urb *urb)
6515 {
6516 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
6517 struct device *dev = &priv->udev->dev;
6518 int ret;
6519
6520 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_INTERRUPT)
6521 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
6522 if (urb->status == 0) {
6523 usb_anchor_urb(urb, &priv->int_anchor);
6524 ret = usb_submit_urb(urb, GFP_ATOMIC);
6525 if (ret)
6526 usb_unanchor_urb(urb);
6527 } else {
6528 dev_dbg(dev, "%s: Error %i\n", __func__, urb->status);
6529 }
6530 }
6531
6532
rtl8xxxu_submit_int_urb(struct ieee80211_hw * hw)6533 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
6534 {
6535 struct rtl8xxxu_priv *priv = hw->priv;
6536 struct urb *urb;
6537 u32 val32;
6538 int ret;
6539
6540 urb = usb_alloc_urb(0, GFP_KERNEL);
6541 if (!urb)
6542 return -ENOMEM;
6543
6544 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
6545 priv->int_buf, USB_INTR_CONTENT_LENGTH,
6546 rtl8xxxu_int_complete, priv, 1);
6547 usb_anchor_urb(urb, &priv->int_anchor);
6548 ret = usb_submit_urb(urb, GFP_KERNEL);
6549 if (ret) {
6550 usb_unanchor_urb(urb);
6551 goto error;
6552 }
6553
6554 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
6555 val32 |= USB_HIMR_CPWM;
6556 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
6557
6558 error:
6559 usb_free_urb(urb);
6560 return ret;
6561 }
6562
rtl8xxxu_add_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)6563 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
6564 struct ieee80211_vif *vif)
6565 {
6566 struct rtl8xxxu_priv *priv = hw->priv;
6567 int ret;
6568 u8 val8;
6569
6570 if (!priv->vif)
6571 priv->vif = vif;
6572 else
6573 return -EOPNOTSUPP;
6574
6575 switch (vif->type) {
6576 case NL80211_IFTYPE_STATION:
6577 rtl8xxxu_stop_tx_beacon(priv);
6578
6579 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6580 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
6581 BEACON_DISABLE_TSF_UPDATE;
6582 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6583 ret = 0;
6584 break;
6585 case NL80211_IFTYPE_AP:
6586 rtl8xxxu_write8(priv, REG_BEACON_CTRL,
6587 BEACON_DISABLE_TSF_UPDATE | BEACON_CTRL_MBSSID);
6588 rtl8xxxu_write8(priv, REG_ATIMWND, 0x0c); /* 12ms */
6589 rtl8xxxu_write16(priv, REG_TSFTR_SYN_OFFSET, 0x7fff); /* ~32ms */
6590 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, DUAL_TSF_RESET_TSF0);
6591
6592 /* enable BCN0 function */
6593 rtl8xxxu_write8(priv, REG_BEACON_CTRL,
6594 BEACON_DISABLE_TSF_UPDATE |
6595 BEACON_FUNCTION_ENABLE | BEACON_CTRL_MBSSID |
6596 BEACON_CTRL_TX_BEACON_RPT);
6597
6598 /* select BCN on port 0 */
6599 val8 = rtl8xxxu_read8(priv, REG_CCK_CHECK);
6600 val8 &= ~BIT_BCN_PORT_SEL;
6601 rtl8xxxu_write8(priv, REG_CCK_CHECK, val8);
6602
6603 ret = 0;
6604 break;
6605 default:
6606 ret = -EOPNOTSUPP;
6607 }
6608
6609 rtl8xxxu_set_linktype(priv, vif->type);
6610 ether_addr_copy(priv->mac_addr, vif->addr);
6611 rtl8xxxu_set_mac(priv);
6612
6613 return ret;
6614 }
6615
rtl8xxxu_remove_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)6616 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
6617 struct ieee80211_vif *vif)
6618 {
6619 struct rtl8xxxu_priv *priv = hw->priv;
6620
6621 dev_dbg(&priv->udev->dev, "%s\n", __func__);
6622
6623 if (priv->vif)
6624 priv->vif = NULL;
6625 }
6626
rtl8xxxu_config(struct ieee80211_hw * hw,u32 changed)6627 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
6628 {
6629 struct rtl8xxxu_priv *priv = hw->priv;
6630 struct device *dev = &priv->udev->dev;
6631 int ret = 0, channel;
6632 bool ht40;
6633
6634 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
6635 dev_info(dev,
6636 "%s: channel: %i (changed %08x chandef.width %02x)\n",
6637 __func__, hw->conf.chandef.chan->hw_value,
6638 changed, hw->conf.chandef.width);
6639
6640 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
6641 switch (hw->conf.chandef.width) {
6642 case NL80211_CHAN_WIDTH_20_NOHT:
6643 case NL80211_CHAN_WIDTH_20:
6644 ht40 = false;
6645 break;
6646 case NL80211_CHAN_WIDTH_40:
6647 ht40 = true;
6648 break;
6649 default:
6650 ret = -ENOTSUPP;
6651 goto exit;
6652 }
6653
6654 channel = hw->conf.chandef.chan->hw_value;
6655
6656 priv->fops->set_tx_power(priv, channel, ht40);
6657
6658 priv->fops->config_channel(hw);
6659 }
6660
6661 exit:
6662 return ret;
6663 }
6664
rtl8xxxu_conf_tx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,unsigned int link_id,u16 queue,const struct ieee80211_tx_queue_params * param)6665 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
6666 struct ieee80211_vif *vif,
6667 unsigned int link_id, u16 queue,
6668 const struct ieee80211_tx_queue_params *param)
6669 {
6670 struct rtl8xxxu_priv *priv = hw->priv;
6671 struct device *dev = &priv->udev->dev;
6672 u32 val32;
6673 u8 aifs, acm_ctrl, acm_bit;
6674
6675 aifs = param->aifs;
6676
6677 val32 = aifs |
6678 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
6679 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
6680 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
6681
6682 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
6683 dev_dbg(dev,
6684 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
6685 __func__, queue, val32, param->acm, acm_ctrl);
6686
6687 switch (queue) {
6688 case IEEE80211_AC_VO:
6689 acm_bit = ACM_HW_CTRL_VO;
6690 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
6691 break;
6692 case IEEE80211_AC_VI:
6693 acm_bit = ACM_HW_CTRL_VI;
6694 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
6695 break;
6696 case IEEE80211_AC_BE:
6697 acm_bit = ACM_HW_CTRL_BE;
6698 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
6699 break;
6700 case IEEE80211_AC_BK:
6701 acm_bit = ACM_HW_CTRL_BK;
6702 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
6703 break;
6704 default:
6705 acm_bit = 0;
6706 break;
6707 }
6708
6709 if (param->acm)
6710 acm_ctrl |= acm_bit;
6711 else
6712 acm_ctrl &= ~acm_bit;
6713 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
6714
6715 return 0;
6716 }
6717
rtl8xxxu_configure_filter(struct ieee80211_hw * hw,unsigned int changed_flags,unsigned int * total_flags,u64 multicast)6718 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
6719 unsigned int changed_flags,
6720 unsigned int *total_flags, u64 multicast)
6721 {
6722 struct rtl8xxxu_priv *priv = hw->priv;
6723 u32 rcr = priv->regrcr;
6724
6725 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
6726 __func__, changed_flags, *total_flags);
6727
6728 /*
6729 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
6730 */
6731
6732 if (*total_flags & FIF_FCSFAIL)
6733 rcr |= RCR_ACCEPT_CRC32;
6734 else
6735 rcr &= ~RCR_ACCEPT_CRC32;
6736
6737 /*
6738 * FIF_PLCPFAIL not supported?
6739 */
6740
6741 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
6742 rcr &= ~(RCR_CHECK_BSSID_BEACON | RCR_CHECK_BSSID_MATCH);
6743 else
6744 rcr |= RCR_CHECK_BSSID_BEACON | RCR_CHECK_BSSID_MATCH;
6745
6746 if (priv->vif && priv->vif->type == NL80211_IFTYPE_AP)
6747 rcr &= ~RCR_CHECK_BSSID_MATCH;
6748
6749 if (*total_flags & FIF_CONTROL)
6750 rcr |= RCR_ACCEPT_CTRL_FRAME;
6751 else
6752 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
6753
6754 if (*total_flags & FIF_OTHER_BSS)
6755 rcr |= RCR_ACCEPT_AP;
6756 else
6757 rcr &= ~RCR_ACCEPT_AP;
6758
6759 if (*total_flags & FIF_PSPOLL)
6760 rcr |= RCR_ACCEPT_PM;
6761 else
6762 rcr &= ~RCR_ACCEPT_PM;
6763
6764 /*
6765 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
6766 */
6767
6768 rtl8xxxu_write32(priv, REG_RCR, rcr);
6769 priv->regrcr = rcr;
6770
6771 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
6772 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
6773 FIF_PROBE_REQ);
6774 }
6775
rtl8xxxu_set_rts_threshold(struct ieee80211_hw * hw,u32 rts)6776 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
6777 {
6778 if (rts > 2347 && rts != (u32)-1)
6779 return -EINVAL;
6780
6781 return 0;
6782 }
6783
rtl8xxxu_set_key(struct ieee80211_hw * hw,enum set_key_cmd cmd,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ieee80211_key_conf * key)6784 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
6785 struct ieee80211_vif *vif,
6786 struct ieee80211_sta *sta,
6787 struct ieee80211_key_conf *key)
6788 {
6789 struct rtl8xxxu_priv *priv = hw->priv;
6790 struct device *dev = &priv->udev->dev;
6791 u8 mac_addr[ETH_ALEN];
6792 u8 val8;
6793 u16 val16;
6794 u32 val32;
6795 int retval = -EOPNOTSUPP;
6796
6797 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
6798 __func__, cmd, key->cipher, key->keyidx);
6799
6800 if (vif->type != NL80211_IFTYPE_STATION)
6801 return -EOPNOTSUPP;
6802
6803 if (key->keyidx > 3)
6804 return -EOPNOTSUPP;
6805
6806 switch (key->cipher) {
6807 case WLAN_CIPHER_SUITE_WEP40:
6808 case WLAN_CIPHER_SUITE_WEP104:
6809
6810 break;
6811 case WLAN_CIPHER_SUITE_CCMP:
6812 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
6813 break;
6814 case WLAN_CIPHER_SUITE_TKIP:
6815 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
6816 break;
6817 default:
6818 return -EOPNOTSUPP;
6819 }
6820
6821 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
6822 dev_dbg(dev, "%s: pairwise key\n", __func__);
6823 ether_addr_copy(mac_addr, sta->addr);
6824 } else {
6825 dev_dbg(dev, "%s: group key\n", __func__);
6826 eth_broadcast_addr(mac_addr);
6827 }
6828
6829 val16 = rtl8xxxu_read16(priv, REG_CR);
6830 val16 |= CR_SECURITY_ENABLE;
6831 rtl8xxxu_write16(priv, REG_CR, val16);
6832
6833 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
6834 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
6835 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
6836 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
6837
6838 switch (cmd) {
6839 case SET_KEY:
6840 key->hw_key_idx = key->keyidx;
6841 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
6842 rtl8xxxu_cam_write(priv, key, mac_addr);
6843 retval = 0;
6844 break;
6845 case DISABLE_KEY:
6846 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
6847 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
6848 key->keyidx << CAM_CMD_KEY_SHIFT;
6849 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
6850 retval = 0;
6851 break;
6852 default:
6853 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
6854 }
6855
6856 return retval;
6857 }
6858
6859 static int
rtl8xxxu_ampdu_action(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_ampdu_params * params)6860 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6861 struct ieee80211_ampdu_params *params)
6862 {
6863 struct rtl8xxxu_priv *priv = hw->priv;
6864 struct device *dev = &priv->udev->dev;
6865 u8 ampdu_factor, ampdu_density;
6866 struct ieee80211_sta *sta = params->sta;
6867 u16 tid = params->tid;
6868 enum ieee80211_ampdu_mlme_action action = params->action;
6869
6870 switch (action) {
6871 case IEEE80211_AMPDU_TX_START:
6872 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
6873 ampdu_factor = sta->deflink.ht_cap.ampdu_factor;
6874 ampdu_density = sta->deflink.ht_cap.ampdu_density;
6875 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
6876 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
6877 dev_dbg(dev,
6878 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
6879 ampdu_factor, ampdu_density);
6880 return IEEE80211_AMPDU_TX_START_IMMEDIATE;
6881 case IEEE80211_AMPDU_TX_STOP_CONT:
6882 case IEEE80211_AMPDU_TX_STOP_FLUSH:
6883 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
6884 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP\n", __func__);
6885 rtl8xxxu_set_ampdu_factor(priv, 0);
6886 rtl8xxxu_set_ampdu_min_space(priv, 0);
6887 clear_bit(tid, priv->tx_aggr_started);
6888 clear_bit(tid, priv->tid_tx_operational);
6889 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
6890 break;
6891 case IEEE80211_AMPDU_TX_OPERATIONAL:
6892 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_OPERATIONAL\n", __func__);
6893 set_bit(tid, priv->tid_tx_operational);
6894 break;
6895 case IEEE80211_AMPDU_RX_START:
6896 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
6897 break;
6898 case IEEE80211_AMPDU_RX_STOP:
6899 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
6900 break;
6901 default:
6902 break;
6903 }
6904 return 0;
6905 }
6906
6907 static void
rtl8xxxu_sta_statistics(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct station_info * sinfo)6908 rtl8xxxu_sta_statistics(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6909 struct ieee80211_sta *sta, struct station_info *sinfo)
6910 {
6911 struct rtl8xxxu_priv *priv = hw->priv;
6912
6913 sinfo->txrate = priv->ra_report.txrate;
6914 sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
6915 }
6916
rtl8xxxu_signal_to_snr(int signal)6917 static u8 rtl8xxxu_signal_to_snr(int signal)
6918 {
6919 if (signal < RTL8XXXU_NOISE_FLOOR_MIN)
6920 signal = RTL8XXXU_NOISE_FLOOR_MIN;
6921 else if (signal > 0)
6922 signal = 0;
6923 return (u8)(signal - RTL8XXXU_NOISE_FLOOR_MIN);
6924 }
6925
rtl8xxxu_refresh_rate_mask(struct rtl8xxxu_priv * priv,int signal,struct ieee80211_sta * sta,bool force)6926 static void rtl8xxxu_refresh_rate_mask(struct rtl8xxxu_priv *priv,
6927 int signal, struct ieee80211_sta *sta,
6928 bool force)
6929 {
6930 struct ieee80211_hw *hw = priv->hw;
6931 u16 wireless_mode;
6932 u8 rssi_level, ratr_idx;
6933 u8 txbw_40mhz;
6934 u8 snr, snr_thresh_high, snr_thresh_low;
6935 u8 go_up_gap = 5;
6936 u8 macid = rtl8xxxu_get_macid(priv, sta);
6937
6938 rssi_level = priv->rssi_level;
6939 snr = rtl8xxxu_signal_to_snr(signal);
6940 snr_thresh_high = RTL8XXXU_SNR_THRESH_HIGH;
6941 snr_thresh_low = RTL8XXXU_SNR_THRESH_LOW;
6942 txbw_40mhz = (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) ? 1 : 0;
6943
6944 switch (rssi_level) {
6945 case RTL8XXXU_RATR_STA_MID:
6946 snr_thresh_high += go_up_gap;
6947 break;
6948 case RTL8XXXU_RATR_STA_LOW:
6949 snr_thresh_high += go_up_gap;
6950 snr_thresh_low += go_up_gap;
6951 break;
6952 default:
6953 break;
6954 }
6955
6956 if (snr > snr_thresh_high)
6957 rssi_level = RTL8XXXU_RATR_STA_HIGH;
6958 else if (snr > snr_thresh_low)
6959 rssi_level = RTL8XXXU_RATR_STA_MID;
6960 else
6961 rssi_level = RTL8XXXU_RATR_STA_LOW;
6962
6963 if (rssi_level != priv->rssi_level || force) {
6964 int sgi = 0;
6965 u32 rate_bitmap = 0;
6966
6967 rcu_read_lock();
6968 rate_bitmap = (sta->deflink.supp_rates[0] & 0xfff) |
6969 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12) |
6970 (sta->deflink.ht_cap.mcs.rx_mask[1] << 20);
6971 if (sta->deflink.ht_cap.cap &
6972 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
6973 sgi = 1;
6974 rcu_read_unlock();
6975
6976 wireless_mode = rtl8xxxu_wireless_mode(hw, sta);
6977 switch (wireless_mode) {
6978 case WIRELESS_MODE_B:
6979 ratr_idx = RATEID_IDX_B;
6980 if (rate_bitmap & 0x0000000c)
6981 rate_bitmap &= 0x0000000d;
6982 else
6983 rate_bitmap &= 0x0000000f;
6984 break;
6985 case WIRELESS_MODE_A:
6986 case WIRELESS_MODE_G:
6987 ratr_idx = RATEID_IDX_G;
6988 if (rssi_level == RTL8XXXU_RATR_STA_HIGH)
6989 rate_bitmap &= 0x00000f00;
6990 else
6991 rate_bitmap &= 0x00000ff0;
6992 break;
6993 case (WIRELESS_MODE_B | WIRELESS_MODE_G):
6994 ratr_idx = RATEID_IDX_BG;
6995 if (rssi_level == RTL8XXXU_RATR_STA_HIGH)
6996 rate_bitmap &= 0x00000f00;
6997 else if (rssi_level == RTL8XXXU_RATR_STA_MID)
6998 rate_bitmap &= 0x00000ff0;
6999 else
7000 rate_bitmap &= 0x00000ff5;
7001 break;
7002 case WIRELESS_MODE_N_24G:
7003 case WIRELESS_MODE_N_5G:
7004 case (WIRELESS_MODE_G | WIRELESS_MODE_N_24G):
7005 case (WIRELESS_MODE_A | WIRELESS_MODE_N_5G):
7006 if (priv->tx_paths == 2 && priv->rx_paths == 2)
7007 ratr_idx = RATEID_IDX_GN_N2SS;
7008 else
7009 ratr_idx = RATEID_IDX_GN_N1SS;
7010 break;
7011 case (WIRELESS_MODE_B | WIRELESS_MODE_G | WIRELESS_MODE_N_24G):
7012 case (WIRELESS_MODE_B | WIRELESS_MODE_N_24G):
7013 if (txbw_40mhz) {
7014 if (priv->tx_paths == 2 && priv->rx_paths == 2)
7015 ratr_idx = RATEID_IDX_BGN_40M_2SS;
7016 else
7017 ratr_idx = RATEID_IDX_BGN_40M_1SS;
7018 } else {
7019 if (priv->tx_paths == 2 && priv->rx_paths == 2)
7020 ratr_idx = RATEID_IDX_BGN_20M_2SS_BN;
7021 else
7022 ratr_idx = RATEID_IDX_BGN_20M_1SS_BN;
7023 }
7024
7025 if (priv->tx_paths == 2 && priv->rx_paths == 2) {
7026 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) {
7027 rate_bitmap &= 0x0f8f0000;
7028 } else if (rssi_level == RTL8XXXU_RATR_STA_MID) {
7029 rate_bitmap &= 0x0f8ff000;
7030 } else {
7031 if (txbw_40mhz)
7032 rate_bitmap &= 0x0f8ff015;
7033 else
7034 rate_bitmap &= 0x0f8ff005;
7035 }
7036 } else {
7037 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) {
7038 rate_bitmap &= 0x000f0000;
7039 } else if (rssi_level == RTL8XXXU_RATR_STA_MID) {
7040 rate_bitmap &= 0x000ff000;
7041 } else {
7042 if (txbw_40mhz)
7043 rate_bitmap &= 0x000ff015;
7044 else
7045 rate_bitmap &= 0x000ff005;
7046 }
7047 }
7048 break;
7049 default:
7050 ratr_idx = RATEID_IDX_BGN_40M_2SS;
7051 rate_bitmap &= 0x0fffffff;
7052 break;
7053 }
7054
7055 priv->rssi_level = rssi_level;
7056 priv->fops->update_rate_mask(priv, rate_bitmap, ratr_idx, sgi, txbw_40mhz, macid);
7057 }
7058 }
7059
rtl8xxxu_set_atc_status(struct rtl8xxxu_priv * priv,bool atc_status)7060 static void rtl8xxxu_set_atc_status(struct rtl8xxxu_priv *priv, bool atc_status)
7061 {
7062 struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking;
7063 u32 val32;
7064
7065 if (atc_status == cfo->atc_status)
7066 return;
7067
7068 cfo->atc_status = atc_status;
7069
7070 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING);
7071 if (atc_status)
7072 val32 |= CFO_TRACKING_ATC_STATUS;
7073 else
7074 val32 &= ~CFO_TRACKING_ATC_STATUS;
7075 rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32);
7076 }
7077
7078 /* Central frequency offset correction */
rtl8xxxu_track_cfo(struct rtl8xxxu_priv * priv)7079 static void rtl8xxxu_track_cfo(struct rtl8xxxu_priv *priv)
7080 {
7081 struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking;
7082 int cfo_khz_a, cfo_khz_b, cfo_average;
7083 int crystal_cap;
7084
7085 if (!priv->vif || !priv->vif->cfg.assoc) {
7086 /* Reset */
7087 cfo->adjust = true;
7088
7089 if (cfo->crystal_cap > priv->default_crystal_cap)
7090 priv->fops->set_crystal_cap(priv, cfo->crystal_cap - 1);
7091 else if (cfo->crystal_cap < priv->default_crystal_cap)
7092 priv->fops->set_crystal_cap(priv, cfo->crystal_cap + 1);
7093
7094 rtl8xxxu_set_atc_status(priv, true);
7095
7096 return;
7097 }
7098
7099 if (cfo->packet_count == cfo->packet_count_pre)
7100 /* No new information. */
7101 return;
7102
7103 cfo->packet_count_pre = cfo->packet_count;
7104
7105 /* CFO_tail[1:0] is S(8,7), (num_subcarrier>>7) x 312.5K = CFO value(K Hz) */
7106 cfo_khz_a = (int)((cfo->cfo_tail[0] * 3125) / 10) >> 7;
7107 cfo_khz_b = (int)((cfo->cfo_tail[1] * 3125) / 10) >> 7;
7108
7109 if (priv->tx_paths == 1)
7110 cfo_average = cfo_khz_a;
7111 else
7112 cfo_average = (cfo_khz_a + cfo_khz_b) / 2;
7113
7114 dev_dbg(&priv->udev->dev, "cfo_average: %d\n", cfo_average);
7115
7116 if (cfo->adjust) {
7117 if (abs(cfo_average) < CFO_TH_XTAL_LOW)
7118 cfo->adjust = false;
7119 } else {
7120 if (abs(cfo_average) > CFO_TH_XTAL_HIGH)
7121 cfo->adjust = true;
7122 }
7123
7124 /*
7125 * TODO: We should return here only if bluetooth is enabled.
7126 * See the vendor drivers for how to determine that.
7127 */
7128 if (priv->has_bluetooth)
7129 return;
7130
7131 if (!cfo->adjust)
7132 return;
7133
7134 crystal_cap = cfo->crystal_cap;
7135
7136 if (cfo_average > CFO_TH_XTAL_LOW)
7137 crystal_cap++;
7138 else if (cfo_average < -CFO_TH_XTAL_LOW)
7139 crystal_cap--;
7140
7141 crystal_cap = clamp(crystal_cap, 0, 0x3f);
7142
7143 priv->fops->set_crystal_cap(priv, crystal_cap);
7144
7145 rtl8xxxu_set_atc_status(priv, abs(cfo_average) >= CFO_TH_ATC);
7146 }
7147
rtl8xxxu_watchdog_callback(struct work_struct * work)7148 static void rtl8xxxu_watchdog_callback(struct work_struct *work)
7149 {
7150 struct ieee80211_vif *vif;
7151 struct rtl8xxxu_priv *priv;
7152
7153 priv = container_of(work, struct rtl8xxxu_priv, ra_watchdog.work);
7154 vif = priv->vif;
7155
7156 if (vif && vif->type == NL80211_IFTYPE_STATION) {
7157 int signal;
7158 struct ieee80211_sta *sta;
7159
7160 rcu_read_lock();
7161 sta = ieee80211_find_sta(vif, vif->bss_conf.bssid);
7162 if (!sta) {
7163 struct device *dev = &priv->udev->dev;
7164
7165 dev_dbg(dev, "%s: no sta found\n", __func__);
7166 rcu_read_unlock();
7167 goto out;
7168 }
7169 rcu_read_unlock();
7170
7171 signal = ieee80211_ave_rssi(vif);
7172
7173 priv->fops->report_rssi(priv, 0,
7174 rtl8xxxu_signal_to_snr(signal));
7175
7176 if (priv->fops->set_crystal_cap)
7177 rtl8xxxu_track_cfo(priv);
7178
7179 rtl8xxxu_refresh_rate_mask(priv, signal, sta, false);
7180 }
7181
7182 out:
7183 schedule_delayed_work(&priv->ra_watchdog, 2 * HZ);
7184 }
7185
rtl8xxxu_start(struct ieee80211_hw * hw)7186 static int rtl8xxxu_start(struct ieee80211_hw *hw)
7187 {
7188 struct rtl8xxxu_priv *priv = hw->priv;
7189 struct rtl8xxxu_rx_urb *rx_urb;
7190 struct rtl8xxxu_tx_urb *tx_urb;
7191 struct sk_buff *skb;
7192 unsigned long flags;
7193 int ret, i;
7194
7195 ret = 0;
7196
7197 init_usb_anchor(&priv->rx_anchor);
7198 init_usb_anchor(&priv->tx_anchor);
7199 init_usb_anchor(&priv->int_anchor);
7200
7201 priv->fops->enable_rf(priv);
7202 if (priv->usb_interrupts) {
7203 ret = rtl8xxxu_submit_int_urb(hw);
7204 if (ret)
7205 goto exit;
7206 }
7207
7208 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
7209 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
7210 if (!tx_urb) {
7211 if (!i)
7212 ret = -ENOMEM;
7213
7214 goto error_out;
7215 }
7216 usb_init_urb(&tx_urb->urb);
7217 INIT_LIST_HEAD(&tx_urb->list);
7218 tx_urb->hw = hw;
7219 list_add(&tx_urb->list, &priv->tx_urb_free_list);
7220 priv->tx_urb_free_count++;
7221 }
7222
7223 priv->tx_stopped = false;
7224
7225 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7226 priv->shutdown = false;
7227 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7228
7229 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
7230 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
7231 if (!rx_urb) {
7232 if (!i)
7233 ret = -ENOMEM;
7234
7235 goto error_out;
7236 }
7237 usb_init_urb(&rx_urb->urb);
7238 INIT_LIST_HEAD(&rx_urb->list);
7239 rx_urb->hw = hw;
7240
7241 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
7242 if (ret) {
7243 if (ret != -ENOMEM) {
7244 skb = (struct sk_buff *)rx_urb->urb.context;
7245 dev_kfree_skb(skb);
7246 }
7247 rtl8xxxu_queue_rx_urb(priv, rx_urb);
7248 }
7249 }
7250
7251 schedule_delayed_work(&priv->ra_watchdog, 2 * HZ);
7252 exit:
7253 /*
7254 * Accept all data and mgmt frames
7255 */
7256 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
7257 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
7258
7259 rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1,
7260 OFDM0_X_AGC_CORE1_IGI_MASK, 0x1e);
7261
7262 return ret;
7263
7264 error_out:
7265 rtl8xxxu_free_tx_resources(priv);
7266 /*
7267 * Disable all data and mgmt frames
7268 */
7269 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
7270 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
7271
7272 return ret;
7273 }
7274
rtl8xxxu_stop(struct ieee80211_hw * hw)7275 static void rtl8xxxu_stop(struct ieee80211_hw *hw)
7276 {
7277 struct rtl8xxxu_priv *priv = hw->priv;
7278 unsigned long flags;
7279
7280 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
7281
7282 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
7283 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
7284
7285 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7286 priv->shutdown = true;
7287 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7288
7289 usb_kill_anchored_urbs(&priv->rx_anchor);
7290 usb_kill_anchored_urbs(&priv->tx_anchor);
7291 if (priv->usb_interrupts)
7292 usb_kill_anchored_urbs(&priv->int_anchor);
7293
7294 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
7295
7296 priv->fops->disable_rf(priv);
7297
7298 /*
7299 * Disable interrupts
7300 */
7301 if (priv->usb_interrupts)
7302 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
7303
7304 cancel_work_sync(&priv->c2hcmd_work);
7305 cancel_delayed_work_sync(&priv->ra_watchdog);
7306
7307 rtl8xxxu_free_rx_resources(priv);
7308 rtl8xxxu_free_tx_resources(priv);
7309 }
7310
rtl8xxxu_sta_add(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)7311 static int rtl8xxxu_sta_add(struct ieee80211_hw *hw,
7312 struct ieee80211_vif *vif,
7313 struct ieee80211_sta *sta)
7314 {
7315 struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv;
7316 struct rtl8xxxu_priv *priv = hw->priv;
7317
7318 if (vif->type == NL80211_IFTYPE_AP) {
7319 sta_info->macid = rtl8xxxu_acquire_macid(priv);
7320 if (sta_info->macid >= RTL8XXXU_MAX_MAC_ID_NUM)
7321 return -ENOSPC;
7322
7323 rtl8xxxu_refresh_rate_mask(priv, 0, sta, true);
7324 priv->fops->report_connect(priv, sta_info->macid, H2C_MACID_ROLE_STA, true);
7325 }
7326
7327 return 0;
7328 }
7329
rtl8xxxu_sta_remove(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)7330 static int rtl8xxxu_sta_remove(struct ieee80211_hw *hw,
7331 struct ieee80211_vif *vif,
7332 struct ieee80211_sta *sta)
7333 {
7334 struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv;
7335 struct rtl8xxxu_priv *priv = hw->priv;
7336
7337 if (vif->type == NL80211_IFTYPE_AP)
7338 rtl8xxxu_release_macid(priv, sta_info->macid);
7339
7340 return 0;
7341 }
7342
7343 static const struct ieee80211_ops rtl8xxxu_ops = {
7344 .tx = rtl8xxxu_tx,
7345 .wake_tx_queue = ieee80211_handle_wake_tx_queue,
7346 .add_interface = rtl8xxxu_add_interface,
7347 .remove_interface = rtl8xxxu_remove_interface,
7348 .config = rtl8xxxu_config,
7349 .conf_tx = rtl8xxxu_conf_tx,
7350 .bss_info_changed = rtl8xxxu_bss_info_changed,
7351 .start_ap = rtl8xxxu_start_ap,
7352 .configure_filter = rtl8xxxu_configure_filter,
7353 .set_rts_threshold = rtl8xxxu_set_rts_threshold,
7354 .start = rtl8xxxu_start,
7355 .stop = rtl8xxxu_stop,
7356 .sw_scan_start = rtl8xxxu_sw_scan_start,
7357 .sw_scan_complete = rtl8xxxu_sw_scan_complete,
7358 .set_key = rtl8xxxu_set_key,
7359 .ampdu_action = rtl8xxxu_ampdu_action,
7360 .sta_statistics = rtl8xxxu_sta_statistics,
7361 .get_antenna = rtl8xxxu_get_antenna,
7362 .set_tim = rtl8xxxu_set_tim,
7363 .sta_add = rtl8xxxu_sta_add,
7364 .sta_remove = rtl8xxxu_sta_remove,
7365 };
7366
rtl8xxxu_parse_usb(struct rtl8xxxu_priv * priv,struct usb_interface * interface)7367 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
7368 struct usb_interface *interface)
7369 {
7370 struct usb_interface_descriptor *interface_desc;
7371 struct usb_host_interface *host_interface;
7372 struct usb_endpoint_descriptor *endpoint;
7373 struct device *dev = &priv->udev->dev;
7374 int i, j = 0, endpoints;
7375 u8 dir, xtype, num;
7376 int ret = 0;
7377
7378 host_interface = interface->cur_altsetting;
7379 interface_desc = &host_interface->desc;
7380 endpoints = interface_desc->bNumEndpoints;
7381
7382 for (i = 0; i < endpoints; i++) {
7383 endpoint = &host_interface->endpoint[i].desc;
7384
7385 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
7386 num = usb_endpoint_num(endpoint);
7387 xtype = usb_endpoint_type(endpoint);
7388 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7389 dev_dbg(dev,
7390 "%s: endpoint: dir %02x, # %02x, type %02x\n",
7391 __func__, dir, num, xtype);
7392 if (usb_endpoint_dir_in(endpoint) &&
7393 usb_endpoint_xfer_bulk(endpoint)) {
7394 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7395 dev_dbg(dev, "%s: in endpoint num %i\n",
7396 __func__, num);
7397
7398 if (priv->pipe_in) {
7399 dev_warn(dev,
7400 "%s: Too many IN pipes\n", __func__);
7401 ret = -EINVAL;
7402 goto exit;
7403 }
7404
7405 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
7406 }
7407
7408 if (usb_endpoint_dir_in(endpoint) &&
7409 usb_endpoint_xfer_int(endpoint)) {
7410 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7411 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
7412 __func__, num);
7413
7414 if (priv->pipe_interrupt) {
7415 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
7416 __func__);
7417 ret = -EINVAL;
7418 goto exit;
7419 }
7420
7421 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
7422 }
7423
7424 if (usb_endpoint_dir_out(endpoint) &&
7425 usb_endpoint_xfer_bulk(endpoint)) {
7426 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7427 dev_dbg(dev, "%s: out endpoint num %i\n",
7428 __func__, num);
7429 if (j >= RTL8XXXU_OUT_ENDPOINTS) {
7430 dev_warn(dev,
7431 "%s: Too many OUT pipes\n", __func__);
7432 ret = -EINVAL;
7433 goto exit;
7434 }
7435 priv->out_ep[j++] = num;
7436 }
7437 }
7438 exit:
7439 priv->nr_out_eps = j;
7440 return ret;
7441 }
7442
rtl8xxxu_init_led(struct rtl8xxxu_priv * priv)7443 static void rtl8xxxu_init_led(struct rtl8xxxu_priv *priv)
7444 {
7445 struct led_classdev *led = &priv->led_cdev;
7446
7447 if (!priv->fops->led_classdev_brightness_set)
7448 return;
7449
7450 led->brightness_set_blocking = priv->fops->led_classdev_brightness_set;
7451
7452 snprintf(priv->led_name, sizeof(priv->led_name),
7453 "rtl8xxxu-usb%s", dev_name(&priv->udev->dev));
7454 led->name = priv->led_name;
7455 led->max_brightness = RTL8XXXU_HW_LED_CONTROL;
7456
7457 if (led_classdev_register(&priv->udev->dev, led))
7458 return;
7459
7460 priv->led_registered = true;
7461
7462 led->brightness = led->max_brightness;
7463 priv->fops->led_classdev_brightness_set(led, led->brightness);
7464 }
7465
rtl8xxxu_deinit_led(struct rtl8xxxu_priv * priv)7466 static void rtl8xxxu_deinit_led(struct rtl8xxxu_priv *priv)
7467 {
7468 struct led_classdev *led = &priv->led_cdev;
7469
7470 if (!priv->led_registered)
7471 return;
7472
7473 priv->fops->led_classdev_brightness_set(led, LED_OFF);
7474 led_classdev_unregister(led);
7475 }
7476
rtl8xxxu_probe(struct usb_interface * interface,const struct usb_device_id * id)7477 static int rtl8xxxu_probe(struct usb_interface *interface,
7478 const struct usb_device_id *id)
7479 {
7480 struct rtl8xxxu_priv *priv;
7481 struct ieee80211_hw *hw;
7482 struct usb_device *udev;
7483 struct ieee80211_supported_band *sband;
7484 int ret;
7485 int untested = 1;
7486
7487 udev = usb_get_dev(interface_to_usbdev(interface));
7488
7489 switch (id->idVendor) {
7490 case USB_VENDOR_ID_REALTEK:
7491 switch(id->idProduct) {
7492 case 0x1724:
7493 case 0x8176:
7494 case 0x8178:
7495 case 0x817f:
7496 case 0x818b:
7497 case 0xf179:
7498 case 0x8179:
7499 case 0xb711:
7500 case 0xf192:
7501 untested = 0;
7502 break;
7503 }
7504 break;
7505 case 0x7392:
7506 if (id->idProduct == 0x7811 || id->idProduct == 0xa611 || id->idProduct == 0xb811)
7507 untested = 0;
7508 break;
7509 case 0x050d:
7510 if (id->idProduct == 0x1004)
7511 untested = 0;
7512 break;
7513 case 0x20f4:
7514 if (id->idProduct == 0x648b)
7515 untested = 0;
7516 break;
7517 case 0x2001:
7518 if (id->idProduct == 0x3308)
7519 untested = 0;
7520 break;
7521 case 0x2357:
7522 if (id->idProduct == 0x0109)
7523 untested = 0;
7524 break;
7525 case 0x0b05:
7526 if (id->idProduct == 0x18f1)
7527 untested = 0;
7528 break;
7529 default:
7530 break;
7531 }
7532
7533 if (untested) {
7534 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE;
7535 dev_info(&udev->dev,
7536 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
7537 id->idVendor, id->idProduct);
7538 dev_info(&udev->dev,
7539 "Please report results to Jes.Sorensen@gmail.com\n");
7540 }
7541
7542 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
7543 if (!hw) {
7544 ret = -ENOMEM;
7545 goto err_put_dev;
7546 }
7547
7548 priv = hw->priv;
7549 priv->hw = hw;
7550 priv->udev = udev;
7551 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
7552 mutex_init(&priv->usb_buf_mutex);
7553 mutex_init(&priv->syson_indirect_access_mutex);
7554 mutex_init(&priv->h2c_mutex);
7555 INIT_LIST_HEAD(&priv->tx_urb_free_list);
7556 spin_lock_init(&priv->tx_urb_lock);
7557 INIT_LIST_HEAD(&priv->rx_urb_pending_list);
7558 spin_lock_init(&priv->rx_urb_lock);
7559 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
7560 INIT_DELAYED_WORK(&priv->ra_watchdog, rtl8xxxu_watchdog_callback);
7561 INIT_WORK(&priv->update_beacon_work, rtl8xxxu_update_beacon_work_callback);
7562 skb_queue_head_init(&priv->c2hcmd_queue);
7563
7564 usb_set_intfdata(interface, hw);
7565
7566 ret = rtl8xxxu_parse_usb(priv, interface);
7567 if (ret)
7568 goto err_set_intfdata;
7569
7570 ret = priv->fops->identify_chip(priv);
7571 if (ret) {
7572 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
7573 goto err_set_intfdata;
7574 }
7575
7576 hw->wiphy->available_antennas_tx = BIT(priv->tx_paths) - 1;
7577 hw->wiphy->available_antennas_rx = BIT(priv->rx_paths) - 1;
7578
7579 if (priv->rtl_chip == RTL8188E)
7580 INIT_WORK(&priv->c2hcmd_work, rtl8188e_c2hcmd_callback);
7581 else
7582 INIT_WORK(&priv->c2hcmd_work, rtl8xxxu_c2hcmd_callback);
7583
7584 ret = priv->fops->read_efuse(priv);
7585 if (ret) {
7586 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
7587 goto err_set_intfdata;
7588 }
7589
7590 ret = priv->fops->parse_efuse(priv);
7591 if (ret) {
7592 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
7593 goto err_set_intfdata;
7594 }
7595
7596 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE)
7597 rtl8xxxu_dump_efuse(priv);
7598
7599 rtl8xxxu_print_chipinfo(priv);
7600
7601 ret = priv->fops->load_firmware(priv);
7602 if (ret) {
7603 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
7604 goto err_set_intfdata;
7605 }
7606
7607 ret = rtl8xxxu_init_device(hw);
7608 if (ret)
7609 goto err_set_intfdata;
7610
7611 hw->wiphy->max_scan_ssids = 1;
7612 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
7613 if (priv->fops->max_macid_num)
7614 hw->wiphy->max_ap_assoc_sta = priv->fops->max_macid_num - 1;
7615 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
7616 if (priv->fops->supports_ap)
7617 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP);
7618 hw->queues = 4;
7619
7620 sband = &rtl8xxxu_supported_band;
7621 sband->ht_cap.ht_supported = true;
7622 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
7623 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
7624 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
7625 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
7626 sband->ht_cap.mcs.rx_mask[0] = 0xff;
7627 sband->ht_cap.mcs.rx_mask[4] = 0x01;
7628 if (priv->rf_paths > 1) {
7629 sband->ht_cap.mcs.rx_mask[1] = 0xff;
7630 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
7631 }
7632 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
7633 /*
7634 * Some APs will negotiate HT20_40 in a noisy environment leading
7635 * to miserable performance. Rather than defaulting to this, only
7636 * enable it if explicitly requested at module load time.
7637 */
7638 if (rtl8xxxu_ht40_2g) {
7639 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
7640 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
7641 }
7642 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
7643
7644 hw->wiphy->rts_threshold = 2347;
7645
7646 SET_IEEE80211_DEV(priv->hw, &interface->dev);
7647 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
7648
7649 hw->extra_tx_headroom = priv->fops->tx_desc_size;
7650 ieee80211_hw_set(hw, SIGNAL_DBM);
7651
7652 /*
7653 * The firmware handles rate control, except for RTL8188EU,
7654 * where we handle the rate control in the driver.
7655 */
7656 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
7657 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
7658 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
7659 ieee80211_hw_set(hw, MFP_CAPABLE);
7660
7661 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
7662
7663 ret = ieee80211_register_hw(priv->hw);
7664 if (ret) {
7665 dev_err(&udev->dev, "%s: Failed to register: %i\n",
7666 __func__, ret);
7667 goto err_set_intfdata;
7668 }
7669
7670 rtl8xxxu_init_led(priv);
7671
7672 return 0;
7673
7674 err_set_intfdata:
7675 usb_set_intfdata(interface, NULL);
7676
7677 kfree(priv->fw_data);
7678 mutex_destroy(&priv->usb_buf_mutex);
7679 mutex_destroy(&priv->syson_indirect_access_mutex);
7680 mutex_destroy(&priv->h2c_mutex);
7681
7682 ieee80211_free_hw(hw);
7683 err_put_dev:
7684 usb_put_dev(udev);
7685
7686 return ret;
7687 }
7688
rtl8xxxu_disconnect(struct usb_interface * interface)7689 static void rtl8xxxu_disconnect(struct usb_interface *interface)
7690 {
7691 struct rtl8xxxu_priv *priv;
7692 struct ieee80211_hw *hw;
7693
7694 hw = usb_get_intfdata(interface);
7695 priv = hw->priv;
7696
7697 rtl8xxxu_deinit_led(priv);
7698
7699 ieee80211_unregister_hw(hw);
7700
7701 priv->fops->power_off(priv);
7702
7703 usb_set_intfdata(interface, NULL);
7704
7705 dev_info(&priv->udev->dev, "disconnecting\n");
7706
7707 kfree(priv->fw_data);
7708 mutex_destroy(&priv->usb_buf_mutex);
7709 mutex_destroy(&priv->syson_indirect_access_mutex);
7710 mutex_destroy(&priv->h2c_mutex);
7711
7712 if (priv->udev->state != USB_STATE_NOTATTACHED) {
7713 dev_info(&priv->udev->dev,
7714 "Device still attached, trying to reset\n");
7715 usb_reset_device(priv->udev);
7716 }
7717 usb_put_dev(priv->udev);
7718 ieee80211_free_hw(hw);
7719 }
7720
7721 static const struct usb_device_id dev_table[] = {
7722 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
7723 .driver_info = (unsigned long)&rtl8723au_fops},
7724 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
7725 .driver_info = (unsigned long)&rtl8723au_fops},
7726 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
7727 .driver_info = (unsigned long)&rtl8723au_fops},
7728 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
7729 .driver_info = (unsigned long)&rtl8192eu_fops},
7730 /* TP-Link TL-WN822N v4 */
7731 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0108, 0xff, 0xff, 0xff),
7732 .driver_info = (unsigned long)&rtl8192eu_fops},
7733 /* D-Link DWA-131 rev E1, tested by David Patiño */
7734 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3319, 0xff, 0xff, 0xff),
7735 .driver_info = (unsigned long)&rtl8192eu_fops},
7736 /* Tested by Myckel Habets */
7737 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0109, 0xff, 0xff, 0xff),
7738 .driver_info = (unsigned long)&rtl8192eu_fops},
7739 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
7740 .driver_info = (unsigned long)&rtl8723bu_fops},
7741 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xa611, 0xff, 0xff, 0xff),
7742 .driver_info = (unsigned long)&rtl8723bu_fops},
7743 /* RTL8188FU */
7744 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xf179, 0xff, 0xff, 0xff),
7745 .driver_info = (unsigned long)&rtl8188fu_fops},
7746 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8179, 0xff, 0xff, 0xff),
7747 .driver_info = (unsigned long)&rtl8188eu_fops},
7748 /* Tested by Hans de Goede - rtl8188etv */
7749 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0179, 0xff, 0xff, 0xff),
7750 .driver_info = (unsigned long)&rtl8188eu_fops},
7751 /* Sitecom rtl8188eus */
7752 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0076, 0xff, 0xff, 0xff),
7753 .driver_info = (unsigned long)&rtl8188eu_fops},
7754 /* D-Link USB-GO-N150 */
7755 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3311, 0xff, 0xff, 0xff),
7756 .driver_info = (unsigned long)&rtl8188eu_fops},
7757 /* D-Link DWA-125 REV D1 */
7758 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330f, 0xff, 0xff, 0xff),
7759 .driver_info = (unsigned long)&rtl8188eu_fops},
7760 /* D-Link DWA-123 REV D1 */
7761 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3310, 0xff, 0xff, 0xff),
7762 .driver_info = (unsigned long)&rtl8188eu_fops},
7763 /* D-Link DWA-121 rev B1 */
7764 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x331b, 0xff, 0xff, 0xff),
7765 .driver_info = (unsigned long)&rtl8188eu_fops},
7766 /* Abocom - Abocom */
7767 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8179, 0xff, 0xff, 0xff),
7768 .driver_info = (unsigned long)&rtl8188eu_fops},
7769 /* Elecom WDC-150SU2M */
7770 {USB_DEVICE_AND_INTERFACE_INFO(0x056e, 0x4008, 0xff, 0xff, 0xff),
7771 .driver_info = (unsigned long)&rtl8188eu_fops},
7772 /* TP-Link TL-WN722N v2 */
7773 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x010c, 0xff, 0xff, 0xff),
7774 .driver_info = (unsigned long)&rtl8188eu_fops},
7775 /* TP-Link TL-WN727N v5.21 */
7776 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0111, 0xff, 0xff, 0xff),
7777 .driver_info = (unsigned long)&rtl8188eu_fops},
7778 /* MERCUSYS MW150US v2 */
7779 {USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0102, 0xff, 0xff, 0xff),
7780 .driver_info = (unsigned long)&rtl8188eu_fops},
7781 /* ASUS USB-N10 Nano B1 */
7782 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x18f0, 0xff, 0xff, 0xff),
7783 .driver_info = (unsigned long)&rtl8188eu_fops},
7784 /* Edimax EW-7811Un V2 */
7785 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xb811, 0xff, 0xff, 0xff),
7786 .driver_info = (unsigned long)&rtl8188eu_fops},
7787 /* Rosewill USB-N150 Nano */
7788 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xffef, 0xff, 0xff, 0xff),
7789 .driver_info = (unsigned long)&rtl8188eu_fops},
7790 /* RTL8710BU aka RTL8188GU (not to be confused with RTL8188GTVU) */
7791 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb711, 0xff, 0xff, 0xff),
7792 .driver_info = (unsigned long)&rtl8710bu_fops},
7793 /* TOTOLINK N150UA V5 / N150UA-B */
7794 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2005, 0xff, 0xff, 0xff),
7795 .driver_info = (unsigned long)&rtl8710bu_fops},
7796 /* Comfast CF-826F */
7797 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xf192, 0xff, 0xff, 0xff),
7798 .driver_info = (unsigned long)&rtl8192fu_fops},
7799 /* Asus USB-N13 rev C1 */
7800 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x18f1, 0xff, 0xff, 0xff),
7801 .driver_info = (unsigned long)&rtl8192fu_fops},
7802 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xb722, 0xff, 0xff, 0xff),
7803 .driver_info = (unsigned long)&rtl8192fu_fops},
7804 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x318b, 0xff, 0xff, 0xff),
7805 .driver_info = (unsigned long)&rtl8192fu_fops},
7806 #ifdef CONFIG_RTL8XXXU_UNTESTED
7807 /* Still supported by rtlwifi */
7808 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
7809 .driver_info = (unsigned long)&rtl8192cu_fops},
7810 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
7811 .driver_info = (unsigned long)&rtl8192cu_fops},
7812 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
7813 .driver_info = (unsigned long)&rtl8192cu_fops},
7814 /* Tested by Larry Finger */
7815 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
7816 .driver_info = (unsigned long)&rtl8192cu_fops},
7817 /* Tested by Andrea Merello */
7818 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
7819 .driver_info = (unsigned long)&rtl8192cu_fops},
7820 /* Tested by Jocelyn Mayer */
7821 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
7822 .driver_info = (unsigned long)&rtl8192cu_fops},
7823 /* Tested by Stefano Bravi */
7824 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
7825 .driver_info = (unsigned long)&rtl8192cu_fops},
7826 /* Currently untested 8188 series devices */
7827 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x018a, 0xff, 0xff, 0xff),
7828 .driver_info = (unsigned long)&rtl8192cu_fops},
7829 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
7830 .driver_info = (unsigned long)&rtl8192cu_fops},
7831 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
7832 .driver_info = (unsigned long)&rtl8192cu_fops},
7833 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
7834 .driver_info = (unsigned long)&rtl8192cu_fops},
7835 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
7836 .driver_info = (unsigned long)&rtl8192cu_fops},
7837 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
7838 .driver_info = (unsigned long)&rtl8192cu_fops},
7839 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
7840 .driver_info = (unsigned long)&rtl8192cu_fops},
7841 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
7842 .driver_info = (unsigned long)&rtl8192cu_fops},
7843 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
7844 .driver_info = (unsigned long)&rtl8192cu_fops},
7845 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
7846 .driver_info = (unsigned long)&rtl8192cu_fops},
7847 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
7848 .driver_info = (unsigned long)&rtl8192cu_fops},
7849 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
7850 .driver_info = (unsigned long)&rtl8192cu_fops},
7851 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
7852 .driver_info = (unsigned long)&rtl8192cu_fops},
7853 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
7854 .driver_info = (unsigned long)&rtl8192cu_fops},
7855 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
7856 .driver_info = (unsigned long)&rtl8192cu_fops},
7857 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
7858 .driver_info = (unsigned long)&rtl8192cu_fops},
7859 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
7860 .driver_info = (unsigned long)&rtl8192cu_fops},
7861 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
7862 .driver_info = (unsigned long)&rtl8192cu_fops},
7863 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
7864 .driver_info = (unsigned long)&rtl8192cu_fops},
7865 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
7866 .driver_info = (unsigned long)&rtl8192cu_fops},
7867 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
7868 .driver_info = (unsigned long)&rtl8192cu_fops},
7869 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
7870 .driver_info = (unsigned long)&rtl8192cu_fops},
7871 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
7872 .driver_info = (unsigned long)&rtl8192cu_fops},
7873 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
7874 .driver_info = (unsigned long)&rtl8192cu_fops},
7875 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
7876 .driver_info = (unsigned long)&rtl8192cu_fops},
7877 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
7878 .driver_info = (unsigned long)&rtl8192cu_fops},
7879 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
7880 .driver_info = (unsigned long)&rtl8192cu_fops},
7881 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
7882 .driver_info = (unsigned long)&rtl8192cu_fops},
7883 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
7884 .driver_info = (unsigned long)&rtl8192cu_fops},
7885 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
7886 .driver_info = (unsigned long)&rtl8192cu_fops},
7887 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
7888 .driver_info = (unsigned long)&rtl8192cu_fops},
7889 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
7890 .driver_info = (unsigned long)&rtl8192cu_fops},
7891 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
7892 .driver_info = (unsigned long)&rtl8192cu_fops},
7893 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
7894 .driver_info = (unsigned long)&rtl8192cu_fops},
7895 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
7896 .driver_info = (unsigned long)&rtl8192cu_fops},
7897 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
7898 .driver_info = (unsigned long)&rtl8192cu_fops},
7899 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
7900 .driver_info = (unsigned long)&rtl8192cu_fops},
7901 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
7902 .driver_info = (unsigned long)&rtl8192cu_fops},
7903 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
7904 .driver_info = (unsigned long)&rtl8192cu_fops},
7905 /* Currently untested 8192 series devices */
7906 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
7907 .driver_info = (unsigned long)&rtl8192cu_fops},
7908 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
7909 .driver_info = (unsigned long)&rtl8192cu_fops},
7910 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
7911 .driver_info = (unsigned long)&rtl8192cu_fops},
7912 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
7913 .driver_info = (unsigned long)&rtl8192cu_fops},
7914 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
7915 .driver_info = (unsigned long)&rtl8192cu_fops},
7916 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
7917 .driver_info = (unsigned long)&rtl8192cu_fops},
7918 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
7919 .driver_info = (unsigned long)&rtl8192cu_fops},
7920 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
7921 .driver_info = (unsigned long)&rtl8192cu_fops},
7922 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
7923 .driver_info = (unsigned long)&rtl8192cu_fops},
7924 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
7925 .driver_info = (unsigned long)&rtl8192cu_fops},
7926 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
7927 .driver_info = (unsigned long)&rtl8192cu_fops},
7928 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
7929 .driver_info = (unsigned long)&rtl8192cu_fops},
7930 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
7931 .driver_info = (unsigned long)&rtl8192cu_fops},
7932 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
7933 .driver_info = (unsigned long)&rtl8192cu_fops},
7934 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
7935 .driver_info = (unsigned long)&rtl8192cu_fops},
7936 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
7937 .driver_info = (unsigned long)&rtl8192cu_fops},
7938 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
7939 .driver_info = (unsigned long)&rtl8192cu_fops},
7940 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
7941 .driver_info = (unsigned long)&rtl8192cu_fops},
7942 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
7943 .driver_info = (unsigned long)&rtl8192cu_fops},
7944 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
7945 .driver_info = (unsigned long)&rtl8192cu_fops},
7946 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
7947 .driver_info = (unsigned long)&rtl8192cu_fops},
7948 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
7949 .driver_info = (unsigned long)&rtl8192cu_fops},
7950 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
7951 .driver_info = (unsigned long)&rtl8192cu_fops},
7952 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
7953 .driver_info = (unsigned long)&rtl8192cu_fops},
7954 /* found in rtl8192eu vendor driver */
7955 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0107, 0xff, 0xff, 0xff),
7956 .driver_info = (unsigned long)&rtl8192eu_fops},
7957 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab33, 0xff, 0xff, 0xff),
7958 .driver_info = (unsigned long)&rtl8192eu_fops},
7959 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818c, 0xff, 0xff, 0xff),
7960 .driver_info = (unsigned long)&rtl8192eu_fops},
7961 /* D-Link DWA-131 rev C1 */
7962 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3312, 0xff, 0xff, 0xff),
7963 .driver_info = (unsigned long)&rtl8192eu_fops},
7964 /* TP-Link TL-WN8200ND V2 */
7965 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0126, 0xff, 0xff, 0xff),
7966 .driver_info = (unsigned long)&rtl8192eu_fops},
7967 /* Mercusys MW300UM */
7968 {USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0100, 0xff, 0xff, 0xff),
7969 .driver_info = (unsigned long)&rtl8192eu_fops},
7970 /* Mercusys MW300UH */
7971 {USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0104, 0xff, 0xff, 0xff),
7972 .driver_info = (unsigned long)&rtl8192eu_fops},
7973 #endif
7974 { }
7975 };
7976
7977 static struct usb_driver rtl8xxxu_driver = {
7978 .name = DRIVER_NAME,
7979 .probe = rtl8xxxu_probe,
7980 .disconnect = rtl8xxxu_disconnect,
7981 .id_table = dev_table,
7982 .no_dynamic_id = 1,
7983 .disable_hub_initiated_lpm = 1,
7984 };
7985
7986 MODULE_DEVICE_TABLE(usb, dev_table);
7987
7988 module_usb_driver(rtl8xxxu_driver);
7989