1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * RTL8XXXU mac80211 USB driver 4 * 5 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> 6 * 7 * Portions, notably calibration code: 8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 9 * 10 * This driver was written as a replacement for the vendor provided 11 * rtl8723au driver. As the Realtek 8xxx chips are very similar in 12 * their programming interface, I have started adding support for 13 * additional 8xxx chips like the 8192cu, 8188cus, etc. 14 */ 15 16 #include <linux/init.h> 17 #include <linux/kernel.h> 18 #include <linux/sched.h> 19 #include <linux/errno.h> 20 #include <linux/slab.h> 21 #include <linux/module.h> 22 #include <linux/spinlock.h> 23 #include <linux/list.h> 24 #include <linux/usb.h> 25 #include <linux/netdevice.h> 26 #include <linux/etherdevice.h> 27 #include <linux/ethtool.h> 28 #include <linux/wireless.h> 29 #include <linux/firmware.h> 30 #include <linux/moduleparam.h> 31 #include <net/mac80211.h> 32 #include "rtl8xxxu.h" 33 #include "rtl8xxxu_regs.h" 34 35 #define DRIVER_NAME "rtl8xxxu" 36 37 int rtl8xxxu_debug; 38 static bool rtl8xxxu_ht40_2g; 39 static bool rtl8xxxu_dma_aggregation; 40 static int rtl8xxxu_dma_agg_timeout = -1; 41 static int rtl8xxxu_dma_agg_pages = -1; 42 43 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@gmail.com>"); 44 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver"); 45 MODULE_LICENSE("GPL"); 46 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin"); 47 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin"); 48 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin"); 49 MODULE_FIRMWARE("rtlwifi/rtl8188eufw.bin"); 50 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin"); 51 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin"); 52 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin"); 53 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin"); 54 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin"); 55 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin"); 56 MODULE_FIRMWARE("rtlwifi/rtl8188fufw.bin"); 57 MODULE_FIRMWARE("rtlwifi/rtl8710bufw_SMIC.bin"); 58 MODULE_FIRMWARE("rtlwifi/rtl8710bufw_UMC.bin"); 59 60 module_param_named(debug, rtl8xxxu_debug, int, 0600); 61 MODULE_PARM_DESC(debug, "Set debug mask"); 62 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600); 63 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band"); 64 module_param_named(dma_aggregation, rtl8xxxu_dma_aggregation, bool, 0600); 65 MODULE_PARM_DESC(dma_aggregation, "Enable DMA packet aggregation"); 66 module_param_named(dma_agg_timeout, rtl8xxxu_dma_agg_timeout, int, 0600); 67 MODULE_PARM_DESC(dma_agg_timeout, "Set DMA aggregation timeout (range 1-127)"); 68 module_param_named(dma_agg_pages, rtl8xxxu_dma_agg_pages, int, 0600); 69 MODULE_PARM_DESC(dma_agg_pages, "Set DMA aggregation pages (range 1-127, 0 to disable)"); 70 71 #define USB_VENDOR_ID_REALTEK 0x0bda 72 #define RTL8XXXU_RX_URBS 32 73 #define RTL8XXXU_RX_URB_PENDING_WATER 8 74 #define RTL8XXXU_TX_URBS 64 75 #define RTL8XXXU_TX_URB_LOW_WATER 25 76 #define RTL8XXXU_TX_URB_HIGH_WATER 32 77 78 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv, 79 struct rtl8xxxu_rx_urb *rx_urb); 80 81 static struct ieee80211_rate rtl8xxxu_rates[] = { 82 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 }, 83 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 }, 84 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 }, 85 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 }, 86 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 }, 87 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 }, 88 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 }, 89 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 }, 90 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 }, 91 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 }, 92 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 }, 93 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 }, 94 }; 95 96 static struct ieee80211_channel rtl8xxxu_channels_2g[] = { 97 { .band = NL80211_BAND_2GHZ, .center_freq = 2412, 98 .hw_value = 1, .max_power = 30 }, 99 { .band = NL80211_BAND_2GHZ, .center_freq = 2417, 100 .hw_value = 2, .max_power = 30 }, 101 { .band = NL80211_BAND_2GHZ, .center_freq = 2422, 102 .hw_value = 3, .max_power = 30 }, 103 { .band = NL80211_BAND_2GHZ, .center_freq = 2427, 104 .hw_value = 4, .max_power = 30 }, 105 { .band = NL80211_BAND_2GHZ, .center_freq = 2432, 106 .hw_value = 5, .max_power = 30 }, 107 { .band = NL80211_BAND_2GHZ, .center_freq = 2437, 108 .hw_value = 6, .max_power = 30 }, 109 { .band = NL80211_BAND_2GHZ, .center_freq = 2442, 110 .hw_value = 7, .max_power = 30 }, 111 { .band = NL80211_BAND_2GHZ, .center_freq = 2447, 112 .hw_value = 8, .max_power = 30 }, 113 { .band = NL80211_BAND_2GHZ, .center_freq = 2452, 114 .hw_value = 9, .max_power = 30 }, 115 { .band = NL80211_BAND_2GHZ, .center_freq = 2457, 116 .hw_value = 10, .max_power = 30 }, 117 { .band = NL80211_BAND_2GHZ, .center_freq = 2462, 118 .hw_value = 11, .max_power = 30 }, 119 { .band = NL80211_BAND_2GHZ, .center_freq = 2467, 120 .hw_value = 12, .max_power = 30 }, 121 { .band = NL80211_BAND_2GHZ, .center_freq = 2472, 122 .hw_value = 13, .max_power = 30 }, 123 { .band = NL80211_BAND_2GHZ, .center_freq = 2484, 124 .hw_value = 14, .max_power = 30 } 125 }; 126 127 static struct ieee80211_supported_band rtl8xxxu_supported_band = { 128 .channels = rtl8xxxu_channels_2g, 129 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g), 130 .bitrates = rtl8xxxu_rates, 131 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates), 132 }; 133 134 const struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[] = { 135 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00}, 136 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, 137 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00}, 138 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05}, 139 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01}, 140 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f}, 141 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72}, 142 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08}, 143 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, 144 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, 145 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, 146 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, 147 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, 148 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, 149 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16}, 150 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00}, 151 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02}, 152 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, 153 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, 154 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, 155 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, 156 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff}, 157 }; 158 159 static const struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = { 160 {0x800, 0x80040000}, {0x804, 0x00000003}, 161 {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, 162 {0x810, 0x10001331}, {0x814, 0x020c3d10}, 163 {0x818, 0x02200385}, {0x81c, 0x00000000}, 164 {0x820, 0x01000100}, {0x824, 0x00390004}, 165 {0x828, 0x00000000}, {0x82c, 0x00000000}, 166 {0x830, 0x00000000}, {0x834, 0x00000000}, 167 {0x838, 0x00000000}, {0x83c, 0x00000000}, 168 {0x840, 0x00010000}, {0x844, 0x00000000}, 169 {0x848, 0x00000000}, {0x84c, 0x00000000}, 170 {0x850, 0x00000000}, {0x854, 0x00000000}, 171 {0x858, 0x569a569a}, {0x85c, 0x001b25a4}, 172 {0x860, 0x66f60110}, {0x864, 0x061f0130}, 173 {0x868, 0x00000000}, {0x86c, 0x32323200}, 174 {0x870, 0x07000760}, {0x874, 0x22004000}, 175 {0x878, 0x00000808}, {0x87c, 0x00000000}, 176 {0x880, 0xc0083070}, {0x884, 0x000004d5}, 177 {0x888, 0x00000000}, {0x88c, 0xccc000c0}, 178 {0x890, 0x00000800}, {0x894, 0xfffffffe}, 179 {0x898, 0x40302010}, {0x89c, 0x00706050}, 180 {0x900, 0x00000000}, {0x904, 0x00000023}, 181 {0x908, 0x00000000}, {0x90c, 0x81121111}, 182 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c}, 183 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f}, 184 {0xa10, 0x9500bb78}, {0xa14, 0x11144028}, 185 {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, 186 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, 187 {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, 188 {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, 189 {0xa78, 0x00000900}, 190 {0xc00, 0x48071d40}, {0xc04, 0x03a05611}, 191 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, 192 {0xc10, 0x08800000}, {0xc14, 0x40000100}, 193 {0xc18, 0x08800000}, {0xc1c, 0x40000100}, 194 {0xc20, 0x00000000}, {0xc24, 0x00000000}, 195 {0xc28, 0x00000000}, {0xc2c, 0x00000000}, 196 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af}, 197 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, 198 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, 199 {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, 200 {0xc50, 0x69543420}, {0xc54, 0x43bc0094}, 201 {0xc58, 0x69543420}, {0xc5c, 0x433c0094}, 202 {0xc60, 0x00000000}, {0xc64, 0x7112848b}, 203 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, 204 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db}, 205 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612}, 206 {0xc80, 0x40000100}, {0xc84, 0x20f60000}, 207 {0xc88, 0x40000100}, {0xc8c, 0x20200000}, 208 {0xc90, 0x00121820}, {0xc94, 0x00000000}, 209 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, 210 {0xca0, 0x00000000}, {0xca4, 0x00000080}, 211 {0xca8, 0x00000000}, {0xcac, 0x00000000}, 212 {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, 213 {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, 214 {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, 215 {0xcc8, 0x00000000}, {0xccc, 0x00000000}, 216 {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, 217 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, 218 {0xce0, 0x00222222}, {0xce4, 0x00000000}, 219 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, 220 {0xd00, 0x00080740}, {0xd04, 0x00020401}, 221 {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, 222 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, 223 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975}, 224 {0xd30, 0x00000000}, {0xd34, 0x80608000}, 225 {0xd38, 0x00000000}, {0xd3c, 0x00027293}, 226 {0xd40, 0x00000000}, {0xd44, 0x00000000}, 227 {0xd48, 0x00000000}, {0xd4c, 0x00000000}, 228 {0xd50, 0x6437140a}, {0xd54, 0x00000000}, 229 {0xd58, 0x00000000}, {0xd5c, 0x30032064}, 230 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, 231 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, 232 {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, 233 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a}, 234 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a}, 235 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a}, 236 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a}, 237 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, 238 {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, 239 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, 240 {0xe44, 0x01004800}, {0xe48, 0xfb000000}, 241 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, 242 {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, 243 {0xe5c, 0x28160d05}, {0xe60, 0x00000008}, 244 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0}, 245 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0}, 246 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0}, 247 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0}, 248 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0}, 249 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0}, 250 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0}, 251 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0}, 252 {0xf14, 0x00000003}, {0xf4c, 0x00000000}, 253 {0xf00, 0x00000300}, 254 {0xffff, 0xffffffff}, 255 }; 256 257 static const struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = { 258 {0x024, 0x0011800f}, {0x028, 0x00ffdb83}, 259 {0x800, 0x80040002}, {0x804, 0x00000003}, 260 {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, 261 {0x810, 0x10000330}, {0x814, 0x020c3d10}, 262 {0x818, 0x02200385}, {0x81c, 0x00000000}, 263 {0x820, 0x01000100}, {0x824, 0x00390004}, 264 {0x828, 0x01000100}, {0x82c, 0x00390004}, 265 {0x830, 0x27272727}, {0x834, 0x27272727}, 266 {0x838, 0x27272727}, {0x83c, 0x27272727}, 267 {0x840, 0x00010000}, {0x844, 0x00010000}, 268 {0x848, 0x27272727}, {0x84c, 0x27272727}, 269 {0x850, 0x00000000}, {0x854, 0x00000000}, 270 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4}, 271 {0x860, 0x66e60230}, {0x864, 0x061f0130}, 272 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27}, 273 {0x870, 0x07000700}, {0x874, 0x22184000}, 274 {0x878, 0x08080808}, {0x87c, 0x00000000}, 275 {0x880, 0xc0083070}, {0x884, 0x000004d5}, 276 {0x888, 0x00000000}, {0x88c, 0xcc0000c0}, 277 {0x890, 0x00000800}, {0x894, 0xfffffffe}, 278 {0x898, 0x40302010}, {0x89c, 0x00706050}, 279 {0x900, 0x00000000}, {0x904, 0x00000023}, 280 {0x908, 0x00000000}, {0x90c, 0x81121313}, 281 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c}, 282 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f}, 283 {0xa10, 0x9500bb78}, {0xa14, 0x11144028}, 284 {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, 285 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, 286 {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, 287 {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, 288 {0xc00, 0x48071d40}, {0xc04, 0x03a05633}, 289 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, 290 {0xc10, 0x08800000}, {0xc14, 0x40000100}, 291 {0xc18, 0x08800000}, {0xc1c, 0x40000100}, 292 {0xc20, 0x00000000}, {0xc24, 0x00000000}, 293 {0xc28, 0x00000000}, {0xc2c, 0x00000000}, 294 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf}, 295 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, 296 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, 297 {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, 298 {0xc50, 0x69543420}, {0xc54, 0x43bc0094}, 299 {0xc58, 0x69543420}, {0xc5c, 0x433c0094}, 300 {0xc60, 0x00000000}, {0xc64, 0x5116848b}, 301 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, 302 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b}, 303 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612}, 304 {0xc80, 0x40000100}, {0xc84, 0x20f60000}, 305 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000}, 306 {0xc90, 0x00121820}, {0xc94, 0x00000000}, 307 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, 308 {0xca0, 0x00000000}, {0xca4, 0x00000080}, 309 {0xca8, 0x00000000}, {0xcac, 0x00000000}, 310 {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, 311 {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, 312 {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, 313 {0xcc8, 0x00000000}, {0xccc, 0x00000000}, 314 {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, 315 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, 316 {0xce0, 0x00222222}, {0xce4, 0x00000000}, 317 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, 318 {0xd00, 0x00080740}, {0xd04, 0x00020403}, 319 {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, 320 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, 321 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975}, 322 {0xd30, 0x00000000}, {0xd34, 0x80608000}, 323 {0xd38, 0x00000000}, {0xd3c, 0x00027293}, 324 {0xd40, 0x00000000}, {0xd44, 0x00000000}, 325 {0xd48, 0x00000000}, {0xd4c, 0x00000000}, 326 {0xd50, 0x6437140a}, {0xd54, 0x00000000}, 327 {0xd58, 0x00000000}, {0xd5c, 0x30032064}, 328 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, 329 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, 330 {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, 331 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a}, 332 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a}, 333 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a}, 334 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a}, 335 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, 336 {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, 337 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, 338 {0xe44, 0x01004800}, {0xe48, 0xfb000000}, 339 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, 340 {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, 341 {0xe5c, 0x28160d05}, {0xe60, 0x00000010}, 342 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4}, 343 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4}, 344 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4}, 345 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4}, 346 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4}, 347 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4}, 348 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4}, 349 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4}, 350 {0xf14, 0x00000003}, {0xf4c, 0x00000000}, 351 {0xf00, 0x00000300}, 352 {0xffff, 0xffffffff}, 353 }; 354 355 static const struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = { 356 {0x024, 0x0011800f}, {0x028, 0x00ffdb83}, 357 {0x040, 0x000c0004}, {0x800, 0x80040000}, 358 {0x804, 0x00000001}, {0x808, 0x0000fc00}, 359 {0x80c, 0x0000000a}, {0x810, 0x10005388}, 360 {0x814, 0x020c3d10}, {0x818, 0x02200385}, 361 {0x81c, 0x00000000}, {0x820, 0x01000100}, 362 {0x824, 0x00390204}, {0x828, 0x00000000}, 363 {0x82c, 0x00000000}, {0x830, 0x00000000}, 364 {0x834, 0x00000000}, {0x838, 0x00000000}, 365 {0x83c, 0x00000000}, {0x840, 0x00010000}, 366 {0x844, 0x00000000}, {0x848, 0x00000000}, 367 {0x84c, 0x00000000}, {0x850, 0x00000000}, 368 {0x854, 0x00000000}, {0x858, 0x569a569a}, 369 {0x85c, 0x001b25a4}, {0x860, 0x66e60230}, 370 {0x864, 0x061f0130}, {0x868, 0x00000000}, 371 {0x86c, 0x20202000}, {0x870, 0x03000300}, 372 {0x874, 0x22004000}, {0x878, 0x00000808}, 373 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070}, 374 {0x884, 0x000004d5}, {0x888, 0x00000000}, 375 {0x88c, 0xccc000c0}, {0x890, 0x00000800}, 376 {0x894, 0xfffffffe}, {0x898, 0x40302010}, 377 {0x89c, 0x00706050}, {0x900, 0x00000000}, 378 {0x904, 0x00000023}, {0x908, 0x00000000}, 379 {0x90c, 0x81121111}, {0xa00, 0x00d047c8}, 380 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300}, 381 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78}, 382 {0xa14, 0x11144028}, {0xa18, 0x00881117}, 383 {0xa1c, 0x89140f00}, {0xa20, 0x15160000}, 384 {0xa24, 0x070b0f12}, {0xa28, 0x00000104}, 385 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00}, 386 {0xa74, 0x00000007}, {0xc00, 0x48071d40}, 387 {0xc04, 0x03a05611}, {0xc08, 0x000000e4}, 388 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000}, 389 {0xc14, 0x40000100}, {0xc18, 0x08800000}, 390 {0xc1c, 0x40000100}, {0xc20, 0x00000000}, 391 {0xc24, 0x00000000}, {0xc28, 0x00000000}, 392 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44}, 393 {0xc34, 0x469652cf}, {0xc38, 0x49795994}, 394 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f}, 395 {0xc44, 0x000100b7}, {0xc48, 0xec020107}, 396 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e}, 397 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f}, 398 {0xc5c, 0x433c0094}, {0xc60, 0x00000000}, 399 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff}, 400 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d}, 401 {0xc74, 0x018610db}, {0xc78, 0x0000001f}, 402 {0xc7c, 0x00b91612}, {0xc80, 0x24000090}, 403 {0xc84, 0x20f60000}, {0xc88, 0x24000090}, 404 {0xc8c, 0x20200000}, {0xc90, 0x00121820}, 405 {0xc94, 0x00000000}, {0xc98, 0x00121820}, 406 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000}, 407 {0xca4, 0x00000080}, {0xca8, 0x00000000}, 408 {0xcac, 0x00000000}, {0xcb0, 0x00000000}, 409 {0xcb4, 0x00000000}, {0xcb8, 0x00000000}, 410 {0xcbc, 0x28000000}, {0xcc0, 0x00000000}, 411 {0xcc4, 0x00000000}, {0xcc8, 0x00000000}, 412 {0xccc, 0x00000000}, {0xcd0, 0x00000000}, 413 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427}, 414 {0xcdc, 0x00766932}, {0xce0, 0x00222222}, 415 {0xce4, 0x00000000}, {0xce8, 0x37644302}, 416 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740}, 417 {0xd04, 0x00020401}, {0xd08, 0x0000907f}, 418 {0xd0c, 0x20010201}, {0xd10, 0xa0633333}, 419 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b}, 420 {0xd2c, 0xcc979975}, {0xd30, 0x00000000}, 421 {0xd34, 0x80608000}, {0xd38, 0x00000000}, 422 {0xd3c, 0x00027293}, {0xd40, 0x00000000}, 423 {0xd44, 0x00000000}, {0xd48, 0x00000000}, 424 {0xd4c, 0x00000000}, {0xd50, 0x6437140a}, 425 {0xd54, 0x00000000}, {0xd58, 0x00000000}, 426 {0xd5c, 0x30032064}, {0xd60, 0x4653de68}, 427 {0xd64, 0x04518a3c}, {0xd68, 0x00002101}, 428 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e}, 429 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24}, 430 {0xe00, 0x24242424}, {0xe04, 0x24242424}, 431 {0xe08, 0x03902024}, {0xe10, 0x24242424}, 432 {0xe14, 0x24242424}, {0xe18, 0x24242424}, 433 {0xe1c, 0x24242424}, {0xe28, 0x00000000}, 434 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f}, 435 {0xe38, 0x02140102}, {0xe3c, 0x681604c2}, 436 {0xe40, 0x01007c00}, {0xe44, 0x01004800}, 437 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1}, 438 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f}, 439 {0xe58, 0x02140102}, {0xe5c, 0x28160d05}, 440 {0xe60, 0x00000008}, {0xe68, 0x001b25a4}, 441 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0}, 442 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0}, 443 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0}, 444 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0}, 445 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0}, 446 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0}, 447 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0}, 448 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448}, 449 {0xf14, 0x00000003}, {0xf4c, 0x00000000}, 450 {0xf00, 0x00000300}, 451 {0xffff, 0xffffffff}, 452 }; 453 454 static const struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = { 455 {0xc78, 0x7b000001}, {0xc78, 0x7b010001}, 456 {0xc78, 0x7b020001}, {0xc78, 0x7b030001}, 457 {0xc78, 0x7b040001}, {0xc78, 0x7b050001}, 458 {0xc78, 0x7a060001}, {0xc78, 0x79070001}, 459 {0xc78, 0x78080001}, {0xc78, 0x77090001}, 460 {0xc78, 0x760a0001}, {0xc78, 0x750b0001}, 461 {0xc78, 0x740c0001}, {0xc78, 0x730d0001}, 462 {0xc78, 0x720e0001}, {0xc78, 0x710f0001}, 463 {0xc78, 0x70100001}, {0xc78, 0x6f110001}, 464 {0xc78, 0x6e120001}, {0xc78, 0x6d130001}, 465 {0xc78, 0x6c140001}, {0xc78, 0x6b150001}, 466 {0xc78, 0x6a160001}, {0xc78, 0x69170001}, 467 {0xc78, 0x68180001}, {0xc78, 0x67190001}, 468 {0xc78, 0x661a0001}, {0xc78, 0x651b0001}, 469 {0xc78, 0x641c0001}, {0xc78, 0x631d0001}, 470 {0xc78, 0x621e0001}, {0xc78, 0x611f0001}, 471 {0xc78, 0x60200001}, {0xc78, 0x49210001}, 472 {0xc78, 0x48220001}, {0xc78, 0x47230001}, 473 {0xc78, 0x46240001}, {0xc78, 0x45250001}, 474 {0xc78, 0x44260001}, {0xc78, 0x43270001}, 475 {0xc78, 0x42280001}, {0xc78, 0x41290001}, 476 {0xc78, 0x402a0001}, {0xc78, 0x262b0001}, 477 {0xc78, 0x252c0001}, {0xc78, 0x242d0001}, 478 {0xc78, 0x232e0001}, {0xc78, 0x222f0001}, 479 {0xc78, 0x21300001}, {0xc78, 0x20310001}, 480 {0xc78, 0x06320001}, {0xc78, 0x05330001}, 481 {0xc78, 0x04340001}, {0xc78, 0x03350001}, 482 {0xc78, 0x02360001}, {0xc78, 0x01370001}, 483 {0xc78, 0x00380001}, {0xc78, 0x00390001}, 484 {0xc78, 0x003a0001}, {0xc78, 0x003b0001}, 485 {0xc78, 0x003c0001}, {0xc78, 0x003d0001}, 486 {0xc78, 0x003e0001}, {0xc78, 0x003f0001}, 487 {0xc78, 0x7b400001}, {0xc78, 0x7b410001}, 488 {0xc78, 0x7b420001}, {0xc78, 0x7b430001}, 489 {0xc78, 0x7b440001}, {0xc78, 0x7b450001}, 490 {0xc78, 0x7a460001}, {0xc78, 0x79470001}, 491 {0xc78, 0x78480001}, {0xc78, 0x77490001}, 492 {0xc78, 0x764a0001}, {0xc78, 0x754b0001}, 493 {0xc78, 0x744c0001}, {0xc78, 0x734d0001}, 494 {0xc78, 0x724e0001}, {0xc78, 0x714f0001}, 495 {0xc78, 0x70500001}, {0xc78, 0x6f510001}, 496 {0xc78, 0x6e520001}, {0xc78, 0x6d530001}, 497 {0xc78, 0x6c540001}, {0xc78, 0x6b550001}, 498 {0xc78, 0x6a560001}, {0xc78, 0x69570001}, 499 {0xc78, 0x68580001}, {0xc78, 0x67590001}, 500 {0xc78, 0x665a0001}, {0xc78, 0x655b0001}, 501 {0xc78, 0x645c0001}, {0xc78, 0x635d0001}, 502 {0xc78, 0x625e0001}, {0xc78, 0x615f0001}, 503 {0xc78, 0x60600001}, {0xc78, 0x49610001}, 504 {0xc78, 0x48620001}, {0xc78, 0x47630001}, 505 {0xc78, 0x46640001}, {0xc78, 0x45650001}, 506 {0xc78, 0x44660001}, {0xc78, 0x43670001}, 507 {0xc78, 0x42680001}, {0xc78, 0x41690001}, 508 {0xc78, 0x406a0001}, {0xc78, 0x266b0001}, 509 {0xc78, 0x256c0001}, {0xc78, 0x246d0001}, 510 {0xc78, 0x236e0001}, {0xc78, 0x226f0001}, 511 {0xc78, 0x21700001}, {0xc78, 0x20710001}, 512 {0xc78, 0x06720001}, {0xc78, 0x05730001}, 513 {0xc78, 0x04740001}, {0xc78, 0x03750001}, 514 {0xc78, 0x02760001}, {0xc78, 0x01770001}, 515 {0xc78, 0x00780001}, {0xc78, 0x00790001}, 516 {0xc78, 0x007a0001}, {0xc78, 0x007b0001}, 517 {0xc78, 0x007c0001}, {0xc78, 0x007d0001}, 518 {0xc78, 0x007e0001}, {0xc78, 0x007f0001}, 519 {0xc78, 0x3800001e}, {0xc78, 0x3801001e}, 520 {0xc78, 0x3802001e}, {0xc78, 0x3803001e}, 521 {0xc78, 0x3804001e}, {0xc78, 0x3805001e}, 522 {0xc78, 0x3806001e}, {0xc78, 0x3807001e}, 523 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e}, 524 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e}, 525 {0xc78, 0x440c001e}, {0xc78, 0x480d001e}, 526 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e}, 527 {0xc78, 0x5210001e}, {0xc78, 0x5611001e}, 528 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e}, 529 {0xc78, 0x6014001e}, {0xc78, 0x6015001e}, 530 {0xc78, 0x6016001e}, {0xc78, 0x6217001e}, 531 {0xc78, 0x6218001e}, {0xc78, 0x6219001e}, 532 {0xc78, 0x621a001e}, {0xc78, 0x621b001e}, 533 {0xc78, 0x621c001e}, {0xc78, 0x621d001e}, 534 {0xc78, 0x621e001e}, {0xc78, 0x621f001e}, 535 {0xffff, 0xffffffff} 536 }; 537 538 static const struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = { 539 {0xc78, 0x7b000001}, {0xc78, 0x7b010001}, 540 {0xc78, 0x7b020001}, {0xc78, 0x7b030001}, 541 {0xc78, 0x7b040001}, {0xc78, 0x7b050001}, 542 {0xc78, 0x7b060001}, {0xc78, 0x7b070001}, 543 {0xc78, 0x7b080001}, {0xc78, 0x7a090001}, 544 {0xc78, 0x790a0001}, {0xc78, 0x780b0001}, 545 {0xc78, 0x770c0001}, {0xc78, 0x760d0001}, 546 {0xc78, 0x750e0001}, {0xc78, 0x740f0001}, 547 {0xc78, 0x73100001}, {0xc78, 0x72110001}, 548 {0xc78, 0x71120001}, {0xc78, 0x70130001}, 549 {0xc78, 0x6f140001}, {0xc78, 0x6e150001}, 550 {0xc78, 0x6d160001}, {0xc78, 0x6c170001}, 551 {0xc78, 0x6b180001}, {0xc78, 0x6a190001}, 552 {0xc78, 0x691a0001}, {0xc78, 0x681b0001}, 553 {0xc78, 0x671c0001}, {0xc78, 0x661d0001}, 554 {0xc78, 0x651e0001}, {0xc78, 0x641f0001}, 555 {0xc78, 0x63200001}, {0xc78, 0x62210001}, 556 {0xc78, 0x61220001}, {0xc78, 0x60230001}, 557 {0xc78, 0x46240001}, {0xc78, 0x45250001}, 558 {0xc78, 0x44260001}, {0xc78, 0x43270001}, 559 {0xc78, 0x42280001}, {0xc78, 0x41290001}, 560 {0xc78, 0x402a0001}, {0xc78, 0x262b0001}, 561 {0xc78, 0x252c0001}, {0xc78, 0x242d0001}, 562 {0xc78, 0x232e0001}, {0xc78, 0x222f0001}, 563 {0xc78, 0x21300001}, {0xc78, 0x20310001}, 564 {0xc78, 0x06320001}, {0xc78, 0x05330001}, 565 {0xc78, 0x04340001}, {0xc78, 0x03350001}, 566 {0xc78, 0x02360001}, {0xc78, 0x01370001}, 567 {0xc78, 0x00380001}, {0xc78, 0x00390001}, 568 {0xc78, 0x003a0001}, {0xc78, 0x003b0001}, 569 {0xc78, 0x003c0001}, {0xc78, 0x003d0001}, 570 {0xc78, 0x003e0001}, {0xc78, 0x003f0001}, 571 {0xc78, 0x7b400001}, {0xc78, 0x7b410001}, 572 {0xc78, 0x7b420001}, {0xc78, 0x7b430001}, 573 {0xc78, 0x7b440001}, {0xc78, 0x7b450001}, 574 {0xc78, 0x7b460001}, {0xc78, 0x7b470001}, 575 {0xc78, 0x7b480001}, {0xc78, 0x7a490001}, 576 {0xc78, 0x794a0001}, {0xc78, 0x784b0001}, 577 {0xc78, 0x774c0001}, {0xc78, 0x764d0001}, 578 {0xc78, 0x754e0001}, {0xc78, 0x744f0001}, 579 {0xc78, 0x73500001}, {0xc78, 0x72510001}, 580 {0xc78, 0x71520001}, {0xc78, 0x70530001}, 581 {0xc78, 0x6f540001}, {0xc78, 0x6e550001}, 582 {0xc78, 0x6d560001}, {0xc78, 0x6c570001}, 583 {0xc78, 0x6b580001}, {0xc78, 0x6a590001}, 584 {0xc78, 0x695a0001}, {0xc78, 0x685b0001}, 585 {0xc78, 0x675c0001}, {0xc78, 0x665d0001}, 586 {0xc78, 0x655e0001}, {0xc78, 0x645f0001}, 587 {0xc78, 0x63600001}, {0xc78, 0x62610001}, 588 {0xc78, 0x61620001}, {0xc78, 0x60630001}, 589 {0xc78, 0x46640001}, {0xc78, 0x45650001}, 590 {0xc78, 0x44660001}, {0xc78, 0x43670001}, 591 {0xc78, 0x42680001}, {0xc78, 0x41690001}, 592 {0xc78, 0x406a0001}, {0xc78, 0x266b0001}, 593 {0xc78, 0x256c0001}, {0xc78, 0x246d0001}, 594 {0xc78, 0x236e0001}, {0xc78, 0x226f0001}, 595 {0xc78, 0x21700001}, {0xc78, 0x20710001}, 596 {0xc78, 0x06720001}, {0xc78, 0x05730001}, 597 {0xc78, 0x04740001}, {0xc78, 0x03750001}, 598 {0xc78, 0x02760001}, {0xc78, 0x01770001}, 599 {0xc78, 0x00780001}, {0xc78, 0x00790001}, 600 {0xc78, 0x007a0001}, {0xc78, 0x007b0001}, 601 {0xc78, 0x007c0001}, {0xc78, 0x007d0001}, 602 {0xc78, 0x007e0001}, {0xc78, 0x007f0001}, 603 {0xc78, 0x3800001e}, {0xc78, 0x3801001e}, 604 {0xc78, 0x3802001e}, {0xc78, 0x3803001e}, 605 {0xc78, 0x3804001e}, {0xc78, 0x3805001e}, 606 {0xc78, 0x3806001e}, {0xc78, 0x3807001e}, 607 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e}, 608 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e}, 609 {0xc78, 0x440c001e}, {0xc78, 0x480d001e}, 610 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e}, 611 {0xc78, 0x5210001e}, {0xc78, 0x5611001e}, 612 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e}, 613 {0xc78, 0x6014001e}, {0xc78, 0x6015001e}, 614 {0xc78, 0x6016001e}, {0xc78, 0x6217001e}, 615 {0xc78, 0x6218001e}, {0xc78, 0x6219001e}, 616 {0xc78, 0x621a001e}, {0xc78, 0x621b001e}, 617 {0xc78, 0x621c001e}, {0xc78, 0x621d001e}, 618 {0xc78, 0x621e001e}, {0xc78, 0x621f001e}, 619 {0xffff, 0xffffffff} 620 }; 621 622 static const struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = { 623 { /* RF_A */ 624 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1, 625 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2, 626 .lssiparm = REG_FPGA0_XA_LSSI_PARM, 627 .hspiread = REG_HSPI_XA_READBACK, 628 .lssiread = REG_FPGA0_XA_LSSI_READBACK, 629 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL, 630 }, 631 { /* RF_B */ 632 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1, 633 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2, 634 .lssiparm = REG_FPGA0_XB_LSSI_PARM, 635 .hspiread = REG_HSPI_XB_READBACK, 636 .lssiread = REG_FPGA0_XB_LSSI_READBACK, 637 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL, 638 }, 639 }; 640 641 const u32 rtl8xxxu_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = { 642 REG_OFDM0_XA_RX_IQ_IMBALANCE, 643 REG_OFDM0_XB_RX_IQ_IMBALANCE, 644 REG_OFDM0_ENERGY_CCA_THRES, 645 REG_OFDM0_AGCR_SSI_TABLE, 646 REG_OFDM0_XA_TX_IQ_IMBALANCE, 647 REG_OFDM0_XB_TX_IQ_IMBALANCE, 648 REG_OFDM0_XC_TX_AFE, 649 REG_OFDM0_XD_TX_AFE, 650 REG_OFDM0_RX_IQ_EXT_ANTA 651 }; 652 653 u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr) 654 { 655 struct usb_device *udev = priv->udev; 656 int len; 657 u8 data; 658 659 if (priv->rtl_chip == RTL8710B && addr <= 0xff) 660 addr |= 0x8000; 661 662 mutex_lock(&priv->usb_buf_mutex); 663 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 664 REALTEK_USB_CMD_REQ, REALTEK_USB_READ, 665 addr, 0, &priv->usb_buf.val8, sizeof(u8), 666 RTW_USB_CONTROL_MSG_TIMEOUT); 667 data = priv->usb_buf.val8; 668 mutex_unlock(&priv->usb_buf_mutex); 669 670 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) 671 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n", 672 __func__, addr, data, len); 673 return data; 674 } 675 676 u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr) 677 { 678 struct usb_device *udev = priv->udev; 679 int len; 680 u16 data; 681 682 if (priv->rtl_chip == RTL8710B && addr <= 0xff) 683 addr |= 0x8000; 684 685 mutex_lock(&priv->usb_buf_mutex); 686 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 687 REALTEK_USB_CMD_REQ, REALTEK_USB_READ, 688 addr, 0, &priv->usb_buf.val16, sizeof(u16), 689 RTW_USB_CONTROL_MSG_TIMEOUT); 690 data = le16_to_cpu(priv->usb_buf.val16); 691 mutex_unlock(&priv->usb_buf_mutex); 692 693 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) 694 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n", 695 __func__, addr, data, len); 696 return data; 697 } 698 699 u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr) 700 { 701 struct usb_device *udev = priv->udev; 702 int len; 703 u32 data; 704 705 if (priv->rtl_chip == RTL8710B && addr <= 0xff) 706 addr |= 0x8000; 707 708 mutex_lock(&priv->usb_buf_mutex); 709 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 710 REALTEK_USB_CMD_REQ, REALTEK_USB_READ, 711 addr, 0, &priv->usb_buf.val32, sizeof(u32), 712 RTW_USB_CONTROL_MSG_TIMEOUT); 713 data = le32_to_cpu(priv->usb_buf.val32); 714 mutex_unlock(&priv->usb_buf_mutex); 715 716 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) 717 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n", 718 __func__, addr, data, len); 719 return data; 720 } 721 722 int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val) 723 { 724 struct usb_device *udev = priv->udev; 725 int ret; 726 727 if (priv->rtl_chip == RTL8710B && addr <= 0xff) 728 addr |= 0x8000; 729 730 mutex_lock(&priv->usb_buf_mutex); 731 priv->usb_buf.val8 = val; 732 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 733 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 734 addr, 0, &priv->usb_buf.val8, sizeof(u8), 735 RTW_USB_CONTROL_MSG_TIMEOUT); 736 737 mutex_unlock(&priv->usb_buf_mutex); 738 739 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) 740 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n", 741 __func__, addr, val); 742 return ret; 743 } 744 745 int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val) 746 { 747 struct usb_device *udev = priv->udev; 748 int ret; 749 750 if (priv->rtl_chip == RTL8710B && addr <= 0xff) 751 addr |= 0x8000; 752 753 mutex_lock(&priv->usb_buf_mutex); 754 priv->usb_buf.val16 = cpu_to_le16(val); 755 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 756 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 757 addr, 0, &priv->usb_buf.val16, sizeof(u16), 758 RTW_USB_CONTROL_MSG_TIMEOUT); 759 mutex_unlock(&priv->usb_buf_mutex); 760 761 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) 762 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n", 763 __func__, addr, val); 764 return ret; 765 } 766 767 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val) 768 { 769 struct usb_device *udev = priv->udev; 770 int ret; 771 772 if (priv->rtl_chip == RTL8710B && addr <= 0xff) 773 addr |= 0x8000; 774 775 mutex_lock(&priv->usb_buf_mutex); 776 priv->usb_buf.val32 = cpu_to_le32(val); 777 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 778 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 779 addr, 0, &priv->usb_buf.val32, sizeof(u32), 780 RTW_USB_CONTROL_MSG_TIMEOUT); 781 mutex_unlock(&priv->usb_buf_mutex); 782 783 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) 784 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n", 785 __func__, addr, val); 786 return ret; 787 } 788 789 int rtl8xxxu_write8_set(struct rtl8xxxu_priv *priv, u16 addr, u8 bits) 790 { 791 u8 val8; 792 793 val8 = rtl8xxxu_read8(priv, addr); 794 val8 |= bits; 795 return rtl8xxxu_write8(priv, addr, val8); 796 } 797 798 int rtl8xxxu_write8_clear(struct rtl8xxxu_priv *priv, u16 addr, u8 bits) 799 { 800 u8 val8; 801 802 val8 = rtl8xxxu_read8(priv, addr); 803 val8 &= ~bits; 804 return rtl8xxxu_write8(priv, addr, val8); 805 } 806 807 int rtl8xxxu_write16_set(struct rtl8xxxu_priv *priv, u16 addr, u16 bits) 808 { 809 u16 val16; 810 811 val16 = rtl8xxxu_read16(priv, addr); 812 val16 |= bits; 813 return rtl8xxxu_write16(priv, addr, val16); 814 } 815 816 int rtl8xxxu_write16_clear(struct rtl8xxxu_priv *priv, u16 addr, u16 bits) 817 { 818 u16 val16; 819 820 val16 = rtl8xxxu_read16(priv, addr); 821 val16 &= ~bits; 822 return rtl8xxxu_write16(priv, addr, val16); 823 } 824 825 int rtl8xxxu_write32_set(struct rtl8xxxu_priv *priv, u16 addr, u32 bits) 826 { 827 u32 val32; 828 829 val32 = rtl8xxxu_read32(priv, addr); 830 val32 |= bits; 831 return rtl8xxxu_write32(priv, addr, val32); 832 } 833 834 int rtl8xxxu_write32_clear(struct rtl8xxxu_priv *priv, u16 addr, u32 bits) 835 { 836 u32 val32; 837 838 val32 = rtl8xxxu_read32(priv, addr); 839 val32 &= ~bits; 840 return rtl8xxxu_write32(priv, addr, val32); 841 } 842 843 int rtl8xxxu_write32_mask(struct rtl8xxxu_priv *priv, u16 addr, 844 u32 mask, u32 val) 845 { 846 u32 orig, new, shift; 847 848 shift = __ffs(mask); 849 850 orig = rtl8xxxu_read32(priv, addr); 851 new = (orig & ~mask) | ((val << shift) & mask); 852 return rtl8xxxu_write32(priv, addr, new); 853 } 854 855 int rtl8xxxu_write_rfreg_mask(struct rtl8xxxu_priv *priv, 856 enum rtl8xxxu_rfpath path, u8 reg, 857 u32 mask, u32 val) 858 { 859 u32 orig, new, shift; 860 861 shift = __ffs(mask); 862 863 orig = rtl8xxxu_read_rfreg(priv, path, reg); 864 new = (orig & ~mask) | ((val << shift) & mask); 865 return rtl8xxxu_write_rfreg(priv, path, reg, new); 866 } 867 868 static int 869 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len) 870 { 871 struct usb_device *udev = priv->udev; 872 int blocksize = priv->fops->writeN_block_size; 873 int ret, i, count, remainder; 874 875 count = len / blocksize; 876 remainder = len % blocksize; 877 878 for (i = 0; i < count; i++) { 879 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 880 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 881 addr, 0, buf, blocksize, 882 RTW_USB_CONTROL_MSG_TIMEOUT); 883 if (ret != blocksize) 884 goto write_error; 885 886 addr += blocksize; 887 buf += blocksize; 888 } 889 890 if (remainder) { 891 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 892 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 893 addr, 0, buf, remainder, 894 RTW_USB_CONTROL_MSG_TIMEOUT); 895 if (ret != remainder) 896 goto write_error; 897 } 898 899 return len; 900 901 write_error: 902 dev_info(&udev->dev, 903 "%s: Failed to write block at addr: %04x size: %04x\n", 904 __func__, addr, blocksize); 905 return -EAGAIN; 906 } 907 908 u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv, 909 enum rtl8xxxu_rfpath path, u8 reg) 910 { 911 u32 hssia, val32, retval; 912 913 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2); 914 if (path != RF_A) 915 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2); 916 else 917 val32 = hssia; 918 919 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK; 920 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT); 921 val32 |= FPGA0_HSSI_PARM2_EDGE_READ; 922 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ; 923 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); 924 925 udelay(10); 926 927 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32); 928 udelay(100); 929 930 hssia |= FPGA0_HSSI_PARM2_EDGE_READ; 931 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); 932 udelay(10); 933 934 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1); 935 if (val32 & FPGA0_HSSI_PARM1_PI) 936 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread); 937 else 938 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread); 939 940 retval &= 0xfffff; 941 942 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ) 943 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n", 944 __func__, reg, retval); 945 return retval; 946 } 947 948 /* 949 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can 950 * have write issues in high temperature conditions. We may have to 951 * retry writing them. 952 */ 953 int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv, 954 enum rtl8xxxu_rfpath path, u8 reg, u32 data) 955 { 956 int ret, retval; 957 u32 dataaddr, val32; 958 959 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE) 960 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n", 961 __func__, reg, data); 962 963 data &= FPGA0_LSSI_PARM_DATA_MASK; 964 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data; 965 966 if (priv->rtl_chip == RTL8192E) { 967 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 968 val32 &= ~0x20000; 969 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 970 } 971 972 /* Use XB for path B */ 973 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr); 974 if (ret != sizeof(dataaddr)) 975 retval = -EIO; 976 else 977 retval = 0; 978 979 udelay(1); 980 981 if (priv->rtl_chip == RTL8192E) { 982 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 983 val32 |= 0x20000; 984 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 985 } 986 987 return retval; 988 } 989 990 static int 991 rtl8xxxu_gen1_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len) 992 { 993 struct device *dev = &priv->udev->dev; 994 int mbox_nr, retry, retval = 0; 995 int mbox_reg, mbox_ext_reg; 996 u8 val8; 997 998 mutex_lock(&priv->h2c_mutex); 999 1000 mbox_nr = priv->next_mbox; 1001 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4); 1002 mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2); 1003 1004 /* 1005 * MBOX ready? 1006 */ 1007 retry = 100; 1008 do { 1009 val8 = rtl8xxxu_read8(priv, REG_HMTFR); 1010 if (!(val8 & BIT(mbox_nr))) 1011 break; 1012 } while (retry--); 1013 1014 if (!retry) { 1015 dev_info(dev, "%s: Mailbox busy\n", __func__); 1016 retval = -EBUSY; 1017 goto error; 1018 } 1019 1020 /* 1021 * Need to swap as it's being swapped again by rtl8xxxu_write16/32() 1022 */ 1023 if (len > sizeof(u32)) { 1024 rtl8xxxu_write16(priv, mbox_ext_reg, le16_to_cpu(h2c->raw.ext)); 1025 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 1026 dev_info(dev, "H2C_EXT %04x\n", 1027 le16_to_cpu(h2c->raw.ext)); 1028 } 1029 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data)); 1030 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 1031 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data)); 1032 1033 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX; 1034 1035 error: 1036 mutex_unlock(&priv->h2c_mutex); 1037 return retval; 1038 } 1039 1040 int 1041 rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len) 1042 { 1043 struct device *dev = &priv->udev->dev; 1044 int mbox_nr, retry, retval = 0; 1045 int mbox_reg, mbox_ext_reg; 1046 u8 val8; 1047 1048 mutex_lock(&priv->h2c_mutex); 1049 1050 mbox_nr = priv->next_mbox; 1051 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4); 1052 mbox_ext_reg = REG_HMBOX_EXT0_8723B + (mbox_nr * 4); 1053 1054 /* 1055 * MBOX ready? 1056 */ 1057 retry = 100; 1058 do { 1059 val8 = rtl8xxxu_read8(priv, REG_HMTFR); 1060 if (!(val8 & BIT(mbox_nr))) 1061 break; 1062 } while (retry--); 1063 1064 if (!retry) { 1065 dev_info(dev, "%s: Mailbox busy\n", __func__); 1066 retval = -EBUSY; 1067 goto error; 1068 } 1069 1070 /* 1071 * Need to swap as it's being swapped again by rtl8xxxu_write16/32() 1072 */ 1073 if (len > sizeof(u32)) { 1074 rtl8xxxu_write32(priv, mbox_ext_reg, 1075 le32_to_cpu(h2c->raw_wide.ext)); 1076 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 1077 dev_info(dev, "H2C_EXT %08x\n", 1078 le32_to_cpu(h2c->raw_wide.ext)); 1079 } 1080 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data)); 1081 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 1082 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data)); 1083 1084 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX; 1085 1086 error: 1087 mutex_unlock(&priv->h2c_mutex); 1088 return retval; 1089 } 1090 1091 void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv) 1092 { 1093 u8 val8; 1094 u32 val32; 1095 1096 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL); 1097 val8 |= BIT(0) | BIT(3); 1098 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8); 1099 1100 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); 1101 val32 &= ~(BIT(4) | BIT(5)); 1102 val32 |= BIT(3); 1103 if (priv->rf_paths == 2) { 1104 val32 &= ~(BIT(20) | BIT(21)); 1105 val32 |= BIT(19); 1106 } 1107 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); 1108 1109 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1110 val32 &= ~OFDM_RF_PATH_TX_MASK; 1111 if (priv->tx_paths == 2) 1112 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B; 1113 else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C) 1114 val32 |= OFDM_RF_PATH_TX_B; 1115 else 1116 val32 |= OFDM_RF_PATH_TX_A; 1117 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1118 1119 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1120 val32 &= ~FPGA_RF_MODE_JAPAN; 1121 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1122 1123 if (priv->rf_paths == 2) 1124 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0); 1125 else 1126 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0); 1127 1128 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95); 1129 if (priv->rf_paths == 2) 1130 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95); 1131 1132 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); 1133 } 1134 1135 void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv) 1136 { 1137 u8 sps0; 1138 u32 val32; 1139 1140 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL); 1141 1142 /* RF RX code for preamble power saving */ 1143 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); 1144 val32 &= ~(BIT(3) | BIT(4) | BIT(5)); 1145 if (priv->rf_paths == 2) 1146 val32 &= ~(BIT(19) | BIT(20) | BIT(21)); 1147 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); 1148 1149 /* Disable TX for four paths */ 1150 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1151 val32 &= ~OFDM_RF_PATH_TX_MASK; 1152 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1153 1154 /* Enable power saving */ 1155 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1156 val32 |= FPGA_RF_MODE_JAPAN; 1157 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1158 1159 /* AFE control register to power down bits [30:22] */ 1160 if (priv->rf_paths == 2) 1161 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0); 1162 else 1163 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0); 1164 1165 /* Power down RF module */ 1166 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); 1167 if (priv->rf_paths == 2) 1168 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0); 1169 1170 sps0 &= ~(BIT(0) | BIT(3)); 1171 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0); 1172 } 1173 1174 static void rtl8xxxu_stop_tx_beacon(struct rtl8xxxu_priv *priv) 1175 { 1176 u8 val8; 1177 1178 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2); 1179 val8 &= ~BIT(6); 1180 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8); 1181 1182 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64); 1183 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2); 1184 val8 &= ~BIT(0); 1185 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8); 1186 } 1187 1188 1189 /* 1190 * The rtl8723a has 3 channel groups for it's efuse settings. It only 1191 * supports the 2.4GHz band, so channels 1 - 14: 1192 * group 0: channels 1 - 3 1193 * group 1: channels 4 - 9 1194 * group 2: channels 10 - 14 1195 * 1196 * Note: We index from 0 in the code 1197 */ 1198 static int rtl8xxxu_gen1_channel_to_group(int channel) 1199 { 1200 int group; 1201 1202 if (channel < 4) 1203 group = 0; 1204 else if (channel < 10) 1205 group = 1; 1206 else 1207 group = 2; 1208 1209 return group; 1210 } 1211 1212 /* 1213 * Valid for rtl8723bu and rtl8192eu 1214 */ 1215 int rtl8xxxu_gen2_channel_to_group(int channel) 1216 { 1217 int group; 1218 1219 if (channel < 3) 1220 group = 0; 1221 else if (channel < 6) 1222 group = 1; 1223 else if (channel < 9) 1224 group = 2; 1225 else if (channel < 12) 1226 group = 3; 1227 else 1228 group = 4; 1229 1230 return group; 1231 } 1232 1233 void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw) 1234 { 1235 struct rtl8xxxu_priv *priv = hw->priv; 1236 u32 val32, rsr; 1237 u8 val8, opmode; 1238 bool ht = true; 1239 int sec_ch_above, channel; 1240 int i; 1241 1242 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE); 1243 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 1244 channel = hw->conf.chandef.chan->hw_value; 1245 1246 switch (hw->conf.chandef.width) { 1247 case NL80211_CHAN_WIDTH_20_NOHT: 1248 ht = false; 1249 fallthrough; 1250 case NL80211_CHAN_WIDTH_20: 1251 opmode |= BW_OPMODE_20MHZ; 1252 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); 1253 1254 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1255 val32 &= ~FPGA_RF_MODE; 1256 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1257 1258 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1259 val32 &= ~FPGA_RF_MODE; 1260 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1261 1262 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); 1263 val32 |= FPGA0_ANALOG2_20MHZ; 1264 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); 1265 break; 1266 case NL80211_CHAN_WIDTH_40: 1267 if (hw->conf.chandef.center_freq1 > 1268 hw->conf.chandef.chan->center_freq) { 1269 sec_ch_above = 1; 1270 channel += 2; 1271 } else { 1272 sec_ch_above = 0; 1273 channel -= 2; 1274 } 1275 1276 opmode &= ~BW_OPMODE_20MHZ; 1277 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); 1278 rsr &= ~RSR_RSC_BANDWIDTH_40M; 1279 if (sec_ch_above) 1280 rsr |= RSR_RSC_UPPER_SUB_CHANNEL; 1281 else 1282 rsr |= RSR_RSC_LOWER_SUB_CHANNEL; 1283 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr); 1284 1285 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1286 val32 |= FPGA_RF_MODE; 1287 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1288 1289 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1290 val32 |= FPGA_RF_MODE; 1291 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1292 1293 /* 1294 * Set Control channel to upper or lower. These settings 1295 * are required only for 40MHz 1296 */ 1297 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); 1298 val32 &= ~CCK0_SIDEBAND; 1299 if (!sec_ch_above) 1300 val32 |= CCK0_SIDEBAND; 1301 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); 1302 1303 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 1304 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ 1305 if (sec_ch_above) 1306 val32 |= OFDM_LSTF_PRIME_CH_LOW; 1307 else 1308 val32 |= OFDM_LSTF_PRIME_CH_HIGH; 1309 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 1310 1311 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); 1312 val32 &= ~FPGA0_ANALOG2_20MHZ; 1313 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); 1314 1315 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 1316 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); 1317 if (sec_ch_above) 1318 val32 |= FPGA0_PS_UPPER_CHANNEL; 1319 else 1320 val32 |= FPGA0_PS_LOWER_CHANNEL; 1321 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 1322 break; 1323 1324 default: 1325 break; 1326 } 1327 1328 for (i = RF_A; i < priv->rf_paths; i++) { 1329 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1330 val32 &= ~MODE_AG_CHANNEL_MASK; 1331 val32 |= channel; 1332 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1333 } 1334 1335 if (ht) 1336 val8 = 0x0e; 1337 else 1338 val8 = 0x0a; 1339 1340 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8); 1341 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8); 1342 1343 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808); 1344 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a); 1345 1346 for (i = RF_A; i < priv->rf_paths; i++) { 1347 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1348 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) 1349 val32 &= ~MODE_AG_CHANNEL_20MHZ; 1350 else 1351 val32 |= MODE_AG_CHANNEL_20MHZ; 1352 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1353 } 1354 } 1355 1356 void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw) 1357 { 1358 struct rtl8xxxu_priv *priv = hw->priv; 1359 u32 val32; 1360 u8 val8, subchannel; 1361 u16 rf_mode_bw; 1362 bool ht = true; 1363 int sec_ch_above, channel; 1364 int i; 1365 1366 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL); 1367 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK; 1368 channel = hw->conf.chandef.chan->hw_value; 1369 1370 /* Hack */ 1371 subchannel = 0; 1372 1373 switch (hw->conf.chandef.width) { 1374 case NL80211_CHAN_WIDTH_20_NOHT: 1375 ht = false; 1376 fallthrough; 1377 case NL80211_CHAN_WIDTH_20: 1378 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20; 1379 subchannel = 0; 1380 1381 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1382 val32 &= ~FPGA_RF_MODE; 1383 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1384 1385 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1386 val32 &= ~FPGA_RF_MODE; 1387 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1388 1389 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); 1390 val32 &= ~(BIT(30) | BIT(31)); 1391 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); 1392 1393 break; 1394 case NL80211_CHAN_WIDTH_40: 1395 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40; 1396 1397 if (hw->conf.chandef.center_freq1 > 1398 hw->conf.chandef.chan->center_freq) { 1399 sec_ch_above = 1; 1400 channel += 2; 1401 } else { 1402 sec_ch_above = 0; 1403 channel -= 2; 1404 } 1405 1406 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1407 val32 |= FPGA_RF_MODE; 1408 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1409 1410 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1411 val32 |= FPGA_RF_MODE; 1412 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1413 1414 /* 1415 * Set Control channel to upper or lower. These settings 1416 * are required only for 40MHz 1417 */ 1418 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); 1419 val32 &= ~CCK0_SIDEBAND; 1420 if (!sec_ch_above) 1421 val32 |= CCK0_SIDEBAND; 1422 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); 1423 1424 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 1425 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ 1426 if (sec_ch_above) 1427 val32 |= OFDM_LSTF_PRIME_CH_LOW; 1428 else 1429 val32 |= OFDM_LSTF_PRIME_CH_HIGH; 1430 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 1431 1432 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 1433 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); 1434 if (sec_ch_above) 1435 val32 |= FPGA0_PS_UPPER_CHANNEL; 1436 else 1437 val32 |= FPGA0_PS_LOWER_CHANNEL; 1438 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 1439 break; 1440 case NL80211_CHAN_WIDTH_80: 1441 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80; 1442 break; 1443 default: 1444 break; 1445 } 1446 1447 for (i = RF_A; i < priv->rf_paths; i++) { 1448 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1449 val32 &= ~MODE_AG_CHANNEL_MASK; 1450 val32 |= channel; 1451 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1452 } 1453 1454 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw); 1455 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel); 1456 1457 if (ht) 1458 val8 = 0x0e; 1459 else 1460 val8 = 0x0a; 1461 1462 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8); 1463 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8); 1464 1465 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808); 1466 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a); 1467 1468 for (i = RF_A; i < priv->rf_paths; i++) { 1469 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1470 val32 &= ~MODE_AG_BW_MASK; 1471 switch(hw->conf.chandef.width) { 1472 case NL80211_CHAN_WIDTH_80: 1473 val32 |= MODE_AG_BW_80MHZ_8723B; 1474 break; 1475 case NL80211_CHAN_WIDTH_40: 1476 val32 |= MODE_AG_BW_40MHZ_8723B; 1477 break; 1478 default: 1479 val32 |= MODE_AG_BW_20MHZ_8723B; 1480 break; 1481 } 1482 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1483 } 1484 } 1485 1486 void 1487 rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) 1488 { 1489 struct rtl8xxxu_power_base *power_base = priv->power_base; 1490 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS]; 1491 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS]; 1492 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b; 1493 u8 val8; 1494 int group, i; 1495 1496 group = rtl8xxxu_gen1_channel_to_group(channel); 1497 1498 cck[0] = priv->cck_tx_power_index_A[group] - 1; 1499 cck[1] = priv->cck_tx_power_index_B[group] - 1; 1500 1501 if (priv->hi_pa) { 1502 if (cck[0] > 0x20) 1503 cck[0] = 0x20; 1504 if (cck[1] > 0x20) 1505 cck[1] = 0x20; 1506 } 1507 1508 ofdm[0] = priv->ht40_1s_tx_power_index_A[group]; 1509 ofdm[1] = priv->ht40_1s_tx_power_index_B[group]; 1510 if (ofdm[0]) 1511 ofdm[0] -= 1; 1512 if (ofdm[1]) 1513 ofdm[1] -= 1; 1514 1515 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a; 1516 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b; 1517 1518 mcsbase[0] = ofdm[0]; 1519 mcsbase[1] = ofdm[1]; 1520 if (!ht40) { 1521 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a; 1522 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b; 1523 } 1524 1525 if (priv->tx_paths > 1) { 1526 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a) 1527 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a; 1528 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b) 1529 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b; 1530 } 1531 1532 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL) 1533 dev_info(&priv->udev->dev, 1534 "%s: Setting TX power CCK A: %02x, " 1535 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n", 1536 __func__, cck[0], cck[1], ofdm[0], ofdm[1]); 1537 1538 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) { 1539 if (cck[i] > RF6052_MAX_TX_PWR) 1540 cck[i] = RF6052_MAX_TX_PWR; 1541 if (ofdm[i] > RF6052_MAX_TX_PWR) 1542 ofdm[i] = RF6052_MAX_TX_PWR; 1543 } 1544 1545 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); 1546 val32 &= 0xffff00ff; 1547 val32 |= (cck[0] << 8); 1548 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); 1549 1550 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); 1551 val32 &= 0xff; 1552 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24)); 1553 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); 1554 1555 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); 1556 val32 &= 0xffffff00; 1557 val32 |= cck[1]; 1558 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); 1559 1560 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32); 1561 val32 &= 0xff; 1562 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24)); 1563 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32); 1564 1565 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 | 1566 ofdmbase[0] << 16 | ofdmbase[0] << 24; 1567 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 | 1568 ofdmbase[1] << 16 | ofdmbase[1] << 24; 1569 1570 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, 1571 ofdm_a + power_base->reg_0e00); 1572 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, 1573 ofdm_b + power_base->reg_0830); 1574 1575 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, 1576 ofdm_a + power_base->reg_0e04); 1577 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, 1578 ofdm_b + power_base->reg_0834); 1579 1580 mcs_a = mcsbase[0] | mcsbase[0] << 8 | 1581 mcsbase[0] << 16 | mcsbase[0] << 24; 1582 mcs_b = mcsbase[1] | mcsbase[1] << 8 | 1583 mcsbase[1] << 16 | mcsbase[1] << 24; 1584 1585 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, 1586 mcs_a + power_base->reg_0e10); 1587 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, 1588 mcs_b + power_base->reg_083c); 1589 1590 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, 1591 mcs_a + power_base->reg_0e14); 1592 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, 1593 mcs_b + power_base->reg_0848); 1594 1595 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, 1596 mcs_a + power_base->reg_0e18); 1597 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, 1598 mcs_b + power_base->reg_084c); 1599 1600 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, 1601 mcs_a + power_base->reg_0e1c); 1602 for (i = 0; i < 3; i++) { 1603 if (i != 2) 1604 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0; 1605 else 1606 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0; 1607 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8); 1608 } 1609 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, 1610 mcs_b + power_base->reg_0868); 1611 for (i = 0; i < 3; i++) { 1612 if (i != 2) 1613 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0; 1614 else 1615 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0; 1616 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8); 1617 } 1618 } 1619 1620 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv, 1621 enum nl80211_iftype linktype) 1622 { 1623 u8 val8; 1624 1625 val8 = rtl8xxxu_read8(priv, REG_MSR); 1626 val8 &= ~MSR_LINKTYPE_MASK; 1627 1628 switch (linktype) { 1629 case NL80211_IFTYPE_UNSPECIFIED: 1630 val8 |= MSR_LINKTYPE_NONE; 1631 break; 1632 case NL80211_IFTYPE_ADHOC: 1633 val8 |= MSR_LINKTYPE_ADHOC; 1634 break; 1635 case NL80211_IFTYPE_STATION: 1636 val8 |= MSR_LINKTYPE_STATION; 1637 break; 1638 case NL80211_IFTYPE_AP: 1639 val8 |= MSR_LINKTYPE_AP; 1640 break; 1641 default: 1642 goto out; 1643 } 1644 1645 rtl8xxxu_write8(priv, REG_MSR, val8); 1646 out: 1647 return; 1648 } 1649 1650 static void 1651 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry) 1652 { 1653 u16 val16; 1654 1655 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) & 1656 RETRY_LIMIT_SHORT_MASK) | 1657 ((long_retry << RETRY_LIMIT_LONG_SHIFT) & 1658 RETRY_LIMIT_LONG_MASK); 1659 1660 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16); 1661 } 1662 1663 static void 1664 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm) 1665 { 1666 u16 val16; 1667 1668 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) | 1669 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK); 1670 1671 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16); 1672 } 1673 1674 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv) 1675 { 1676 struct device *dev = &priv->udev->dev; 1677 char cut = 'A' + priv->chip_cut; 1678 1679 dev_info(dev, 1680 "RTL%s rev %c (%s) romver %d, %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n", 1681 priv->chip_name, cut, priv->chip_vendor, priv->rom_rev, 1682 priv->tx_paths, priv->rx_paths, priv->ep_tx_count, 1683 priv->has_wifi, priv->has_bluetooth, priv->has_gps, 1684 priv->hi_pa); 1685 1686 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr); 1687 } 1688 1689 void rtl8xxxu_identify_vendor_1bit(struct rtl8xxxu_priv *priv, u32 vendor) 1690 { 1691 if (vendor) { 1692 strscpy(priv->chip_vendor, "UMC", sizeof(priv->chip_vendor)); 1693 priv->vendor_umc = 1; 1694 } else { 1695 strscpy(priv->chip_vendor, "TSMC", sizeof(priv->chip_vendor)); 1696 } 1697 } 1698 1699 void rtl8xxxu_identify_vendor_2bits(struct rtl8xxxu_priv *priv, u32 vendor) 1700 { 1701 switch (vendor) { 1702 case SYS_CFG_VENDOR_ID_TSMC: 1703 strscpy(priv->chip_vendor, "TSMC", sizeof(priv->chip_vendor)); 1704 break; 1705 case SYS_CFG_VENDOR_ID_SMIC: 1706 strscpy(priv->chip_vendor, "SMIC", sizeof(priv->chip_vendor)); 1707 priv->vendor_smic = 1; 1708 break; 1709 case SYS_CFG_VENDOR_ID_UMC: 1710 strscpy(priv->chip_vendor, "UMC", sizeof(priv->chip_vendor)); 1711 priv->vendor_umc = 1; 1712 break; 1713 default: 1714 strscpy(priv->chip_vendor, "unknown", sizeof(priv->chip_vendor)); 1715 } 1716 } 1717 1718 void rtl8xxxu_config_endpoints_sie(struct rtl8xxxu_priv *priv) 1719 { 1720 u16 val16; 1721 1722 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX); 1723 1724 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) { 1725 priv->ep_tx_high_queue = 1; 1726 priv->ep_tx_count++; 1727 } 1728 1729 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) { 1730 priv->ep_tx_normal_queue = 1; 1731 priv->ep_tx_count++; 1732 } 1733 1734 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) { 1735 priv->ep_tx_low_queue = 1; 1736 priv->ep_tx_count++; 1737 } 1738 } 1739 1740 int rtl8xxxu_config_endpoints_no_sie(struct rtl8xxxu_priv *priv) 1741 { 1742 struct device *dev = &priv->udev->dev; 1743 1744 switch (priv->nr_out_eps) { 1745 case 6: 1746 case 5: 1747 case 4: 1748 case 3: 1749 priv->ep_tx_low_queue = 1; 1750 priv->ep_tx_count++; 1751 fallthrough; 1752 case 2: 1753 priv->ep_tx_normal_queue = 1; 1754 priv->ep_tx_count++; 1755 fallthrough; 1756 case 1: 1757 priv->ep_tx_high_queue = 1; 1758 priv->ep_tx_count++; 1759 break; 1760 default: 1761 dev_info(dev, "Unsupported USB TX end-points\n"); 1762 return -ENOTSUPP; 1763 } 1764 1765 return 0; 1766 } 1767 1768 int 1769 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data) 1770 { 1771 int i; 1772 u8 val8; 1773 u32 val32; 1774 1775 /* Write Address */ 1776 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff); 1777 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2); 1778 val8 &= 0xfc; 1779 val8 |= (offset >> 8) & 0x03; 1780 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8); 1781 1782 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3); 1783 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f); 1784 1785 /* Poll for data read */ 1786 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); 1787 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) { 1788 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); 1789 if (val32 & BIT(31)) 1790 break; 1791 } 1792 1793 if (i == RTL8XXXU_MAX_REG_POLL) 1794 return -EIO; 1795 1796 udelay(50); 1797 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); 1798 1799 *data = val32 & 0xff; 1800 return 0; 1801 } 1802 1803 int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv) 1804 { 1805 struct device *dev = &priv->udev->dev; 1806 int i, ret = 0; 1807 u8 val8, word_mask, header, extheader; 1808 u16 val16, efuse_addr, offset; 1809 u32 val32; 1810 1811 val16 = rtl8xxxu_read16(priv, REG_9346CR); 1812 if (val16 & EEPROM_ENABLE) 1813 priv->has_eeprom = 1; 1814 if (val16 & EEPROM_BOOT) 1815 priv->boot_eeprom = 1; 1816 1817 if (priv->is_multi_func) { 1818 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST); 1819 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT; 1820 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32); 1821 } 1822 1823 dev_dbg(dev, "Booting from %s\n", 1824 priv->boot_eeprom ? "EEPROM" : "EFUSE"); 1825 1826 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE); 1827 1828 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */ 1829 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL); 1830 if (!(val16 & SYS_ISO_PWC_EV12V)) { 1831 val16 |= SYS_ISO_PWC_EV12V; 1832 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16); 1833 } 1834 /* Reset: 0x0000[28], default valid */ 1835 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1836 if (!(val16 & SYS_FUNC_ELDR)) { 1837 val16 |= SYS_FUNC_ELDR; 1838 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 1839 } 1840 1841 /* 1842 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid 1843 */ 1844 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR); 1845 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) { 1846 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M); 1847 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16); 1848 } 1849 1850 /* Default value is 0xff */ 1851 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN); 1852 1853 efuse_addr = 0; 1854 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) { 1855 u16 map_addr; 1856 1857 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header); 1858 if (ret || header == 0xff) 1859 goto exit; 1860 1861 if ((header & 0x1f) == 0x0f) { /* extended header */ 1862 offset = (header & 0xe0) >> 5; 1863 1864 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, 1865 &extheader); 1866 if (ret) 1867 goto exit; 1868 /* All words disabled */ 1869 if ((extheader & 0x0f) == 0x0f) 1870 continue; 1871 1872 offset |= ((extheader & 0xf0) >> 1); 1873 word_mask = extheader & 0x0f; 1874 } else { 1875 offset = (header >> 4) & 0x0f; 1876 word_mask = header & 0x0f; 1877 } 1878 1879 /* Get word enable value from PG header */ 1880 1881 /* We have 8 bits to indicate validity */ 1882 map_addr = offset * 8; 1883 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { 1884 /* Check word enable condition in the section */ 1885 if (word_mask & BIT(i)) { 1886 map_addr += 2; 1887 continue; 1888 } 1889 1890 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8); 1891 if (ret) 1892 goto exit; 1893 if (map_addr >= EFUSE_MAP_LEN - 1) { 1894 dev_warn(dev, "%s: Illegal map_addr (%04x), " 1895 "efuse corrupt!\n", 1896 __func__, map_addr); 1897 ret = -EINVAL; 1898 goto exit; 1899 } 1900 priv->efuse_wifi.raw[map_addr++] = val8; 1901 1902 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8); 1903 if (ret) 1904 goto exit; 1905 priv->efuse_wifi.raw[map_addr++] = val8; 1906 } 1907 } 1908 1909 exit: 1910 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE); 1911 1912 return ret; 1913 } 1914 1915 static void rtl8xxxu_dump_efuse(struct rtl8xxxu_priv *priv) 1916 { 1917 dev_info(&priv->udev->dev, 1918 "Dumping efuse for RTL%s (0x%02x bytes):\n", 1919 priv->chip_name, EFUSE_MAP_LEN); 1920 1921 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, 1922 priv->efuse_wifi.raw, EFUSE_MAP_LEN, true); 1923 } 1924 1925 void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv) 1926 { 1927 u8 val8; 1928 u16 sys_func; 1929 1930 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 1931 val8 &= ~BIT(0); 1932 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 1933 1934 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1935 sys_func &= ~SYS_FUNC_CPU_ENABLE; 1936 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); 1937 1938 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 1939 val8 |= BIT(0); 1940 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 1941 1942 sys_func |= SYS_FUNC_CPU_ENABLE; 1943 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); 1944 } 1945 1946 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv) 1947 { 1948 struct device *dev = &priv->udev->dev; 1949 u16 reg_mcu_fw_dl; 1950 int ret = 0, i; 1951 u32 val32; 1952 1953 if (priv->rtl_chip == RTL8710B) 1954 reg_mcu_fw_dl = REG_8051FW_CTRL_V1_8710B; 1955 else 1956 reg_mcu_fw_dl = REG_MCU_FW_DL; 1957 1958 /* Poll checksum report */ 1959 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) { 1960 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl); 1961 if (val32 & MCU_FW_DL_CSUM_REPORT) 1962 break; 1963 } 1964 1965 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) { 1966 dev_warn(dev, "Firmware checksum poll timed out\n"); 1967 ret = -EAGAIN; 1968 goto exit; 1969 } 1970 1971 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl); 1972 val32 |= MCU_FW_DL_READY; 1973 val32 &= ~MCU_WINT_INIT_READY; 1974 rtl8xxxu_write32(priv, reg_mcu_fw_dl, val32); 1975 1976 /* 1977 * Reset the 8051 in order for the firmware to start running, 1978 * otherwise it won't come up on the 8192eu 1979 */ 1980 priv->fops->reset_8051(priv); 1981 1982 /* Wait for firmware to become ready */ 1983 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) { 1984 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl); 1985 if (val32 & MCU_WINT_INIT_READY) 1986 break; 1987 1988 udelay(100); 1989 } 1990 1991 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) { 1992 dev_warn(dev, "Firmware failed to start\n"); 1993 ret = -EAGAIN; 1994 goto exit; 1995 } 1996 1997 /* 1998 * Init H2C command 1999 */ 2000 if (priv->fops->init_reg_hmtfr) 2001 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f); 2002 exit: 2003 return ret; 2004 } 2005 2006 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv) 2007 { 2008 int pages, remainder, i, ret; 2009 u16 reg_mcu_fw_dl; 2010 u8 val8; 2011 u16 val16; 2012 u32 val32; 2013 u8 *fwptr; 2014 2015 if (priv->rtl_chip == RTL8710B) { 2016 reg_mcu_fw_dl = REG_8051FW_CTRL_V1_8710B; 2017 } else { 2018 reg_mcu_fw_dl = REG_MCU_FW_DL; 2019 2020 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1); 2021 val8 |= 4; 2022 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8); 2023 2024 /* 8051 enable */ 2025 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2026 val16 |= SYS_FUNC_CPU_ENABLE; 2027 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 2028 } 2029 2030 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl); 2031 if (val8 & MCU_FW_RAM_SEL) { 2032 dev_info(&priv->udev->dev, 2033 "Firmware is already running, resetting the MCU.\n"); 2034 rtl8xxxu_write8(priv, reg_mcu_fw_dl, 0x00); 2035 priv->fops->reset_8051(priv); 2036 } 2037 2038 /* MCU firmware download enable */ 2039 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl); 2040 val8 |= MCU_FW_DL_ENABLE; 2041 rtl8xxxu_write8(priv, reg_mcu_fw_dl, val8); 2042 2043 /* 8051 reset */ 2044 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl); 2045 val32 &= ~BIT(19); 2046 rtl8xxxu_write32(priv, reg_mcu_fw_dl, val32); 2047 2048 if (priv->rtl_chip == RTL8710B) { 2049 /* We must set 0x8090[8]=1 before download FW. */ 2050 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 1); 2051 val8 |= BIT(0); 2052 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 1, val8); 2053 } 2054 2055 /* Reset firmware download checksum */ 2056 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl); 2057 val8 |= MCU_FW_DL_CSUM_REPORT; 2058 rtl8xxxu_write8(priv, reg_mcu_fw_dl, val8); 2059 2060 pages = priv->fw_size / RTL_FW_PAGE_SIZE; 2061 remainder = priv->fw_size % RTL_FW_PAGE_SIZE; 2062 2063 fwptr = priv->fw_data->data; 2064 2065 for (i = 0; i < pages; i++) { 2066 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 2) & 0xF8; 2067 val8 |= i; 2068 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 2, val8); 2069 2070 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS, 2071 fwptr, RTL_FW_PAGE_SIZE); 2072 if (ret != RTL_FW_PAGE_SIZE) { 2073 ret = -EAGAIN; 2074 goto fw_abort; 2075 } 2076 2077 fwptr += RTL_FW_PAGE_SIZE; 2078 } 2079 2080 if (remainder) { 2081 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 2) & 0xF8; 2082 val8 |= i; 2083 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 2, val8); 2084 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS, 2085 fwptr, remainder); 2086 if (ret != remainder) { 2087 ret = -EAGAIN; 2088 goto fw_abort; 2089 } 2090 } 2091 2092 ret = 0; 2093 fw_abort: 2094 /* MCU firmware download disable */ 2095 val16 = rtl8xxxu_read16(priv, reg_mcu_fw_dl); 2096 val16 &= ~MCU_FW_DL_ENABLE; 2097 rtl8xxxu_write16(priv, reg_mcu_fw_dl, val16); 2098 2099 return ret; 2100 } 2101 2102 int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, const char *fw_name) 2103 { 2104 struct device *dev = &priv->udev->dev; 2105 const struct firmware *fw; 2106 int ret = 0; 2107 u16 signature; 2108 2109 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name); 2110 if (request_firmware(&fw, fw_name, &priv->udev->dev)) { 2111 dev_warn(dev, "request_firmware(%s) failed\n", fw_name); 2112 ret = -EAGAIN; 2113 goto exit; 2114 } 2115 if (!fw) { 2116 dev_warn(dev, "Firmware data not available\n"); 2117 ret = -EINVAL; 2118 goto exit; 2119 } 2120 2121 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL); 2122 if (!priv->fw_data) { 2123 ret = -ENOMEM; 2124 goto exit; 2125 } 2126 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header); 2127 2128 signature = le16_to_cpu(priv->fw_data->signature); 2129 switch (signature & 0xfff0) { 2130 case 0x92e0: 2131 case 0x92c0: 2132 case 0x88e0: 2133 case 0x88c0: 2134 case 0x5300: 2135 case 0x2300: 2136 case 0x88f0: 2137 case 0x10b0: 2138 break; 2139 default: 2140 ret = -EINVAL; 2141 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n", 2142 __func__, signature); 2143 } 2144 2145 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n", 2146 le16_to_cpu(priv->fw_data->major_version), 2147 priv->fw_data->minor_version, signature); 2148 2149 exit: 2150 release_firmware(fw); 2151 return ret; 2152 } 2153 2154 void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv) 2155 { 2156 u16 val16; 2157 int i = 100; 2158 2159 /* Inform 8051 to perform reset */ 2160 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20); 2161 2162 for (i = 100; i > 0; i--) { 2163 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2164 2165 if (!(val16 & SYS_FUNC_CPU_ENABLE)) { 2166 dev_dbg(&priv->udev->dev, 2167 "%s: Firmware self reset success!\n", __func__); 2168 break; 2169 } 2170 udelay(50); 2171 } 2172 2173 if (!i) { 2174 /* Force firmware reset */ 2175 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2176 val16 &= ~SYS_FUNC_CPU_ENABLE; 2177 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 2178 } 2179 } 2180 2181 static int 2182 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv) 2183 { 2184 const struct rtl8xxxu_reg8val *array = priv->fops->mactable; 2185 int i, ret; 2186 u16 reg; 2187 u8 val; 2188 2189 for (i = 0; ; i++) { 2190 reg = array[i].reg; 2191 val = array[i].val; 2192 2193 if (reg == 0xffff && val == 0xff) 2194 break; 2195 2196 ret = rtl8xxxu_write8(priv, reg, val); 2197 if (ret != 1) { 2198 dev_warn(&priv->udev->dev, 2199 "Failed to initialize MAC " 2200 "(reg: %04x, val %02x)\n", reg, val); 2201 return -EAGAIN; 2202 } 2203 } 2204 2205 switch (priv->rtl_chip) { 2206 case RTL8188C: 2207 case RTL8188R: 2208 case RTL8191C: 2209 case RTL8192C: 2210 case RTL8723A: 2211 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a); 2212 break; 2213 case RTL8188E: 2214 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0707); 2215 break; 2216 default: 2217 break; 2218 } 2219 2220 return 0; 2221 } 2222 2223 int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv, 2224 const struct rtl8xxxu_reg32val *array) 2225 { 2226 int i, ret; 2227 u16 reg; 2228 u32 val; 2229 2230 for (i = 0; ; i++) { 2231 reg = array[i].reg; 2232 val = array[i].val; 2233 2234 if (reg == 0xffff && val == 0xffffffff) 2235 break; 2236 2237 ret = rtl8xxxu_write32(priv, reg, val); 2238 if (ret != sizeof(val)) { 2239 dev_warn(&priv->udev->dev, 2240 "Failed to initialize PHY\n"); 2241 return -EAGAIN; 2242 } 2243 udelay(1); 2244 } 2245 2246 return 0; 2247 } 2248 2249 void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv) 2250 { 2251 u8 val8, ldoa15, ldov12d, lpldo, ldohci12; 2252 u16 val16; 2253 u32 val32; 2254 2255 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); 2256 udelay(2); 2257 val8 |= AFE_PLL_320_ENABLE; 2258 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); 2259 udelay(2); 2260 2261 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff); 2262 udelay(2); 2263 2264 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2265 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB; 2266 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 2267 2268 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); 2269 val32 &= ~AFE_XTAL_RF_GATE; 2270 if (priv->has_bluetooth) 2271 val32 &= ~AFE_XTAL_BT_GATE; 2272 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); 2273 2274 /* 6. 0x1f[7:0] = 0x07 */ 2275 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; 2276 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); 2277 2278 if (priv->hi_pa) 2279 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table); 2280 else if (priv->tx_paths == 2) 2281 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table); 2282 else 2283 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table); 2284 2285 if (priv->rtl_chip == RTL8188R && priv->hi_pa && 2286 priv->vendor_umc && priv->chip_cut == 1) 2287 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50); 2288 2289 if (priv->hi_pa) 2290 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table); 2291 else 2292 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table); 2293 2294 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF; 2295 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT); 2296 ldohci12 = 0x57; 2297 lpldo = 1; 2298 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15; 2299 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32); 2300 } 2301 2302 /* 2303 * Most of this is black magic retrieved from the old rtl8723au driver 2304 */ 2305 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv) 2306 { 2307 u32 val32; 2308 2309 priv->fops->init_phy_bb(priv); 2310 2311 if (priv->tx_paths == 1 && priv->rx_paths == 2) { 2312 /* 2313 * For 1T2R boards, patch the registers. 2314 * 2315 * It looks like 8191/2 1T2R boards use path B for TX 2316 */ 2317 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO); 2318 val32 &= ~(BIT(0) | BIT(1)); 2319 val32 |= BIT(1); 2320 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32); 2321 2322 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO); 2323 val32 &= ~0x300033; 2324 val32 |= 0x200022; 2325 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32); 2326 2327 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); 2328 val32 &= ~CCK0_AFE_RX_MASK; 2329 val32 &= 0x00ffffff; 2330 val32 |= 0x40000000; 2331 val32 |= CCK0_AFE_RX_ANT_B; 2332 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); 2333 2334 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 2335 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); 2336 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B | 2337 OFDM_RF_PATH_TX_B); 2338 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 2339 2340 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1); 2341 val32 &= ~(BIT(4) | BIT(5)); 2342 val32 |= BIT(4); 2343 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32); 2344 2345 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON); 2346 val32 &= ~(BIT(27) | BIT(26)); 2347 val32 |= BIT(27); 2348 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32); 2349 2350 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON); 2351 val32 &= ~(BIT(27) | BIT(26)); 2352 val32 |= BIT(27); 2353 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32); 2354 2355 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON); 2356 val32 &= ~(BIT(27) | BIT(26)); 2357 val32 |= BIT(27); 2358 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32); 2359 2360 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON); 2361 val32 &= ~(BIT(27) | BIT(26)); 2362 val32 |= BIT(27); 2363 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32); 2364 2365 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX); 2366 val32 &= ~(BIT(27) | BIT(26)); 2367 val32 |= BIT(27); 2368 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32); 2369 } 2370 2371 if (priv->fops->set_crystal_cap) 2372 priv->fops->set_crystal_cap(priv, priv->default_crystal_cap); 2373 2374 if (priv->rtl_chip == RTL8192E) 2375 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x000f81fb); 2376 2377 return 0; 2378 } 2379 2380 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv, 2381 const struct rtl8xxxu_rfregval *array, 2382 enum rtl8xxxu_rfpath path) 2383 { 2384 int i, ret; 2385 u8 reg; 2386 u32 val; 2387 2388 for (i = 0; ; i++) { 2389 reg = array[i].reg; 2390 val = array[i].val; 2391 2392 if (reg == 0xff && val == 0xffffffff) 2393 break; 2394 2395 switch (reg) { 2396 case 0xfe: 2397 msleep(50); 2398 continue; 2399 case 0xfd: 2400 mdelay(5); 2401 continue; 2402 case 0xfc: 2403 mdelay(1); 2404 continue; 2405 case 0xfb: 2406 udelay(50); 2407 continue; 2408 case 0xfa: 2409 udelay(5); 2410 continue; 2411 case 0xf9: 2412 udelay(1); 2413 continue; 2414 } 2415 2416 ret = rtl8xxxu_write_rfreg(priv, path, reg, val); 2417 if (ret) { 2418 dev_warn(&priv->udev->dev, 2419 "Failed to initialize RF\n"); 2420 return -EAGAIN; 2421 } 2422 udelay(1); 2423 } 2424 2425 return 0; 2426 } 2427 2428 int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv, 2429 const struct rtl8xxxu_rfregval *table, 2430 enum rtl8xxxu_rfpath path) 2431 { 2432 u32 val32; 2433 u16 val16, rfsi_rfenv; 2434 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2; 2435 2436 switch (path) { 2437 case RF_A: 2438 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL; 2439 reg_int_oe = REG_FPGA0_XA_RF_INT_OE; 2440 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2; 2441 break; 2442 case RF_B: 2443 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL; 2444 reg_int_oe = REG_FPGA0_XB_RF_INT_OE; 2445 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2; 2446 break; 2447 default: 2448 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n", 2449 __func__, path + 'A'); 2450 return -EINVAL; 2451 } 2452 /* For path B, use XB */ 2453 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl); 2454 rfsi_rfenv &= FPGA0_RF_RFENV; 2455 2456 /* 2457 * These two we might be able to optimize into one 2458 */ 2459 val32 = rtl8xxxu_read32(priv, reg_int_oe); 2460 val32 |= BIT(20); /* 0x10 << 16 */ 2461 rtl8xxxu_write32(priv, reg_int_oe, val32); 2462 udelay(1); 2463 2464 val32 = rtl8xxxu_read32(priv, reg_int_oe); 2465 val32 |= BIT(4); 2466 rtl8xxxu_write32(priv, reg_int_oe, val32); 2467 udelay(1); 2468 2469 /* 2470 * These two we might be able to optimize into one 2471 */ 2472 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); 2473 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN; 2474 rtl8xxxu_write32(priv, reg_hssi_parm2, val32); 2475 udelay(1); 2476 2477 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); 2478 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN; 2479 rtl8xxxu_write32(priv, reg_hssi_parm2, val32); 2480 udelay(1); 2481 2482 rtl8xxxu_init_rf_regs(priv, table, path); 2483 2484 /* For path B, use XB */ 2485 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl); 2486 val16 &= ~FPGA0_RF_RFENV; 2487 val16 |= rfsi_rfenv; 2488 rtl8xxxu_write16(priv, reg_sw_ctrl, val16); 2489 2490 return 0; 2491 } 2492 2493 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data) 2494 { 2495 int ret = -EBUSY; 2496 int count = 0; 2497 u32 value; 2498 2499 value = LLT_OP_WRITE | address << 8 | data; 2500 2501 rtl8xxxu_write32(priv, REG_LLT_INIT, value); 2502 2503 do { 2504 value = rtl8xxxu_read32(priv, REG_LLT_INIT); 2505 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) { 2506 ret = 0; 2507 break; 2508 } 2509 } while (count++ < 20); 2510 2511 return ret; 2512 } 2513 2514 int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv) 2515 { 2516 int ret; 2517 int i, last_entry; 2518 u8 last_tx_page; 2519 2520 last_tx_page = priv->fops->total_page_num; 2521 2522 if (priv->fops->last_llt_entry) 2523 last_entry = priv->fops->last_llt_entry; 2524 else 2525 last_entry = 255; 2526 2527 for (i = 0; i < last_tx_page; i++) { 2528 ret = rtl8xxxu_llt_write(priv, i, i + 1); 2529 if (ret) 2530 goto exit; 2531 } 2532 2533 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff); 2534 if (ret) 2535 goto exit; 2536 2537 /* Mark remaining pages as a ring buffer */ 2538 for (i = last_tx_page + 1; i < last_entry; i++) { 2539 ret = rtl8xxxu_llt_write(priv, i, (i + 1)); 2540 if (ret) 2541 goto exit; 2542 } 2543 2544 /* Let last entry point to the start entry of ring buffer */ 2545 ret = rtl8xxxu_llt_write(priv, last_entry, last_tx_page + 1); 2546 if (ret) 2547 goto exit; 2548 2549 exit: 2550 return ret; 2551 } 2552 2553 int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv) 2554 { 2555 u32 val32; 2556 int ret = 0; 2557 int i; 2558 2559 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT); 2560 val32 |= AUTO_LLT_INIT_LLT; 2561 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32); 2562 2563 for (i = 500; i; i--) { 2564 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT); 2565 if (!(val32 & AUTO_LLT_INIT_LLT)) 2566 break; 2567 usleep_range(2, 4); 2568 } 2569 2570 if (!i) { 2571 ret = -EBUSY; 2572 dev_warn(&priv->udev->dev, "LLT table init failed\n"); 2573 } 2574 2575 return ret; 2576 } 2577 2578 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv) 2579 { 2580 u16 val16, hi, lo; 2581 u16 hiq, mgq, bkq, beq, viq, voq; 2582 int hip, mgp, bkp, bep, vip, vop; 2583 int ret = 0; 2584 2585 switch (priv->ep_tx_count) { 2586 case 1: 2587 if (priv->ep_tx_high_queue) { 2588 hi = TRXDMA_QUEUE_HIGH; 2589 } else if (priv->ep_tx_low_queue) { 2590 hi = TRXDMA_QUEUE_LOW; 2591 } else if (priv->ep_tx_normal_queue) { 2592 hi = TRXDMA_QUEUE_NORMAL; 2593 } else { 2594 hi = 0; 2595 ret = -EINVAL; 2596 } 2597 2598 hiq = hi; 2599 mgq = hi; 2600 bkq = hi; 2601 beq = hi; 2602 viq = hi; 2603 voq = hi; 2604 2605 hip = 0; 2606 mgp = 0; 2607 bkp = 0; 2608 bep = 0; 2609 vip = 0; 2610 vop = 0; 2611 break; 2612 case 2: 2613 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) { 2614 hi = TRXDMA_QUEUE_HIGH; 2615 lo = TRXDMA_QUEUE_LOW; 2616 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) { 2617 hi = TRXDMA_QUEUE_NORMAL; 2618 lo = TRXDMA_QUEUE_LOW; 2619 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) { 2620 hi = TRXDMA_QUEUE_HIGH; 2621 lo = TRXDMA_QUEUE_NORMAL; 2622 } else { 2623 ret = -EINVAL; 2624 hi = 0; 2625 lo = 0; 2626 } 2627 2628 hiq = hi; 2629 mgq = hi; 2630 bkq = lo; 2631 beq = lo; 2632 viq = hi; 2633 voq = hi; 2634 2635 hip = 0; 2636 mgp = 0; 2637 bkp = 1; 2638 bep = 1; 2639 vip = 0; 2640 vop = 0; 2641 break; 2642 case 3: 2643 beq = TRXDMA_QUEUE_LOW; 2644 bkq = TRXDMA_QUEUE_LOW; 2645 viq = TRXDMA_QUEUE_NORMAL; 2646 voq = TRXDMA_QUEUE_HIGH; 2647 mgq = TRXDMA_QUEUE_HIGH; 2648 hiq = TRXDMA_QUEUE_HIGH; 2649 2650 hip = hiq ^ 3; 2651 mgp = mgq ^ 3; 2652 bkp = bkq ^ 3; 2653 bep = beq ^ 3; 2654 vip = viq ^ 3; 2655 vop = viq ^ 3; 2656 break; 2657 default: 2658 ret = -EINVAL; 2659 } 2660 2661 /* 2662 * None of the vendor drivers are configuring the beacon 2663 * queue here .... why? 2664 */ 2665 if (!ret) { 2666 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL); 2667 val16 &= 0x7; 2668 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) | 2669 (viq << TRXDMA_CTRL_VIQ_SHIFT) | 2670 (beq << TRXDMA_CTRL_BEQ_SHIFT) | 2671 (bkq << TRXDMA_CTRL_BKQ_SHIFT) | 2672 (mgq << TRXDMA_CTRL_MGQ_SHIFT) | 2673 (hiq << TRXDMA_CTRL_HIQ_SHIFT); 2674 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16); 2675 2676 priv->pipe_out[TXDESC_QUEUE_VO] = 2677 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]); 2678 priv->pipe_out[TXDESC_QUEUE_VI] = 2679 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]); 2680 priv->pipe_out[TXDESC_QUEUE_BE] = 2681 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]); 2682 priv->pipe_out[TXDESC_QUEUE_BK] = 2683 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]); 2684 priv->pipe_out[TXDESC_QUEUE_BEACON] = 2685 usb_sndbulkpipe(priv->udev, priv->out_ep[0]); 2686 priv->pipe_out[TXDESC_QUEUE_MGNT] = 2687 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]); 2688 priv->pipe_out[TXDESC_QUEUE_HIGH] = 2689 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]); 2690 priv->pipe_out[TXDESC_QUEUE_CMD] = 2691 usb_sndbulkpipe(priv->udev, priv->out_ep[0]); 2692 } 2693 2694 return ret; 2695 } 2696 2697 void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok, 2698 int result[][8], int candidate, bool tx_only) 2699 { 2700 u32 oldval, x, tx0_a, reg; 2701 int y, tx0_c; 2702 u32 val32; 2703 2704 if (!iqk_ok) 2705 return; 2706 2707 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); 2708 oldval = val32 >> 22; 2709 2710 x = result[candidate][0]; 2711 if ((x & 0x00000200) != 0) 2712 x = x | 0xfffffc00; 2713 tx0_a = (x * oldval) >> 8; 2714 2715 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); 2716 val32 &= ~0x3ff; 2717 val32 |= tx0_a; 2718 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); 2719 2720 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2721 val32 &= ~BIT(31); 2722 if ((x * oldval >> 7) & 0x1) 2723 val32 |= BIT(31); 2724 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2725 2726 y = result[candidate][1]; 2727 if ((y & 0x00000200) != 0) 2728 y = y | 0xfffffc00; 2729 tx0_c = (y * oldval) >> 8; 2730 2731 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE); 2732 val32 &= ~0xf0000000; 2733 val32 |= (((tx0_c & 0x3c0) >> 6) << 28); 2734 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32); 2735 2736 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); 2737 val32 &= ~0x003f0000; 2738 val32 |= ((tx0_c & 0x3f) << 16); 2739 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); 2740 2741 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2742 val32 &= ~BIT(29); 2743 if ((y * oldval >> 7) & 0x1) 2744 val32 |= BIT(29); 2745 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2746 2747 if (tx_only) { 2748 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__); 2749 return; 2750 } 2751 2752 reg = result[candidate][2]; 2753 2754 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); 2755 val32 &= ~0x3ff; 2756 val32 |= (reg & 0x3ff); 2757 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); 2758 2759 reg = result[candidate][3] & 0x3F; 2760 2761 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); 2762 val32 &= ~0xfc00; 2763 val32 |= ((reg << 10) & 0xfc00); 2764 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); 2765 2766 reg = (result[candidate][3] >> 6) & 0xF; 2767 2768 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA); 2769 val32 &= ~0xf0000000; 2770 val32 |= (reg << 28); 2771 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32); 2772 } 2773 2774 void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok, 2775 int result[][8], int candidate, bool tx_only) 2776 { 2777 u32 oldval, x, tx1_a, reg; 2778 int y, tx1_c; 2779 u32 val32; 2780 2781 if (!iqk_ok) 2782 return; 2783 2784 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); 2785 oldval = val32 >> 22; 2786 2787 x = result[candidate][4]; 2788 if ((x & 0x00000200) != 0) 2789 x = x | 0xfffffc00; 2790 tx1_a = (x * oldval) >> 8; 2791 2792 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); 2793 val32 &= ~0x3ff; 2794 val32 |= tx1_a; 2795 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); 2796 2797 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2798 val32 &= ~BIT(27); 2799 if ((x * oldval >> 7) & 0x1) 2800 val32 |= BIT(27); 2801 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2802 2803 y = result[candidate][5]; 2804 if ((y & 0x00000200) != 0) 2805 y = y | 0xfffffc00; 2806 tx1_c = (y * oldval) >> 8; 2807 2808 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE); 2809 val32 &= ~0xf0000000; 2810 val32 |= (((tx1_c & 0x3c0) >> 6) << 28); 2811 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32); 2812 2813 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); 2814 val32 &= ~0x003f0000; 2815 val32 |= ((tx1_c & 0x3f) << 16); 2816 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); 2817 2818 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2819 val32 &= ~BIT(25); 2820 if ((y * oldval >> 7) & 0x1) 2821 val32 |= BIT(25); 2822 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2823 2824 if (tx_only) { 2825 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__); 2826 return; 2827 } 2828 2829 reg = result[candidate][6]; 2830 2831 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); 2832 val32 &= ~0x3ff; 2833 val32 |= (reg & 0x3ff); 2834 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); 2835 2836 reg = result[candidate][7] & 0x3f; 2837 2838 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); 2839 val32 &= ~0xfc00; 2840 val32 |= ((reg << 10) & 0xfc00); 2841 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); 2842 2843 reg = (result[candidate][7] >> 6) & 0xf; 2844 2845 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE); 2846 val32 &= ~0x0000f000; 2847 val32 |= (reg << 12); 2848 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32); 2849 } 2850 2851 #define MAX_TOLERANCE 5 2852 2853 bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv, 2854 int result[][8], int c1, int c2) 2855 { 2856 u32 i, j, diff, simubitmap, bound = 0; 2857 int candidate[2] = {-1, -1}; /* for path A and path B */ 2858 bool retval = true; 2859 2860 if (priv->tx_paths > 1) 2861 bound = 8; 2862 else 2863 bound = 4; 2864 2865 simubitmap = 0; 2866 2867 for (i = 0; i < bound; i++) { 2868 diff = (result[c1][i] > result[c2][i]) ? 2869 (result[c1][i] - result[c2][i]) : 2870 (result[c2][i] - result[c1][i]); 2871 if (diff > MAX_TOLERANCE) { 2872 if ((i == 2 || i == 6) && !simubitmap) { 2873 if (result[c1][i] + result[c1][i + 1] == 0) 2874 candidate[(i / 4)] = c2; 2875 else if (result[c2][i] + result[c2][i + 1] == 0) 2876 candidate[(i / 4)] = c1; 2877 else 2878 simubitmap = simubitmap | (1 << i); 2879 } else { 2880 simubitmap = simubitmap | (1 << i); 2881 } 2882 } 2883 } 2884 2885 if (simubitmap == 0) { 2886 for (i = 0; i < (bound / 4); i++) { 2887 if (candidate[i] >= 0) { 2888 for (j = i * 4; j < (i + 1) * 4 - 2; j++) 2889 result[3][j] = result[candidate[i]][j]; 2890 retval = false; 2891 } 2892 } 2893 return retval; 2894 } else if (!(simubitmap & 0x0f)) { 2895 /* path A OK */ 2896 for (i = 0; i < 4; i++) 2897 result[3][i] = result[c1][i]; 2898 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) { 2899 /* path B OK */ 2900 for (i = 4; i < 8; i++) 2901 result[3][i] = result[c1][i]; 2902 } 2903 2904 return false; 2905 } 2906 2907 bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv, 2908 int result[][8], int c1, int c2) 2909 { 2910 u32 i, j, diff, simubitmap, bound = 0; 2911 int candidate[2] = {-1, -1}; /* for path A and path B */ 2912 int tmp1, tmp2; 2913 bool retval = true; 2914 2915 if (priv->tx_paths > 1) 2916 bound = 8; 2917 else 2918 bound = 4; 2919 2920 simubitmap = 0; 2921 2922 for (i = 0; i < bound; i++) { 2923 if (i & 1) { 2924 if ((result[c1][i] & 0x00000200)) 2925 tmp1 = result[c1][i] | 0xfffffc00; 2926 else 2927 tmp1 = result[c1][i]; 2928 2929 if ((result[c2][i]& 0x00000200)) 2930 tmp2 = result[c2][i] | 0xfffffc00; 2931 else 2932 tmp2 = result[c2][i]; 2933 } else { 2934 tmp1 = result[c1][i]; 2935 tmp2 = result[c2][i]; 2936 } 2937 2938 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); 2939 2940 if (diff > MAX_TOLERANCE) { 2941 if ((i == 2 || i == 6) && !simubitmap) { 2942 if (result[c1][i] + result[c1][i + 1] == 0) 2943 candidate[(i / 4)] = c2; 2944 else if (result[c2][i] + result[c2][i + 1] == 0) 2945 candidate[(i / 4)] = c1; 2946 else 2947 simubitmap = simubitmap | (1 << i); 2948 } else { 2949 simubitmap = simubitmap | (1 << i); 2950 } 2951 } 2952 } 2953 2954 if (simubitmap == 0) { 2955 for (i = 0; i < (bound / 4); i++) { 2956 if (candidate[i] >= 0) { 2957 for (j = i * 4; j < (i + 1) * 4 - 2; j++) 2958 result[3][j] = result[candidate[i]][j]; 2959 retval = false; 2960 } 2961 } 2962 return retval; 2963 } else { 2964 if (!(simubitmap & 0x03)) { 2965 /* path A TX OK */ 2966 for (i = 0; i < 2; i++) 2967 result[3][i] = result[c1][i]; 2968 } 2969 2970 if (!(simubitmap & 0x0c)) { 2971 /* path A RX OK */ 2972 for (i = 2; i < 4; i++) 2973 result[3][i] = result[c1][i]; 2974 } 2975 2976 if (!(simubitmap & 0x30) && priv->tx_paths > 1) { 2977 /* path B TX OK */ 2978 for (i = 4; i < 6; i++) 2979 result[3][i] = result[c1][i]; 2980 } 2981 2982 if (!(simubitmap & 0xc0) && priv->tx_paths > 1) { 2983 /* path B RX OK */ 2984 for (i = 6; i < 8; i++) 2985 result[3][i] = result[c1][i]; 2986 } 2987 } 2988 2989 return false; 2990 } 2991 2992 void 2993 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup) 2994 { 2995 int i; 2996 2997 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++) 2998 backup[i] = rtl8xxxu_read8(priv, reg[i]); 2999 3000 backup[i] = rtl8xxxu_read32(priv, reg[i]); 3001 } 3002 3003 void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv, 3004 const u32 *reg, u32 *backup) 3005 { 3006 int i; 3007 3008 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++) 3009 rtl8xxxu_write8(priv, reg[i], backup[i]); 3010 3011 rtl8xxxu_write32(priv, reg[i], backup[i]); 3012 } 3013 3014 void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 3015 u32 *backup, int count) 3016 { 3017 int i; 3018 3019 for (i = 0; i < count; i++) 3020 backup[i] = rtl8xxxu_read32(priv, regs[i]); 3021 } 3022 3023 void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 3024 u32 *backup, int count) 3025 { 3026 int i; 3027 3028 for (i = 0; i < count; i++) 3029 rtl8xxxu_write32(priv, regs[i], backup[i]); 3030 } 3031 3032 3033 void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs, 3034 bool path_a_on) 3035 { 3036 u32 path_on; 3037 int i; 3038 3039 if (priv->tx_paths == 1) { 3040 path_on = priv->fops->adda_1t_path_on; 3041 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init); 3042 } else { 3043 path_on = path_a_on ? priv->fops->adda_2t_path_on_a : 3044 priv->fops->adda_2t_path_on_b; 3045 3046 rtl8xxxu_write32(priv, regs[0], path_on); 3047 } 3048 3049 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++) 3050 rtl8xxxu_write32(priv, regs[i], path_on); 3051 } 3052 3053 void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv, 3054 const u32 *regs, u32 *backup) 3055 { 3056 int i = 0; 3057 3058 rtl8xxxu_write8(priv, regs[i], 0x3f); 3059 3060 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++) 3061 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3))); 3062 3063 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5))); 3064 } 3065 3066 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv) 3067 { 3068 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32; 3069 int result = 0; 3070 3071 /* path-A IQK setting */ 3072 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f); 3073 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f); 3074 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102); 3075 3076 val32 = (priv->rf_paths > 1) ? 0x28160202 : 3077 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */ 3078 0x28160502; 3079 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32); 3080 3081 /* path-B IQK setting */ 3082 if (priv->rf_paths > 1) { 3083 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22); 3084 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22); 3085 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102); 3086 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202); 3087 } 3088 3089 /* LO calibration setting */ 3090 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1); 3091 3092 /* One shot, path A LOK & IQK */ 3093 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 3094 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 3095 3096 mdelay(1); 3097 3098 /* Check failed */ 3099 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 3100 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 3101 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 3102 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); 3103 3104 if (!(reg_eac & BIT(28)) && 3105 ((reg_e94 & 0x03ff0000) != 0x01420000) && 3106 ((reg_e9c & 0x03ff0000) != 0x00420000)) 3107 result |= 0x01; 3108 else /* If TX not OK, ignore RX */ 3109 goto out; 3110 3111 /* If TX is OK, check whether RX is OK */ 3112 if (!(reg_eac & BIT(27)) && 3113 ((reg_ea4 & 0x03ff0000) != 0x01320000) && 3114 ((reg_eac & 0x03ff0000) != 0x00360000)) 3115 result |= 0x02; 3116 else 3117 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n", 3118 __func__); 3119 out: 3120 return result; 3121 } 3122 3123 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv) 3124 { 3125 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc; 3126 int result = 0; 3127 3128 /* One shot, path B LOK & IQK */ 3129 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002); 3130 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000); 3131 3132 mdelay(1); 3133 3134 /* Check failed */ 3135 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 3136 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 3137 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 3138 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); 3139 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); 3140 3141 if (!(reg_eac & BIT(31)) && 3142 ((reg_eb4 & 0x03ff0000) != 0x01420000) && 3143 ((reg_ebc & 0x03ff0000) != 0x00420000)) 3144 result |= 0x01; 3145 else 3146 goto out; 3147 3148 if (!(reg_eac & BIT(30)) && 3149 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) && 3150 (((reg_ecc & 0x03ff0000) >> 16) != 0x36)) 3151 result |= 0x02; 3152 else 3153 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", 3154 __func__); 3155 out: 3156 return result; 3157 } 3158 3159 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, 3160 int result[][8], int t) 3161 { 3162 struct device *dev = &priv->udev->dev; 3163 u32 i, val32; 3164 int path_a_ok, path_b_ok; 3165 int retry = 2; 3166 static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { 3167 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, 3168 REG_RX_WAIT_CCA, REG_TX_CCK_RFON, 3169 REG_TX_CCK_BBON, REG_TX_OFDM_RFON, 3170 REG_TX_OFDM_BBON, REG_TX_TO_RX, 3171 REG_TX_TO_TX, REG_RX_CCK, 3172 REG_RX_OFDM, REG_RX_WAIT_RIFS, 3173 REG_RX_TO_RX, REG_STANDBY, 3174 REG_SLEEP, REG_PMPD_ANAEN 3175 }; 3176 static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { 3177 REG_TXPAUSE, REG_BEACON_CTRL, 3178 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG 3179 }; 3180 static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { 3181 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, 3182 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, 3183 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, 3184 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE 3185 }; 3186 3187 /* 3188 * Note: IQ calibration must be performed after loading 3189 * PHY_REG.txt , and radio_a, radio_b.txt 3190 */ 3191 3192 if (t == 0) { 3193 /* Save ADDA parameters, turn Path A ADDA on */ 3194 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, 3195 RTL8XXXU_ADDA_REGS); 3196 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 3197 rtl8xxxu_save_regs(priv, iqk_bb_regs, 3198 priv->bb_backup, RTL8XXXU_BB_REGS); 3199 } 3200 3201 rtl8xxxu_path_adda_on(priv, adda_regs, true); 3202 3203 if (t == 0) { 3204 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); 3205 if (val32 & FPGA0_HSSI_PARM1_PI) 3206 priv->pi_enabled = 1; 3207 } 3208 3209 if (!priv->pi_enabled) { 3210 /* Switch BB to PI mode to do IQ Calibration. */ 3211 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); 3212 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100); 3213 } 3214 3215 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 3216 val32 &= ~FPGA_RF_MODE_CCK; 3217 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 3218 3219 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); 3220 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); 3221 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); 3222 3223 if (!priv->no_pape) { 3224 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); 3225 val32 |= (FPGA0_RF_PAPE | 3226 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); 3227 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); 3228 } 3229 3230 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); 3231 val32 &= ~BIT(10); 3232 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); 3233 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); 3234 val32 &= ~BIT(10); 3235 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); 3236 3237 if (priv->tx_paths > 1) { 3238 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); 3239 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000); 3240 } 3241 3242 /* MAC settings */ 3243 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); 3244 3245 /* Page B init */ 3246 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000); 3247 3248 if (priv->tx_paths > 1) 3249 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000); 3250 3251 /* IQ calibration setting */ 3252 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); 3253 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 3254 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 3255 3256 for (i = 0; i < retry; i++) { 3257 path_a_ok = rtl8xxxu_iqk_path_a(priv); 3258 if (path_a_ok == 0x03) { 3259 val32 = rtl8xxxu_read32(priv, 3260 REG_TX_POWER_BEFORE_IQK_A); 3261 result[t][0] = (val32 >> 16) & 0x3ff; 3262 val32 = rtl8xxxu_read32(priv, 3263 REG_TX_POWER_AFTER_IQK_A); 3264 result[t][1] = (val32 >> 16) & 0x3ff; 3265 val32 = rtl8xxxu_read32(priv, 3266 REG_RX_POWER_BEFORE_IQK_A_2); 3267 result[t][2] = (val32 >> 16) & 0x3ff; 3268 val32 = rtl8xxxu_read32(priv, 3269 REG_RX_POWER_AFTER_IQK_A_2); 3270 result[t][3] = (val32 >> 16) & 0x3ff; 3271 break; 3272 } else if (i == (retry - 1) && path_a_ok == 0x01) { 3273 /* TX IQK OK */ 3274 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n", 3275 __func__); 3276 3277 val32 = rtl8xxxu_read32(priv, 3278 REG_TX_POWER_BEFORE_IQK_A); 3279 result[t][0] = (val32 >> 16) & 0x3ff; 3280 val32 = rtl8xxxu_read32(priv, 3281 REG_TX_POWER_AFTER_IQK_A); 3282 result[t][1] = (val32 >> 16) & 0x3ff; 3283 } 3284 } 3285 3286 if (!path_a_ok) 3287 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__); 3288 3289 if (priv->tx_paths > 1) { 3290 /* 3291 * Path A into standby 3292 */ 3293 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0); 3294 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); 3295 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); 3296 3297 /* Turn Path B ADDA on */ 3298 rtl8xxxu_path_adda_on(priv, adda_regs, false); 3299 3300 for (i = 0; i < retry; i++) { 3301 path_b_ok = rtl8xxxu_iqk_path_b(priv); 3302 if (path_b_ok == 0x03) { 3303 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 3304 result[t][4] = (val32 >> 16) & 0x3ff; 3305 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 3306 result[t][5] = (val32 >> 16) & 0x3ff; 3307 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); 3308 result[t][6] = (val32 >> 16) & 0x3ff; 3309 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); 3310 result[t][7] = (val32 >> 16) & 0x3ff; 3311 break; 3312 } else if (i == (retry - 1) && path_b_ok == 0x01) { 3313 /* TX IQK OK */ 3314 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 3315 result[t][4] = (val32 >> 16) & 0x3ff; 3316 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 3317 result[t][5] = (val32 >> 16) & 0x3ff; 3318 } 3319 } 3320 3321 if (!path_b_ok) 3322 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__); 3323 } 3324 3325 /* Back to BB mode, load original value */ 3326 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0); 3327 3328 if (t) { 3329 if (!priv->pi_enabled) { 3330 /* 3331 * Switch back BB to SI mode after finishing 3332 * IQ Calibration 3333 */ 3334 val32 = 0x01000000; 3335 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32); 3336 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32); 3337 } 3338 3339 /* Reload ADDA power saving parameters */ 3340 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, 3341 RTL8XXXU_ADDA_REGS); 3342 3343 /* Reload MAC parameters */ 3344 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 3345 3346 /* Reload BB parameters */ 3347 rtl8xxxu_restore_regs(priv, iqk_bb_regs, 3348 priv->bb_backup, RTL8XXXU_BB_REGS); 3349 3350 /* Restore RX initial gain */ 3351 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3); 3352 3353 if (priv->tx_paths > 1) { 3354 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 3355 0x00032ed3); 3356 } 3357 3358 /* Load 0xe30 IQC default value */ 3359 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); 3360 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); 3361 } 3362 } 3363 3364 void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start) 3365 { 3366 struct h2c_cmd h2c; 3367 3368 memset(&h2c, 0, sizeof(struct h2c_cmd)); 3369 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION; 3370 h2c.bt_wlan_calibration.data = start; 3371 3372 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration)); 3373 } 3374 3375 void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv) 3376 { 3377 struct device *dev = &priv->udev->dev; 3378 int result[4][8]; /* last is final result */ 3379 int i, candidate; 3380 bool path_a_ok, path_b_ok; 3381 u32 reg_e94, reg_e9c, reg_ea4, reg_eac; 3382 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; 3383 s32 reg_tmp = 0; 3384 bool simu; 3385 3386 memset(result, 0, sizeof(result)); 3387 candidate = -1; 3388 3389 path_a_ok = false; 3390 path_b_ok = false; 3391 3392 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 3393 3394 for (i = 0; i < 3; i++) { 3395 rtl8xxxu_phy_iqcalibrate(priv, result, i); 3396 3397 if (i == 1) { 3398 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1); 3399 if (simu) { 3400 candidate = 0; 3401 break; 3402 } 3403 } 3404 3405 if (i == 2) { 3406 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2); 3407 if (simu) { 3408 candidate = 0; 3409 break; 3410 } 3411 3412 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2); 3413 if (simu) { 3414 candidate = 1; 3415 } else { 3416 for (i = 0; i < 8; i++) 3417 reg_tmp += result[3][i]; 3418 3419 if (reg_tmp) 3420 candidate = 3; 3421 else 3422 candidate = -1; 3423 } 3424 } 3425 } 3426 3427 for (i = 0; i < 4; i++) { 3428 reg_e94 = result[i][0]; 3429 reg_e9c = result[i][1]; 3430 reg_ea4 = result[i][2]; 3431 reg_eac = result[i][3]; 3432 reg_eb4 = result[i][4]; 3433 reg_ebc = result[i][5]; 3434 reg_ec4 = result[i][6]; 3435 reg_ecc = result[i][7]; 3436 } 3437 3438 if (candidate >= 0) { 3439 reg_e94 = result[candidate][0]; 3440 priv->rege94 = reg_e94; 3441 reg_e9c = result[candidate][1]; 3442 priv->rege9c = reg_e9c; 3443 reg_ea4 = result[candidate][2]; 3444 reg_eac = result[candidate][3]; 3445 reg_eb4 = result[candidate][4]; 3446 priv->regeb4 = reg_eb4; 3447 reg_ebc = result[candidate][5]; 3448 priv->regebc = reg_ebc; 3449 reg_ec4 = result[candidate][6]; 3450 reg_ecc = result[candidate][7]; 3451 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); 3452 dev_dbg(dev, 3453 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n", 3454 __func__, reg_e94, reg_e9c, 3455 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); 3456 path_a_ok = true; 3457 path_b_ok = true; 3458 } else { 3459 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; 3460 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; 3461 } 3462 3463 if (reg_e94 && candidate >= 0) 3464 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, 3465 candidate, (reg_ea4 == 0)); 3466 3467 if (priv->tx_paths > 1 && reg_eb4) 3468 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, 3469 candidate, (reg_ec4 == 0)); 3470 3471 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, 3472 priv->bb_recovery_backup, RTL8XXXU_BB_REGS); 3473 } 3474 3475 void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv) 3476 { 3477 u32 val32; 3478 u32 rf_amode, rf_bmode = 0, lstf; 3479 3480 /* Check continuous TX and Packet TX */ 3481 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 3482 3483 if (lstf & OFDM_LSTF_MASK) { 3484 /* Disable all continuous TX */ 3485 val32 = lstf & ~OFDM_LSTF_MASK; 3486 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 3487 3488 /* Read original RF mode Path A */ 3489 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC); 3490 3491 /* Set RF mode to standby Path A */ 3492 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 3493 (rf_amode & 0x8ffff) | 0x10000); 3494 3495 /* Path-B */ 3496 if (priv->tx_paths > 1) { 3497 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B, 3498 RF6052_REG_AC); 3499 3500 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 3501 (rf_bmode & 0x8ffff) | 0x10000); 3502 } 3503 } else { 3504 /* Deal with Packet TX case */ 3505 /* block all queues */ 3506 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 3507 } 3508 3509 /* Start LC calibration */ 3510 if (priv->fops->has_s0s1) 3511 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0); 3512 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); 3513 val32 |= 0x08000; 3514 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); 3515 3516 msleep(100); 3517 3518 if (priv->fops->has_s0s1) 3519 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0); 3520 3521 /* Restore original parameters */ 3522 if (lstf & OFDM_LSTF_MASK) { 3523 /* Path-A */ 3524 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf); 3525 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode); 3526 3527 /* Path-B */ 3528 if (priv->tx_paths > 1) 3529 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 3530 rf_bmode); 3531 } else /* Deal with Packet TX case */ 3532 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); 3533 } 3534 3535 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv) 3536 { 3537 int i; 3538 u16 reg; 3539 3540 reg = REG_MACID; 3541 3542 for (i = 0; i < ETH_ALEN; i++) 3543 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]); 3544 3545 return 0; 3546 } 3547 3548 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid) 3549 { 3550 int i; 3551 u16 reg; 3552 3553 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid); 3554 3555 reg = REG_BSSID; 3556 3557 for (i = 0; i < ETH_ALEN; i++) 3558 rtl8xxxu_write8(priv, reg + i, bssid[i]); 3559 3560 return 0; 3561 } 3562 3563 static void 3564 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor) 3565 { 3566 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 }; 3567 u8 max_agg = 0xf; 3568 int i; 3569 3570 ampdu_factor = 1 << (ampdu_factor + 2); 3571 if (ampdu_factor > max_agg) 3572 ampdu_factor = max_agg; 3573 3574 for (i = 0; i < 4; i++) { 3575 if ((vals[i] & 0xf0) > (ampdu_factor << 4)) 3576 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4); 3577 3578 if ((vals[i] & 0x0f) > ampdu_factor) 3579 vals[i] = (vals[i] & 0xf0) | ampdu_factor; 3580 3581 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]); 3582 } 3583 } 3584 3585 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density) 3586 { 3587 u8 val8; 3588 3589 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE); 3590 val8 &= 0xf8; 3591 val8 |= density; 3592 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8); 3593 } 3594 3595 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv) 3596 { 3597 u8 val8; 3598 int count, ret = 0; 3599 3600 /* Start of rtl8723AU_card_enable_flow */ 3601 /* Act to Cardemu sequence*/ 3602 /* Turn off RF */ 3603 rtl8xxxu_write8(priv, REG_RF_CTRL, 0); 3604 3605 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */ 3606 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); 3607 val8 &= ~LEDCFG2_DPDT_SELECT; 3608 rtl8xxxu_write8(priv, REG_LEDCFG2, val8); 3609 3610 /* 0x0005[1] = 1 turn off MAC by HW state machine*/ 3611 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3612 val8 |= BIT(1); 3613 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3614 3615 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 3616 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3617 if ((val8 & BIT(1)) == 0) 3618 break; 3619 udelay(10); 3620 } 3621 3622 if (!count) { 3623 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", 3624 __func__); 3625 ret = -EBUSY; 3626 goto exit; 3627 } 3628 3629 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */ 3630 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); 3631 val8 |= SYS_ISO_ANALOG_IPS; 3632 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); 3633 3634 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/ 3635 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); 3636 val8 &= ~LDOA15_ENABLE; 3637 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); 3638 3639 exit: 3640 return ret; 3641 } 3642 3643 int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv) 3644 { 3645 u8 val8; 3646 u8 val32; 3647 int count, ret = 0; 3648 3649 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 3650 3651 /* 3652 * Poll - wait for RX packet to complete 3653 */ 3654 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 3655 val32 = rtl8xxxu_read32(priv, 0x5f8); 3656 if (!val32) 3657 break; 3658 udelay(10); 3659 } 3660 3661 if (!count) { 3662 dev_warn(&priv->udev->dev, 3663 "%s: RX poll timed out (0x05f8)\n", __func__); 3664 ret = -EBUSY; 3665 goto exit; 3666 } 3667 3668 /* Disable CCK and OFDM, clock gated */ 3669 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 3670 val8 &= ~SYS_FUNC_BBRSTB; 3671 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 3672 3673 udelay(2); 3674 3675 /* Reset baseband */ 3676 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 3677 val8 &= ~SYS_FUNC_BB_GLB_RSTN; 3678 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 3679 3680 /* Reset MAC TRX */ 3681 val8 = rtl8xxxu_read8(priv, REG_CR); 3682 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE; 3683 rtl8xxxu_write8(priv, REG_CR, val8); 3684 3685 /* Reset MAC TRX */ 3686 val8 = rtl8xxxu_read8(priv, REG_CR + 1); 3687 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */ 3688 rtl8xxxu_write8(priv, REG_CR + 1, val8); 3689 3690 /* Respond TX OK to scheduler */ 3691 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); 3692 val8 |= DUAL_TSF_TX_OK; 3693 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); 3694 3695 exit: 3696 return ret; 3697 } 3698 3699 void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv) 3700 { 3701 u8 val8; 3702 3703 /* Clear suspend enable and power down enable*/ 3704 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3705 val8 &= ~(BIT(3) | BIT(7)); 3706 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3707 3708 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ 3709 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); 3710 val8 &= ~BIT(0); 3711 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); 3712 3713 /* 0x04[12:11] = 11 enable WL suspend*/ 3714 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3715 val8 &= ~(BIT(3) | BIT(4)); 3716 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3717 } 3718 3719 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv) 3720 { 3721 u8 val8; 3722 3723 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */ 3724 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20); 3725 3726 /* 0x04[12:11] = 01 enable WL suspend */ 3727 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3728 val8 &= ~BIT(4); 3729 val8 |= BIT(3); 3730 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3731 3732 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3733 val8 |= BIT(7); 3734 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3735 3736 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */ 3737 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); 3738 val8 |= BIT(0); 3739 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); 3740 3741 return 0; 3742 } 3743 3744 int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv) 3745 { 3746 struct device *dev = &priv->udev->dev; 3747 u32 val32; 3748 int retry, retval; 3749 3750 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 3751 3752 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM); 3753 val32 |= RXPKT_NUM_RW_RELEASE_EN; 3754 rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32); 3755 3756 retry = 100; 3757 retval = -EBUSY; 3758 3759 do { 3760 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM); 3761 if (val32 & RXPKT_NUM_RXDMA_IDLE) { 3762 retval = 0; 3763 break; 3764 } 3765 } while (retry--); 3766 3767 rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0); 3768 rtl8xxxu_write32(priv, REG_RQPN, 0x80000000); 3769 mdelay(2); 3770 3771 if (!retry) 3772 dev_warn(dev, "Failed to flush FIFO\n"); 3773 3774 return retval; 3775 } 3776 3777 void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv) 3778 { 3779 /* Fix USB interface interference issue */ 3780 rtl8xxxu_write8(priv, 0xfe40, 0xe0); 3781 rtl8xxxu_write8(priv, 0xfe41, 0x8d); 3782 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3783 /* 3784 * This sets TXDMA_OFFSET_DROP_DATA_EN (bit 9) as well as bits 3785 * 8 and 5, for which I have found no documentation. 3786 */ 3787 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320); 3788 3789 /* 3790 * Solve too many protocol error on USB bus. 3791 * Can't do this for 8188/8192 UMC A cut parts 3792 */ 3793 if (!(!priv->chip_cut && priv->vendor_umc)) { 3794 rtl8xxxu_write8(priv, 0xfe40, 0xe6); 3795 rtl8xxxu_write8(priv, 0xfe41, 0x94); 3796 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3797 3798 rtl8xxxu_write8(priv, 0xfe40, 0xe0); 3799 rtl8xxxu_write8(priv, 0xfe41, 0x19); 3800 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3801 3802 rtl8xxxu_write8(priv, 0xfe40, 0xe5); 3803 rtl8xxxu_write8(priv, 0xfe41, 0x91); 3804 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3805 3806 rtl8xxxu_write8(priv, 0xfe40, 0xe2); 3807 rtl8xxxu_write8(priv, 0xfe41, 0x81); 3808 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3809 } 3810 } 3811 3812 void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv) 3813 { 3814 u32 val32; 3815 3816 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK); 3817 val32 |= TXDMA_OFFSET_DROP_DATA_EN; 3818 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32); 3819 } 3820 3821 void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv) 3822 { 3823 u8 val8; 3824 u16 val16; 3825 u32 val32; 3826 3827 /* 3828 * Workaround for 8188RU LNA power leakage problem. 3829 */ 3830 if (priv->rtl_chip == RTL8188R) { 3831 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM); 3832 val32 |= BIT(1); 3833 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32); 3834 } 3835 3836 rtl8xxxu_flush_fifo(priv); 3837 3838 rtl8xxxu_active_to_lps(priv); 3839 3840 /* Turn off RF */ 3841 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); 3842 3843 /* Reset Firmware if running in RAM */ 3844 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) 3845 rtl8xxxu_firmware_self_reset(priv); 3846 3847 /* Reset MCU */ 3848 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 3849 val16 &= ~SYS_FUNC_CPU_ENABLE; 3850 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 3851 3852 /* Reset MCU ready status */ 3853 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); 3854 3855 rtl8xxxu_active_to_emu(priv); 3856 rtl8xxxu_emu_to_disabled(priv); 3857 3858 /* Reset MCU IO Wrapper */ 3859 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 3860 val8 &= ~BIT(0); 3861 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 3862 3863 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 3864 val8 |= BIT(0); 3865 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 3866 3867 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */ 3868 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e); 3869 } 3870 3871 void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv, 3872 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5) 3873 { 3874 struct h2c_cmd h2c; 3875 3876 memset(&h2c, 0, sizeof(struct h2c_cmd)); 3877 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA; 3878 h2c.b_type_dma.data1 = arg1; 3879 h2c.b_type_dma.data2 = arg2; 3880 h2c.b_type_dma.data3 = arg3; 3881 h2c.b_type_dma.data4 = arg4; 3882 h2c.b_type_dma.data5 = arg5; 3883 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma)); 3884 } 3885 3886 void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv) 3887 { 3888 u32 val32; 3889 3890 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); 3891 val32 &= ~(BIT(22) | BIT(23)); 3892 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); 3893 } 3894 3895 static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv *priv) 3896 { 3897 struct rtl8xxxu_fileops *fops = priv->fops; 3898 u32 hq, lq, nq, eq, pubq; 3899 u32 val32; 3900 3901 hq = 0; 3902 lq = 0; 3903 nq = 0; 3904 eq = 0; 3905 pubq = 0; 3906 3907 if (priv->ep_tx_high_queue) 3908 hq = fops->page_num_hi; 3909 if (priv->ep_tx_low_queue) 3910 lq = fops->page_num_lo; 3911 if (priv->ep_tx_normal_queue) 3912 nq = fops->page_num_norm; 3913 3914 val32 = (nq << RQPN_NPQ_SHIFT) | (eq << RQPN_EPQ_SHIFT); 3915 rtl8xxxu_write32(priv, REG_RQPN_NPQ, val32); 3916 3917 pubq = fops->total_page_num - hq - lq - nq - 1; 3918 3919 val32 = RQPN_LOAD; 3920 val32 |= (hq << RQPN_HI_PQ_SHIFT); 3921 val32 |= (lq << RQPN_LO_PQ_SHIFT); 3922 val32 |= (pubq << RQPN_PUB_PQ_SHIFT); 3923 3924 rtl8xxxu_write32(priv, REG_RQPN, val32); 3925 } 3926 3927 void rtl8xxxu_init_burst(struct rtl8xxxu_priv *priv) 3928 { 3929 u8 val8; 3930 3931 /* 3932 * For USB high speed set 512B packets 3933 */ 3934 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B); 3935 u8p_replace_bits(&val8, 1, RXDMA_PRO_DMA_BURST_SIZE); 3936 u8p_replace_bits(&val8, 3, RXDMA_PRO_DMA_BURST_CNT); 3937 val8 |= RXDMA_PRO_DMA_MODE; 3938 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8); 3939 3940 /* 3941 * Enable single packet AMPDU 3942 */ 3943 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B); 3944 val8 |= HT_SINGLE_AMPDU_ENABLE; 3945 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8); 3946 3947 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14); 3948 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 3949 priv->fops->ampdu_max_time); 3950 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff); 3951 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18); 3952 rtl8xxxu_write8(priv, REG_PIFS, 0x00); 3953 if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8710B) { 3954 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, FWHW_TXQ_CTRL_AMPDU_RETRY); 3955 rtl8xxxu_write32(priv, REG_FAST_EDCA_CTRL, 0x03086666); 3956 } 3957 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, priv->fops->ustime_tsf_edca); 3958 rtl8xxxu_write8(priv, REG_USTIME_EDCA, priv->fops->ustime_tsf_edca); 3959 3960 /* to prevent mac is reseted by bus. */ 3961 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); 3962 val8 |= RSV_CTRL_WLOCK_1C | RSV_CTRL_DIS_PRST; 3963 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); 3964 } 3965 3966 static int rtl8xxxu_init_device(struct ieee80211_hw *hw) 3967 { 3968 struct rtl8xxxu_priv *priv = hw->priv; 3969 struct device *dev = &priv->udev->dev; 3970 struct rtl8xxxu_fileops *fops = priv->fops; 3971 bool macpower; 3972 int ret; 3973 u8 val8; 3974 u16 val16; 3975 u32 val32; 3976 3977 /* Check if MAC is already powered on */ 3978 val8 = rtl8xxxu_read8(priv, REG_CR); 3979 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR); 3980 3981 /* 3982 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not 3983 * initialized. First MAC returns 0xea, second MAC returns 0x00 3984 */ 3985 if (val8 == 0xea || !(val16 & SYS_CLK_MAC_CLK_ENABLE)) 3986 macpower = false; 3987 else 3988 macpower = true; 3989 3990 if (fops->needs_full_init) 3991 macpower = false; 3992 3993 ret = fops->power_on(priv); 3994 if (ret < 0) { 3995 dev_warn(dev, "%s: Failed power on\n", __func__); 3996 goto exit; 3997 } 3998 3999 if (!macpower) 4000 rtl8xxxu_init_queue_reserved_page(priv); 4001 4002 ret = rtl8xxxu_init_queue_priority(priv); 4003 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret); 4004 if (ret) 4005 goto exit; 4006 4007 /* 4008 * Set RX page boundary 4009 */ 4010 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, fops->trxff_boundary); 4011 4012 ret = rtl8xxxu_download_firmware(priv); 4013 dev_dbg(dev, "%s: download_firmware %i\n", __func__, ret); 4014 if (ret) 4015 goto exit; 4016 ret = rtl8xxxu_start_firmware(priv); 4017 dev_dbg(dev, "%s: start_firmware %i\n", __func__, ret); 4018 if (ret) 4019 goto exit; 4020 4021 if (fops->phy_init_antenna_selection) 4022 fops->phy_init_antenna_selection(priv); 4023 4024 ret = rtl8xxxu_init_mac(priv); 4025 4026 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret); 4027 if (ret) 4028 goto exit; 4029 4030 ret = rtl8xxxu_init_phy_bb(priv); 4031 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret); 4032 if (ret) 4033 goto exit; 4034 4035 ret = fops->init_phy_rf(priv); 4036 if (ret) 4037 goto exit; 4038 4039 /* RFSW Control - clear bit 14 ?? */ 4040 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E && 4041 priv->rtl_chip != RTL8188E && priv->rtl_chip != RTL8710B) 4042 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003); 4043 4044 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW | 4045 FPGA0_RF_ANTSWB | 4046 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB) << FPGA0_RF_BD_CTRL_SHIFT); 4047 if (!priv->no_pape) { 4048 val32 |= (FPGA0_RF_PAPE | 4049 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); 4050 } 4051 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); 4052 4053 /* 0x860[6:5]= 00 - why? - this sets antenna B */ 4054 if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188E && 4055 priv->rtl_chip != RTL8710B) 4056 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210); 4057 4058 if (!macpower) { 4059 /* 4060 * Set TX buffer boundary 4061 */ 4062 val8 = fops->total_page_num + 1; 4063 4064 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8); 4065 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8); 4066 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8); 4067 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8); 4068 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8); 4069 } 4070 4071 /* 4072 * The vendor drivers set PBP for all devices, except 8192e. 4073 * There is no explanation for this in any of the sources. 4074 */ 4075 val8 = (fops->pbp_rx << PBP_PAGE_SIZE_RX_SHIFT) | 4076 (fops->pbp_tx << PBP_PAGE_SIZE_TX_SHIFT); 4077 if (priv->rtl_chip != RTL8192E) 4078 rtl8xxxu_write8(priv, REG_PBP, val8); 4079 4080 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower); 4081 if (!macpower) { 4082 ret = fops->llt_init(priv); 4083 if (ret) { 4084 dev_warn(dev, "%s: LLT table init failed\n", __func__); 4085 goto exit; 4086 } 4087 4088 /* 4089 * Chip specific quirks 4090 */ 4091 fops->usb_quirks(priv); 4092 4093 /* 4094 * Enable TX report and TX report timer for 8723bu/8188eu/... 4095 */ 4096 if (fops->has_tx_report) { 4097 /* 4098 * The RTL8188EU has two types of TX reports: 4099 * rpt_sel=1: 4100 * One report for one frame. We can use this for frames 4101 * with IEEE80211_TX_CTL_REQ_TX_STATUS. 4102 * rpt_sel=2: 4103 * One report for many frames transmitted over a period 4104 * of time. (This is what REG_TX_REPORT_TIME is for.) The 4105 * report includes the number of frames transmitted 4106 * successfully, and the number of unsuccessful 4107 * transmissions. We use this for software rate control. 4108 * 4109 * Bit 0 of REG_TX_REPORT_CTRL is required for both types. 4110 * Bit 1 (TX_REPORT_CTRL_TIMER_ENABLE) is required for 4111 * type 2. 4112 */ 4113 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); 4114 if (priv->rtl_chip == RTL8188E) 4115 val8 |= BIT(0); 4116 val8 |= TX_REPORT_CTRL_TIMER_ENABLE; 4117 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); 4118 /* Set MAX RPT MACID */ 4119 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02); 4120 /* TX report Timer. Unit: 32us */ 4121 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0); 4122 4123 /* tmp ps ? */ 4124 val8 = rtl8xxxu_read8(priv, 0xa3); 4125 val8 &= 0xf8; 4126 rtl8xxxu_write8(priv, 0xa3, val8); 4127 } 4128 4129 if (priv->rtl_chip == RTL8710B) 4130 rtl8xxxu_write8(priv, REG_EARLY_MODE_CONTROL_8710B, 0); 4131 } 4132 4133 /* 4134 * Unit in 8 bytes. 4135 * Get Rx PHY status in order to report RSSI and others. 4136 */ 4137 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4); 4138 4139 if (priv->rtl_chip == RTL8192E) { 4140 rtl8xxxu_write32(priv, REG_HIMR0, 0x00); 4141 rtl8xxxu_write32(priv, REG_HIMR1, 0x00); 4142 } else if (priv->rtl_chip == RTL8188F) { 4143 rtl8xxxu_write32(priv, REG_HISR0, 0xffffffff); 4144 rtl8xxxu_write32(priv, REG_HISR1, 0xffffffff); 4145 } else if (priv->rtl_chip == RTL8188E) { 4146 rtl8xxxu_write32(priv, REG_HISR0, 0xffffffff); 4147 val32 = IMR0_PSTIMEOUT | IMR0_TBDER | IMR0_CPWM | IMR0_CPWM2; 4148 rtl8xxxu_write32(priv, REG_HIMR0, val32); 4149 val32 = IMR1_TXERR | IMR1_RXERR | IMR1_TXFOVW | IMR1_RXFOVW; 4150 rtl8xxxu_write32(priv, REG_HIMR1, val32); 4151 val8 = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION); 4152 val8 |= USB_SPEC_INT_BULK_SELECT; 4153 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, val8); 4154 } else if (priv->rtl_chip == RTL8710B) { 4155 rtl8xxxu_write32(priv, REG_HIMR0_8710B, 0); 4156 } else { 4157 /* 4158 * Enable all interrupts - not obvious USB needs to do this 4159 */ 4160 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff); 4161 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff); 4162 } 4163 4164 rtl8xxxu_set_mac(priv); 4165 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION); 4166 4167 /* 4168 * Configure initial WMAC settings 4169 */ 4170 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST | 4171 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL | 4172 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC; 4173 rtl8xxxu_write32(priv, REG_RCR, val32); 4174 4175 if (fops->init_reg_rxfltmap) { 4176 /* Accept all data frames */ 4177 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff); 4178 4179 /* 4180 * Since ADF is removed from RCR, ps-poll will not be indicate to driver, 4181 * RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. 4182 */ 4183 rtl8xxxu_write16(priv, REG_RXFLTMAP1, 0x400); 4184 4185 /* Accept all management frames */ 4186 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff); 4187 } else { 4188 /* 4189 * Accept all multicast 4190 */ 4191 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff); 4192 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff); 4193 } 4194 4195 /* 4196 * Init adaptive controls 4197 */ 4198 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 4199 val32 &= ~RESPONSE_RATE_BITMAP_ALL; 4200 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M; 4201 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 4202 4203 /* CCK = 0x0a, OFDM = 0x10 */ 4204 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10); 4205 rtl8xxxu_set_retry(priv, 0x30, 0x30); 4206 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10); 4207 4208 /* 4209 * Init EDCA 4210 */ 4211 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a); 4212 4213 /* Set CCK SIFS */ 4214 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a); 4215 4216 /* Set OFDM SIFS */ 4217 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a); 4218 4219 /* TXOP */ 4220 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b); 4221 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f); 4222 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324); 4223 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226); 4224 4225 /* Set data auto rate fallback retry count */ 4226 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000); 4227 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404); 4228 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201); 4229 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605); 4230 4231 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL); 4232 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY; 4233 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8); 4234 4235 /* Set ACK timeout */ 4236 rtl8xxxu_write8(priv, REG_ACKTO, 0x40); 4237 4238 /* 4239 * Initialize beacon parameters 4240 */ 4241 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8); 4242 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16); 4243 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404); 4244 if (priv->rtl_chip != RTL8188F && priv->rtl_chip != RTL8710B) 4245 /* Firmware will control REG_DRVERLYINT when power saving is enable, */ 4246 /* so don't set this register on STA mode. */ 4247 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME); 4248 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME); 4249 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F); 4250 4251 /* 4252 * Initialize burst parameters 4253 */ 4254 if (priv->fops->init_burst) 4255 priv->fops->init_burst(priv); 4256 4257 if (fops->init_aggregation) 4258 fops->init_aggregation(priv); 4259 4260 if (fops->init_reg_pkt_life_time) { 4261 rtl8xxxu_write16(priv, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ 4262 rtl8xxxu_write16(priv, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ 4263 } 4264 4265 /* 4266 * Enable CCK and OFDM block 4267 */ 4268 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 4269 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM); 4270 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 4271 4272 /* 4273 * Invalidate all CAM entries - bit 30 is undocumented 4274 */ 4275 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30)); 4276 4277 /* 4278 * Start out with default power levels for channel 6, 20MHz 4279 */ 4280 fops->set_tx_power(priv, 1, false); 4281 4282 /* Let the 8051 take control of antenna setting */ 4283 if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188F && 4284 priv->rtl_chip != RTL8710B) { 4285 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); 4286 val8 |= LEDCFG2_DPDT_SELECT; 4287 rtl8xxxu_write8(priv, REG_LEDCFG2, val8); 4288 } 4289 4290 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff); 4291 4292 /* Disable BAR - not sure if this has any effect on USB */ 4293 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff); 4294 4295 if (priv->rtl_chip != RTL8188F && priv->rtl_chip != RTL8188E && priv->rtl_chip != RTL8710B) 4296 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0); 4297 4298 if (fops->init_statistics) 4299 fops->init_statistics(priv); 4300 4301 if (priv->rtl_chip == RTL8192E) { 4302 /* 4303 * 0x4c6[3] 1: RTS BW = Data BW 4304 * 0: RTS BW depends on CCA / secondary CCA result. 4305 */ 4306 val8 = rtl8xxxu_read8(priv, REG_QUEUE_CTRL); 4307 val8 &= ~BIT(3); 4308 rtl8xxxu_write8(priv, REG_QUEUE_CTRL, val8); 4309 /* 4310 * Reset USB mode switch setting 4311 */ 4312 rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00); 4313 } else if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8188E) { 4314 /* 4315 * Init GPIO settings for 8188f, 8188e 4316 */ 4317 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG); 4318 val8 &= ~GPIO_MUXCFG_IO_SEL_ENBT; 4319 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8); 4320 } 4321 4322 if (priv->rtl_chip == RTL8188F) 4323 /* CCK PD */ 4324 rtl8xxxu_write8(priv, REG_CCK_PD_THRESH, CCK_PD_TYPE1_LV1_TH); 4325 4326 fops->phy_lc_calibrate(priv); 4327 4328 fops->phy_iq_calibrate(priv); 4329 4330 /* 4331 * This should enable thermal meter 4332 */ 4333 if (fops->gen2_thermal_meter) { 4334 if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8710B) { 4335 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B); 4336 val32 |= 0x30000; 4337 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B, val32); 4338 } else { 4339 rtl8xxxu_write_rfreg(priv, 4340 RF_A, RF6052_REG_T_METER_8723B, 0x37cf8); 4341 } 4342 } else { 4343 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60); 4344 } 4345 4346 /* Set NAV_UPPER to 30000us */ 4347 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT); 4348 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8); 4349 4350 if (priv->rtl_chip == RTL8723A) { 4351 /* 4352 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test, 4353 * but we need to find root cause. 4354 * This is 8723au only. 4355 */ 4356 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 4357 if ((val32 & 0xff000000) != 0x83000000) { 4358 val32 |= FPGA_RF_MODE_CCK; 4359 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 4360 } 4361 } else if (priv->rtl_chip == RTL8192E || priv->rtl_chip == RTL8188E) { 4362 rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00); 4363 } 4364 4365 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL); 4366 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK; 4367 /* ack for xmit mgmt frames. */ 4368 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32); 4369 4370 if (priv->rtl_chip == RTL8192E) { 4371 /* 4372 * Fix LDPC rx hang issue. 4373 */ 4374 val32 = rtl8xxxu_read32(priv, REG_AFE_MISC); 4375 rtl8xxxu_write8(priv, REG_8192E_LDOV12_CTRL, 0x75); 4376 val32 &= 0xfff00fff; 4377 val32 |= 0x0007e000; 4378 rtl8xxxu_write32(priv, REG_AFE_MISC, val32); 4379 4380 /* 4381 * 0x824[9] = 0x82C[9] = 0xA80[7] those registers setting 4382 * should be equal or CCK RSSI report may be incorrect 4383 */ 4384 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2); 4385 priv->cck_agc_report_type = 4386 u32_get_bits(val32, FPGA0_HSSI_PARM2_CCK_HIGH_PWR); 4387 4388 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_HSSI_PARM2); 4389 if (priv->cck_agc_report_type != 4390 u32_get_bits(val32, FPGA0_HSSI_PARM2_CCK_HIGH_PWR)) { 4391 if (priv->cck_agc_report_type) 4392 val32 |= FPGA0_HSSI_PARM2_CCK_HIGH_PWR; 4393 else 4394 val32 &= ~FPGA0_HSSI_PARM2_CCK_HIGH_PWR; 4395 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM2, val32); 4396 } 4397 4398 val32 = rtl8xxxu_read32(priv, REG_AGC_RPT); 4399 if (priv->cck_agc_report_type) 4400 val32 |= AGC_RPT_CCK; 4401 else 4402 val32 &= ~AGC_RPT_CCK; 4403 rtl8xxxu_write32(priv, REG_AGC_RPT, val32); 4404 } 4405 4406 if (priv->rtl_chip == RTL8710B) { 4407 /* 4408 * 0x76D[5:4] is Port0,Port1 Enable Bit. 4409 * This is only for 8710B, 2b'00 for MP and 2b'11 for Normal Driver 4410 */ 4411 val8 = rtl8xxxu_read8(priv, REG_PORT_CONTROL_8710B); 4412 val8 |= BIT(5) | BIT(4); 4413 rtl8xxxu_write8(priv, REG_PORT_CONTROL_8710B, val8); 4414 4415 /* Set 0x5c[8] and [2:0] = 1, LDO mode */ 4416 val32 = rtl8xxxu_read32(priv, REG_WL_RF_PSS_8710B); 4417 val32 |= 0x107; 4418 rtl8xxxu_write32(priv, REG_WL_RF_PSS_8710B, val32); 4419 } 4420 4421 val32 = rtl8xxxu_read32(priv, 0xa9c); 4422 priv->cck_new_agc = u32_get_bits(val32, BIT(17)); 4423 4424 /* Initialise the center frequency offset tracking */ 4425 if (priv->fops->set_crystal_cap) { 4426 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); 4427 priv->cfo_tracking.atc_status = val32 & CFO_TRACKING_ATC_STATUS; 4428 priv->cfo_tracking.adjust = true; 4429 priv->cfo_tracking.crystal_cap = priv->default_crystal_cap; 4430 } 4431 4432 if (priv->rtl_chip == RTL8188E) 4433 rtl8188e_ra_info_init_all(&priv->ra_info); 4434 4435 exit: 4436 return ret; 4437 } 4438 4439 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv, 4440 struct ieee80211_key_conf *key, const u8 *mac) 4441 { 4442 u32 cmd, val32, addr, ctrl; 4443 int j, i, tmp_debug; 4444 4445 tmp_debug = rtl8xxxu_debug; 4446 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY) 4447 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE; 4448 4449 /* 4450 * This is a bit of a hack - the lower bits of the cipher 4451 * suite selector happens to match the cipher index in the CAM 4452 */ 4453 addr = key->keyidx << CAM_CMD_KEY_SHIFT; 4454 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID; 4455 4456 for (j = 5; j >= 0; j--) { 4457 switch (j) { 4458 case 0: 4459 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24); 4460 break; 4461 case 1: 4462 val32 = mac[2] | (mac[3] << 8) | 4463 (mac[4] << 16) | (mac[5] << 24); 4464 break; 4465 default: 4466 i = (j - 2) << 2; 4467 val32 = key->key[i] | (key->key[i + 1] << 8) | 4468 key->key[i + 2] << 16 | key->key[i + 3] << 24; 4469 break; 4470 } 4471 4472 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32); 4473 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j); 4474 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd); 4475 udelay(100); 4476 } 4477 4478 rtl8xxxu_debug = tmp_debug; 4479 } 4480 4481 static 4482 int rtl8xxxu_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) 4483 { 4484 struct rtl8xxxu_priv *priv = hw->priv; 4485 4486 *tx_ant = BIT(priv->tx_paths) - 1; 4487 *rx_ant = BIT(priv->rx_paths) - 1; 4488 4489 return 0; 4490 } 4491 4492 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw, 4493 struct ieee80211_vif *vif, const u8 *mac) 4494 { 4495 struct rtl8xxxu_priv *priv = hw->priv; 4496 u8 val8; 4497 4498 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 4499 val8 |= BEACON_DISABLE_TSF_UPDATE; 4500 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 4501 } 4502 4503 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw, 4504 struct ieee80211_vif *vif) 4505 { 4506 struct rtl8xxxu_priv *priv = hw->priv; 4507 u8 val8; 4508 4509 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 4510 val8 &= ~BEACON_DISABLE_TSF_UPDATE; 4511 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 4512 } 4513 4514 void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv, 4515 u32 ramask, u8 rateid, int sgi, int txbw_40mhz) 4516 { 4517 struct h2c_cmd h2c; 4518 4519 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4520 4521 h2c.ramask.cmd = H2C_SET_RATE_MASK; 4522 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff); 4523 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16); 4524 4525 h2c.ramask.arg = 0x80; 4526 if (sgi) 4527 h2c.ramask.arg |= 0x20; 4528 4529 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n", 4530 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask)); 4531 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.ramask)); 4532 } 4533 4534 void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv, 4535 u32 ramask, u8 rateid, int sgi, int txbw_40mhz) 4536 { 4537 struct h2c_cmd h2c; 4538 u8 bw; 4539 4540 if (txbw_40mhz) 4541 bw = RTL8XXXU_CHANNEL_WIDTH_40; 4542 else 4543 bw = RTL8XXXU_CHANNEL_WIDTH_20; 4544 4545 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4546 4547 h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID; 4548 h2c.b_macid_cfg.ramask0 = ramask & 0xff; 4549 h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff; 4550 h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff; 4551 h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff; 4552 4553 h2c.b_macid_cfg.data1 = rateid; 4554 if (sgi) 4555 h2c.b_macid_cfg.data1 |= BIT(7); 4556 4557 h2c.b_macid_cfg.data2 = bw; 4558 4559 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, rateid %02x, sgi %d, size %zi\n", 4560 __func__, ramask, rateid, sgi, sizeof(h2c.b_macid_cfg)); 4561 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg)); 4562 } 4563 4564 void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv, 4565 u8 macid, bool connect) 4566 { 4567 struct h2c_cmd h2c; 4568 4569 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4570 4571 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT; 4572 4573 if (connect) 4574 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT; 4575 else 4576 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT; 4577 4578 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss)); 4579 } 4580 4581 void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv, 4582 u8 macid, bool connect) 4583 { 4584 /* 4585 * The firmware turns on the rate control when it knows it's 4586 * connected to a network. 4587 */ 4588 struct h2c_cmd h2c; 4589 4590 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4591 4592 h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT; 4593 if (connect) 4594 h2c.media_status_rpt.parm |= BIT(0); 4595 else 4596 h2c.media_status_rpt.parm &= ~BIT(0); 4597 4598 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt)); 4599 } 4600 4601 void rtl8xxxu_gen1_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi) 4602 { 4603 struct h2c_cmd h2c; 4604 const int h2c_size = 4; 4605 4606 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4607 4608 h2c.rssi_report.cmd = H2C_SET_RSSI; 4609 h2c.rssi_report.macid = macid; 4610 h2c.rssi_report.rssi = rssi; 4611 4612 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, h2c_size); 4613 } 4614 4615 void rtl8xxxu_gen2_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi) 4616 { 4617 struct h2c_cmd h2c; 4618 int h2c_size = sizeof(h2c.rssi_report); 4619 4620 if (priv->rtl_chip == RTL8723B) 4621 h2c_size = 4; 4622 4623 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4624 4625 h2c.rssi_report.cmd = H2C_8723B_RSSI_SETTING; 4626 h2c.rssi_report.macid = macid; 4627 h2c.rssi_report.rssi = rssi; 4628 4629 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, h2c_size); 4630 } 4631 4632 void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv) 4633 { 4634 u8 agg_ctrl, usb_spec, page_thresh, timeout; 4635 4636 usb_spec = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION); 4637 usb_spec &= ~USB_SPEC_USB_AGG_ENABLE; 4638 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, usb_spec); 4639 4640 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); 4641 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; 4642 4643 if (!rtl8xxxu_dma_aggregation) { 4644 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); 4645 return; 4646 } 4647 4648 agg_ctrl |= TRXDMA_CTRL_RXDMA_AGG_EN; 4649 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); 4650 4651 /* 4652 * The number of packets we can take looks to be buffer size / 512 4653 * which matches the 512 byte rounding we have to do when de-muxing 4654 * the packets. 4655 * 4656 * Sample numbers from the vendor driver: 4657 * USB High-Speed mode values: 4658 * RxAggBlockCount = 8 : 512 byte unit 4659 * RxAggBlockTimeout = 6 4660 * RxAggPageCount = 48 : 128 byte unit 4661 * RxAggPageTimeout = 4 or 6 (absolute time 34ms/(2^6)) 4662 */ 4663 4664 page_thresh = (priv->fops->rx_agg_buf_size / 512); 4665 if (rtl8xxxu_dma_agg_pages >= 0) { 4666 if (rtl8xxxu_dma_agg_pages <= page_thresh) 4667 timeout = page_thresh; 4668 else if (rtl8xxxu_dma_agg_pages <= 6) 4669 dev_err(&priv->udev->dev, 4670 "%s: dma_agg_pages=%i too small, minimum is 6\n", 4671 __func__, rtl8xxxu_dma_agg_pages); 4672 else 4673 dev_err(&priv->udev->dev, 4674 "%s: dma_agg_pages=%i larger than limit %i\n", 4675 __func__, rtl8xxxu_dma_agg_pages, page_thresh); 4676 } 4677 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH, page_thresh); 4678 /* 4679 * REG_RXDMA_AGG_PG_TH + 1 seems to be the timeout register on 4680 * gen2 chips and rtl8188eu. The rtl8723au seems unhappy if we 4681 * don't set it, so better set both. 4682 */ 4683 timeout = 4; 4684 4685 if (rtl8xxxu_dma_agg_timeout >= 0) { 4686 if (rtl8xxxu_dma_agg_timeout <= 127) 4687 timeout = rtl8xxxu_dma_agg_timeout; 4688 else 4689 dev_err(&priv->udev->dev, 4690 "%s: Invalid dma_agg_timeout: %i\n", 4691 __func__, rtl8xxxu_dma_agg_timeout); 4692 } 4693 4694 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH + 1, timeout); 4695 rtl8xxxu_write8(priv, REG_USB_DMA_AGG_TO, timeout); 4696 priv->rx_buf_aggregation = 1; 4697 } 4698 4699 static const struct ieee80211_rate rtl8xxxu_legacy_ratetable[] = { 4700 {.bitrate = 10, .hw_value = 0x00,}, 4701 {.bitrate = 20, .hw_value = 0x01,}, 4702 {.bitrate = 55, .hw_value = 0x02,}, 4703 {.bitrate = 110, .hw_value = 0x03,}, 4704 {.bitrate = 60, .hw_value = 0x04,}, 4705 {.bitrate = 90, .hw_value = 0x05,}, 4706 {.bitrate = 120, .hw_value = 0x06,}, 4707 {.bitrate = 180, .hw_value = 0x07,}, 4708 {.bitrate = 240, .hw_value = 0x08,}, 4709 {.bitrate = 360, .hw_value = 0x09,}, 4710 {.bitrate = 480, .hw_value = 0x0a,}, 4711 {.bitrate = 540, .hw_value = 0x0b,}, 4712 }; 4713 4714 static void rtl8xxxu_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss) 4715 { 4716 if (rate <= DESC_RATE_54M) 4717 return; 4718 4719 if (rate >= DESC_RATE_MCS0 && rate <= DESC_RATE_MCS15) { 4720 if (rate < DESC_RATE_MCS8) 4721 *nss = 1; 4722 else 4723 *nss = 2; 4724 *mcs = rate - DESC_RATE_MCS0; 4725 } 4726 } 4727 4728 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg) 4729 { 4730 struct ieee80211_hw *hw = priv->hw; 4731 u32 val32; 4732 u8 rate_idx = 0; 4733 4734 rate_cfg &= RESPONSE_RATE_BITMAP_ALL; 4735 4736 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 4737 if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ) 4738 val32 &= RESPONSE_RATE_RRSR_INIT_5G; 4739 else 4740 val32 &= RESPONSE_RATE_RRSR_INIT_2G; 4741 val32 |= rate_cfg; 4742 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 4743 4744 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg); 4745 4746 while (rate_cfg) { 4747 rate_cfg = (rate_cfg >> 1); 4748 rate_idx++; 4749 } 4750 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx); 4751 } 4752 4753 static u16 4754 rtl8xxxu_wireless_mode(struct ieee80211_hw *hw, struct ieee80211_sta *sta) 4755 { 4756 u16 network_type = WIRELESS_MODE_UNKNOWN; 4757 4758 if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ) { 4759 if (sta->deflink.vht_cap.vht_supported) 4760 network_type = WIRELESS_MODE_AC; 4761 else if (sta->deflink.ht_cap.ht_supported) 4762 network_type = WIRELESS_MODE_N_5G; 4763 4764 network_type |= WIRELESS_MODE_A; 4765 } else { 4766 if (sta->deflink.vht_cap.vht_supported) 4767 network_type = WIRELESS_MODE_AC; 4768 else if (sta->deflink.ht_cap.ht_supported) 4769 network_type = WIRELESS_MODE_N_24G; 4770 4771 if (sta->deflink.supp_rates[0] <= 0xf) 4772 network_type |= WIRELESS_MODE_B; 4773 else if (sta->deflink.supp_rates[0] & 0xf) 4774 network_type |= (WIRELESS_MODE_B | WIRELESS_MODE_G); 4775 else 4776 network_type |= WIRELESS_MODE_G; 4777 } 4778 4779 return network_type; 4780 } 4781 4782 static void rtl8xxxu_set_aifs(struct rtl8xxxu_priv *priv, u8 slot_time) 4783 { 4784 u32 reg_edca_param[IEEE80211_NUM_ACS] = { 4785 [IEEE80211_AC_VO] = REG_EDCA_VO_PARAM, 4786 [IEEE80211_AC_VI] = REG_EDCA_VI_PARAM, 4787 [IEEE80211_AC_BE] = REG_EDCA_BE_PARAM, 4788 [IEEE80211_AC_BK] = REG_EDCA_BK_PARAM, 4789 }; 4790 u32 val32; 4791 u16 wireless_mode = 0; 4792 u8 aifs, aifsn, sifs; 4793 int i; 4794 4795 if (priv->vif) { 4796 struct ieee80211_sta *sta; 4797 4798 rcu_read_lock(); 4799 sta = ieee80211_find_sta(priv->vif, priv->vif->bss_conf.bssid); 4800 if (sta) 4801 wireless_mode = rtl8xxxu_wireless_mode(priv->hw, sta); 4802 rcu_read_unlock(); 4803 } 4804 4805 if (priv->hw->conf.chandef.chan->band == NL80211_BAND_5GHZ || 4806 (wireless_mode & WIRELESS_MODE_N_24G)) 4807 sifs = 16; 4808 else 4809 sifs = 10; 4810 4811 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 4812 val32 = rtl8xxxu_read32(priv, reg_edca_param[i]); 4813 4814 /* It was set in conf_tx. */ 4815 aifsn = val32 & 0xff; 4816 4817 /* aifsn not set yet or already fixed */ 4818 if (aifsn < 2 || aifsn > 15) 4819 continue; 4820 4821 aifs = aifsn * slot_time + sifs; 4822 4823 val32 &= ~0xff; 4824 val32 |= aifs; 4825 rtl8xxxu_write32(priv, reg_edca_param[i], val32); 4826 } 4827 } 4828 4829 void rtl8xxxu_update_ra_report(struct rtl8xxxu_ra_report *rarpt, 4830 u8 rate, u8 sgi, u8 bw) 4831 { 4832 u8 mcs, nss; 4833 4834 rarpt->txrate.flags = 0; 4835 4836 if (rate <= DESC_RATE_54M) { 4837 rarpt->txrate.legacy = rtl8xxxu_legacy_ratetable[rate].bitrate; 4838 } else { 4839 rtl8xxxu_desc_to_mcsrate(rate, &mcs, &nss); 4840 rarpt->txrate.flags |= RATE_INFO_FLAGS_MCS; 4841 4842 rarpt->txrate.mcs = mcs; 4843 rarpt->txrate.nss = nss; 4844 4845 if (sgi) 4846 rarpt->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 4847 4848 rarpt->txrate.bw = bw; 4849 } 4850 4851 rarpt->bit_rate = cfg80211_calculate_bitrate(&rarpt->txrate); 4852 rarpt->desc_rate = rate; 4853 } 4854 4855 static void 4856 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 4857 struct ieee80211_bss_conf *bss_conf, u64 changed) 4858 { 4859 struct rtl8xxxu_priv *priv = hw->priv; 4860 struct device *dev = &priv->udev->dev; 4861 struct ieee80211_sta *sta; 4862 struct rtl8xxxu_ra_report *rarpt; 4863 u32 val32; 4864 u8 val8; 4865 4866 rarpt = &priv->ra_report; 4867 4868 if (changed & BSS_CHANGED_ASSOC) { 4869 dev_dbg(dev, "Changed ASSOC: %i!\n", vif->cfg.assoc); 4870 4871 rtl8xxxu_set_linktype(priv, vif->type); 4872 4873 if (vif->cfg.assoc) { 4874 u32 ramask; 4875 int sgi = 0; 4876 u8 highest_rate; 4877 u8 bw; 4878 4879 rcu_read_lock(); 4880 sta = ieee80211_find_sta(vif, bss_conf->bssid); 4881 if (!sta) { 4882 dev_info(dev, "%s: ASSOC no sta found\n", 4883 __func__); 4884 rcu_read_unlock(); 4885 goto error; 4886 } 4887 4888 if (sta->deflink.ht_cap.ht_supported) 4889 dev_info(dev, "%s: HT supported\n", __func__); 4890 if (sta->deflink.vht_cap.vht_supported) 4891 dev_info(dev, "%s: VHT supported\n", __func__); 4892 4893 /* TODO: Set bits 28-31 for rate adaptive id */ 4894 ramask = (sta->deflink.supp_rates[0] & 0xfff) | 4895 sta->deflink.ht_cap.mcs.rx_mask[0] << 12 | 4896 sta->deflink.ht_cap.mcs.rx_mask[1] << 20; 4897 if (sta->deflink.ht_cap.cap & 4898 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)) 4899 sgi = 1; 4900 4901 highest_rate = fls(ramask) - 1; 4902 if (rtl8xxxu_ht40_2g && 4903 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)) 4904 bw = RATE_INFO_BW_40; 4905 else 4906 bw = RATE_INFO_BW_20; 4907 rcu_read_unlock(); 4908 4909 rtl8xxxu_update_ra_report(rarpt, highest_rate, sgi, bw); 4910 4911 priv->vif = vif; 4912 priv->rssi_level = RTL8XXXU_RATR_STA_INIT; 4913 4914 priv->fops->update_rate_mask(priv, ramask, 0, sgi, bw == RATE_INFO_BW_40); 4915 4916 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff); 4917 4918 rtl8xxxu_stop_tx_beacon(priv); 4919 4920 /* joinbss sequence */ 4921 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT, 4922 0xc000 | vif->cfg.aid); 4923 4924 priv->fops->report_connect(priv, 0, true); 4925 } else { 4926 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 4927 val8 |= BEACON_DISABLE_TSF_UPDATE; 4928 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 4929 4930 priv->fops->report_connect(priv, 0, false); 4931 } 4932 } 4933 4934 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 4935 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n", 4936 bss_conf->use_short_preamble); 4937 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 4938 if (bss_conf->use_short_preamble) 4939 val32 |= RSR_ACK_SHORT_PREAMBLE; 4940 else 4941 val32 &= ~RSR_ACK_SHORT_PREAMBLE; 4942 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 4943 } 4944 4945 if (changed & BSS_CHANGED_ERP_SLOT) { 4946 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n", 4947 bss_conf->use_short_slot); 4948 4949 if (bss_conf->use_short_slot) 4950 val8 = 9; 4951 else 4952 val8 = 20; 4953 rtl8xxxu_write8(priv, REG_SLOT, val8); 4954 4955 rtl8xxxu_set_aifs(priv, val8); 4956 } 4957 4958 if (changed & BSS_CHANGED_BSSID) { 4959 dev_dbg(dev, "Changed BSSID!\n"); 4960 rtl8xxxu_set_bssid(priv, bss_conf->bssid); 4961 } 4962 4963 if (changed & BSS_CHANGED_BASIC_RATES) { 4964 dev_dbg(dev, "Changed BASIC_RATES!\n"); 4965 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates); 4966 } 4967 error: 4968 return; 4969 } 4970 4971 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue) 4972 { 4973 u32 rtlqueue; 4974 4975 switch (queue) { 4976 case IEEE80211_AC_VO: 4977 rtlqueue = TXDESC_QUEUE_VO; 4978 break; 4979 case IEEE80211_AC_VI: 4980 rtlqueue = TXDESC_QUEUE_VI; 4981 break; 4982 case IEEE80211_AC_BE: 4983 rtlqueue = TXDESC_QUEUE_BE; 4984 break; 4985 case IEEE80211_AC_BK: 4986 rtlqueue = TXDESC_QUEUE_BK; 4987 break; 4988 default: 4989 rtlqueue = TXDESC_QUEUE_BE; 4990 } 4991 4992 return rtlqueue; 4993 } 4994 4995 static u32 rtl8xxxu_queue_select(struct ieee80211_hdr *hdr, struct sk_buff *skb) 4996 { 4997 u32 queue; 4998 4999 if (ieee80211_is_mgmt(hdr->frame_control)) 5000 queue = TXDESC_QUEUE_MGNT; 5001 else 5002 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb)); 5003 5004 return queue; 5005 } 5006 5007 /* 5008 * Despite newer chips 8723b/8812/8821 having a larger TX descriptor 5009 * format. The descriptor checksum is still only calculated over the 5010 * initial 32 bytes of the descriptor! 5011 */ 5012 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc) 5013 { 5014 __le16 *ptr = (__le16 *)tx_desc; 5015 u16 csum = 0; 5016 int i; 5017 5018 /* 5019 * Clear csum field before calculation, as the csum field is 5020 * in the middle of the struct. 5021 */ 5022 tx_desc->csum = cpu_to_le16(0); 5023 5024 for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++) 5025 csum = csum ^ le16_to_cpu(ptr[i]); 5026 5027 tx_desc->csum |= cpu_to_le16(csum); 5028 } 5029 5030 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv) 5031 { 5032 struct rtl8xxxu_tx_urb *tx_urb, *tmp; 5033 unsigned long flags; 5034 5035 spin_lock_irqsave(&priv->tx_urb_lock, flags); 5036 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) { 5037 list_del(&tx_urb->list); 5038 priv->tx_urb_free_count--; 5039 usb_free_urb(&tx_urb->urb); 5040 } 5041 spin_unlock_irqrestore(&priv->tx_urb_lock, flags); 5042 } 5043 5044 static struct rtl8xxxu_tx_urb * 5045 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv) 5046 { 5047 struct rtl8xxxu_tx_urb *tx_urb; 5048 unsigned long flags; 5049 5050 spin_lock_irqsave(&priv->tx_urb_lock, flags); 5051 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list, 5052 struct rtl8xxxu_tx_urb, list); 5053 if (tx_urb) { 5054 list_del(&tx_urb->list); 5055 priv->tx_urb_free_count--; 5056 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER && 5057 !priv->tx_stopped) { 5058 priv->tx_stopped = true; 5059 ieee80211_stop_queues(priv->hw); 5060 } 5061 } 5062 5063 spin_unlock_irqrestore(&priv->tx_urb_lock, flags); 5064 5065 return tx_urb; 5066 } 5067 5068 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv, 5069 struct rtl8xxxu_tx_urb *tx_urb) 5070 { 5071 unsigned long flags; 5072 5073 INIT_LIST_HEAD(&tx_urb->list); 5074 5075 spin_lock_irqsave(&priv->tx_urb_lock, flags); 5076 5077 list_add(&tx_urb->list, &priv->tx_urb_free_list); 5078 priv->tx_urb_free_count++; 5079 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER && 5080 priv->tx_stopped) { 5081 priv->tx_stopped = false; 5082 ieee80211_wake_queues(priv->hw); 5083 } 5084 5085 spin_unlock_irqrestore(&priv->tx_urb_lock, flags); 5086 } 5087 5088 static void rtl8xxxu_tx_complete(struct urb *urb) 5089 { 5090 struct sk_buff *skb = (struct sk_buff *)urb->context; 5091 struct ieee80211_tx_info *tx_info; 5092 struct ieee80211_hw *hw; 5093 struct rtl8xxxu_priv *priv; 5094 struct rtl8xxxu_tx_urb *tx_urb = 5095 container_of(urb, struct rtl8xxxu_tx_urb, urb); 5096 5097 tx_info = IEEE80211_SKB_CB(skb); 5098 hw = tx_info->rate_driver_data[0]; 5099 priv = hw->priv; 5100 5101 skb_pull(skb, priv->fops->tx_desc_size); 5102 5103 ieee80211_tx_info_clear_status(tx_info); 5104 tx_info->status.rates[0].idx = -1; 5105 tx_info->status.rates[0].count = 0; 5106 5107 if (!urb->status) 5108 tx_info->flags |= IEEE80211_TX_STAT_ACK; 5109 5110 ieee80211_tx_status_irqsafe(hw, skb); 5111 5112 rtl8xxxu_free_tx_urb(priv, tx_urb); 5113 } 5114 5115 static void rtl8xxxu_dump_action(struct device *dev, 5116 struct ieee80211_hdr *hdr) 5117 { 5118 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr; 5119 u16 cap, timeout; 5120 5121 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION)) 5122 return; 5123 5124 switch (mgmt->u.action.u.addba_resp.action_code) { 5125 case WLAN_ACTION_ADDBA_RESP: 5126 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab); 5127 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout); 5128 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: " 5129 "timeout %i, tid %02x, buf_size %02x, policy %02x, " 5130 "status %02x\n", 5131 timeout, 5132 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2, 5133 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6, 5134 (cap >> 1) & 0x1, 5135 le16_to_cpu(mgmt->u.action.u.addba_resp.status)); 5136 break; 5137 case WLAN_ACTION_ADDBA_REQ: 5138 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab); 5139 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout); 5140 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: " 5141 "timeout %i, tid %02x, buf_size %02x, policy %02x\n", 5142 timeout, 5143 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2, 5144 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6, 5145 (cap >> 1) & 0x1); 5146 break; 5147 default: 5148 dev_info(dev, "action frame %02x\n", 5149 mgmt->u.action.u.addba_resp.action_code); 5150 break; 5151 } 5152 } 5153 5154 /* 5155 * Fill in v1 (gen1) specific TX descriptor bits. 5156 * This format is used on 8188cu/8192cu/8723au 5157 */ 5158 void 5159 rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 5160 struct ieee80211_tx_info *tx_info, 5161 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 5162 bool short_preamble, bool ampdu_enable, u32 rts_rate) 5163 { 5164 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info); 5165 struct rtl8xxxu_priv *priv = hw->priv; 5166 struct device *dev = &priv->udev->dev; 5167 u8 *qc = ieee80211_get_qos_ctl(hdr); 5168 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; 5169 u32 rate; 5170 u16 rate_flags = tx_info->control.rates[0].flags; 5171 u16 seq_number; 5172 5173 if (rate_flags & IEEE80211_TX_RC_MCS && 5174 !ieee80211_is_mgmt(hdr->frame_control)) 5175 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0; 5176 else 5177 rate = tx_rate->hw_value; 5178 5179 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) 5180 dev_info(dev, "%s: TX rate: %d, pkt size %u\n", 5181 __func__, rate, le16_to_cpu(tx_desc->pkt_size)); 5182 5183 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 5184 5185 tx_desc->txdw5 = cpu_to_le32(rate); 5186 5187 if (ieee80211_is_data(hdr->frame_control)) 5188 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00); 5189 5190 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT); 5191 5192 if (ampdu_enable && test_bit(tid, priv->tid_tx_operational)) 5193 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE); 5194 else 5195 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK); 5196 5197 if (ieee80211_is_mgmt(hdr->frame_control)) { 5198 tx_desc->txdw5 = cpu_to_le32(rate); 5199 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE); 5200 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT); 5201 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE); 5202 } 5203 5204 if (ieee80211_is_data_qos(hdr->frame_control)) 5205 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS); 5206 5207 if (short_preamble) 5208 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE); 5209 5210 if (sgi) 5211 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI); 5212 5213 /* 5214 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled 5215 */ 5216 tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT); 5217 if (ampdu_enable || (rate_flags & IEEE80211_TX_RC_USE_RTS_CTS)) { 5218 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE); 5219 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); 5220 } else if (rate_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 5221 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE); 5222 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); 5223 } 5224 } 5225 5226 /* 5227 * Fill in v2 (gen2) specific TX descriptor bits. 5228 * This format is used on 8192eu/8723bu 5229 */ 5230 void 5231 rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 5232 struct ieee80211_tx_info *tx_info, 5233 struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi, 5234 bool short_preamble, bool ampdu_enable, u32 rts_rate) 5235 { 5236 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info); 5237 struct rtl8xxxu_priv *priv = hw->priv; 5238 struct device *dev = &priv->udev->dev; 5239 struct rtl8xxxu_txdesc40 *tx_desc40; 5240 u8 *qc = ieee80211_get_qos_ctl(hdr); 5241 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; 5242 u32 rate; 5243 u16 rate_flags = tx_info->control.rates[0].flags; 5244 u16 seq_number; 5245 5246 tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc32; 5247 5248 if (rate_flags & IEEE80211_TX_RC_MCS && 5249 !ieee80211_is_mgmt(hdr->frame_control)) 5250 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0; 5251 else 5252 rate = tx_rate->hw_value; 5253 5254 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) 5255 dev_info(dev, "%s: TX rate: %d, pkt size %u\n", 5256 __func__, rate, le16_to_cpu(tx_desc40->pkt_size)); 5257 5258 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 5259 5260 tx_desc40->txdw4 = cpu_to_le32(rate); 5261 if (ieee80211_is_data(hdr->frame_control)) { 5262 tx_desc40->txdw4 |= cpu_to_le32(0x1f << 5263 TXDESC40_DATA_RATE_FB_SHIFT); 5264 } 5265 5266 tx_desc40->txdw9 = cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT); 5267 5268 if (ampdu_enable && test_bit(tid, priv->tid_tx_operational)) 5269 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE); 5270 else 5271 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK); 5272 5273 if (ieee80211_is_mgmt(hdr->frame_control)) { 5274 tx_desc40->txdw4 = cpu_to_le32(rate); 5275 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_USE_DRIVER_RATE); 5276 tx_desc40->txdw4 |= 5277 cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT); 5278 tx_desc40->txdw4 |= cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE); 5279 } 5280 5281 if (short_preamble) 5282 tx_desc40->txdw5 |= cpu_to_le32(TXDESC40_SHORT_PREAMBLE); 5283 5284 tx_desc40->txdw4 |= cpu_to_le32(rts_rate << TXDESC40_RTS_RATE_SHIFT); 5285 /* 5286 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled 5287 */ 5288 if (ampdu_enable || (rate_flags & IEEE80211_TX_RC_USE_RTS_CTS)) { 5289 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE); 5290 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE); 5291 } else if (rate_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 5292 /* 5293 * For some reason the vendor driver doesn't set 5294 * TXDESC40_HW_RTS_ENABLE for CTS to SELF 5295 */ 5296 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_CTS_SELF_ENABLE); 5297 } 5298 } 5299 5300 /* 5301 * Fill in v3 (gen1) specific TX descriptor bits. 5302 * This format is a hybrid between the v1 and v2 formats, only seen 5303 * on 8188eu devices so far. 5304 */ 5305 void 5306 rtl8xxxu_fill_txdesc_v3(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 5307 struct ieee80211_tx_info *tx_info, 5308 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 5309 bool short_preamble, bool ampdu_enable, u32 rts_rate) 5310 { 5311 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info); 5312 struct rtl8xxxu_priv *priv = hw->priv; 5313 struct device *dev = &priv->udev->dev; 5314 struct rtl8xxxu_ra_info *ra = &priv->ra_info; 5315 u8 *qc = ieee80211_get_qos_ctl(hdr); 5316 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; 5317 u32 rate; 5318 u16 rate_flags = tx_info->control.rates[0].flags; 5319 u16 seq_number; 5320 5321 if (rate_flags & IEEE80211_TX_RC_MCS && 5322 !ieee80211_is_mgmt(hdr->frame_control)) 5323 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0; 5324 else 5325 rate = tx_rate->hw_value; 5326 5327 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 5328 5329 if (ieee80211_is_data(hdr->frame_control)) { 5330 rate = ra->decision_rate; 5331 tx_desc->txdw5 = cpu_to_le32(rate); 5332 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE); 5333 tx_desc->txdw4 |= le32_encode_bits(ra->pt_stage, TXDESC32_PT_STAGE_MASK); 5334 /* Data/RTS rate FB limit */ 5335 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00); 5336 } 5337 5338 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) 5339 dev_info(dev, "%s: TX rate: %d, pkt size %d\n", 5340 __func__, rate, le16_to_cpu(tx_desc->pkt_size)); 5341 5342 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT); 5343 5344 if (ampdu_enable && test_bit(tid, priv->tid_tx_operational)) 5345 tx_desc->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE); 5346 else 5347 tx_desc->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK); 5348 5349 if (ieee80211_is_mgmt(hdr->frame_control)) { 5350 tx_desc->txdw5 = cpu_to_le32(rate); 5351 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE); 5352 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT); 5353 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE); 5354 } 5355 5356 if (ieee80211_is_data_qos(hdr->frame_control)) { 5357 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS); 5358 5359 if (conf_is_ht40(&hw->conf)) { 5360 tx_desc->txdw4 |= cpu_to_le32(TXDESC_DATA_BW); 5361 5362 if (conf_is_ht40_minus(&hw->conf)) 5363 tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_UPPER); 5364 else 5365 tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_LOWER); 5366 } 5367 } 5368 5369 if (short_preamble) 5370 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE); 5371 5372 if (sgi && ra->rate_sgi) 5373 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI); 5374 5375 /* 5376 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled 5377 */ 5378 tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT); 5379 if (ampdu_enable || (rate_flags & IEEE80211_TX_RC_USE_RTS_CTS)) { 5380 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE); 5381 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); 5382 } else if (rate_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 5383 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE); 5384 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); 5385 } 5386 5387 tx_desc->txdw2 |= cpu_to_le32(TXDESC_ANTENNA_SELECT_A | 5388 TXDESC_ANTENNA_SELECT_B); 5389 tx_desc->txdw7 |= cpu_to_le16(TXDESC_ANTENNA_SELECT_C >> 16); 5390 } 5391 5392 static void rtl8xxxu_tx(struct ieee80211_hw *hw, 5393 struct ieee80211_tx_control *control, 5394 struct sk_buff *skb) 5395 { 5396 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 5397 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 5398 struct rtl8xxxu_priv *priv = hw->priv; 5399 struct rtl8xxxu_txdesc32 *tx_desc; 5400 struct rtl8xxxu_tx_urb *tx_urb; 5401 struct ieee80211_sta *sta = NULL; 5402 struct ieee80211_vif *vif = tx_info->control.vif; 5403 struct device *dev = &priv->udev->dev; 5404 u32 queue, rts_rate; 5405 u16 pktlen = skb->len; 5406 u16 rate_flag = tx_info->control.rates[0].flags; 5407 int tx_desc_size = priv->fops->tx_desc_size; 5408 int ret; 5409 bool ampdu_enable, sgi = false, short_preamble = false; 5410 5411 if (skb_headroom(skb) < tx_desc_size) { 5412 dev_warn(dev, 5413 "%s: Not enough headroom (%i) for tx descriptor\n", 5414 __func__, skb_headroom(skb)); 5415 goto error; 5416 } 5417 5418 if (unlikely(skb->len > (65535 - tx_desc_size))) { 5419 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n", 5420 __func__, skb->len); 5421 goto error; 5422 } 5423 5424 tx_urb = rtl8xxxu_alloc_tx_urb(priv); 5425 if (!tx_urb) { 5426 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__); 5427 goto error; 5428 } 5429 5430 if (ieee80211_is_action(hdr->frame_control)) 5431 rtl8xxxu_dump_action(dev, hdr); 5432 5433 tx_info->rate_driver_data[0] = hw; 5434 5435 if (control && control->sta) 5436 sta = control->sta; 5437 5438 queue = rtl8xxxu_queue_select(hdr, skb); 5439 5440 tx_desc = skb_push(skb, tx_desc_size); 5441 5442 memset(tx_desc, 0, tx_desc_size); 5443 tx_desc->pkt_size = cpu_to_le16(pktlen); 5444 tx_desc->pkt_offset = tx_desc_size; 5445 5446 tx_desc->txdw0 = 5447 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT; 5448 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) || 5449 is_broadcast_ether_addr(ieee80211_get_DA(hdr))) 5450 tx_desc->txdw0 |= TXDESC_BROADMULTICAST; 5451 5452 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT); 5453 5454 if (tx_info->control.hw_key) { 5455 switch (tx_info->control.hw_key->cipher) { 5456 case WLAN_CIPHER_SUITE_WEP40: 5457 case WLAN_CIPHER_SUITE_WEP104: 5458 case WLAN_CIPHER_SUITE_TKIP: 5459 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4); 5460 break; 5461 case WLAN_CIPHER_SUITE_CCMP: 5462 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES); 5463 break; 5464 default: 5465 break; 5466 } 5467 } 5468 5469 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */ 5470 ampdu_enable = false; 5471 if (ieee80211_is_data_qos(hdr->frame_control) && sta) { 5472 if (sta->deflink.ht_cap.ht_supported) { 5473 u32 ampdu, val32; 5474 u8 *qc = ieee80211_get_qos_ctl(hdr); 5475 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; 5476 5477 ampdu = (u32)sta->deflink.ht_cap.ampdu_density; 5478 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT; 5479 tx_desc->txdw2 |= cpu_to_le32(val32); 5480 5481 ampdu_enable = true; 5482 5483 if (!test_bit(tid, priv->tx_aggr_started) && 5484 !(skb->protocol == cpu_to_be16(ETH_P_PAE))) 5485 if (!ieee80211_start_tx_ba_session(sta, tid, 0)) 5486 set_bit(tid, priv->tx_aggr_started); 5487 } 5488 } 5489 5490 if (rate_flag & IEEE80211_TX_RC_SHORT_GI || 5491 (ieee80211_is_data_qos(hdr->frame_control) && 5492 sta && sta->deflink.ht_cap.cap & 5493 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) 5494 sgi = true; 5495 5496 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE || 5497 (sta && vif && vif->bss_conf.use_short_preamble)) 5498 short_preamble = true; 5499 5500 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) 5501 rts_rate = ieee80211_get_rts_cts_rate(hw, tx_info)->hw_value; 5502 else if (rate_flag & IEEE80211_TX_RC_USE_CTS_PROTECT) 5503 rts_rate = ieee80211_get_rts_cts_rate(hw, tx_info)->hw_value; 5504 else 5505 rts_rate = 0; 5506 5507 5508 priv->fops->fill_txdesc(hw, hdr, tx_info, tx_desc, sgi, short_preamble, 5509 ampdu_enable, rts_rate); 5510 5511 rtl8xxxu_calc_tx_desc_csum(tx_desc); 5512 5513 /* avoid zero checksum make tx hang */ 5514 if (priv->rtl_chip == RTL8710B) 5515 tx_desc->csum = ~tx_desc->csum; 5516 5517 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue], 5518 skb->data, skb->len, rtl8xxxu_tx_complete, skb); 5519 5520 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor); 5521 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC); 5522 if (ret) { 5523 usb_unanchor_urb(&tx_urb->urb); 5524 rtl8xxxu_free_tx_urb(priv, tx_urb); 5525 goto error; 5526 } 5527 return; 5528 error: 5529 dev_kfree_skb(skb); 5530 } 5531 5532 void rtl8723au_rx_parse_phystats(struct rtl8xxxu_priv *priv, 5533 struct ieee80211_rx_status *rx_status, 5534 struct rtl8723au_phy_stats *phy_stats, 5535 u32 rxmcs, struct ieee80211_hdr *hdr, 5536 bool crc_icv_err) 5537 { 5538 if (phy_stats->sgi_en) 5539 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 5540 5541 if (rxmcs < DESC_RATE_6M) { 5542 /* 5543 * Handle PHY stats for CCK rates 5544 */ 5545 rx_status->signal = priv->fops->cck_rssi(priv, phy_stats); 5546 } else { 5547 bool parse_cfo = priv->fops->set_crystal_cap && 5548 priv->vif && 5549 priv->vif->type == NL80211_IFTYPE_STATION && 5550 priv->vif->cfg.assoc && 5551 !crc_icv_err && 5552 !ieee80211_is_ctl(hdr->frame_control) && 5553 ether_addr_equal(priv->vif->bss_conf.bssid, hdr->addr2); 5554 5555 if (parse_cfo) { 5556 priv->cfo_tracking.cfo_tail[0] = phy_stats->path_cfotail[0]; 5557 priv->cfo_tracking.cfo_tail[1] = phy_stats->path_cfotail[1]; 5558 5559 priv->cfo_tracking.packet_count++; 5560 } 5561 5562 rx_status->signal = 5563 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110; 5564 } 5565 } 5566 5567 static void jaguar2_rx_parse_phystats_type0(struct rtl8xxxu_priv *priv, 5568 struct ieee80211_rx_status *rx_status, 5569 struct jaguar2_phy_stats_type0 *phy_stats0, 5570 u32 rxmcs, struct ieee80211_hdr *hdr, 5571 bool crc_icv_err) 5572 { 5573 s8 rx_power = phy_stats0->pwdb - 110; 5574 5575 if (!priv->cck_new_agc) 5576 rx_power = priv->fops->cck_rssi(priv, (struct rtl8723au_phy_stats *)phy_stats0); 5577 5578 rx_status->signal = rx_power; 5579 } 5580 5581 static void jaguar2_rx_parse_phystats_type1(struct rtl8xxxu_priv *priv, 5582 struct ieee80211_rx_status *rx_status, 5583 struct jaguar2_phy_stats_type1 *phy_stats1, 5584 u32 rxmcs, struct ieee80211_hdr *hdr, 5585 bool crc_icv_err) 5586 { 5587 bool parse_cfo = priv->fops->set_crystal_cap && 5588 priv->vif && 5589 priv->vif->type == NL80211_IFTYPE_STATION && 5590 priv->vif->cfg.assoc && 5591 !crc_icv_err && 5592 !ieee80211_is_ctl(hdr->frame_control) && 5593 ether_addr_equal(priv->vif->bss_conf.bssid, hdr->addr2); 5594 u8 pwdb_max = 0; 5595 int rx_path; 5596 5597 if (parse_cfo) { 5598 /* Only path-A and path-B have CFO tail and short CFO */ 5599 priv->cfo_tracking.cfo_tail[RF_A] = phy_stats1->cfo_tail[RF_A]; 5600 priv->cfo_tracking.cfo_tail[RF_B] = phy_stats1->cfo_tail[RF_B]; 5601 5602 priv->cfo_tracking.packet_count++; 5603 } 5604 5605 for (rx_path = 0; rx_path < priv->rx_paths; rx_path++) 5606 pwdb_max = max(pwdb_max, phy_stats1->pwdb[rx_path]); 5607 5608 rx_status->signal = pwdb_max - 110; 5609 } 5610 5611 static void jaguar2_rx_parse_phystats_type2(struct rtl8xxxu_priv *priv, 5612 struct ieee80211_rx_status *rx_status, 5613 struct jaguar2_phy_stats_type2 *phy_stats2, 5614 u32 rxmcs, struct ieee80211_hdr *hdr, 5615 bool crc_icv_err) 5616 { 5617 u8 pwdb_max = 0; 5618 int rx_path; 5619 5620 for (rx_path = 0; rx_path < priv->rx_paths; rx_path++) 5621 pwdb_max = max(pwdb_max, phy_stats2->pwdb[rx_path]); 5622 5623 rx_status->signal = pwdb_max - 110; 5624 } 5625 5626 void jaguar2_rx_parse_phystats(struct rtl8xxxu_priv *priv, 5627 struct ieee80211_rx_status *rx_status, 5628 struct rtl8723au_phy_stats *phy_stats, 5629 u32 rxmcs, struct ieee80211_hdr *hdr, 5630 bool crc_icv_err) 5631 { 5632 struct jaguar2_phy_stats_type0 *phy_stats0 = (struct jaguar2_phy_stats_type0 *)phy_stats; 5633 struct jaguar2_phy_stats_type1 *phy_stats1 = (struct jaguar2_phy_stats_type1 *)phy_stats; 5634 struct jaguar2_phy_stats_type2 *phy_stats2 = (struct jaguar2_phy_stats_type2 *)phy_stats; 5635 5636 switch (phy_stats0->page_num) { 5637 case 0: 5638 /* CCK */ 5639 jaguar2_rx_parse_phystats_type0(priv, rx_status, phy_stats0, 5640 rxmcs, hdr, crc_icv_err); 5641 break; 5642 case 1: 5643 /* OFDM */ 5644 jaguar2_rx_parse_phystats_type1(priv, rx_status, phy_stats1, 5645 rxmcs, hdr, crc_icv_err); 5646 break; 5647 case 2: 5648 /* Also OFDM but different (how?) */ 5649 jaguar2_rx_parse_phystats_type2(priv, rx_status, phy_stats2, 5650 rxmcs, hdr, crc_icv_err); 5651 break; 5652 default: 5653 return; 5654 } 5655 } 5656 5657 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv) 5658 { 5659 struct rtl8xxxu_rx_urb *rx_urb, *tmp; 5660 unsigned long flags; 5661 5662 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5663 5664 list_for_each_entry_safe(rx_urb, tmp, 5665 &priv->rx_urb_pending_list, list) { 5666 list_del(&rx_urb->list); 5667 priv->rx_urb_pending_count--; 5668 usb_free_urb(&rx_urb->urb); 5669 } 5670 5671 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5672 } 5673 5674 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv, 5675 struct rtl8xxxu_rx_urb *rx_urb) 5676 { 5677 struct sk_buff *skb; 5678 unsigned long flags; 5679 int pending = 0; 5680 5681 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5682 5683 if (!priv->shutdown) { 5684 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list); 5685 priv->rx_urb_pending_count++; 5686 pending = priv->rx_urb_pending_count; 5687 } else { 5688 skb = (struct sk_buff *)rx_urb->urb.context; 5689 dev_kfree_skb_irq(skb); 5690 usb_free_urb(&rx_urb->urb); 5691 } 5692 5693 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5694 5695 if (pending > RTL8XXXU_RX_URB_PENDING_WATER) 5696 schedule_work(&priv->rx_urb_wq); 5697 } 5698 5699 static void rtl8xxxu_rx_urb_work(struct work_struct *work) 5700 { 5701 struct rtl8xxxu_priv *priv; 5702 struct rtl8xxxu_rx_urb *rx_urb, *tmp; 5703 struct list_head local; 5704 struct sk_buff *skb; 5705 unsigned long flags; 5706 int ret; 5707 5708 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq); 5709 INIT_LIST_HEAD(&local); 5710 5711 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5712 5713 list_splice_init(&priv->rx_urb_pending_list, &local); 5714 priv->rx_urb_pending_count = 0; 5715 5716 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5717 5718 list_for_each_entry_safe(rx_urb, tmp, &local, list) { 5719 list_del_init(&rx_urb->list); 5720 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb); 5721 /* 5722 * If out of memory or temporary error, put it back on the 5723 * queue and try again. Otherwise the device is dead/gone 5724 * and we should drop it. 5725 */ 5726 switch (ret) { 5727 case 0: 5728 break; 5729 case -ENOMEM: 5730 case -EAGAIN: 5731 rtl8xxxu_queue_rx_urb(priv, rx_urb); 5732 break; 5733 default: 5734 dev_warn(&priv->udev->dev, 5735 "failed to requeue urb with error %i\n", ret); 5736 skb = (struct sk_buff *)rx_urb->urb.context; 5737 dev_kfree_skb(skb); 5738 usb_free_urb(&rx_urb->urb); 5739 } 5740 } 5741 } 5742 5743 /* 5744 * The RTL8723BU/RTL8192EU vendor driver use coexistence table type 5745 * 0-7 to represent writing different combinations of register values 5746 * to REG_BT_COEX_TABLEs. It's for different kinds of coexistence use 5747 * cases which Realtek doesn't provide detail for these settings. Keep 5748 * this aligned with vendor driver for easier maintenance. 5749 */ 5750 static 5751 void rtl8723bu_set_coex_with_type(struct rtl8xxxu_priv *priv, u8 type) 5752 { 5753 switch (type) { 5754 case 0: 5755 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); 5756 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555); 5757 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5758 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5759 break; 5760 case 1: 5761 case 3: 5762 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); 5763 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a); 5764 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5765 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5766 break; 5767 case 2: 5768 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a); 5769 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a); 5770 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5771 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5772 break; 5773 case 4: 5774 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a); 5775 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaa5a5a); 5776 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5777 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5778 break; 5779 case 5: 5780 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a); 5781 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaa5a5a5a); 5782 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5783 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5784 break; 5785 case 6: 5786 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); 5787 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa); 5788 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5789 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5790 break; 5791 case 7: 5792 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0xaaaaaaaa); 5793 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa); 5794 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5795 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5796 break; 5797 default: 5798 break; 5799 } 5800 } 5801 5802 static 5803 void rtl8723bu_update_bt_link_info(struct rtl8xxxu_priv *priv, u8 bt_info) 5804 { 5805 struct rtl8xxxu_btcoex *btcoex = &priv->bt_coex; 5806 5807 if (bt_info & BT_INFO_8723B_1ANT_B_INQ_PAGE) 5808 btcoex->c2h_bt_inquiry = true; 5809 else 5810 btcoex->c2h_bt_inquiry = false; 5811 5812 if (!(bt_info & BT_INFO_8723B_1ANT_B_CONNECTION)) { 5813 btcoex->bt_status = BT_8723B_1ANT_STATUS_NON_CONNECTED_IDLE; 5814 btcoex->has_sco = false; 5815 btcoex->has_hid = false; 5816 btcoex->has_pan = false; 5817 btcoex->has_a2dp = false; 5818 } else { 5819 if ((bt_info & 0x1f) == BT_INFO_8723B_1ANT_B_CONNECTION) 5820 btcoex->bt_status = BT_8723B_1ANT_STATUS_CONNECTED_IDLE; 5821 else if ((bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) || 5822 (bt_info & BT_INFO_8723B_1ANT_B_SCO_BUSY)) 5823 btcoex->bt_status = BT_8723B_1ANT_STATUS_SCO_BUSY; 5824 else if (bt_info & BT_INFO_8723B_1ANT_B_ACL_BUSY) 5825 btcoex->bt_status = BT_8723B_1ANT_STATUS_ACL_BUSY; 5826 else 5827 btcoex->bt_status = BT_8723B_1ANT_STATUS_MAX; 5828 5829 if (bt_info & BT_INFO_8723B_1ANT_B_FTP) 5830 btcoex->has_pan = true; 5831 else 5832 btcoex->has_pan = false; 5833 5834 if (bt_info & BT_INFO_8723B_1ANT_B_A2DP) 5835 btcoex->has_a2dp = true; 5836 else 5837 btcoex->has_a2dp = false; 5838 5839 if (bt_info & BT_INFO_8723B_1ANT_B_HID) 5840 btcoex->has_hid = true; 5841 else 5842 btcoex->has_hid = false; 5843 5844 if (bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) 5845 btcoex->has_sco = true; 5846 else 5847 btcoex->has_sco = false; 5848 } 5849 5850 if (!btcoex->has_a2dp && !btcoex->has_sco && 5851 !btcoex->has_pan && btcoex->has_hid) 5852 btcoex->hid_only = true; 5853 else 5854 btcoex->hid_only = false; 5855 5856 if (!btcoex->has_sco && !btcoex->has_pan && 5857 !btcoex->has_hid && btcoex->has_a2dp) 5858 btcoex->has_a2dp = true; 5859 else 5860 btcoex->has_a2dp = false; 5861 5862 if (btcoex->bt_status == BT_8723B_1ANT_STATUS_SCO_BUSY || 5863 btcoex->bt_status == BT_8723B_1ANT_STATUS_ACL_BUSY) 5864 btcoex->bt_busy = true; 5865 else 5866 btcoex->bt_busy = false; 5867 } 5868 5869 static 5870 void rtl8723bu_handle_bt_inquiry(struct rtl8xxxu_priv *priv) 5871 { 5872 struct ieee80211_vif *vif; 5873 struct rtl8xxxu_btcoex *btcoex; 5874 bool wifi_connected; 5875 5876 vif = priv->vif; 5877 btcoex = &priv->bt_coex; 5878 wifi_connected = (vif && vif->cfg.assoc); 5879 5880 if (!wifi_connected) { 5881 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); 5882 rtl8723bu_set_coex_with_type(priv, 0); 5883 } else if (btcoex->has_sco || btcoex->has_hid || btcoex->has_a2dp) { 5884 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, 0x3, 0x11, 0x11); 5885 rtl8723bu_set_coex_with_type(priv, 4); 5886 } else if (btcoex->has_pan) { 5887 rtl8723bu_set_ps_tdma(priv, 0x61, 0x3f, 0x3, 0x11, 0x11); 5888 rtl8723bu_set_coex_with_type(priv, 4); 5889 } else { 5890 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); 5891 rtl8723bu_set_coex_with_type(priv, 7); 5892 } 5893 } 5894 5895 static 5896 void rtl8723bu_handle_bt_info(struct rtl8xxxu_priv *priv) 5897 { 5898 struct ieee80211_vif *vif; 5899 struct rtl8xxxu_btcoex *btcoex; 5900 bool wifi_connected; 5901 5902 vif = priv->vif; 5903 btcoex = &priv->bt_coex; 5904 wifi_connected = (vif && vif->cfg.assoc); 5905 5906 if (wifi_connected) { 5907 u32 val32 = 0; 5908 u32 high_prio_tx = 0, high_prio_rx = 0; 5909 5910 val32 = rtl8xxxu_read32(priv, 0x770); 5911 high_prio_tx = val32 & 0x0000ffff; 5912 high_prio_rx = (val32 & 0xffff0000) >> 16; 5913 5914 if (btcoex->bt_busy) { 5915 if (btcoex->hid_only) { 5916 rtl8723bu_set_ps_tdma(priv, 0x61, 0x20, 5917 0x3, 0x11, 0x11); 5918 rtl8723bu_set_coex_with_type(priv, 5); 5919 } else if (btcoex->a2dp_only) { 5920 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, 5921 0x3, 0x11, 0x11); 5922 rtl8723bu_set_coex_with_type(priv, 4); 5923 } else if ((btcoex->has_a2dp && btcoex->has_pan) || 5924 (btcoex->has_hid && btcoex->has_a2dp && 5925 btcoex->has_pan)) { 5926 rtl8723bu_set_ps_tdma(priv, 0x51, 0x21, 5927 0x3, 0x10, 0x10); 5928 rtl8723bu_set_coex_with_type(priv, 4); 5929 } else if (btcoex->has_hid && btcoex->has_a2dp) { 5930 rtl8723bu_set_ps_tdma(priv, 0x51, 0x21, 5931 0x3, 0x10, 0x10); 5932 rtl8723bu_set_coex_with_type(priv, 3); 5933 } else { 5934 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, 5935 0x3, 0x11, 0x11); 5936 rtl8723bu_set_coex_with_type(priv, 4); 5937 } 5938 } else { 5939 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); 5940 if (high_prio_tx + high_prio_rx <= 60) 5941 rtl8723bu_set_coex_with_type(priv, 2); 5942 else 5943 rtl8723bu_set_coex_with_type(priv, 7); 5944 } 5945 } else { 5946 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); 5947 rtl8723bu_set_coex_with_type(priv, 0); 5948 } 5949 } 5950 5951 static void rtl8xxxu_c2hcmd_callback(struct work_struct *work) 5952 { 5953 struct rtl8xxxu_priv *priv; 5954 struct rtl8723bu_c2h *c2h; 5955 struct sk_buff *skb = NULL; 5956 u8 bt_info = 0; 5957 struct rtl8xxxu_btcoex *btcoex; 5958 struct rtl8xxxu_ra_report *rarpt; 5959 u8 bw; 5960 5961 priv = container_of(work, struct rtl8xxxu_priv, c2hcmd_work); 5962 btcoex = &priv->bt_coex; 5963 rarpt = &priv->ra_report; 5964 5965 while (!skb_queue_empty(&priv->c2hcmd_queue)) { 5966 skb = skb_dequeue(&priv->c2hcmd_queue); 5967 5968 c2h = (struct rtl8723bu_c2h *)skb->data; 5969 5970 switch (c2h->id) { 5971 case C2H_8723B_BT_INFO: 5972 bt_info = c2h->bt_info.bt_info; 5973 5974 rtl8723bu_update_bt_link_info(priv, bt_info); 5975 if (btcoex->c2h_bt_inquiry) { 5976 rtl8723bu_handle_bt_inquiry(priv); 5977 break; 5978 } 5979 rtl8723bu_handle_bt_info(priv); 5980 break; 5981 case C2H_8723B_RA_REPORT: 5982 bw = rarpt->txrate.bw; 5983 5984 if (skb->len >= offsetofend(typeof(*c2h), ra_report.bw)) { 5985 if (c2h->ra_report.bw == RTL8XXXU_CHANNEL_WIDTH_40) 5986 bw = RATE_INFO_BW_40; 5987 else 5988 bw = RATE_INFO_BW_20; 5989 } 5990 5991 rtl8xxxu_update_ra_report(rarpt, c2h->ra_report.rate, 5992 c2h->ra_report.sgi, bw); 5993 break; 5994 default: 5995 break; 5996 } 5997 5998 dev_kfree_skb(skb); 5999 } 6000 } 6001 6002 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv, 6003 struct sk_buff *skb) 6004 { 6005 struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data; 6006 struct device *dev = &priv->udev->dev; 6007 int len; 6008 6009 len = skb->len - 2; 6010 6011 dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n", 6012 c2h->id, c2h->seq, len, c2h->bt_info.response_source); 6013 6014 switch(c2h->id) { 6015 case C2H_8723B_BT_INFO: 6016 if (c2h->bt_info.response_source > 6017 BT_INFO_SRC_8723B_BT_ACTIVE_SEND) 6018 dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n"); 6019 else 6020 dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n"); 6021 6022 if (c2h->bt_info.bt_has_reset) 6023 dev_dbg(dev, "BT has been reset\n"); 6024 if (c2h->bt_info.tx_rx_mask) 6025 dev_dbg(dev, "BT TRx mask\n"); 6026 6027 break; 6028 case C2H_8723B_BT_MP_INFO: 6029 dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n", 6030 c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status); 6031 break; 6032 case C2H_8723B_RA_REPORT: 6033 dev_dbg(dev, 6034 "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n", 6035 c2h->ra_report.rate, c2h->ra_report.sgi, 6036 c2h->ra_report.macid, c2h->ra_report.noisy_state); 6037 break; 6038 default: 6039 dev_info(dev, "Unhandled C2H event %02x seq %02x\n", 6040 c2h->id, c2h->seq); 6041 print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE, 6042 16, 1, c2h->raw.payload, len, false); 6043 break; 6044 } 6045 6046 skb_queue_tail(&priv->c2hcmd_queue, skb); 6047 6048 schedule_work(&priv->c2hcmd_work); 6049 } 6050 6051 static void rtl8188e_c2hcmd_callback(struct work_struct *work) 6052 { 6053 struct rtl8xxxu_priv *priv = container_of(work, struct rtl8xxxu_priv, c2hcmd_work); 6054 struct device *dev = &priv->udev->dev; 6055 struct sk_buff *skb = NULL; 6056 struct rtl8xxxu_rxdesc16 *rx_desc; 6057 6058 while (!skb_queue_empty(&priv->c2hcmd_queue)) { 6059 skb = skb_dequeue(&priv->c2hcmd_queue); 6060 6061 rx_desc = (struct rtl8xxxu_rxdesc16 *)(skb->data - sizeof(struct rtl8xxxu_rxdesc16)); 6062 6063 switch (rx_desc->rpt_sel) { 6064 case 1: 6065 dev_dbg(dev, "C2H TX report type 1\n"); 6066 6067 break; 6068 case 2: 6069 dev_dbg(dev, "C2H TX report type 2\n"); 6070 6071 rtl8188e_handle_ra_tx_report2(priv, skb); 6072 6073 break; 6074 case 3: 6075 dev_dbg(dev, "C2H USB interrupt report\n"); 6076 6077 break; 6078 default: 6079 dev_warn(dev, "%s: rpt_sel should not be %d\n", 6080 __func__, rx_desc->rpt_sel); 6081 6082 break; 6083 } 6084 6085 dev_kfree_skb(skb); 6086 } 6087 } 6088 6089 int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb) 6090 { 6091 struct ieee80211_hw *hw = priv->hw; 6092 struct ieee80211_rx_status *rx_status; 6093 struct rtl8xxxu_rxdesc16 *rx_desc; 6094 struct rtl8723au_phy_stats *phy_stats; 6095 struct sk_buff *next_skb = NULL; 6096 __le32 *_rx_desc_le; 6097 u32 *_rx_desc; 6098 int drvinfo_sz, desc_shift; 6099 int i, pkt_cnt, pkt_len, urb_len, pkt_offset; 6100 6101 urb_len = skb->len; 6102 pkt_cnt = 0; 6103 6104 if (urb_len < sizeof(struct rtl8xxxu_rxdesc16)) { 6105 kfree_skb(skb); 6106 return RX_TYPE_ERROR; 6107 } 6108 6109 do { 6110 rx_desc = (struct rtl8xxxu_rxdesc16 *)skb->data; 6111 _rx_desc_le = (__le32 *)skb->data; 6112 _rx_desc = (u32 *)skb->data; 6113 6114 for (i = 0; 6115 i < (sizeof(struct rtl8xxxu_rxdesc16) / sizeof(u32)); i++) 6116 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]); 6117 6118 /* 6119 * Only read pkt_cnt from the header if we're parsing the 6120 * first packet 6121 */ 6122 if (!pkt_cnt) 6123 pkt_cnt = rx_desc->pkt_cnt; 6124 pkt_len = rx_desc->pktlen; 6125 6126 drvinfo_sz = rx_desc->drvinfo_sz * 8; 6127 desc_shift = rx_desc->shift; 6128 pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift + 6129 sizeof(struct rtl8xxxu_rxdesc16), 128); 6130 6131 /* 6132 * Only clone the skb if there's enough data at the end to 6133 * at least cover the rx descriptor 6134 */ 6135 if (pkt_cnt > 1 && 6136 urb_len >= (pkt_offset + sizeof(struct rtl8xxxu_rxdesc16))) 6137 next_skb = skb_clone(skb, GFP_ATOMIC); 6138 6139 rx_status = IEEE80211_SKB_RXCB(skb); 6140 memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); 6141 6142 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc16)); 6143 6144 if (rx_desc->rpt_sel) { 6145 skb_queue_tail(&priv->c2hcmd_queue, skb); 6146 schedule_work(&priv->c2hcmd_work); 6147 } else { 6148 phy_stats = (struct rtl8723au_phy_stats *)skb->data; 6149 6150 skb_pull(skb, drvinfo_sz + desc_shift); 6151 6152 skb_trim(skb, pkt_len); 6153 6154 if (rx_desc->phy_stats) 6155 priv->fops->parse_phystats( 6156 priv, rx_status, phy_stats, 6157 rx_desc->rxmcs, 6158 (struct ieee80211_hdr *)skb->data, 6159 rx_desc->crc32 || rx_desc->icverr); 6160 6161 rx_status->mactime = rx_desc->tsfl; 6162 rx_status->flag |= RX_FLAG_MACTIME_START; 6163 6164 if (!rx_desc->swdec) 6165 rx_status->flag |= RX_FLAG_DECRYPTED; 6166 if (rx_desc->crc32) 6167 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 6168 if (rx_desc->bw) 6169 rx_status->bw = RATE_INFO_BW_40; 6170 6171 if (rx_desc->rxht) { 6172 rx_status->encoding = RX_ENC_HT; 6173 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0; 6174 } else { 6175 rx_status->rate_idx = rx_desc->rxmcs; 6176 } 6177 6178 rx_status->freq = hw->conf.chandef.chan->center_freq; 6179 rx_status->band = hw->conf.chandef.chan->band; 6180 6181 ieee80211_rx_irqsafe(hw, skb); 6182 } 6183 6184 skb = next_skb; 6185 if (skb) 6186 skb_pull(next_skb, pkt_offset); 6187 6188 pkt_cnt--; 6189 urb_len -= pkt_offset; 6190 next_skb = NULL; 6191 } while (skb && pkt_cnt > 0 && 6192 urb_len >= sizeof(struct rtl8xxxu_rxdesc16)); 6193 6194 return RX_TYPE_DATA_PKT; 6195 } 6196 6197 int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb) 6198 { 6199 struct ieee80211_hw *hw = priv->hw; 6200 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 6201 struct rtl8xxxu_rxdesc24 *rx_desc = 6202 (struct rtl8xxxu_rxdesc24 *)skb->data; 6203 struct rtl8723au_phy_stats *phy_stats; 6204 __le32 *_rx_desc_le = (__le32 *)skb->data; 6205 u32 *_rx_desc = (u32 *)skb->data; 6206 int drvinfo_sz, desc_shift; 6207 int i; 6208 6209 for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++) 6210 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]); 6211 6212 memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); 6213 6214 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24)); 6215 6216 phy_stats = (struct rtl8723au_phy_stats *)skb->data; 6217 6218 drvinfo_sz = rx_desc->drvinfo_sz * 8; 6219 desc_shift = rx_desc->shift; 6220 skb_pull(skb, drvinfo_sz + desc_shift); 6221 6222 if (rx_desc->rpt_sel) { 6223 struct device *dev = &priv->udev->dev; 6224 dev_dbg(dev, "%s: C2H packet\n", __func__); 6225 rtl8723bu_handle_c2h(priv, skb); 6226 return RX_TYPE_C2H; 6227 } 6228 6229 if (rx_desc->phy_stats) 6230 priv->fops->parse_phystats(priv, rx_status, phy_stats, 6231 rx_desc->rxmcs, (struct ieee80211_hdr *)skb->data, 6232 rx_desc->crc32 || rx_desc->icverr); 6233 6234 rx_status->mactime = rx_desc->tsfl; 6235 rx_status->flag |= RX_FLAG_MACTIME_START; 6236 6237 if (!rx_desc->swdec) 6238 rx_status->flag |= RX_FLAG_DECRYPTED; 6239 if (rx_desc->crc32) 6240 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 6241 if (rx_desc->bw) 6242 rx_status->bw = RATE_INFO_BW_40; 6243 6244 if (rx_desc->rxmcs >= DESC_RATE_MCS0) { 6245 rx_status->encoding = RX_ENC_HT; 6246 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0; 6247 } else { 6248 rx_status->rate_idx = rx_desc->rxmcs; 6249 } 6250 6251 rx_status->freq = hw->conf.chandef.chan->center_freq; 6252 rx_status->band = hw->conf.chandef.chan->band; 6253 6254 ieee80211_rx_irqsafe(hw, skb); 6255 return RX_TYPE_DATA_PKT; 6256 } 6257 6258 static void rtl8xxxu_rx_complete(struct urb *urb) 6259 { 6260 struct rtl8xxxu_rx_urb *rx_urb = 6261 container_of(urb, struct rtl8xxxu_rx_urb, urb); 6262 struct ieee80211_hw *hw = rx_urb->hw; 6263 struct rtl8xxxu_priv *priv = hw->priv; 6264 struct sk_buff *skb = (struct sk_buff *)urb->context; 6265 struct device *dev = &priv->udev->dev; 6266 6267 skb_put(skb, urb->actual_length); 6268 6269 if (urb->status == 0) { 6270 priv->fops->parse_rx_desc(priv, skb); 6271 6272 skb = NULL; 6273 rx_urb->urb.context = NULL; 6274 rtl8xxxu_queue_rx_urb(priv, rx_urb); 6275 } else { 6276 dev_dbg(dev, "%s: status %i\n", __func__, urb->status); 6277 goto cleanup; 6278 } 6279 return; 6280 6281 cleanup: 6282 usb_free_urb(urb); 6283 dev_kfree_skb(skb); 6284 return; 6285 } 6286 6287 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv, 6288 struct rtl8xxxu_rx_urb *rx_urb) 6289 { 6290 struct rtl8xxxu_fileops *fops = priv->fops; 6291 struct sk_buff *skb; 6292 int skb_size; 6293 int ret, rx_desc_sz; 6294 6295 rx_desc_sz = fops->rx_desc_size; 6296 6297 if (priv->rx_buf_aggregation && fops->rx_agg_buf_size) { 6298 skb_size = fops->rx_agg_buf_size; 6299 skb_size += (rx_desc_sz + sizeof(struct rtl8723au_phy_stats)); 6300 } else { 6301 skb_size = IEEE80211_MAX_FRAME_LEN; 6302 } 6303 6304 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL); 6305 if (!skb) 6306 return -ENOMEM; 6307 6308 memset(skb->data, 0, rx_desc_sz); 6309 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data, 6310 skb_size, rtl8xxxu_rx_complete, skb); 6311 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor); 6312 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC); 6313 if (ret) 6314 usb_unanchor_urb(&rx_urb->urb); 6315 return ret; 6316 } 6317 6318 static void rtl8xxxu_int_complete(struct urb *urb) 6319 { 6320 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context; 6321 struct device *dev = &priv->udev->dev; 6322 int ret; 6323 6324 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_INTERRUPT) 6325 dev_dbg(dev, "%s: status %i\n", __func__, urb->status); 6326 if (urb->status == 0) { 6327 usb_anchor_urb(urb, &priv->int_anchor); 6328 ret = usb_submit_urb(urb, GFP_ATOMIC); 6329 if (ret) 6330 usb_unanchor_urb(urb); 6331 } else { 6332 dev_dbg(dev, "%s: Error %i\n", __func__, urb->status); 6333 } 6334 } 6335 6336 6337 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw) 6338 { 6339 struct rtl8xxxu_priv *priv = hw->priv; 6340 struct urb *urb; 6341 u32 val32; 6342 int ret; 6343 6344 urb = usb_alloc_urb(0, GFP_KERNEL); 6345 if (!urb) 6346 return -ENOMEM; 6347 6348 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt, 6349 priv->int_buf, USB_INTR_CONTENT_LENGTH, 6350 rtl8xxxu_int_complete, priv, 1); 6351 usb_anchor_urb(urb, &priv->int_anchor); 6352 ret = usb_submit_urb(urb, GFP_KERNEL); 6353 if (ret) { 6354 usb_unanchor_urb(urb); 6355 goto error; 6356 } 6357 6358 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR); 6359 val32 |= USB_HIMR_CPWM; 6360 rtl8xxxu_write32(priv, REG_USB_HIMR, val32); 6361 6362 error: 6363 usb_free_urb(urb); 6364 return ret; 6365 } 6366 6367 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw, 6368 struct ieee80211_vif *vif) 6369 { 6370 struct rtl8xxxu_priv *priv = hw->priv; 6371 int ret; 6372 u8 val8; 6373 6374 switch (vif->type) { 6375 case NL80211_IFTYPE_STATION: 6376 if (!priv->vif) 6377 priv->vif = vif; 6378 else 6379 return -EOPNOTSUPP; 6380 rtl8xxxu_stop_tx_beacon(priv); 6381 6382 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 6383 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE | 6384 BEACON_DISABLE_TSF_UPDATE; 6385 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 6386 ret = 0; 6387 break; 6388 default: 6389 ret = -EOPNOTSUPP; 6390 } 6391 6392 rtl8xxxu_set_linktype(priv, vif->type); 6393 6394 return ret; 6395 } 6396 6397 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw, 6398 struct ieee80211_vif *vif) 6399 { 6400 struct rtl8xxxu_priv *priv = hw->priv; 6401 6402 dev_dbg(&priv->udev->dev, "%s\n", __func__); 6403 6404 if (priv->vif) 6405 priv->vif = NULL; 6406 } 6407 6408 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed) 6409 { 6410 struct rtl8xxxu_priv *priv = hw->priv; 6411 struct device *dev = &priv->udev->dev; 6412 int ret = 0, channel; 6413 bool ht40; 6414 6415 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL) 6416 dev_info(dev, 6417 "%s: channel: %i (changed %08x chandef.width %02x)\n", 6418 __func__, hw->conf.chandef.chan->hw_value, 6419 changed, hw->conf.chandef.width); 6420 6421 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { 6422 switch (hw->conf.chandef.width) { 6423 case NL80211_CHAN_WIDTH_20_NOHT: 6424 case NL80211_CHAN_WIDTH_20: 6425 ht40 = false; 6426 break; 6427 case NL80211_CHAN_WIDTH_40: 6428 ht40 = true; 6429 break; 6430 default: 6431 ret = -ENOTSUPP; 6432 goto exit; 6433 } 6434 6435 channel = hw->conf.chandef.chan->hw_value; 6436 6437 priv->fops->set_tx_power(priv, channel, ht40); 6438 6439 priv->fops->config_channel(hw); 6440 } 6441 6442 exit: 6443 return ret; 6444 } 6445 6446 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw, 6447 struct ieee80211_vif *vif, 6448 unsigned int link_id, u16 queue, 6449 const struct ieee80211_tx_queue_params *param) 6450 { 6451 struct rtl8xxxu_priv *priv = hw->priv; 6452 struct device *dev = &priv->udev->dev; 6453 u32 val32; 6454 u8 aifs, acm_ctrl, acm_bit; 6455 6456 aifs = param->aifs; 6457 6458 val32 = aifs | 6459 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT | 6460 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT | 6461 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT; 6462 6463 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL); 6464 dev_dbg(dev, 6465 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n", 6466 __func__, queue, val32, param->acm, acm_ctrl); 6467 6468 switch (queue) { 6469 case IEEE80211_AC_VO: 6470 acm_bit = ACM_HW_CTRL_VO; 6471 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32); 6472 break; 6473 case IEEE80211_AC_VI: 6474 acm_bit = ACM_HW_CTRL_VI; 6475 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32); 6476 break; 6477 case IEEE80211_AC_BE: 6478 acm_bit = ACM_HW_CTRL_BE; 6479 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32); 6480 break; 6481 case IEEE80211_AC_BK: 6482 acm_bit = ACM_HW_CTRL_BK; 6483 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32); 6484 break; 6485 default: 6486 acm_bit = 0; 6487 break; 6488 } 6489 6490 if (param->acm) 6491 acm_ctrl |= acm_bit; 6492 else 6493 acm_ctrl &= ~acm_bit; 6494 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl); 6495 6496 return 0; 6497 } 6498 6499 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw, 6500 unsigned int changed_flags, 6501 unsigned int *total_flags, u64 multicast) 6502 { 6503 struct rtl8xxxu_priv *priv = hw->priv; 6504 u32 rcr = rtl8xxxu_read32(priv, REG_RCR); 6505 6506 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n", 6507 __func__, changed_flags, *total_flags); 6508 6509 /* 6510 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR) 6511 */ 6512 6513 if (*total_flags & FIF_FCSFAIL) 6514 rcr |= RCR_ACCEPT_CRC32; 6515 else 6516 rcr &= ~RCR_ACCEPT_CRC32; 6517 6518 /* 6519 * FIF_PLCPFAIL not supported? 6520 */ 6521 6522 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) 6523 rcr &= ~RCR_CHECK_BSSID_BEACON; 6524 else 6525 rcr |= RCR_CHECK_BSSID_BEACON; 6526 6527 if (*total_flags & FIF_CONTROL) 6528 rcr |= RCR_ACCEPT_CTRL_FRAME; 6529 else 6530 rcr &= ~RCR_ACCEPT_CTRL_FRAME; 6531 6532 if (*total_flags & FIF_OTHER_BSS) { 6533 rcr |= RCR_ACCEPT_AP; 6534 rcr &= ~RCR_CHECK_BSSID_MATCH; 6535 } else { 6536 rcr &= ~RCR_ACCEPT_AP; 6537 rcr |= RCR_CHECK_BSSID_MATCH; 6538 } 6539 6540 if (*total_flags & FIF_PSPOLL) 6541 rcr |= RCR_ACCEPT_PM; 6542 else 6543 rcr &= ~RCR_ACCEPT_PM; 6544 6545 /* 6546 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted 6547 */ 6548 6549 rtl8xxxu_write32(priv, REG_RCR, rcr); 6550 6551 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC | 6552 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL | 6553 FIF_PROBE_REQ); 6554 } 6555 6556 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts) 6557 { 6558 if (rts > 2347) 6559 return -EINVAL; 6560 6561 return 0; 6562 } 6563 6564 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 6565 struct ieee80211_vif *vif, 6566 struct ieee80211_sta *sta, 6567 struct ieee80211_key_conf *key) 6568 { 6569 struct rtl8xxxu_priv *priv = hw->priv; 6570 struct device *dev = &priv->udev->dev; 6571 u8 mac_addr[ETH_ALEN]; 6572 u8 val8; 6573 u16 val16; 6574 u32 val32; 6575 int retval = -EOPNOTSUPP; 6576 6577 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n", 6578 __func__, cmd, key->cipher, key->keyidx); 6579 6580 if (vif->type != NL80211_IFTYPE_STATION) 6581 return -EOPNOTSUPP; 6582 6583 if (key->keyidx > 3) 6584 return -EOPNOTSUPP; 6585 6586 switch (key->cipher) { 6587 case WLAN_CIPHER_SUITE_WEP40: 6588 case WLAN_CIPHER_SUITE_WEP104: 6589 6590 break; 6591 case WLAN_CIPHER_SUITE_CCMP: 6592 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; 6593 break; 6594 case WLAN_CIPHER_SUITE_TKIP: 6595 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 6596 break; 6597 default: 6598 return -EOPNOTSUPP; 6599 } 6600 6601 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { 6602 dev_dbg(dev, "%s: pairwise key\n", __func__); 6603 ether_addr_copy(mac_addr, sta->addr); 6604 } else { 6605 dev_dbg(dev, "%s: group key\n", __func__); 6606 eth_broadcast_addr(mac_addr); 6607 } 6608 6609 val16 = rtl8xxxu_read16(priv, REG_CR); 6610 val16 |= CR_SECURITY_ENABLE; 6611 rtl8xxxu_write16(priv, REG_CR, val16); 6612 6613 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY | 6614 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY; 6615 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY; 6616 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8); 6617 6618 switch (cmd) { 6619 case SET_KEY: 6620 key->hw_key_idx = key->keyidx; 6621 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 6622 rtl8xxxu_cam_write(priv, key, mac_addr); 6623 retval = 0; 6624 break; 6625 case DISABLE_KEY: 6626 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000); 6627 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE | 6628 key->keyidx << CAM_CMD_KEY_SHIFT; 6629 rtl8xxxu_write32(priv, REG_CAM_CMD, val32); 6630 retval = 0; 6631 break; 6632 default: 6633 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd); 6634 } 6635 6636 return retval; 6637 } 6638 6639 static int 6640 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 6641 struct ieee80211_ampdu_params *params) 6642 { 6643 struct rtl8xxxu_priv *priv = hw->priv; 6644 struct device *dev = &priv->udev->dev; 6645 u8 ampdu_factor, ampdu_density; 6646 struct ieee80211_sta *sta = params->sta; 6647 u16 tid = params->tid; 6648 enum ieee80211_ampdu_mlme_action action = params->action; 6649 6650 switch (action) { 6651 case IEEE80211_AMPDU_TX_START: 6652 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__); 6653 ampdu_factor = sta->deflink.ht_cap.ampdu_factor; 6654 ampdu_density = sta->deflink.ht_cap.ampdu_density; 6655 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor); 6656 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density); 6657 dev_dbg(dev, 6658 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n", 6659 ampdu_factor, ampdu_density); 6660 return IEEE80211_AMPDU_TX_START_IMMEDIATE; 6661 case IEEE80211_AMPDU_TX_STOP_CONT: 6662 case IEEE80211_AMPDU_TX_STOP_FLUSH: 6663 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 6664 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP\n", __func__); 6665 rtl8xxxu_set_ampdu_factor(priv, 0); 6666 rtl8xxxu_set_ampdu_min_space(priv, 0); 6667 clear_bit(tid, priv->tx_aggr_started); 6668 clear_bit(tid, priv->tid_tx_operational); 6669 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 6670 break; 6671 case IEEE80211_AMPDU_TX_OPERATIONAL: 6672 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_OPERATIONAL\n", __func__); 6673 set_bit(tid, priv->tid_tx_operational); 6674 break; 6675 case IEEE80211_AMPDU_RX_START: 6676 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__); 6677 break; 6678 case IEEE80211_AMPDU_RX_STOP: 6679 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__); 6680 break; 6681 default: 6682 break; 6683 } 6684 return 0; 6685 } 6686 6687 static void 6688 rtl8xxxu_sta_statistics(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 6689 struct ieee80211_sta *sta, struct station_info *sinfo) 6690 { 6691 struct rtl8xxxu_priv *priv = hw->priv; 6692 6693 sinfo->txrate = priv->ra_report.txrate; 6694 sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE); 6695 } 6696 6697 static u8 rtl8xxxu_signal_to_snr(int signal) 6698 { 6699 if (signal < RTL8XXXU_NOISE_FLOOR_MIN) 6700 signal = RTL8XXXU_NOISE_FLOOR_MIN; 6701 else if (signal > 0) 6702 signal = 0; 6703 return (u8)(signal - RTL8XXXU_NOISE_FLOOR_MIN); 6704 } 6705 6706 static void rtl8xxxu_refresh_rate_mask(struct rtl8xxxu_priv *priv, 6707 int signal, struct ieee80211_sta *sta) 6708 { 6709 struct ieee80211_hw *hw = priv->hw; 6710 u16 wireless_mode; 6711 u8 rssi_level, ratr_idx; 6712 u8 txbw_40mhz; 6713 u8 snr, snr_thresh_high, snr_thresh_low; 6714 u8 go_up_gap = 5; 6715 6716 rssi_level = priv->rssi_level; 6717 snr = rtl8xxxu_signal_to_snr(signal); 6718 snr_thresh_high = RTL8XXXU_SNR_THRESH_HIGH; 6719 snr_thresh_low = RTL8XXXU_SNR_THRESH_LOW; 6720 txbw_40mhz = (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) ? 1 : 0; 6721 6722 switch (rssi_level) { 6723 case RTL8XXXU_RATR_STA_MID: 6724 snr_thresh_high += go_up_gap; 6725 break; 6726 case RTL8XXXU_RATR_STA_LOW: 6727 snr_thresh_high += go_up_gap; 6728 snr_thresh_low += go_up_gap; 6729 break; 6730 default: 6731 break; 6732 } 6733 6734 if (snr > snr_thresh_high) 6735 rssi_level = RTL8XXXU_RATR_STA_HIGH; 6736 else if (snr > snr_thresh_low) 6737 rssi_level = RTL8XXXU_RATR_STA_MID; 6738 else 6739 rssi_level = RTL8XXXU_RATR_STA_LOW; 6740 6741 if (rssi_level != priv->rssi_level) { 6742 int sgi = 0; 6743 u32 rate_bitmap = 0; 6744 6745 rcu_read_lock(); 6746 rate_bitmap = (sta->deflink.supp_rates[0] & 0xfff) | 6747 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12) | 6748 (sta->deflink.ht_cap.mcs.rx_mask[1] << 20); 6749 if (sta->deflink.ht_cap.cap & 6750 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)) 6751 sgi = 1; 6752 rcu_read_unlock(); 6753 6754 wireless_mode = rtl8xxxu_wireless_mode(hw, sta); 6755 switch (wireless_mode) { 6756 case WIRELESS_MODE_B: 6757 ratr_idx = RATEID_IDX_B; 6758 if (rate_bitmap & 0x0000000c) 6759 rate_bitmap &= 0x0000000d; 6760 else 6761 rate_bitmap &= 0x0000000f; 6762 break; 6763 case WIRELESS_MODE_A: 6764 case WIRELESS_MODE_G: 6765 ratr_idx = RATEID_IDX_G; 6766 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) 6767 rate_bitmap &= 0x00000f00; 6768 else 6769 rate_bitmap &= 0x00000ff0; 6770 break; 6771 case (WIRELESS_MODE_B | WIRELESS_MODE_G): 6772 ratr_idx = RATEID_IDX_BG; 6773 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) 6774 rate_bitmap &= 0x00000f00; 6775 else if (rssi_level == RTL8XXXU_RATR_STA_MID) 6776 rate_bitmap &= 0x00000ff0; 6777 else 6778 rate_bitmap &= 0x00000ff5; 6779 break; 6780 case WIRELESS_MODE_N_24G: 6781 case WIRELESS_MODE_N_5G: 6782 case (WIRELESS_MODE_G | WIRELESS_MODE_N_24G): 6783 case (WIRELESS_MODE_A | WIRELESS_MODE_N_5G): 6784 if (priv->tx_paths == 2 && priv->rx_paths == 2) 6785 ratr_idx = RATEID_IDX_GN_N2SS; 6786 else 6787 ratr_idx = RATEID_IDX_GN_N1SS; 6788 break; 6789 case (WIRELESS_MODE_B | WIRELESS_MODE_G | WIRELESS_MODE_N_24G): 6790 case (WIRELESS_MODE_B | WIRELESS_MODE_N_24G): 6791 if (txbw_40mhz) { 6792 if (priv->tx_paths == 2 && priv->rx_paths == 2) 6793 ratr_idx = RATEID_IDX_BGN_40M_2SS; 6794 else 6795 ratr_idx = RATEID_IDX_BGN_40M_1SS; 6796 } else { 6797 if (priv->tx_paths == 2 && priv->rx_paths == 2) 6798 ratr_idx = RATEID_IDX_BGN_20M_2SS_BN; 6799 else 6800 ratr_idx = RATEID_IDX_BGN_20M_1SS_BN; 6801 } 6802 6803 if (priv->tx_paths == 2 && priv->rx_paths == 2) { 6804 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) { 6805 rate_bitmap &= 0x0f8f0000; 6806 } else if (rssi_level == RTL8XXXU_RATR_STA_MID) { 6807 rate_bitmap &= 0x0f8ff000; 6808 } else { 6809 if (txbw_40mhz) 6810 rate_bitmap &= 0x0f8ff015; 6811 else 6812 rate_bitmap &= 0x0f8ff005; 6813 } 6814 } else { 6815 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) { 6816 rate_bitmap &= 0x000f0000; 6817 } else if (rssi_level == RTL8XXXU_RATR_STA_MID) { 6818 rate_bitmap &= 0x000ff000; 6819 } else { 6820 if (txbw_40mhz) 6821 rate_bitmap &= 0x000ff015; 6822 else 6823 rate_bitmap &= 0x000ff005; 6824 } 6825 } 6826 break; 6827 default: 6828 ratr_idx = RATEID_IDX_BGN_40M_2SS; 6829 rate_bitmap &= 0x0fffffff; 6830 break; 6831 } 6832 6833 priv->rssi_level = rssi_level; 6834 priv->fops->update_rate_mask(priv, rate_bitmap, ratr_idx, sgi, txbw_40mhz); 6835 } 6836 } 6837 6838 static void rtl8xxxu_set_atc_status(struct rtl8xxxu_priv *priv, bool atc_status) 6839 { 6840 struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; 6841 u32 val32; 6842 6843 if (atc_status == cfo->atc_status) 6844 return; 6845 6846 cfo->atc_status = atc_status; 6847 6848 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); 6849 if (atc_status) 6850 val32 |= CFO_TRACKING_ATC_STATUS; 6851 else 6852 val32 &= ~CFO_TRACKING_ATC_STATUS; 6853 rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); 6854 } 6855 6856 /* Central frequency offset correction */ 6857 static void rtl8xxxu_track_cfo(struct rtl8xxxu_priv *priv) 6858 { 6859 struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; 6860 int cfo_khz_a, cfo_khz_b, cfo_average; 6861 int crystal_cap; 6862 6863 if (!priv->vif || !priv->vif->cfg.assoc) { 6864 /* Reset */ 6865 cfo->adjust = true; 6866 6867 if (cfo->crystal_cap > priv->default_crystal_cap) 6868 priv->fops->set_crystal_cap(priv, cfo->crystal_cap - 1); 6869 else if (cfo->crystal_cap < priv->default_crystal_cap) 6870 priv->fops->set_crystal_cap(priv, cfo->crystal_cap + 1); 6871 6872 rtl8xxxu_set_atc_status(priv, true); 6873 6874 return; 6875 } 6876 6877 if (cfo->packet_count == cfo->packet_count_pre) 6878 /* No new information. */ 6879 return; 6880 6881 cfo->packet_count_pre = cfo->packet_count; 6882 6883 /* CFO_tail[1:0] is S(8,7), (num_subcarrier>>7) x 312.5K = CFO value(K Hz) */ 6884 cfo_khz_a = (int)((cfo->cfo_tail[0] * 3125) / 10) >> 7; 6885 cfo_khz_b = (int)((cfo->cfo_tail[1] * 3125) / 10) >> 7; 6886 6887 if (priv->tx_paths == 1) 6888 cfo_average = cfo_khz_a; 6889 else 6890 cfo_average = (cfo_khz_a + cfo_khz_b) / 2; 6891 6892 dev_dbg(&priv->udev->dev, "cfo_average: %d\n", cfo_average); 6893 6894 if (cfo->adjust) { 6895 if (abs(cfo_average) < CFO_TH_XTAL_LOW) 6896 cfo->adjust = false; 6897 } else { 6898 if (abs(cfo_average) > CFO_TH_XTAL_HIGH) 6899 cfo->adjust = true; 6900 } 6901 6902 /* 6903 * TODO: We should return here only if bluetooth is enabled. 6904 * See the vendor drivers for how to determine that. 6905 */ 6906 if (priv->has_bluetooth) 6907 return; 6908 6909 if (!cfo->adjust) 6910 return; 6911 6912 crystal_cap = cfo->crystal_cap; 6913 6914 if (cfo_average > CFO_TH_XTAL_LOW) 6915 crystal_cap++; 6916 else if (cfo_average < -CFO_TH_XTAL_LOW) 6917 crystal_cap--; 6918 6919 crystal_cap = clamp(crystal_cap, 0, 0x3f); 6920 6921 priv->fops->set_crystal_cap(priv, crystal_cap); 6922 6923 rtl8xxxu_set_atc_status(priv, abs(cfo_average) >= CFO_TH_ATC); 6924 } 6925 6926 static void rtl8xxxu_watchdog_callback(struct work_struct *work) 6927 { 6928 struct ieee80211_vif *vif; 6929 struct rtl8xxxu_priv *priv; 6930 6931 priv = container_of(work, struct rtl8xxxu_priv, ra_watchdog.work); 6932 vif = priv->vif; 6933 6934 if (vif && vif->type == NL80211_IFTYPE_STATION) { 6935 int signal; 6936 struct ieee80211_sta *sta; 6937 6938 rcu_read_lock(); 6939 sta = ieee80211_find_sta(vif, vif->bss_conf.bssid); 6940 if (!sta) { 6941 struct device *dev = &priv->udev->dev; 6942 6943 dev_dbg(dev, "%s: no sta found\n", __func__); 6944 rcu_read_unlock(); 6945 goto out; 6946 } 6947 rcu_read_unlock(); 6948 6949 signal = ieee80211_ave_rssi(vif); 6950 6951 priv->fops->report_rssi(priv, 0, 6952 rtl8xxxu_signal_to_snr(signal)); 6953 6954 if (priv->fops->set_crystal_cap) 6955 rtl8xxxu_track_cfo(priv); 6956 6957 rtl8xxxu_refresh_rate_mask(priv, signal, sta); 6958 } 6959 6960 out: 6961 schedule_delayed_work(&priv->ra_watchdog, 2 * HZ); 6962 } 6963 6964 static int rtl8xxxu_start(struct ieee80211_hw *hw) 6965 { 6966 struct rtl8xxxu_priv *priv = hw->priv; 6967 struct rtl8xxxu_rx_urb *rx_urb; 6968 struct rtl8xxxu_tx_urb *tx_urb; 6969 struct sk_buff *skb; 6970 unsigned long flags; 6971 int ret, i; 6972 6973 ret = 0; 6974 6975 init_usb_anchor(&priv->rx_anchor); 6976 init_usb_anchor(&priv->tx_anchor); 6977 init_usb_anchor(&priv->int_anchor); 6978 6979 priv->fops->enable_rf(priv); 6980 if (priv->usb_interrupts) { 6981 ret = rtl8xxxu_submit_int_urb(hw); 6982 if (ret) 6983 goto exit; 6984 } 6985 6986 for (i = 0; i < RTL8XXXU_TX_URBS; i++) { 6987 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL); 6988 if (!tx_urb) { 6989 if (!i) 6990 ret = -ENOMEM; 6991 6992 goto error_out; 6993 } 6994 usb_init_urb(&tx_urb->urb); 6995 INIT_LIST_HEAD(&tx_urb->list); 6996 tx_urb->hw = hw; 6997 list_add(&tx_urb->list, &priv->tx_urb_free_list); 6998 priv->tx_urb_free_count++; 6999 } 7000 7001 priv->tx_stopped = false; 7002 7003 spin_lock_irqsave(&priv->rx_urb_lock, flags); 7004 priv->shutdown = false; 7005 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 7006 7007 for (i = 0; i < RTL8XXXU_RX_URBS; i++) { 7008 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL); 7009 if (!rx_urb) { 7010 if (!i) 7011 ret = -ENOMEM; 7012 7013 goto error_out; 7014 } 7015 usb_init_urb(&rx_urb->urb); 7016 INIT_LIST_HEAD(&rx_urb->list); 7017 rx_urb->hw = hw; 7018 7019 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb); 7020 if (ret) { 7021 if (ret != -ENOMEM) { 7022 skb = (struct sk_buff *)rx_urb->urb.context; 7023 dev_kfree_skb(skb); 7024 } 7025 rtl8xxxu_queue_rx_urb(priv, rx_urb); 7026 } 7027 } 7028 7029 schedule_delayed_work(&priv->ra_watchdog, 2 * HZ); 7030 exit: 7031 /* 7032 * Accept all data and mgmt frames 7033 */ 7034 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff); 7035 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff); 7036 7037 rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1, 7038 OFDM0_X_AGC_CORE1_IGI_MASK, 0x1e); 7039 7040 return ret; 7041 7042 error_out: 7043 rtl8xxxu_free_tx_resources(priv); 7044 /* 7045 * Disable all data and mgmt frames 7046 */ 7047 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); 7048 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000); 7049 7050 return ret; 7051 } 7052 7053 static void rtl8xxxu_stop(struct ieee80211_hw *hw) 7054 { 7055 struct rtl8xxxu_priv *priv = hw->priv; 7056 unsigned long flags; 7057 7058 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 7059 7060 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000); 7061 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); 7062 7063 spin_lock_irqsave(&priv->rx_urb_lock, flags); 7064 priv->shutdown = true; 7065 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 7066 7067 usb_kill_anchored_urbs(&priv->rx_anchor); 7068 usb_kill_anchored_urbs(&priv->tx_anchor); 7069 if (priv->usb_interrupts) 7070 usb_kill_anchored_urbs(&priv->int_anchor); 7071 7072 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 7073 7074 priv->fops->disable_rf(priv); 7075 7076 /* 7077 * Disable interrupts 7078 */ 7079 if (priv->usb_interrupts) 7080 rtl8xxxu_write32(priv, REG_USB_HIMR, 0); 7081 7082 cancel_delayed_work_sync(&priv->ra_watchdog); 7083 7084 rtl8xxxu_free_rx_resources(priv); 7085 rtl8xxxu_free_tx_resources(priv); 7086 } 7087 7088 static const struct ieee80211_ops rtl8xxxu_ops = { 7089 .tx = rtl8xxxu_tx, 7090 .wake_tx_queue = ieee80211_handle_wake_tx_queue, 7091 .add_interface = rtl8xxxu_add_interface, 7092 .remove_interface = rtl8xxxu_remove_interface, 7093 .config = rtl8xxxu_config, 7094 .conf_tx = rtl8xxxu_conf_tx, 7095 .bss_info_changed = rtl8xxxu_bss_info_changed, 7096 .configure_filter = rtl8xxxu_configure_filter, 7097 .set_rts_threshold = rtl8xxxu_set_rts_threshold, 7098 .start = rtl8xxxu_start, 7099 .stop = rtl8xxxu_stop, 7100 .sw_scan_start = rtl8xxxu_sw_scan_start, 7101 .sw_scan_complete = rtl8xxxu_sw_scan_complete, 7102 .set_key = rtl8xxxu_set_key, 7103 .ampdu_action = rtl8xxxu_ampdu_action, 7104 .sta_statistics = rtl8xxxu_sta_statistics, 7105 .get_antenna = rtl8xxxu_get_antenna, 7106 }; 7107 7108 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv, 7109 struct usb_interface *interface) 7110 { 7111 struct usb_interface_descriptor *interface_desc; 7112 struct usb_host_interface *host_interface; 7113 struct usb_endpoint_descriptor *endpoint; 7114 struct device *dev = &priv->udev->dev; 7115 int i, j = 0, endpoints; 7116 u8 dir, xtype, num; 7117 int ret = 0; 7118 7119 host_interface = interface->cur_altsetting; 7120 interface_desc = &host_interface->desc; 7121 endpoints = interface_desc->bNumEndpoints; 7122 7123 for (i = 0; i < endpoints; i++) { 7124 endpoint = &host_interface->endpoint[i].desc; 7125 7126 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK; 7127 num = usb_endpoint_num(endpoint); 7128 xtype = usb_endpoint_type(endpoint); 7129 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 7130 dev_dbg(dev, 7131 "%s: endpoint: dir %02x, # %02x, type %02x\n", 7132 __func__, dir, num, xtype); 7133 if (usb_endpoint_dir_in(endpoint) && 7134 usb_endpoint_xfer_bulk(endpoint)) { 7135 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 7136 dev_dbg(dev, "%s: in endpoint num %i\n", 7137 __func__, num); 7138 7139 if (priv->pipe_in) { 7140 dev_warn(dev, 7141 "%s: Too many IN pipes\n", __func__); 7142 ret = -EINVAL; 7143 goto exit; 7144 } 7145 7146 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num); 7147 } 7148 7149 if (usb_endpoint_dir_in(endpoint) && 7150 usb_endpoint_xfer_int(endpoint)) { 7151 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 7152 dev_dbg(dev, "%s: interrupt endpoint num %i\n", 7153 __func__, num); 7154 7155 if (priv->pipe_interrupt) { 7156 dev_warn(dev, "%s: Too many INTERRUPT pipes\n", 7157 __func__); 7158 ret = -EINVAL; 7159 goto exit; 7160 } 7161 7162 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num); 7163 } 7164 7165 if (usb_endpoint_dir_out(endpoint) && 7166 usb_endpoint_xfer_bulk(endpoint)) { 7167 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 7168 dev_dbg(dev, "%s: out endpoint num %i\n", 7169 __func__, num); 7170 if (j >= RTL8XXXU_OUT_ENDPOINTS) { 7171 dev_warn(dev, 7172 "%s: Too many OUT pipes\n", __func__); 7173 ret = -EINVAL; 7174 goto exit; 7175 } 7176 priv->out_ep[j++] = num; 7177 } 7178 } 7179 exit: 7180 priv->nr_out_eps = j; 7181 return ret; 7182 } 7183 7184 static void rtl8xxxu_init_led(struct rtl8xxxu_priv *priv) 7185 { 7186 struct led_classdev *led = &priv->led_cdev; 7187 7188 if (!priv->fops->led_classdev_brightness_set) 7189 return; 7190 7191 led->brightness_set_blocking = priv->fops->led_classdev_brightness_set; 7192 7193 snprintf(priv->led_name, sizeof(priv->led_name), 7194 "rtl8xxxu-usb%s", dev_name(&priv->udev->dev)); 7195 led->name = priv->led_name; 7196 led->max_brightness = RTL8XXXU_HW_LED_CONTROL; 7197 7198 if (led_classdev_register(&priv->udev->dev, led)) 7199 return; 7200 7201 priv->led_registered = true; 7202 7203 led->brightness = led->max_brightness; 7204 priv->fops->led_classdev_brightness_set(led, led->brightness); 7205 } 7206 7207 static void rtl8xxxu_deinit_led(struct rtl8xxxu_priv *priv) 7208 { 7209 struct led_classdev *led = &priv->led_cdev; 7210 7211 if (!priv->led_registered) 7212 return; 7213 7214 priv->fops->led_classdev_brightness_set(led, LED_OFF); 7215 led_classdev_unregister(led); 7216 } 7217 7218 static int rtl8xxxu_probe(struct usb_interface *interface, 7219 const struct usb_device_id *id) 7220 { 7221 struct rtl8xxxu_priv *priv; 7222 struct ieee80211_hw *hw; 7223 struct usb_device *udev; 7224 struct ieee80211_supported_band *sband; 7225 int ret; 7226 int untested = 1; 7227 7228 udev = usb_get_dev(interface_to_usbdev(interface)); 7229 7230 switch (id->idVendor) { 7231 case USB_VENDOR_ID_REALTEK: 7232 switch(id->idProduct) { 7233 case 0x1724: 7234 case 0x8176: 7235 case 0x8178: 7236 case 0x817f: 7237 case 0x818b: 7238 case 0xf179: 7239 case 0x8179: 7240 case 0xb711: 7241 untested = 0; 7242 break; 7243 } 7244 break; 7245 case 0x7392: 7246 if (id->idProduct == 0x7811 || id->idProduct == 0xa611 || id->idProduct == 0xb811) 7247 untested = 0; 7248 break; 7249 case 0x050d: 7250 if (id->idProduct == 0x1004) 7251 untested = 0; 7252 break; 7253 case 0x20f4: 7254 if (id->idProduct == 0x648b) 7255 untested = 0; 7256 break; 7257 case 0x2001: 7258 if (id->idProduct == 0x3308) 7259 untested = 0; 7260 break; 7261 case 0x2357: 7262 if (id->idProduct == 0x0109) 7263 untested = 0; 7264 break; 7265 default: 7266 break; 7267 } 7268 7269 if (untested) { 7270 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE; 7271 dev_info(&udev->dev, 7272 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n", 7273 id->idVendor, id->idProduct); 7274 dev_info(&udev->dev, 7275 "Please report results to Jes.Sorensen@gmail.com\n"); 7276 } 7277 7278 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops); 7279 if (!hw) { 7280 ret = -ENOMEM; 7281 goto err_put_dev; 7282 } 7283 7284 priv = hw->priv; 7285 priv->hw = hw; 7286 priv->udev = udev; 7287 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info; 7288 mutex_init(&priv->usb_buf_mutex); 7289 mutex_init(&priv->syson_indirect_access_mutex); 7290 mutex_init(&priv->h2c_mutex); 7291 INIT_LIST_HEAD(&priv->tx_urb_free_list); 7292 spin_lock_init(&priv->tx_urb_lock); 7293 INIT_LIST_HEAD(&priv->rx_urb_pending_list); 7294 spin_lock_init(&priv->rx_urb_lock); 7295 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work); 7296 INIT_DELAYED_WORK(&priv->ra_watchdog, rtl8xxxu_watchdog_callback); 7297 skb_queue_head_init(&priv->c2hcmd_queue); 7298 7299 usb_set_intfdata(interface, hw); 7300 7301 ret = rtl8xxxu_parse_usb(priv, interface); 7302 if (ret) 7303 goto err_set_intfdata; 7304 7305 ret = priv->fops->identify_chip(priv); 7306 if (ret) { 7307 dev_err(&udev->dev, "Fatal - failed to identify chip\n"); 7308 goto err_set_intfdata; 7309 } 7310 7311 hw->wiphy->available_antennas_tx = BIT(priv->tx_paths) - 1; 7312 hw->wiphy->available_antennas_rx = BIT(priv->rx_paths) - 1; 7313 7314 if (priv->rtl_chip == RTL8188E) 7315 INIT_WORK(&priv->c2hcmd_work, rtl8188e_c2hcmd_callback); 7316 else 7317 INIT_WORK(&priv->c2hcmd_work, rtl8xxxu_c2hcmd_callback); 7318 7319 ret = priv->fops->read_efuse(priv); 7320 if (ret) { 7321 dev_err(&udev->dev, "Fatal - failed to read EFuse\n"); 7322 goto err_set_intfdata; 7323 } 7324 7325 ret = priv->fops->parse_efuse(priv); 7326 if (ret) { 7327 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n"); 7328 goto err_set_intfdata; 7329 } 7330 7331 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) 7332 rtl8xxxu_dump_efuse(priv); 7333 7334 rtl8xxxu_print_chipinfo(priv); 7335 7336 ret = priv->fops->load_firmware(priv); 7337 if (ret) { 7338 dev_err(&udev->dev, "Fatal - failed to load firmware\n"); 7339 goto err_set_intfdata; 7340 } 7341 7342 ret = rtl8xxxu_init_device(hw); 7343 if (ret) 7344 goto err_set_intfdata; 7345 7346 hw->wiphy->max_scan_ssids = 1; 7347 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; 7348 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); 7349 hw->queues = 4; 7350 7351 sband = &rtl8xxxu_supported_band; 7352 sband->ht_cap.ht_supported = true; 7353 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 7354 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16; 7355 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40; 7356 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs)); 7357 sband->ht_cap.mcs.rx_mask[0] = 0xff; 7358 sband->ht_cap.mcs.rx_mask[4] = 0x01; 7359 if (priv->rf_paths > 1) { 7360 sband->ht_cap.mcs.rx_mask[1] = 0xff; 7361 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40; 7362 } 7363 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 7364 /* 7365 * Some APs will negotiate HT20_40 in a noisy environment leading 7366 * to miserable performance. Rather than defaulting to this, only 7367 * enable it if explicitly requested at module load time. 7368 */ 7369 if (rtl8xxxu_ht40_2g) { 7370 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n"); 7371 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; 7372 } 7373 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 7374 7375 hw->wiphy->rts_threshold = 2347; 7376 7377 SET_IEEE80211_DEV(priv->hw, &interface->dev); 7378 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr); 7379 7380 hw->extra_tx_headroom = priv->fops->tx_desc_size; 7381 ieee80211_hw_set(hw, SIGNAL_DBM); 7382 7383 /* 7384 * The firmware handles rate control, except for RTL8188EU, 7385 * where we handle the rate control in the driver. 7386 */ 7387 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 7388 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 7389 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 7390 7391 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); 7392 7393 ret = ieee80211_register_hw(priv->hw); 7394 if (ret) { 7395 dev_err(&udev->dev, "%s: Failed to register: %i\n", 7396 __func__, ret); 7397 goto err_set_intfdata; 7398 } 7399 7400 rtl8xxxu_init_led(priv); 7401 7402 return 0; 7403 7404 err_set_intfdata: 7405 usb_set_intfdata(interface, NULL); 7406 7407 kfree(priv->fw_data); 7408 mutex_destroy(&priv->usb_buf_mutex); 7409 mutex_destroy(&priv->syson_indirect_access_mutex); 7410 mutex_destroy(&priv->h2c_mutex); 7411 7412 ieee80211_free_hw(hw); 7413 err_put_dev: 7414 usb_put_dev(udev); 7415 7416 return ret; 7417 } 7418 7419 static void rtl8xxxu_disconnect(struct usb_interface *interface) 7420 { 7421 struct rtl8xxxu_priv *priv; 7422 struct ieee80211_hw *hw; 7423 7424 hw = usb_get_intfdata(interface); 7425 priv = hw->priv; 7426 7427 rtl8xxxu_deinit_led(priv); 7428 7429 ieee80211_unregister_hw(hw); 7430 7431 priv->fops->power_off(priv); 7432 7433 usb_set_intfdata(interface, NULL); 7434 7435 dev_info(&priv->udev->dev, "disconnecting\n"); 7436 7437 kfree(priv->fw_data); 7438 mutex_destroy(&priv->usb_buf_mutex); 7439 mutex_destroy(&priv->syson_indirect_access_mutex); 7440 mutex_destroy(&priv->h2c_mutex); 7441 7442 if (priv->udev->state != USB_STATE_NOTATTACHED) { 7443 dev_info(&priv->udev->dev, 7444 "Device still attached, trying to reset\n"); 7445 usb_reset_device(priv->udev); 7446 } 7447 usb_put_dev(priv->udev); 7448 ieee80211_free_hw(hw); 7449 } 7450 7451 static const struct usb_device_id dev_table[] = { 7452 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff), 7453 .driver_info = (unsigned long)&rtl8723au_fops}, 7454 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff), 7455 .driver_info = (unsigned long)&rtl8723au_fops}, 7456 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff), 7457 .driver_info = (unsigned long)&rtl8723au_fops}, 7458 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff), 7459 .driver_info = (unsigned long)&rtl8192eu_fops}, 7460 /* TP-Link TL-WN822N v4 */ 7461 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0108, 0xff, 0xff, 0xff), 7462 .driver_info = (unsigned long)&rtl8192eu_fops}, 7463 /* D-Link DWA-131 rev E1, tested by David Patiño */ 7464 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3319, 0xff, 0xff, 0xff), 7465 .driver_info = (unsigned long)&rtl8192eu_fops}, 7466 /* Tested by Myckel Habets */ 7467 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0109, 0xff, 0xff, 0xff), 7468 .driver_info = (unsigned long)&rtl8192eu_fops}, 7469 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff), 7470 .driver_info = (unsigned long)&rtl8723bu_fops}, 7471 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xa611, 0xff, 0xff, 0xff), 7472 .driver_info = (unsigned long)&rtl8723bu_fops}, 7473 /* RTL8188FU */ 7474 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xf179, 0xff, 0xff, 0xff), 7475 .driver_info = (unsigned long)&rtl8188fu_fops}, 7476 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8179, 0xff, 0xff, 0xff), 7477 .driver_info = (unsigned long)&rtl8188eu_fops}, 7478 /* Tested by Hans de Goede - rtl8188etv */ 7479 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0179, 0xff, 0xff, 0xff), 7480 .driver_info = (unsigned long)&rtl8188eu_fops}, 7481 /* Sitecom rtl8188eus */ 7482 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0076, 0xff, 0xff, 0xff), 7483 .driver_info = (unsigned long)&rtl8188eu_fops}, 7484 /* D-Link USB-GO-N150 */ 7485 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3311, 0xff, 0xff, 0xff), 7486 .driver_info = (unsigned long)&rtl8188eu_fops}, 7487 /* D-Link DWA-125 REV D1 */ 7488 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330f, 0xff, 0xff, 0xff), 7489 .driver_info = (unsigned long)&rtl8188eu_fops}, 7490 /* D-Link DWA-123 REV D1 */ 7491 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3310, 0xff, 0xff, 0xff), 7492 .driver_info = (unsigned long)&rtl8188eu_fops}, 7493 /* D-Link DWA-121 rev B1 */ 7494 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x331b, 0xff, 0xff, 0xff), 7495 .driver_info = (unsigned long)&rtl8188eu_fops}, 7496 /* Abocom - Abocom */ 7497 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8179, 0xff, 0xff, 0xff), 7498 .driver_info = (unsigned long)&rtl8188eu_fops}, 7499 /* Elecom WDC-150SU2M */ 7500 {USB_DEVICE_AND_INTERFACE_INFO(0x056e, 0x4008, 0xff, 0xff, 0xff), 7501 .driver_info = (unsigned long)&rtl8188eu_fops}, 7502 /* TP-Link TL-WN722N v2 */ 7503 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x010c, 0xff, 0xff, 0xff), 7504 .driver_info = (unsigned long)&rtl8188eu_fops}, 7505 /* TP-Link TL-WN727N v5.21 */ 7506 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0111, 0xff, 0xff, 0xff), 7507 .driver_info = (unsigned long)&rtl8188eu_fops}, 7508 /* MERCUSYS MW150US v2 */ 7509 {USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0102, 0xff, 0xff, 0xff), 7510 .driver_info = (unsigned long)&rtl8188eu_fops}, 7511 /* ASUS USB-N10 Nano B1 */ 7512 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x18f0, 0xff, 0xff, 0xff), 7513 .driver_info = (unsigned long)&rtl8188eu_fops}, 7514 /* Edimax EW-7811Un V2 */ 7515 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xb811, 0xff, 0xff, 0xff), 7516 .driver_info = (unsigned long)&rtl8188eu_fops}, 7517 /* Rosewill USB-N150 Nano */ 7518 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xffef, 0xff, 0xff, 0xff), 7519 .driver_info = (unsigned long)&rtl8188eu_fops}, 7520 /* RTL8710BU aka RTL8188GU (not to be confused with RTL8188GTVU) */ 7521 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb711, 0xff, 0xff, 0xff), 7522 .driver_info = (unsigned long)&rtl8710bu_fops}, 7523 /* TOTOLINK N150UA V5 / N150UA-B */ 7524 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2005, 0xff, 0xff, 0xff), 7525 .driver_info = (unsigned long)&rtl8710bu_fops}, 7526 #ifdef CONFIG_RTL8XXXU_UNTESTED 7527 /* Still supported by rtlwifi */ 7528 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff), 7529 .driver_info = (unsigned long)&rtl8192cu_fops}, 7530 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff), 7531 .driver_info = (unsigned long)&rtl8192cu_fops}, 7532 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff), 7533 .driver_info = (unsigned long)&rtl8192cu_fops}, 7534 /* Tested by Larry Finger */ 7535 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff), 7536 .driver_info = (unsigned long)&rtl8192cu_fops}, 7537 /* Tested by Andrea Merello */ 7538 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff), 7539 .driver_info = (unsigned long)&rtl8192cu_fops}, 7540 /* Tested by Jocelyn Mayer */ 7541 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff), 7542 .driver_info = (unsigned long)&rtl8192cu_fops}, 7543 /* Tested by Stefano Bravi */ 7544 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff), 7545 .driver_info = (unsigned long)&rtl8192cu_fops}, 7546 /* Currently untested 8188 series devices */ 7547 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x018a, 0xff, 0xff, 0xff), 7548 .driver_info = (unsigned long)&rtl8192cu_fops}, 7549 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff), 7550 .driver_info = (unsigned long)&rtl8192cu_fops}, 7551 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff), 7552 .driver_info = (unsigned long)&rtl8192cu_fops}, 7553 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff), 7554 .driver_info = (unsigned long)&rtl8192cu_fops}, 7555 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff), 7556 .driver_info = (unsigned long)&rtl8192cu_fops}, 7557 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff), 7558 .driver_info = (unsigned long)&rtl8192cu_fops}, 7559 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff), 7560 .driver_info = (unsigned long)&rtl8192cu_fops}, 7561 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff), 7562 .driver_info = (unsigned long)&rtl8192cu_fops}, 7563 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff), 7564 .driver_info = (unsigned long)&rtl8192cu_fops}, 7565 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff), 7566 .driver_info = (unsigned long)&rtl8192cu_fops}, 7567 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff), 7568 .driver_info = (unsigned long)&rtl8192cu_fops}, 7569 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff), 7570 .driver_info = (unsigned long)&rtl8192cu_fops}, 7571 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff), 7572 .driver_info = (unsigned long)&rtl8192cu_fops}, 7573 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff), 7574 .driver_info = (unsigned long)&rtl8192cu_fops}, 7575 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff), 7576 .driver_info = (unsigned long)&rtl8192cu_fops}, 7577 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff), 7578 .driver_info = (unsigned long)&rtl8192cu_fops}, 7579 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff), 7580 .driver_info = (unsigned long)&rtl8192cu_fops}, 7581 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff), 7582 .driver_info = (unsigned long)&rtl8192cu_fops}, 7583 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff), 7584 .driver_info = (unsigned long)&rtl8192cu_fops}, 7585 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff), 7586 .driver_info = (unsigned long)&rtl8192cu_fops}, 7587 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff), 7588 .driver_info = (unsigned long)&rtl8192cu_fops}, 7589 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff), 7590 .driver_info = (unsigned long)&rtl8192cu_fops}, 7591 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff), 7592 .driver_info = (unsigned long)&rtl8192cu_fops}, 7593 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff), 7594 .driver_info = (unsigned long)&rtl8192cu_fops}, 7595 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff), 7596 .driver_info = (unsigned long)&rtl8192cu_fops}, 7597 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff), 7598 .driver_info = (unsigned long)&rtl8192cu_fops}, 7599 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff), 7600 .driver_info = (unsigned long)&rtl8192cu_fops}, 7601 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff), 7602 .driver_info = (unsigned long)&rtl8192cu_fops}, 7603 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff), 7604 .driver_info = (unsigned long)&rtl8192cu_fops}, 7605 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff), 7606 .driver_info = (unsigned long)&rtl8192cu_fops}, 7607 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff), 7608 .driver_info = (unsigned long)&rtl8192cu_fops}, 7609 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff), 7610 .driver_info = (unsigned long)&rtl8192cu_fops}, 7611 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff), 7612 .driver_info = (unsigned long)&rtl8192cu_fops}, 7613 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff), 7614 .driver_info = (unsigned long)&rtl8192cu_fops}, 7615 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff), 7616 .driver_info = (unsigned long)&rtl8192cu_fops}, 7617 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff), 7618 .driver_info = (unsigned long)&rtl8192cu_fops}, 7619 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff), 7620 .driver_info = (unsigned long)&rtl8192cu_fops}, 7621 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff), 7622 .driver_info = (unsigned long)&rtl8192cu_fops}, 7623 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff), 7624 .driver_info = (unsigned long)&rtl8192cu_fops}, 7625 /* Currently untested 8192 series devices */ 7626 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff), 7627 .driver_info = (unsigned long)&rtl8192cu_fops}, 7628 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff), 7629 .driver_info = (unsigned long)&rtl8192cu_fops}, 7630 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff), 7631 .driver_info = (unsigned long)&rtl8192cu_fops}, 7632 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff), 7633 .driver_info = (unsigned long)&rtl8192cu_fops}, 7634 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff), 7635 .driver_info = (unsigned long)&rtl8192cu_fops}, 7636 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff), 7637 .driver_info = (unsigned long)&rtl8192cu_fops}, 7638 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff), 7639 .driver_info = (unsigned long)&rtl8192cu_fops}, 7640 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff), 7641 .driver_info = (unsigned long)&rtl8192cu_fops}, 7642 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff), 7643 .driver_info = (unsigned long)&rtl8192cu_fops}, 7644 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff), 7645 .driver_info = (unsigned long)&rtl8192cu_fops}, 7646 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff), 7647 .driver_info = (unsigned long)&rtl8192cu_fops}, 7648 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff), 7649 .driver_info = (unsigned long)&rtl8192cu_fops}, 7650 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff), 7651 .driver_info = (unsigned long)&rtl8192cu_fops}, 7652 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff), 7653 .driver_info = (unsigned long)&rtl8192cu_fops}, 7654 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff), 7655 .driver_info = (unsigned long)&rtl8192cu_fops}, 7656 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff), 7657 .driver_info = (unsigned long)&rtl8192cu_fops}, 7658 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff), 7659 .driver_info = (unsigned long)&rtl8192cu_fops}, 7660 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff), 7661 .driver_info = (unsigned long)&rtl8192cu_fops}, 7662 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff), 7663 .driver_info = (unsigned long)&rtl8192cu_fops}, 7664 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff), 7665 .driver_info = (unsigned long)&rtl8192cu_fops}, 7666 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff), 7667 .driver_info = (unsigned long)&rtl8192cu_fops}, 7668 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff), 7669 .driver_info = (unsigned long)&rtl8192cu_fops}, 7670 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff), 7671 .driver_info = (unsigned long)&rtl8192cu_fops}, 7672 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff), 7673 .driver_info = (unsigned long)&rtl8192cu_fops}, 7674 /* found in rtl8192eu vendor driver */ 7675 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0107, 0xff, 0xff, 0xff), 7676 .driver_info = (unsigned long)&rtl8192eu_fops}, 7677 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab33, 0xff, 0xff, 0xff), 7678 .driver_info = (unsigned long)&rtl8192eu_fops}, 7679 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818c, 0xff, 0xff, 0xff), 7680 .driver_info = (unsigned long)&rtl8192eu_fops}, 7681 #endif 7682 { } 7683 }; 7684 7685 static struct usb_driver rtl8xxxu_driver = { 7686 .name = DRIVER_NAME, 7687 .probe = rtl8xxxu_probe, 7688 .disconnect = rtl8xxxu_disconnect, 7689 .id_table = dev_table, 7690 .no_dynamic_id = 1, 7691 .disable_hub_initiated_lpm = 1, 7692 }; 7693 7694 MODULE_DEVICE_TABLE(usb, dev_table); 7695 7696 module_usb_driver(rtl8xxxu_driver); 7697