1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * RTL8XXXU mac80211 USB driver 4 * 5 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> 6 * 7 * Portions, notably calibration code: 8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 9 * 10 * This driver was written as a replacement for the vendor provided 11 * rtl8723au driver. As the Realtek 8xxx chips are very similar in 12 * their programming interface, I have started adding support for 13 * additional 8xxx chips like the 8192cu, 8188cus, etc. 14 */ 15 16 #include <linux/init.h> 17 #include <linux/kernel.h> 18 #include <linux/sched.h> 19 #include <linux/errno.h> 20 #include <linux/slab.h> 21 #include <linux/module.h> 22 #include <linux/spinlock.h> 23 #include <linux/list.h> 24 #include <linux/usb.h> 25 #include <linux/netdevice.h> 26 #include <linux/etherdevice.h> 27 #include <linux/ethtool.h> 28 #include <linux/wireless.h> 29 #include <linux/firmware.h> 30 #include <linux/moduleparam.h> 31 #include <net/mac80211.h> 32 #include "rtl8xxxu.h" 33 #include "rtl8xxxu_regs.h" 34 35 #define DRIVER_NAME "rtl8xxxu" 36 37 int rtl8xxxu_debug; 38 static bool rtl8xxxu_ht40_2g; 39 static bool rtl8xxxu_dma_aggregation; 40 static int rtl8xxxu_dma_agg_timeout = -1; 41 static int rtl8xxxu_dma_agg_pages = -1; 42 43 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@gmail.com>"); 44 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver"); 45 MODULE_LICENSE("GPL"); 46 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin"); 47 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin"); 48 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin"); 49 MODULE_FIRMWARE("rtlwifi/rtl8188eufw.bin"); 50 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin"); 51 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin"); 52 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin"); 53 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin"); 54 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin"); 55 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin"); 56 MODULE_FIRMWARE("rtlwifi/rtl8188fufw.bin"); 57 MODULE_FIRMWARE("rtlwifi/rtl8710bufw_SMIC.bin"); 58 MODULE_FIRMWARE("rtlwifi/rtl8710bufw_UMC.bin"); 59 MODULE_FIRMWARE("rtlwifi/rtl8192fufw.bin"); 60 61 module_param_named(debug, rtl8xxxu_debug, int, 0600); 62 MODULE_PARM_DESC(debug, "Set debug mask"); 63 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600); 64 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band"); 65 module_param_named(dma_aggregation, rtl8xxxu_dma_aggregation, bool, 0600); 66 MODULE_PARM_DESC(dma_aggregation, "Enable DMA packet aggregation"); 67 module_param_named(dma_agg_timeout, rtl8xxxu_dma_agg_timeout, int, 0600); 68 MODULE_PARM_DESC(dma_agg_timeout, "Set DMA aggregation timeout (range 1-127)"); 69 module_param_named(dma_agg_pages, rtl8xxxu_dma_agg_pages, int, 0600); 70 MODULE_PARM_DESC(dma_agg_pages, "Set DMA aggregation pages (range 1-127, 0 to disable)"); 71 72 #define USB_VENDOR_ID_REALTEK 0x0bda 73 #define RTL8XXXU_RX_URBS 32 74 #define RTL8XXXU_RX_URB_PENDING_WATER 8 75 #define RTL8XXXU_TX_URBS 64 76 #define RTL8XXXU_TX_URB_LOW_WATER 25 77 #define RTL8XXXU_TX_URB_HIGH_WATER 32 78 79 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv, 80 struct rtl8xxxu_rx_urb *rx_urb); 81 82 static struct ieee80211_rate rtl8xxxu_rates[] = { 83 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 }, 84 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 }, 85 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 }, 86 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 }, 87 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 }, 88 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 }, 89 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 }, 90 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 }, 91 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 }, 92 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 }, 93 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 }, 94 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 }, 95 }; 96 97 static struct ieee80211_channel rtl8xxxu_channels_2g[] = { 98 { .band = NL80211_BAND_2GHZ, .center_freq = 2412, 99 .hw_value = 1, .max_power = 30 }, 100 { .band = NL80211_BAND_2GHZ, .center_freq = 2417, 101 .hw_value = 2, .max_power = 30 }, 102 { .band = NL80211_BAND_2GHZ, .center_freq = 2422, 103 .hw_value = 3, .max_power = 30 }, 104 { .band = NL80211_BAND_2GHZ, .center_freq = 2427, 105 .hw_value = 4, .max_power = 30 }, 106 { .band = NL80211_BAND_2GHZ, .center_freq = 2432, 107 .hw_value = 5, .max_power = 30 }, 108 { .band = NL80211_BAND_2GHZ, .center_freq = 2437, 109 .hw_value = 6, .max_power = 30 }, 110 { .band = NL80211_BAND_2GHZ, .center_freq = 2442, 111 .hw_value = 7, .max_power = 30 }, 112 { .band = NL80211_BAND_2GHZ, .center_freq = 2447, 113 .hw_value = 8, .max_power = 30 }, 114 { .band = NL80211_BAND_2GHZ, .center_freq = 2452, 115 .hw_value = 9, .max_power = 30 }, 116 { .band = NL80211_BAND_2GHZ, .center_freq = 2457, 117 .hw_value = 10, .max_power = 30 }, 118 { .band = NL80211_BAND_2GHZ, .center_freq = 2462, 119 .hw_value = 11, .max_power = 30 }, 120 { .band = NL80211_BAND_2GHZ, .center_freq = 2467, 121 .hw_value = 12, .max_power = 30 }, 122 { .band = NL80211_BAND_2GHZ, .center_freq = 2472, 123 .hw_value = 13, .max_power = 30 }, 124 { .band = NL80211_BAND_2GHZ, .center_freq = 2484, 125 .hw_value = 14, .max_power = 30 } 126 }; 127 128 static struct ieee80211_supported_band rtl8xxxu_supported_band = { 129 .channels = rtl8xxxu_channels_2g, 130 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g), 131 .bitrates = rtl8xxxu_rates, 132 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates), 133 }; 134 135 const struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[] = { 136 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00}, 137 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, 138 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00}, 139 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05}, 140 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01}, 141 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f}, 142 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72}, 143 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08}, 144 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, 145 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, 146 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, 147 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, 148 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, 149 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, 150 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16}, 151 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00}, 152 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02}, 153 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, 154 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, 155 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, 156 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, 157 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff}, 158 }; 159 160 static const struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = { 161 {0x800, 0x80040000}, {0x804, 0x00000003}, 162 {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, 163 {0x810, 0x10001331}, {0x814, 0x020c3d10}, 164 {0x818, 0x02200385}, {0x81c, 0x00000000}, 165 {0x820, 0x01000100}, {0x824, 0x00390004}, 166 {0x828, 0x00000000}, {0x82c, 0x00000000}, 167 {0x830, 0x00000000}, {0x834, 0x00000000}, 168 {0x838, 0x00000000}, {0x83c, 0x00000000}, 169 {0x840, 0x00010000}, {0x844, 0x00000000}, 170 {0x848, 0x00000000}, {0x84c, 0x00000000}, 171 {0x850, 0x00000000}, {0x854, 0x00000000}, 172 {0x858, 0x569a569a}, {0x85c, 0x001b25a4}, 173 {0x860, 0x66f60110}, {0x864, 0x061f0130}, 174 {0x868, 0x00000000}, {0x86c, 0x32323200}, 175 {0x870, 0x07000760}, {0x874, 0x22004000}, 176 {0x878, 0x00000808}, {0x87c, 0x00000000}, 177 {0x880, 0xc0083070}, {0x884, 0x000004d5}, 178 {0x888, 0x00000000}, {0x88c, 0xccc000c0}, 179 {0x890, 0x00000800}, {0x894, 0xfffffffe}, 180 {0x898, 0x40302010}, {0x89c, 0x00706050}, 181 {0x900, 0x00000000}, {0x904, 0x00000023}, 182 {0x908, 0x00000000}, {0x90c, 0x81121111}, 183 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c}, 184 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f}, 185 {0xa10, 0x9500bb78}, {0xa14, 0x11144028}, 186 {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, 187 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, 188 {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, 189 {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, 190 {0xa78, 0x00000900}, 191 {0xc00, 0x48071d40}, {0xc04, 0x03a05611}, 192 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, 193 {0xc10, 0x08800000}, {0xc14, 0x40000100}, 194 {0xc18, 0x08800000}, {0xc1c, 0x40000100}, 195 {0xc20, 0x00000000}, {0xc24, 0x00000000}, 196 {0xc28, 0x00000000}, {0xc2c, 0x00000000}, 197 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af}, 198 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, 199 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, 200 {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, 201 {0xc50, 0x69543420}, {0xc54, 0x43bc0094}, 202 {0xc58, 0x69543420}, {0xc5c, 0x433c0094}, 203 {0xc60, 0x00000000}, {0xc64, 0x7112848b}, 204 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, 205 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db}, 206 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612}, 207 {0xc80, 0x40000100}, {0xc84, 0x20f60000}, 208 {0xc88, 0x40000100}, {0xc8c, 0x20200000}, 209 {0xc90, 0x00121820}, {0xc94, 0x00000000}, 210 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, 211 {0xca0, 0x00000000}, {0xca4, 0x00000080}, 212 {0xca8, 0x00000000}, {0xcac, 0x00000000}, 213 {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, 214 {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, 215 {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, 216 {0xcc8, 0x00000000}, {0xccc, 0x00000000}, 217 {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, 218 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, 219 {0xce0, 0x00222222}, {0xce4, 0x00000000}, 220 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, 221 {0xd00, 0x00080740}, {0xd04, 0x00020401}, 222 {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, 223 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, 224 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975}, 225 {0xd30, 0x00000000}, {0xd34, 0x80608000}, 226 {0xd38, 0x00000000}, {0xd3c, 0x00027293}, 227 {0xd40, 0x00000000}, {0xd44, 0x00000000}, 228 {0xd48, 0x00000000}, {0xd4c, 0x00000000}, 229 {0xd50, 0x6437140a}, {0xd54, 0x00000000}, 230 {0xd58, 0x00000000}, {0xd5c, 0x30032064}, 231 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, 232 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, 233 {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, 234 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a}, 235 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a}, 236 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a}, 237 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a}, 238 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, 239 {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, 240 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, 241 {0xe44, 0x01004800}, {0xe48, 0xfb000000}, 242 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, 243 {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, 244 {0xe5c, 0x28160d05}, {0xe60, 0x00000008}, 245 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0}, 246 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0}, 247 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0}, 248 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0}, 249 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0}, 250 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0}, 251 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0}, 252 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0}, 253 {0xf14, 0x00000003}, {0xf4c, 0x00000000}, 254 {0xf00, 0x00000300}, 255 {0xffff, 0xffffffff}, 256 }; 257 258 static const struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = { 259 {0x024, 0x0011800f}, {0x028, 0x00ffdb83}, 260 {0x800, 0x80040002}, {0x804, 0x00000003}, 261 {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, 262 {0x810, 0x10000330}, {0x814, 0x020c3d10}, 263 {0x818, 0x02200385}, {0x81c, 0x00000000}, 264 {0x820, 0x01000100}, {0x824, 0x00390004}, 265 {0x828, 0x01000100}, {0x82c, 0x00390004}, 266 {0x830, 0x27272727}, {0x834, 0x27272727}, 267 {0x838, 0x27272727}, {0x83c, 0x27272727}, 268 {0x840, 0x00010000}, {0x844, 0x00010000}, 269 {0x848, 0x27272727}, {0x84c, 0x27272727}, 270 {0x850, 0x00000000}, {0x854, 0x00000000}, 271 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4}, 272 {0x860, 0x66e60230}, {0x864, 0x061f0130}, 273 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27}, 274 {0x870, 0x07000700}, {0x874, 0x22184000}, 275 {0x878, 0x08080808}, {0x87c, 0x00000000}, 276 {0x880, 0xc0083070}, {0x884, 0x000004d5}, 277 {0x888, 0x00000000}, {0x88c, 0xcc0000c0}, 278 {0x890, 0x00000800}, {0x894, 0xfffffffe}, 279 {0x898, 0x40302010}, {0x89c, 0x00706050}, 280 {0x900, 0x00000000}, {0x904, 0x00000023}, 281 {0x908, 0x00000000}, {0x90c, 0x81121313}, 282 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c}, 283 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f}, 284 {0xa10, 0x9500bb78}, {0xa14, 0x11144028}, 285 {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, 286 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, 287 {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, 288 {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, 289 {0xc00, 0x48071d40}, {0xc04, 0x03a05633}, 290 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, 291 {0xc10, 0x08800000}, {0xc14, 0x40000100}, 292 {0xc18, 0x08800000}, {0xc1c, 0x40000100}, 293 {0xc20, 0x00000000}, {0xc24, 0x00000000}, 294 {0xc28, 0x00000000}, {0xc2c, 0x00000000}, 295 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf}, 296 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, 297 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, 298 {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, 299 {0xc50, 0x69543420}, {0xc54, 0x43bc0094}, 300 {0xc58, 0x69543420}, {0xc5c, 0x433c0094}, 301 {0xc60, 0x00000000}, {0xc64, 0x5116848b}, 302 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, 303 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b}, 304 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612}, 305 {0xc80, 0x40000100}, {0xc84, 0x20f60000}, 306 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000}, 307 {0xc90, 0x00121820}, {0xc94, 0x00000000}, 308 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, 309 {0xca0, 0x00000000}, {0xca4, 0x00000080}, 310 {0xca8, 0x00000000}, {0xcac, 0x00000000}, 311 {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, 312 {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, 313 {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, 314 {0xcc8, 0x00000000}, {0xccc, 0x00000000}, 315 {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, 316 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, 317 {0xce0, 0x00222222}, {0xce4, 0x00000000}, 318 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, 319 {0xd00, 0x00080740}, {0xd04, 0x00020403}, 320 {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, 321 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, 322 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975}, 323 {0xd30, 0x00000000}, {0xd34, 0x80608000}, 324 {0xd38, 0x00000000}, {0xd3c, 0x00027293}, 325 {0xd40, 0x00000000}, {0xd44, 0x00000000}, 326 {0xd48, 0x00000000}, {0xd4c, 0x00000000}, 327 {0xd50, 0x6437140a}, {0xd54, 0x00000000}, 328 {0xd58, 0x00000000}, {0xd5c, 0x30032064}, 329 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, 330 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, 331 {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, 332 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a}, 333 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a}, 334 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a}, 335 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a}, 336 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, 337 {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, 338 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, 339 {0xe44, 0x01004800}, {0xe48, 0xfb000000}, 340 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, 341 {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, 342 {0xe5c, 0x28160d05}, {0xe60, 0x00000010}, 343 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4}, 344 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4}, 345 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4}, 346 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4}, 347 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4}, 348 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4}, 349 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4}, 350 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4}, 351 {0xf14, 0x00000003}, {0xf4c, 0x00000000}, 352 {0xf00, 0x00000300}, 353 {0xffff, 0xffffffff}, 354 }; 355 356 static const struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = { 357 {0x024, 0x0011800f}, {0x028, 0x00ffdb83}, 358 {0x040, 0x000c0004}, {0x800, 0x80040000}, 359 {0x804, 0x00000001}, {0x808, 0x0000fc00}, 360 {0x80c, 0x0000000a}, {0x810, 0x10005388}, 361 {0x814, 0x020c3d10}, {0x818, 0x02200385}, 362 {0x81c, 0x00000000}, {0x820, 0x01000100}, 363 {0x824, 0x00390204}, {0x828, 0x00000000}, 364 {0x82c, 0x00000000}, {0x830, 0x00000000}, 365 {0x834, 0x00000000}, {0x838, 0x00000000}, 366 {0x83c, 0x00000000}, {0x840, 0x00010000}, 367 {0x844, 0x00000000}, {0x848, 0x00000000}, 368 {0x84c, 0x00000000}, {0x850, 0x00000000}, 369 {0x854, 0x00000000}, {0x858, 0x569a569a}, 370 {0x85c, 0x001b25a4}, {0x860, 0x66e60230}, 371 {0x864, 0x061f0130}, {0x868, 0x00000000}, 372 {0x86c, 0x20202000}, {0x870, 0x03000300}, 373 {0x874, 0x22004000}, {0x878, 0x00000808}, 374 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070}, 375 {0x884, 0x000004d5}, {0x888, 0x00000000}, 376 {0x88c, 0xccc000c0}, {0x890, 0x00000800}, 377 {0x894, 0xfffffffe}, {0x898, 0x40302010}, 378 {0x89c, 0x00706050}, {0x900, 0x00000000}, 379 {0x904, 0x00000023}, {0x908, 0x00000000}, 380 {0x90c, 0x81121111}, {0xa00, 0x00d047c8}, 381 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300}, 382 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78}, 383 {0xa14, 0x11144028}, {0xa18, 0x00881117}, 384 {0xa1c, 0x89140f00}, {0xa20, 0x15160000}, 385 {0xa24, 0x070b0f12}, {0xa28, 0x00000104}, 386 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00}, 387 {0xa74, 0x00000007}, {0xc00, 0x48071d40}, 388 {0xc04, 0x03a05611}, {0xc08, 0x000000e4}, 389 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000}, 390 {0xc14, 0x40000100}, {0xc18, 0x08800000}, 391 {0xc1c, 0x40000100}, {0xc20, 0x00000000}, 392 {0xc24, 0x00000000}, {0xc28, 0x00000000}, 393 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44}, 394 {0xc34, 0x469652cf}, {0xc38, 0x49795994}, 395 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f}, 396 {0xc44, 0x000100b7}, {0xc48, 0xec020107}, 397 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e}, 398 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f}, 399 {0xc5c, 0x433c0094}, {0xc60, 0x00000000}, 400 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff}, 401 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d}, 402 {0xc74, 0x018610db}, {0xc78, 0x0000001f}, 403 {0xc7c, 0x00b91612}, {0xc80, 0x24000090}, 404 {0xc84, 0x20f60000}, {0xc88, 0x24000090}, 405 {0xc8c, 0x20200000}, {0xc90, 0x00121820}, 406 {0xc94, 0x00000000}, {0xc98, 0x00121820}, 407 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000}, 408 {0xca4, 0x00000080}, {0xca8, 0x00000000}, 409 {0xcac, 0x00000000}, {0xcb0, 0x00000000}, 410 {0xcb4, 0x00000000}, {0xcb8, 0x00000000}, 411 {0xcbc, 0x28000000}, {0xcc0, 0x00000000}, 412 {0xcc4, 0x00000000}, {0xcc8, 0x00000000}, 413 {0xccc, 0x00000000}, {0xcd0, 0x00000000}, 414 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427}, 415 {0xcdc, 0x00766932}, {0xce0, 0x00222222}, 416 {0xce4, 0x00000000}, {0xce8, 0x37644302}, 417 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740}, 418 {0xd04, 0x00020401}, {0xd08, 0x0000907f}, 419 {0xd0c, 0x20010201}, {0xd10, 0xa0633333}, 420 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b}, 421 {0xd2c, 0xcc979975}, {0xd30, 0x00000000}, 422 {0xd34, 0x80608000}, {0xd38, 0x00000000}, 423 {0xd3c, 0x00027293}, {0xd40, 0x00000000}, 424 {0xd44, 0x00000000}, {0xd48, 0x00000000}, 425 {0xd4c, 0x00000000}, {0xd50, 0x6437140a}, 426 {0xd54, 0x00000000}, {0xd58, 0x00000000}, 427 {0xd5c, 0x30032064}, {0xd60, 0x4653de68}, 428 {0xd64, 0x04518a3c}, {0xd68, 0x00002101}, 429 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e}, 430 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24}, 431 {0xe00, 0x24242424}, {0xe04, 0x24242424}, 432 {0xe08, 0x03902024}, {0xe10, 0x24242424}, 433 {0xe14, 0x24242424}, {0xe18, 0x24242424}, 434 {0xe1c, 0x24242424}, {0xe28, 0x00000000}, 435 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f}, 436 {0xe38, 0x02140102}, {0xe3c, 0x681604c2}, 437 {0xe40, 0x01007c00}, {0xe44, 0x01004800}, 438 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1}, 439 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f}, 440 {0xe58, 0x02140102}, {0xe5c, 0x28160d05}, 441 {0xe60, 0x00000008}, {0xe68, 0x001b25a4}, 442 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0}, 443 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0}, 444 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0}, 445 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0}, 446 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0}, 447 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0}, 448 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0}, 449 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448}, 450 {0xf14, 0x00000003}, {0xf4c, 0x00000000}, 451 {0xf00, 0x00000300}, 452 {0xffff, 0xffffffff}, 453 }; 454 455 static const struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = { 456 {0xc78, 0x7b000001}, {0xc78, 0x7b010001}, 457 {0xc78, 0x7b020001}, {0xc78, 0x7b030001}, 458 {0xc78, 0x7b040001}, {0xc78, 0x7b050001}, 459 {0xc78, 0x7a060001}, {0xc78, 0x79070001}, 460 {0xc78, 0x78080001}, {0xc78, 0x77090001}, 461 {0xc78, 0x760a0001}, {0xc78, 0x750b0001}, 462 {0xc78, 0x740c0001}, {0xc78, 0x730d0001}, 463 {0xc78, 0x720e0001}, {0xc78, 0x710f0001}, 464 {0xc78, 0x70100001}, {0xc78, 0x6f110001}, 465 {0xc78, 0x6e120001}, {0xc78, 0x6d130001}, 466 {0xc78, 0x6c140001}, {0xc78, 0x6b150001}, 467 {0xc78, 0x6a160001}, {0xc78, 0x69170001}, 468 {0xc78, 0x68180001}, {0xc78, 0x67190001}, 469 {0xc78, 0x661a0001}, {0xc78, 0x651b0001}, 470 {0xc78, 0x641c0001}, {0xc78, 0x631d0001}, 471 {0xc78, 0x621e0001}, {0xc78, 0x611f0001}, 472 {0xc78, 0x60200001}, {0xc78, 0x49210001}, 473 {0xc78, 0x48220001}, {0xc78, 0x47230001}, 474 {0xc78, 0x46240001}, {0xc78, 0x45250001}, 475 {0xc78, 0x44260001}, {0xc78, 0x43270001}, 476 {0xc78, 0x42280001}, {0xc78, 0x41290001}, 477 {0xc78, 0x402a0001}, {0xc78, 0x262b0001}, 478 {0xc78, 0x252c0001}, {0xc78, 0x242d0001}, 479 {0xc78, 0x232e0001}, {0xc78, 0x222f0001}, 480 {0xc78, 0x21300001}, {0xc78, 0x20310001}, 481 {0xc78, 0x06320001}, {0xc78, 0x05330001}, 482 {0xc78, 0x04340001}, {0xc78, 0x03350001}, 483 {0xc78, 0x02360001}, {0xc78, 0x01370001}, 484 {0xc78, 0x00380001}, {0xc78, 0x00390001}, 485 {0xc78, 0x003a0001}, {0xc78, 0x003b0001}, 486 {0xc78, 0x003c0001}, {0xc78, 0x003d0001}, 487 {0xc78, 0x003e0001}, {0xc78, 0x003f0001}, 488 {0xc78, 0x7b400001}, {0xc78, 0x7b410001}, 489 {0xc78, 0x7b420001}, {0xc78, 0x7b430001}, 490 {0xc78, 0x7b440001}, {0xc78, 0x7b450001}, 491 {0xc78, 0x7a460001}, {0xc78, 0x79470001}, 492 {0xc78, 0x78480001}, {0xc78, 0x77490001}, 493 {0xc78, 0x764a0001}, {0xc78, 0x754b0001}, 494 {0xc78, 0x744c0001}, {0xc78, 0x734d0001}, 495 {0xc78, 0x724e0001}, {0xc78, 0x714f0001}, 496 {0xc78, 0x70500001}, {0xc78, 0x6f510001}, 497 {0xc78, 0x6e520001}, {0xc78, 0x6d530001}, 498 {0xc78, 0x6c540001}, {0xc78, 0x6b550001}, 499 {0xc78, 0x6a560001}, {0xc78, 0x69570001}, 500 {0xc78, 0x68580001}, {0xc78, 0x67590001}, 501 {0xc78, 0x665a0001}, {0xc78, 0x655b0001}, 502 {0xc78, 0x645c0001}, {0xc78, 0x635d0001}, 503 {0xc78, 0x625e0001}, {0xc78, 0x615f0001}, 504 {0xc78, 0x60600001}, {0xc78, 0x49610001}, 505 {0xc78, 0x48620001}, {0xc78, 0x47630001}, 506 {0xc78, 0x46640001}, {0xc78, 0x45650001}, 507 {0xc78, 0x44660001}, {0xc78, 0x43670001}, 508 {0xc78, 0x42680001}, {0xc78, 0x41690001}, 509 {0xc78, 0x406a0001}, {0xc78, 0x266b0001}, 510 {0xc78, 0x256c0001}, {0xc78, 0x246d0001}, 511 {0xc78, 0x236e0001}, {0xc78, 0x226f0001}, 512 {0xc78, 0x21700001}, {0xc78, 0x20710001}, 513 {0xc78, 0x06720001}, {0xc78, 0x05730001}, 514 {0xc78, 0x04740001}, {0xc78, 0x03750001}, 515 {0xc78, 0x02760001}, {0xc78, 0x01770001}, 516 {0xc78, 0x00780001}, {0xc78, 0x00790001}, 517 {0xc78, 0x007a0001}, {0xc78, 0x007b0001}, 518 {0xc78, 0x007c0001}, {0xc78, 0x007d0001}, 519 {0xc78, 0x007e0001}, {0xc78, 0x007f0001}, 520 {0xc78, 0x3800001e}, {0xc78, 0x3801001e}, 521 {0xc78, 0x3802001e}, {0xc78, 0x3803001e}, 522 {0xc78, 0x3804001e}, {0xc78, 0x3805001e}, 523 {0xc78, 0x3806001e}, {0xc78, 0x3807001e}, 524 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e}, 525 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e}, 526 {0xc78, 0x440c001e}, {0xc78, 0x480d001e}, 527 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e}, 528 {0xc78, 0x5210001e}, {0xc78, 0x5611001e}, 529 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e}, 530 {0xc78, 0x6014001e}, {0xc78, 0x6015001e}, 531 {0xc78, 0x6016001e}, {0xc78, 0x6217001e}, 532 {0xc78, 0x6218001e}, {0xc78, 0x6219001e}, 533 {0xc78, 0x621a001e}, {0xc78, 0x621b001e}, 534 {0xc78, 0x621c001e}, {0xc78, 0x621d001e}, 535 {0xc78, 0x621e001e}, {0xc78, 0x621f001e}, 536 {0xffff, 0xffffffff} 537 }; 538 539 static const struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = { 540 {0xc78, 0x7b000001}, {0xc78, 0x7b010001}, 541 {0xc78, 0x7b020001}, {0xc78, 0x7b030001}, 542 {0xc78, 0x7b040001}, {0xc78, 0x7b050001}, 543 {0xc78, 0x7b060001}, {0xc78, 0x7b070001}, 544 {0xc78, 0x7b080001}, {0xc78, 0x7a090001}, 545 {0xc78, 0x790a0001}, {0xc78, 0x780b0001}, 546 {0xc78, 0x770c0001}, {0xc78, 0x760d0001}, 547 {0xc78, 0x750e0001}, {0xc78, 0x740f0001}, 548 {0xc78, 0x73100001}, {0xc78, 0x72110001}, 549 {0xc78, 0x71120001}, {0xc78, 0x70130001}, 550 {0xc78, 0x6f140001}, {0xc78, 0x6e150001}, 551 {0xc78, 0x6d160001}, {0xc78, 0x6c170001}, 552 {0xc78, 0x6b180001}, {0xc78, 0x6a190001}, 553 {0xc78, 0x691a0001}, {0xc78, 0x681b0001}, 554 {0xc78, 0x671c0001}, {0xc78, 0x661d0001}, 555 {0xc78, 0x651e0001}, {0xc78, 0x641f0001}, 556 {0xc78, 0x63200001}, {0xc78, 0x62210001}, 557 {0xc78, 0x61220001}, {0xc78, 0x60230001}, 558 {0xc78, 0x46240001}, {0xc78, 0x45250001}, 559 {0xc78, 0x44260001}, {0xc78, 0x43270001}, 560 {0xc78, 0x42280001}, {0xc78, 0x41290001}, 561 {0xc78, 0x402a0001}, {0xc78, 0x262b0001}, 562 {0xc78, 0x252c0001}, {0xc78, 0x242d0001}, 563 {0xc78, 0x232e0001}, {0xc78, 0x222f0001}, 564 {0xc78, 0x21300001}, {0xc78, 0x20310001}, 565 {0xc78, 0x06320001}, {0xc78, 0x05330001}, 566 {0xc78, 0x04340001}, {0xc78, 0x03350001}, 567 {0xc78, 0x02360001}, {0xc78, 0x01370001}, 568 {0xc78, 0x00380001}, {0xc78, 0x00390001}, 569 {0xc78, 0x003a0001}, {0xc78, 0x003b0001}, 570 {0xc78, 0x003c0001}, {0xc78, 0x003d0001}, 571 {0xc78, 0x003e0001}, {0xc78, 0x003f0001}, 572 {0xc78, 0x7b400001}, {0xc78, 0x7b410001}, 573 {0xc78, 0x7b420001}, {0xc78, 0x7b430001}, 574 {0xc78, 0x7b440001}, {0xc78, 0x7b450001}, 575 {0xc78, 0x7b460001}, {0xc78, 0x7b470001}, 576 {0xc78, 0x7b480001}, {0xc78, 0x7a490001}, 577 {0xc78, 0x794a0001}, {0xc78, 0x784b0001}, 578 {0xc78, 0x774c0001}, {0xc78, 0x764d0001}, 579 {0xc78, 0x754e0001}, {0xc78, 0x744f0001}, 580 {0xc78, 0x73500001}, {0xc78, 0x72510001}, 581 {0xc78, 0x71520001}, {0xc78, 0x70530001}, 582 {0xc78, 0x6f540001}, {0xc78, 0x6e550001}, 583 {0xc78, 0x6d560001}, {0xc78, 0x6c570001}, 584 {0xc78, 0x6b580001}, {0xc78, 0x6a590001}, 585 {0xc78, 0x695a0001}, {0xc78, 0x685b0001}, 586 {0xc78, 0x675c0001}, {0xc78, 0x665d0001}, 587 {0xc78, 0x655e0001}, {0xc78, 0x645f0001}, 588 {0xc78, 0x63600001}, {0xc78, 0x62610001}, 589 {0xc78, 0x61620001}, {0xc78, 0x60630001}, 590 {0xc78, 0x46640001}, {0xc78, 0x45650001}, 591 {0xc78, 0x44660001}, {0xc78, 0x43670001}, 592 {0xc78, 0x42680001}, {0xc78, 0x41690001}, 593 {0xc78, 0x406a0001}, {0xc78, 0x266b0001}, 594 {0xc78, 0x256c0001}, {0xc78, 0x246d0001}, 595 {0xc78, 0x236e0001}, {0xc78, 0x226f0001}, 596 {0xc78, 0x21700001}, {0xc78, 0x20710001}, 597 {0xc78, 0x06720001}, {0xc78, 0x05730001}, 598 {0xc78, 0x04740001}, {0xc78, 0x03750001}, 599 {0xc78, 0x02760001}, {0xc78, 0x01770001}, 600 {0xc78, 0x00780001}, {0xc78, 0x00790001}, 601 {0xc78, 0x007a0001}, {0xc78, 0x007b0001}, 602 {0xc78, 0x007c0001}, {0xc78, 0x007d0001}, 603 {0xc78, 0x007e0001}, {0xc78, 0x007f0001}, 604 {0xc78, 0x3800001e}, {0xc78, 0x3801001e}, 605 {0xc78, 0x3802001e}, {0xc78, 0x3803001e}, 606 {0xc78, 0x3804001e}, {0xc78, 0x3805001e}, 607 {0xc78, 0x3806001e}, {0xc78, 0x3807001e}, 608 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e}, 609 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e}, 610 {0xc78, 0x440c001e}, {0xc78, 0x480d001e}, 611 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e}, 612 {0xc78, 0x5210001e}, {0xc78, 0x5611001e}, 613 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e}, 614 {0xc78, 0x6014001e}, {0xc78, 0x6015001e}, 615 {0xc78, 0x6016001e}, {0xc78, 0x6217001e}, 616 {0xc78, 0x6218001e}, {0xc78, 0x6219001e}, 617 {0xc78, 0x621a001e}, {0xc78, 0x621b001e}, 618 {0xc78, 0x621c001e}, {0xc78, 0x621d001e}, 619 {0xc78, 0x621e001e}, {0xc78, 0x621f001e}, 620 {0xffff, 0xffffffff} 621 }; 622 623 static const struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = { 624 { /* RF_A */ 625 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1, 626 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2, 627 .lssiparm = REG_FPGA0_XA_LSSI_PARM, 628 .hspiread = REG_HSPI_XA_READBACK, 629 .lssiread = REG_FPGA0_XA_LSSI_READBACK, 630 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL, 631 }, 632 { /* RF_B */ 633 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1, 634 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2, 635 .lssiparm = REG_FPGA0_XB_LSSI_PARM, 636 .hspiread = REG_HSPI_XB_READBACK, 637 .lssiread = REG_FPGA0_XB_LSSI_READBACK, 638 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL, 639 }, 640 }; 641 642 const u32 rtl8xxxu_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = { 643 REG_OFDM0_XA_RX_IQ_IMBALANCE, 644 REG_OFDM0_XB_RX_IQ_IMBALANCE, 645 REG_OFDM0_ENERGY_CCA_THRES, 646 REG_OFDM0_AGC_RSSI_TABLE, 647 REG_OFDM0_XA_TX_IQ_IMBALANCE, 648 REG_OFDM0_XB_TX_IQ_IMBALANCE, 649 REG_OFDM0_XC_TX_AFE, 650 REG_OFDM0_XD_TX_AFE, 651 REG_OFDM0_RX_IQ_EXT_ANTA 652 }; 653 654 u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr) 655 { 656 struct usb_device *udev = priv->udev; 657 int len; 658 u8 data; 659 660 if (priv->rtl_chip == RTL8710B && addr <= 0xff) 661 addr |= 0x8000; 662 663 mutex_lock(&priv->usb_buf_mutex); 664 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 665 REALTEK_USB_CMD_REQ, REALTEK_USB_READ, 666 addr, 0, &priv->usb_buf.val8, sizeof(u8), 667 RTW_USB_CONTROL_MSG_TIMEOUT); 668 data = priv->usb_buf.val8; 669 mutex_unlock(&priv->usb_buf_mutex); 670 671 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) 672 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n", 673 __func__, addr, data, len); 674 return data; 675 } 676 677 u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr) 678 { 679 struct usb_device *udev = priv->udev; 680 int len; 681 u16 data; 682 683 if (priv->rtl_chip == RTL8710B && addr <= 0xff) 684 addr |= 0x8000; 685 686 mutex_lock(&priv->usb_buf_mutex); 687 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 688 REALTEK_USB_CMD_REQ, REALTEK_USB_READ, 689 addr, 0, &priv->usb_buf.val16, sizeof(u16), 690 RTW_USB_CONTROL_MSG_TIMEOUT); 691 data = le16_to_cpu(priv->usb_buf.val16); 692 mutex_unlock(&priv->usb_buf_mutex); 693 694 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) 695 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n", 696 __func__, addr, data, len); 697 return data; 698 } 699 700 u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr) 701 { 702 struct usb_device *udev = priv->udev; 703 int len; 704 u32 data; 705 706 if (priv->rtl_chip == RTL8710B && addr <= 0xff) 707 addr |= 0x8000; 708 709 mutex_lock(&priv->usb_buf_mutex); 710 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 711 REALTEK_USB_CMD_REQ, REALTEK_USB_READ, 712 addr, 0, &priv->usb_buf.val32, sizeof(u32), 713 RTW_USB_CONTROL_MSG_TIMEOUT); 714 data = le32_to_cpu(priv->usb_buf.val32); 715 mutex_unlock(&priv->usb_buf_mutex); 716 717 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) 718 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n", 719 __func__, addr, data, len); 720 return data; 721 } 722 723 int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val) 724 { 725 struct usb_device *udev = priv->udev; 726 int ret; 727 728 if (priv->rtl_chip == RTL8710B && addr <= 0xff) 729 addr |= 0x8000; 730 731 mutex_lock(&priv->usb_buf_mutex); 732 priv->usb_buf.val8 = val; 733 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 734 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 735 addr, 0, &priv->usb_buf.val8, sizeof(u8), 736 RTW_USB_CONTROL_MSG_TIMEOUT); 737 738 mutex_unlock(&priv->usb_buf_mutex); 739 740 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) 741 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n", 742 __func__, addr, val); 743 return ret; 744 } 745 746 int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val) 747 { 748 struct usb_device *udev = priv->udev; 749 int ret; 750 751 if (priv->rtl_chip == RTL8710B && addr <= 0xff) 752 addr |= 0x8000; 753 754 mutex_lock(&priv->usb_buf_mutex); 755 priv->usb_buf.val16 = cpu_to_le16(val); 756 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 757 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 758 addr, 0, &priv->usb_buf.val16, sizeof(u16), 759 RTW_USB_CONTROL_MSG_TIMEOUT); 760 mutex_unlock(&priv->usb_buf_mutex); 761 762 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) 763 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n", 764 __func__, addr, val); 765 return ret; 766 } 767 768 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val) 769 { 770 struct usb_device *udev = priv->udev; 771 int ret; 772 773 if (priv->rtl_chip == RTL8710B && addr <= 0xff) 774 addr |= 0x8000; 775 776 mutex_lock(&priv->usb_buf_mutex); 777 priv->usb_buf.val32 = cpu_to_le32(val); 778 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 779 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 780 addr, 0, &priv->usb_buf.val32, sizeof(u32), 781 RTW_USB_CONTROL_MSG_TIMEOUT); 782 mutex_unlock(&priv->usb_buf_mutex); 783 784 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) 785 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n", 786 __func__, addr, val); 787 return ret; 788 } 789 790 int rtl8xxxu_write8_set(struct rtl8xxxu_priv *priv, u16 addr, u8 bits) 791 { 792 u8 val8; 793 794 val8 = rtl8xxxu_read8(priv, addr); 795 val8 |= bits; 796 return rtl8xxxu_write8(priv, addr, val8); 797 } 798 799 int rtl8xxxu_write8_clear(struct rtl8xxxu_priv *priv, u16 addr, u8 bits) 800 { 801 u8 val8; 802 803 val8 = rtl8xxxu_read8(priv, addr); 804 val8 &= ~bits; 805 return rtl8xxxu_write8(priv, addr, val8); 806 } 807 808 int rtl8xxxu_write16_set(struct rtl8xxxu_priv *priv, u16 addr, u16 bits) 809 { 810 u16 val16; 811 812 val16 = rtl8xxxu_read16(priv, addr); 813 val16 |= bits; 814 return rtl8xxxu_write16(priv, addr, val16); 815 } 816 817 int rtl8xxxu_write16_clear(struct rtl8xxxu_priv *priv, u16 addr, u16 bits) 818 { 819 u16 val16; 820 821 val16 = rtl8xxxu_read16(priv, addr); 822 val16 &= ~bits; 823 return rtl8xxxu_write16(priv, addr, val16); 824 } 825 826 int rtl8xxxu_write32_set(struct rtl8xxxu_priv *priv, u16 addr, u32 bits) 827 { 828 u32 val32; 829 830 val32 = rtl8xxxu_read32(priv, addr); 831 val32 |= bits; 832 return rtl8xxxu_write32(priv, addr, val32); 833 } 834 835 int rtl8xxxu_write32_clear(struct rtl8xxxu_priv *priv, u16 addr, u32 bits) 836 { 837 u32 val32; 838 839 val32 = rtl8xxxu_read32(priv, addr); 840 val32 &= ~bits; 841 return rtl8xxxu_write32(priv, addr, val32); 842 } 843 844 int rtl8xxxu_write32_mask(struct rtl8xxxu_priv *priv, u16 addr, 845 u32 mask, u32 val) 846 { 847 u32 orig, new, shift; 848 849 shift = __ffs(mask); 850 851 orig = rtl8xxxu_read32(priv, addr); 852 new = (orig & ~mask) | ((val << shift) & mask); 853 return rtl8xxxu_write32(priv, addr, new); 854 } 855 856 int rtl8xxxu_write_rfreg_mask(struct rtl8xxxu_priv *priv, 857 enum rtl8xxxu_rfpath path, u8 reg, 858 u32 mask, u32 val) 859 { 860 u32 orig, new, shift; 861 862 shift = __ffs(mask); 863 864 orig = rtl8xxxu_read_rfreg(priv, path, reg); 865 new = (orig & ~mask) | ((val << shift) & mask); 866 return rtl8xxxu_write_rfreg(priv, path, reg, new); 867 } 868 869 static int 870 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len) 871 { 872 struct usb_device *udev = priv->udev; 873 int blocksize = priv->fops->writeN_block_size; 874 int ret, i, count, remainder; 875 876 count = len / blocksize; 877 remainder = len % blocksize; 878 879 for (i = 0; i < count; i++) { 880 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 881 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 882 addr, 0, buf, blocksize, 883 RTW_USB_CONTROL_MSG_TIMEOUT); 884 if (ret != blocksize) 885 goto write_error; 886 887 addr += blocksize; 888 buf += blocksize; 889 } 890 891 if (remainder) { 892 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 893 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 894 addr, 0, buf, remainder, 895 RTW_USB_CONTROL_MSG_TIMEOUT); 896 if (ret != remainder) 897 goto write_error; 898 } 899 900 return len; 901 902 write_error: 903 dev_info(&udev->dev, 904 "%s: Failed to write block at addr: %04x size: %04x\n", 905 __func__, addr, blocksize); 906 return -EAGAIN; 907 } 908 909 u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv, 910 enum rtl8xxxu_rfpath path, u8 reg) 911 { 912 u32 hssia, val32, retval; 913 914 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2); 915 if (path != RF_A) 916 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2); 917 else 918 val32 = hssia; 919 920 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK; 921 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT); 922 val32 |= FPGA0_HSSI_PARM2_EDGE_READ; 923 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ; 924 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); 925 926 udelay(10); 927 928 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32); 929 udelay(100); 930 931 hssia |= FPGA0_HSSI_PARM2_EDGE_READ; 932 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); 933 udelay(10); 934 935 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1); 936 if (val32 & FPGA0_HSSI_PARM1_PI) 937 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread); 938 else 939 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread); 940 941 retval &= 0xfffff; 942 943 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ) 944 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n", 945 __func__, reg, retval); 946 return retval; 947 } 948 949 /* 950 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can 951 * have write issues in high temperature conditions. We may have to 952 * retry writing them. 953 */ 954 int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv, 955 enum rtl8xxxu_rfpath path, u8 reg, u32 data) 956 { 957 int ret, retval; 958 u32 dataaddr, val32; 959 960 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE) 961 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n", 962 __func__, reg, data); 963 964 data &= FPGA0_LSSI_PARM_DATA_MASK; 965 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data; 966 967 if (priv->rtl_chip == RTL8192E) { 968 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 969 val32 &= ~0x20000; 970 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 971 } 972 973 /* Use XB for path B */ 974 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr); 975 if (ret != sizeof(dataaddr)) 976 retval = -EIO; 977 else 978 retval = 0; 979 980 udelay(1); 981 982 if (priv->rtl_chip == RTL8192E) { 983 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 984 val32 |= 0x20000; 985 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 986 } 987 988 return retval; 989 } 990 991 static int 992 rtl8xxxu_gen1_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len) 993 { 994 struct device *dev = &priv->udev->dev; 995 int mbox_nr, retry, retval = 0; 996 int mbox_reg, mbox_ext_reg; 997 u8 val8; 998 999 mutex_lock(&priv->h2c_mutex); 1000 1001 mbox_nr = priv->next_mbox; 1002 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4); 1003 mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2); 1004 1005 /* 1006 * MBOX ready? 1007 */ 1008 retry = 100; 1009 do { 1010 val8 = rtl8xxxu_read8(priv, REG_HMTFR); 1011 if (!(val8 & BIT(mbox_nr))) 1012 break; 1013 } while (retry--); 1014 1015 if (!retry) { 1016 dev_info(dev, "%s: Mailbox busy\n", __func__); 1017 retval = -EBUSY; 1018 goto error; 1019 } 1020 1021 /* 1022 * Need to swap as it's being swapped again by rtl8xxxu_write16/32() 1023 */ 1024 if (len > sizeof(u32)) { 1025 rtl8xxxu_write16(priv, mbox_ext_reg, le16_to_cpu(h2c->raw.ext)); 1026 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 1027 dev_info(dev, "H2C_EXT %04x\n", 1028 le16_to_cpu(h2c->raw.ext)); 1029 } 1030 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data)); 1031 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 1032 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data)); 1033 1034 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX; 1035 1036 error: 1037 mutex_unlock(&priv->h2c_mutex); 1038 return retval; 1039 } 1040 1041 int 1042 rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len) 1043 { 1044 struct device *dev = &priv->udev->dev; 1045 int mbox_nr, retry, retval = 0; 1046 int mbox_reg, mbox_ext_reg; 1047 u8 val8; 1048 1049 mutex_lock(&priv->h2c_mutex); 1050 1051 mbox_nr = priv->next_mbox; 1052 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4); 1053 mbox_ext_reg = REG_HMBOX_EXT0_8723B + (mbox_nr * 4); 1054 1055 /* 1056 * MBOX ready? 1057 */ 1058 retry = 100; 1059 do { 1060 val8 = rtl8xxxu_read8(priv, REG_HMTFR); 1061 if (!(val8 & BIT(mbox_nr))) 1062 break; 1063 } while (retry--); 1064 1065 if (!retry) { 1066 dev_info(dev, "%s: Mailbox busy\n", __func__); 1067 retval = -EBUSY; 1068 goto error; 1069 } 1070 1071 /* 1072 * Need to swap as it's being swapped again by rtl8xxxu_write16/32() 1073 */ 1074 if (len > sizeof(u32)) { 1075 rtl8xxxu_write32(priv, mbox_ext_reg, 1076 le32_to_cpu(h2c->raw_wide.ext)); 1077 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 1078 dev_info(dev, "H2C_EXT %08x\n", 1079 le32_to_cpu(h2c->raw_wide.ext)); 1080 } 1081 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data)); 1082 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 1083 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data)); 1084 1085 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX; 1086 1087 error: 1088 mutex_unlock(&priv->h2c_mutex); 1089 return retval; 1090 } 1091 1092 void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv) 1093 { 1094 u8 val8; 1095 u32 val32; 1096 1097 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL); 1098 val8 |= BIT(0) | BIT(3); 1099 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8); 1100 1101 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); 1102 val32 &= ~(BIT(4) | BIT(5)); 1103 val32 |= BIT(3); 1104 if (priv->rf_paths == 2) { 1105 val32 &= ~(BIT(20) | BIT(21)); 1106 val32 |= BIT(19); 1107 } 1108 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); 1109 1110 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1111 val32 &= ~OFDM_RF_PATH_TX_MASK; 1112 if (priv->tx_paths == 2) 1113 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B; 1114 else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C) 1115 val32 |= OFDM_RF_PATH_TX_B; 1116 else 1117 val32 |= OFDM_RF_PATH_TX_A; 1118 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1119 1120 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1121 val32 &= ~FPGA_RF_MODE_JAPAN; 1122 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1123 1124 if (priv->rf_paths == 2) 1125 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0); 1126 else 1127 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0); 1128 1129 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95); 1130 if (priv->rf_paths == 2) 1131 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95); 1132 1133 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); 1134 } 1135 1136 void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv) 1137 { 1138 u8 sps0; 1139 u32 val32; 1140 1141 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL); 1142 1143 /* RF RX code for preamble power saving */ 1144 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); 1145 val32 &= ~(BIT(3) | BIT(4) | BIT(5)); 1146 if (priv->rf_paths == 2) 1147 val32 &= ~(BIT(19) | BIT(20) | BIT(21)); 1148 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); 1149 1150 /* Disable TX for four paths */ 1151 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1152 val32 &= ~OFDM_RF_PATH_TX_MASK; 1153 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1154 1155 /* Enable power saving */ 1156 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1157 val32 |= FPGA_RF_MODE_JAPAN; 1158 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1159 1160 /* AFE control register to power down bits [30:22] */ 1161 if (priv->rf_paths == 2) 1162 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0); 1163 else 1164 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0); 1165 1166 /* Power down RF module */ 1167 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); 1168 if (priv->rf_paths == 2) 1169 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0); 1170 1171 sps0 &= ~(BIT(0) | BIT(3)); 1172 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0); 1173 } 1174 1175 static void rtl8xxxu_stop_tx_beacon(struct rtl8xxxu_priv *priv) 1176 { 1177 u8 val8; 1178 1179 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2); 1180 val8 &= ~BIT(6); 1181 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8); 1182 1183 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64); 1184 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2); 1185 val8 &= ~BIT(0); 1186 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8); 1187 } 1188 1189 static void rtl8xxxu_start_tx_beacon(struct rtl8xxxu_priv *priv) 1190 { 1191 u8 val8; 1192 1193 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2); 1194 val8 |= EN_BCNQ_DL >> 16; 1195 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8); 1196 1197 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x80); 1198 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2); 1199 val8 &= 0xF0; 1200 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8); 1201 } 1202 1203 1204 /* 1205 * The rtl8723a has 3 channel groups for it's efuse settings. It only 1206 * supports the 2.4GHz band, so channels 1 - 14: 1207 * group 0: channels 1 - 3 1208 * group 1: channels 4 - 9 1209 * group 2: channels 10 - 14 1210 * 1211 * Note: We index from 0 in the code 1212 */ 1213 static int rtl8xxxu_gen1_channel_to_group(int channel) 1214 { 1215 int group; 1216 1217 if (channel < 4) 1218 group = 0; 1219 else if (channel < 10) 1220 group = 1; 1221 else 1222 group = 2; 1223 1224 return group; 1225 } 1226 1227 /* 1228 * Valid for rtl8723bu and rtl8192eu 1229 */ 1230 int rtl8xxxu_gen2_channel_to_group(int channel) 1231 { 1232 int group; 1233 1234 if (channel < 3) 1235 group = 0; 1236 else if (channel < 6) 1237 group = 1; 1238 else if (channel < 9) 1239 group = 2; 1240 else if (channel < 12) 1241 group = 3; 1242 else 1243 group = 4; 1244 1245 return group; 1246 } 1247 1248 void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw) 1249 { 1250 struct rtl8xxxu_priv *priv = hw->priv; 1251 u32 val32, rsr; 1252 u8 val8, opmode; 1253 bool ht = true; 1254 int sec_ch_above, channel; 1255 int i; 1256 1257 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE); 1258 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 1259 channel = hw->conf.chandef.chan->hw_value; 1260 1261 switch (hw->conf.chandef.width) { 1262 case NL80211_CHAN_WIDTH_20_NOHT: 1263 ht = false; 1264 fallthrough; 1265 case NL80211_CHAN_WIDTH_20: 1266 opmode |= BW_OPMODE_20MHZ; 1267 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); 1268 1269 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1270 val32 &= ~FPGA_RF_MODE; 1271 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1272 1273 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1274 val32 &= ~FPGA_RF_MODE; 1275 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1276 1277 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); 1278 val32 |= FPGA0_ANALOG2_20MHZ; 1279 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); 1280 break; 1281 case NL80211_CHAN_WIDTH_40: 1282 if (hw->conf.chandef.center_freq1 > 1283 hw->conf.chandef.chan->center_freq) { 1284 sec_ch_above = 1; 1285 channel += 2; 1286 } else { 1287 sec_ch_above = 0; 1288 channel -= 2; 1289 } 1290 1291 opmode &= ~BW_OPMODE_20MHZ; 1292 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); 1293 rsr &= ~RSR_RSC_BANDWIDTH_40M; 1294 if (sec_ch_above) 1295 rsr |= RSR_RSC_UPPER_SUB_CHANNEL; 1296 else 1297 rsr |= RSR_RSC_LOWER_SUB_CHANNEL; 1298 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr); 1299 1300 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1301 val32 |= FPGA_RF_MODE; 1302 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1303 1304 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1305 val32 |= FPGA_RF_MODE; 1306 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1307 1308 /* 1309 * Set Control channel to upper or lower. These settings 1310 * are required only for 40MHz 1311 */ 1312 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); 1313 val32 &= ~CCK0_SIDEBAND; 1314 if (!sec_ch_above) 1315 val32 |= CCK0_SIDEBAND; 1316 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); 1317 1318 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 1319 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ 1320 if (sec_ch_above) 1321 val32 |= OFDM_LSTF_PRIME_CH_LOW; 1322 else 1323 val32 |= OFDM_LSTF_PRIME_CH_HIGH; 1324 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 1325 1326 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); 1327 val32 &= ~FPGA0_ANALOG2_20MHZ; 1328 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); 1329 1330 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 1331 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); 1332 if (sec_ch_above) 1333 val32 |= FPGA0_PS_UPPER_CHANNEL; 1334 else 1335 val32 |= FPGA0_PS_LOWER_CHANNEL; 1336 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 1337 break; 1338 1339 default: 1340 break; 1341 } 1342 1343 for (i = RF_A; i < priv->rf_paths; i++) { 1344 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1345 val32 &= ~MODE_AG_CHANNEL_MASK; 1346 val32 |= channel; 1347 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1348 } 1349 1350 if (ht) 1351 val8 = 0x0e; 1352 else 1353 val8 = 0x0a; 1354 1355 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8); 1356 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8); 1357 1358 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808); 1359 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a); 1360 1361 for (i = RF_A; i < priv->rf_paths; i++) { 1362 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1363 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) 1364 val32 &= ~MODE_AG_CHANNEL_20MHZ; 1365 else 1366 val32 |= MODE_AG_CHANNEL_20MHZ; 1367 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1368 } 1369 } 1370 1371 void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw) 1372 { 1373 struct rtl8xxxu_priv *priv = hw->priv; 1374 u32 val32; 1375 u8 val8, subchannel; 1376 u16 rf_mode_bw; 1377 bool ht = true; 1378 int sec_ch_above, channel; 1379 int i; 1380 1381 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL); 1382 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK; 1383 channel = hw->conf.chandef.chan->hw_value; 1384 1385 /* Hack */ 1386 subchannel = 0; 1387 1388 switch (hw->conf.chandef.width) { 1389 case NL80211_CHAN_WIDTH_20_NOHT: 1390 ht = false; 1391 fallthrough; 1392 case NL80211_CHAN_WIDTH_20: 1393 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20; 1394 subchannel = 0; 1395 1396 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1397 val32 &= ~FPGA_RF_MODE; 1398 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1399 1400 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1401 val32 &= ~FPGA_RF_MODE; 1402 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1403 1404 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); 1405 val32 &= ~(BIT(30) | BIT(31)); 1406 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); 1407 1408 break; 1409 case NL80211_CHAN_WIDTH_40: 1410 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40; 1411 1412 if (hw->conf.chandef.center_freq1 > 1413 hw->conf.chandef.chan->center_freq) { 1414 sec_ch_above = 1; 1415 channel += 2; 1416 } else { 1417 sec_ch_above = 0; 1418 channel -= 2; 1419 } 1420 1421 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1422 val32 |= FPGA_RF_MODE; 1423 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1424 1425 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1426 val32 |= FPGA_RF_MODE; 1427 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1428 1429 /* 1430 * Set Control channel to upper or lower. These settings 1431 * are required only for 40MHz 1432 */ 1433 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); 1434 val32 &= ~CCK0_SIDEBAND; 1435 if (!sec_ch_above) 1436 val32 |= CCK0_SIDEBAND; 1437 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); 1438 1439 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 1440 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ 1441 if (sec_ch_above) 1442 val32 |= OFDM_LSTF_PRIME_CH_LOW; 1443 else 1444 val32 |= OFDM_LSTF_PRIME_CH_HIGH; 1445 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 1446 1447 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 1448 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); 1449 if (sec_ch_above) 1450 val32 |= FPGA0_PS_UPPER_CHANNEL; 1451 else 1452 val32 |= FPGA0_PS_LOWER_CHANNEL; 1453 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 1454 break; 1455 case NL80211_CHAN_WIDTH_80: 1456 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80; 1457 break; 1458 default: 1459 break; 1460 } 1461 1462 for (i = RF_A; i < priv->rf_paths; i++) { 1463 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1464 val32 &= ~MODE_AG_CHANNEL_MASK; 1465 val32 |= channel; 1466 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1467 } 1468 1469 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw); 1470 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel); 1471 1472 if (ht) 1473 val8 = 0x0e; 1474 else 1475 val8 = 0x0a; 1476 1477 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8); 1478 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8); 1479 1480 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808); 1481 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a); 1482 1483 for (i = RF_A; i < priv->rf_paths; i++) { 1484 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1485 val32 &= ~MODE_AG_BW_MASK; 1486 switch(hw->conf.chandef.width) { 1487 case NL80211_CHAN_WIDTH_80: 1488 val32 |= MODE_AG_BW_80MHZ_8723B; 1489 break; 1490 case NL80211_CHAN_WIDTH_40: 1491 val32 |= MODE_AG_BW_40MHZ_8723B; 1492 break; 1493 default: 1494 val32 |= MODE_AG_BW_20MHZ_8723B; 1495 break; 1496 } 1497 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1498 } 1499 } 1500 1501 void 1502 rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) 1503 { 1504 struct rtl8xxxu_power_base *power_base = priv->power_base; 1505 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS]; 1506 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS]; 1507 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b; 1508 u8 val8; 1509 int group, i; 1510 1511 group = rtl8xxxu_gen1_channel_to_group(channel); 1512 1513 cck[0] = priv->cck_tx_power_index_A[group] - 1; 1514 cck[1] = priv->cck_tx_power_index_B[group] - 1; 1515 1516 if (priv->hi_pa) { 1517 if (cck[0] > 0x20) 1518 cck[0] = 0x20; 1519 if (cck[1] > 0x20) 1520 cck[1] = 0x20; 1521 } 1522 1523 ofdm[0] = priv->ht40_1s_tx_power_index_A[group]; 1524 ofdm[1] = priv->ht40_1s_tx_power_index_B[group]; 1525 if (ofdm[0]) 1526 ofdm[0] -= 1; 1527 if (ofdm[1]) 1528 ofdm[1] -= 1; 1529 1530 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a; 1531 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b; 1532 1533 mcsbase[0] = ofdm[0]; 1534 mcsbase[1] = ofdm[1]; 1535 if (!ht40) { 1536 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a; 1537 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b; 1538 } 1539 1540 if (priv->tx_paths > 1) { 1541 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a) 1542 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a; 1543 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b) 1544 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b; 1545 } 1546 1547 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL) 1548 dev_info(&priv->udev->dev, 1549 "%s: Setting TX power CCK A: %02x, " 1550 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n", 1551 __func__, cck[0], cck[1], ofdm[0], ofdm[1]); 1552 1553 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) { 1554 if (cck[i] > RF6052_MAX_TX_PWR) 1555 cck[i] = RF6052_MAX_TX_PWR; 1556 if (ofdm[i] > RF6052_MAX_TX_PWR) 1557 ofdm[i] = RF6052_MAX_TX_PWR; 1558 } 1559 1560 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); 1561 val32 &= 0xffff00ff; 1562 val32 |= (cck[0] << 8); 1563 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); 1564 1565 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); 1566 val32 &= 0xff; 1567 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24)); 1568 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); 1569 1570 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); 1571 val32 &= 0xffffff00; 1572 val32 |= cck[1]; 1573 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); 1574 1575 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32); 1576 val32 &= 0xff; 1577 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24)); 1578 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32); 1579 1580 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 | 1581 ofdmbase[0] << 16 | ofdmbase[0] << 24; 1582 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 | 1583 ofdmbase[1] << 16 | ofdmbase[1] << 24; 1584 1585 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, 1586 ofdm_a + power_base->reg_0e00); 1587 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, 1588 ofdm_b + power_base->reg_0830); 1589 1590 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, 1591 ofdm_a + power_base->reg_0e04); 1592 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, 1593 ofdm_b + power_base->reg_0834); 1594 1595 mcs_a = mcsbase[0] | mcsbase[0] << 8 | 1596 mcsbase[0] << 16 | mcsbase[0] << 24; 1597 mcs_b = mcsbase[1] | mcsbase[1] << 8 | 1598 mcsbase[1] << 16 | mcsbase[1] << 24; 1599 1600 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, 1601 mcs_a + power_base->reg_0e10); 1602 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, 1603 mcs_b + power_base->reg_083c); 1604 1605 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, 1606 mcs_a + power_base->reg_0e14); 1607 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, 1608 mcs_b + power_base->reg_0848); 1609 1610 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, 1611 mcs_a + power_base->reg_0e18); 1612 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, 1613 mcs_b + power_base->reg_084c); 1614 1615 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, 1616 mcs_a + power_base->reg_0e1c); 1617 for (i = 0; i < 3; i++) { 1618 if (i != 2) 1619 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0; 1620 else 1621 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0; 1622 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8); 1623 } 1624 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, 1625 mcs_b + power_base->reg_0868); 1626 for (i = 0; i < 3; i++) { 1627 if (i != 2) 1628 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0; 1629 else 1630 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0; 1631 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8); 1632 } 1633 } 1634 1635 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv, 1636 enum nl80211_iftype linktype) 1637 { 1638 u8 val8; 1639 1640 val8 = rtl8xxxu_read8(priv, REG_MSR); 1641 val8 &= ~MSR_LINKTYPE_MASK; 1642 1643 switch (linktype) { 1644 case NL80211_IFTYPE_UNSPECIFIED: 1645 val8 |= MSR_LINKTYPE_NONE; 1646 break; 1647 case NL80211_IFTYPE_ADHOC: 1648 val8 |= MSR_LINKTYPE_ADHOC; 1649 break; 1650 case NL80211_IFTYPE_STATION: 1651 val8 |= MSR_LINKTYPE_STATION; 1652 break; 1653 case NL80211_IFTYPE_AP: 1654 val8 |= MSR_LINKTYPE_AP; 1655 break; 1656 default: 1657 goto out; 1658 } 1659 1660 rtl8xxxu_write8(priv, REG_MSR, val8); 1661 out: 1662 return; 1663 } 1664 1665 static void 1666 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry) 1667 { 1668 u16 val16; 1669 1670 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) & 1671 RETRY_LIMIT_SHORT_MASK) | 1672 ((long_retry << RETRY_LIMIT_LONG_SHIFT) & 1673 RETRY_LIMIT_LONG_MASK); 1674 1675 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16); 1676 } 1677 1678 static void 1679 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm) 1680 { 1681 u16 val16; 1682 1683 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) | 1684 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK); 1685 1686 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16); 1687 } 1688 1689 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv) 1690 { 1691 struct device *dev = &priv->udev->dev; 1692 char cut = 'A' + priv->chip_cut; 1693 1694 dev_info(dev, 1695 "RTL%s rev %c (%s) romver %d, %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n", 1696 priv->chip_name, cut, priv->chip_vendor, priv->rom_rev, 1697 priv->tx_paths, priv->rx_paths, priv->ep_tx_count, 1698 priv->has_wifi, priv->has_bluetooth, priv->has_gps, 1699 priv->hi_pa); 1700 1701 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr); 1702 } 1703 1704 void rtl8xxxu_identify_vendor_1bit(struct rtl8xxxu_priv *priv, u32 vendor) 1705 { 1706 if (vendor) { 1707 strscpy(priv->chip_vendor, "UMC", sizeof(priv->chip_vendor)); 1708 priv->vendor_umc = 1; 1709 } else { 1710 strscpy(priv->chip_vendor, "TSMC", sizeof(priv->chip_vendor)); 1711 } 1712 } 1713 1714 void rtl8xxxu_identify_vendor_2bits(struct rtl8xxxu_priv *priv, u32 vendor) 1715 { 1716 switch (vendor) { 1717 case SYS_CFG_VENDOR_ID_TSMC: 1718 strscpy(priv->chip_vendor, "TSMC", sizeof(priv->chip_vendor)); 1719 break; 1720 case SYS_CFG_VENDOR_ID_SMIC: 1721 strscpy(priv->chip_vendor, "SMIC", sizeof(priv->chip_vendor)); 1722 priv->vendor_smic = 1; 1723 break; 1724 case SYS_CFG_VENDOR_ID_UMC: 1725 strscpy(priv->chip_vendor, "UMC", sizeof(priv->chip_vendor)); 1726 priv->vendor_umc = 1; 1727 break; 1728 default: 1729 strscpy(priv->chip_vendor, "unknown", sizeof(priv->chip_vendor)); 1730 } 1731 } 1732 1733 void rtl8xxxu_config_endpoints_sie(struct rtl8xxxu_priv *priv) 1734 { 1735 u16 val16; 1736 1737 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX); 1738 1739 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) { 1740 priv->ep_tx_high_queue = 1; 1741 priv->ep_tx_count++; 1742 } 1743 1744 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) { 1745 priv->ep_tx_normal_queue = 1; 1746 priv->ep_tx_count++; 1747 } 1748 1749 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) { 1750 priv->ep_tx_low_queue = 1; 1751 priv->ep_tx_count++; 1752 } 1753 } 1754 1755 int rtl8xxxu_config_endpoints_no_sie(struct rtl8xxxu_priv *priv) 1756 { 1757 struct device *dev = &priv->udev->dev; 1758 1759 switch (priv->nr_out_eps) { 1760 case 6: 1761 case 5: 1762 case 4: 1763 case 3: 1764 priv->ep_tx_low_queue = 1; 1765 priv->ep_tx_count++; 1766 fallthrough; 1767 case 2: 1768 priv->ep_tx_normal_queue = 1; 1769 priv->ep_tx_count++; 1770 fallthrough; 1771 case 1: 1772 priv->ep_tx_high_queue = 1; 1773 priv->ep_tx_count++; 1774 break; 1775 default: 1776 dev_info(dev, "Unsupported USB TX end-points\n"); 1777 return -ENOTSUPP; 1778 } 1779 1780 return 0; 1781 } 1782 1783 int 1784 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data) 1785 { 1786 int i; 1787 u8 val8; 1788 u32 val32; 1789 1790 /* Write Address */ 1791 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff); 1792 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2); 1793 val8 &= 0xfc; 1794 val8 |= (offset >> 8) & 0x03; 1795 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8); 1796 1797 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3); 1798 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f); 1799 1800 /* Poll for data read */ 1801 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); 1802 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) { 1803 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); 1804 if (val32 & BIT(31)) 1805 break; 1806 } 1807 1808 if (i == RTL8XXXU_MAX_REG_POLL) 1809 return -EIO; 1810 1811 udelay(50); 1812 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); 1813 1814 *data = val32 & 0xff; 1815 return 0; 1816 } 1817 1818 int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv) 1819 { 1820 struct device *dev = &priv->udev->dev; 1821 int i, ret = 0; 1822 u8 val8, word_mask, header, extheader; 1823 u16 val16, efuse_addr, offset; 1824 u32 val32; 1825 1826 val16 = rtl8xxxu_read16(priv, REG_9346CR); 1827 if (val16 & EEPROM_ENABLE) 1828 priv->has_eeprom = 1; 1829 if (val16 & EEPROM_BOOT) 1830 priv->boot_eeprom = 1; 1831 1832 if (priv->is_multi_func) { 1833 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST); 1834 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT; 1835 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32); 1836 } 1837 1838 dev_dbg(dev, "Booting from %s\n", 1839 priv->boot_eeprom ? "EEPROM" : "EFUSE"); 1840 1841 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE); 1842 1843 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */ 1844 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL); 1845 if (!(val16 & SYS_ISO_PWC_EV12V)) { 1846 val16 |= SYS_ISO_PWC_EV12V; 1847 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16); 1848 } 1849 /* Reset: 0x0000[28], default valid */ 1850 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1851 if (!(val16 & SYS_FUNC_ELDR)) { 1852 val16 |= SYS_FUNC_ELDR; 1853 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 1854 } 1855 1856 /* 1857 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid 1858 */ 1859 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR); 1860 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) { 1861 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M); 1862 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16); 1863 } 1864 1865 /* Default value is 0xff */ 1866 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN); 1867 1868 efuse_addr = 0; 1869 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) { 1870 u16 map_addr; 1871 1872 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header); 1873 if (ret || header == 0xff) 1874 goto exit; 1875 1876 if ((header & 0x1f) == 0x0f) { /* extended header */ 1877 offset = (header & 0xe0) >> 5; 1878 1879 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, 1880 &extheader); 1881 if (ret) 1882 goto exit; 1883 /* All words disabled */ 1884 if ((extheader & 0x0f) == 0x0f) 1885 continue; 1886 1887 offset |= ((extheader & 0xf0) >> 1); 1888 word_mask = extheader & 0x0f; 1889 } else { 1890 offset = (header >> 4) & 0x0f; 1891 word_mask = header & 0x0f; 1892 } 1893 1894 /* Get word enable value from PG header */ 1895 1896 /* We have 8 bits to indicate validity */ 1897 map_addr = offset * 8; 1898 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { 1899 /* Check word enable condition in the section */ 1900 if (word_mask & BIT(i)) { 1901 map_addr += 2; 1902 continue; 1903 } 1904 1905 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8); 1906 if (ret) 1907 goto exit; 1908 if (map_addr >= EFUSE_MAP_LEN - 1) { 1909 dev_warn(dev, "%s: Illegal map_addr (%04x), " 1910 "efuse corrupt!\n", 1911 __func__, map_addr); 1912 ret = -EINVAL; 1913 goto exit; 1914 } 1915 priv->efuse_wifi.raw[map_addr++] = val8; 1916 1917 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8); 1918 if (ret) 1919 goto exit; 1920 priv->efuse_wifi.raw[map_addr++] = val8; 1921 } 1922 } 1923 1924 exit: 1925 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE); 1926 1927 return ret; 1928 } 1929 1930 static void rtl8xxxu_dump_efuse(struct rtl8xxxu_priv *priv) 1931 { 1932 dev_info(&priv->udev->dev, 1933 "Dumping efuse for RTL%s (0x%02x bytes):\n", 1934 priv->chip_name, EFUSE_MAP_LEN); 1935 1936 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, 1937 priv->efuse_wifi.raw, EFUSE_MAP_LEN, true); 1938 } 1939 1940 void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv) 1941 { 1942 u8 val8; 1943 u16 sys_func; 1944 1945 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 1946 val8 &= ~BIT(0); 1947 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 1948 1949 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1950 sys_func &= ~SYS_FUNC_CPU_ENABLE; 1951 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); 1952 1953 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 1954 val8 |= BIT(0); 1955 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 1956 1957 sys_func |= SYS_FUNC_CPU_ENABLE; 1958 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); 1959 } 1960 1961 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv) 1962 { 1963 struct device *dev = &priv->udev->dev; 1964 u16 reg_mcu_fw_dl; 1965 int ret = 0, i; 1966 u32 val32; 1967 1968 if (priv->rtl_chip == RTL8710B) 1969 reg_mcu_fw_dl = REG_8051FW_CTRL_V1_8710B; 1970 else 1971 reg_mcu_fw_dl = REG_MCU_FW_DL; 1972 1973 /* Poll checksum report */ 1974 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) { 1975 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl); 1976 if (val32 & MCU_FW_DL_CSUM_REPORT) 1977 break; 1978 } 1979 1980 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) { 1981 dev_warn(dev, "Firmware checksum poll timed out\n"); 1982 ret = -EAGAIN; 1983 goto exit; 1984 } 1985 1986 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl); 1987 val32 |= MCU_FW_DL_READY; 1988 val32 &= ~MCU_WINT_INIT_READY; 1989 rtl8xxxu_write32(priv, reg_mcu_fw_dl, val32); 1990 1991 /* 1992 * Reset the 8051 in order for the firmware to start running, 1993 * otherwise it won't come up on the 8192eu 1994 */ 1995 priv->fops->reset_8051(priv); 1996 1997 /* Wait for firmware to become ready */ 1998 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) { 1999 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl); 2000 if (val32 & MCU_WINT_INIT_READY) 2001 break; 2002 2003 udelay(100); 2004 } 2005 2006 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) { 2007 dev_warn(dev, "Firmware failed to start\n"); 2008 ret = -EAGAIN; 2009 goto exit; 2010 } 2011 2012 /* 2013 * Init H2C command 2014 */ 2015 if (priv->fops->init_reg_hmtfr) 2016 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f); 2017 exit: 2018 return ret; 2019 } 2020 2021 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv) 2022 { 2023 int pages, remainder, i, ret; 2024 u16 reg_fw_start_address; 2025 u16 reg_mcu_fw_dl; 2026 u8 val8; 2027 u16 val16; 2028 u32 val32; 2029 u8 *fwptr; 2030 2031 if (priv->rtl_chip == RTL8192F) 2032 reg_fw_start_address = REG_FW_START_ADDRESS_8192F; 2033 else 2034 reg_fw_start_address = REG_FW_START_ADDRESS; 2035 2036 if (priv->rtl_chip == RTL8710B) { 2037 reg_mcu_fw_dl = REG_8051FW_CTRL_V1_8710B; 2038 } else { 2039 reg_mcu_fw_dl = REG_MCU_FW_DL; 2040 2041 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1); 2042 val8 |= 4; 2043 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8); 2044 2045 /* 8051 enable */ 2046 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2047 val16 |= SYS_FUNC_CPU_ENABLE; 2048 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 2049 } 2050 2051 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl); 2052 if (val8 & MCU_FW_RAM_SEL) { 2053 dev_info(&priv->udev->dev, 2054 "Firmware is already running, resetting the MCU.\n"); 2055 rtl8xxxu_write8(priv, reg_mcu_fw_dl, 0x00); 2056 priv->fops->reset_8051(priv); 2057 } 2058 2059 /* MCU firmware download enable */ 2060 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl); 2061 val8 |= MCU_FW_DL_ENABLE; 2062 rtl8xxxu_write8(priv, reg_mcu_fw_dl, val8); 2063 2064 /* 8051 reset */ 2065 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl); 2066 val32 &= ~BIT(19); 2067 rtl8xxxu_write32(priv, reg_mcu_fw_dl, val32); 2068 2069 if (priv->rtl_chip == RTL8710B) { 2070 /* We must set 0x8090[8]=1 before download FW. */ 2071 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 1); 2072 val8 |= BIT(0); 2073 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 1, val8); 2074 } 2075 2076 /* Reset firmware download checksum */ 2077 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl); 2078 val8 |= MCU_FW_DL_CSUM_REPORT; 2079 rtl8xxxu_write8(priv, reg_mcu_fw_dl, val8); 2080 2081 pages = priv->fw_size / RTL_FW_PAGE_SIZE; 2082 remainder = priv->fw_size % RTL_FW_PAGE_SIZE; 2083 2084 fwptr = priv->fw_data->data; 2085 2086 for (i = 0; i < pages; i++) { 2087 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 2) & 0xF8; 2088 val8 |= i; 2089 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 2, val8); 2090 2091 ret = rtl8xxxu_writeN(priv, reg_fw_start_address, 2092 fwptr, RTL_FW_PAGE_SIZE); 2093 if (ret != RTL_FW_PAGE_SIZE) { 2094 ret = -EAGAIN; 2095 goto fw_abort; 2096 } 2097 2098 fwptr += RTL_FW_PAGE_SIZE; 2099 } 2100 2101 if (remainder) { 2102 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 2) & 0xF8; 2103 val8 |= i; 2104 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 2, val8); 2105 ret = rtl8xxxu_writeN(priv, reg_fw_start_address, 2106 fwptr, remainder); 2107 if (ret != remainder) { 2108 ret = -EAGAIN; 2109 goto fw_abort; 2110 } 2111 } 2112 2113 ret = 0; 2114 fw_abort: 2115 /* MCU firmware download disable */ 2116 val16 = rtl8xxxu_read16(priv, reg_mcu_fw_dl); 2117 val16 &= ~MCU_FW_DL_ENABLE; 2118 rtl8xxxu_write16(priv, reg_mcu_fw_dl, val16); 2119 2120 return ret; 2121 } 2122 2123 int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, const char *fw_name) 2124 { 2125 struct device *dev = &priv->udev->dev; 2126 const struct firmware *fw; 2127 int ret = 0; 2128 u16 signature; 2129 2130 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name); 2131 if (request_firmware(&fw, fw_name, &priv->udev->dev)) { 2132 dev_warn(dev, "request_firmware(%s) failed\n", fw_name); 2133 ret = -EAGAIN; 2134 goto exit; 2135 } 2136 if (!fw) { 2137 dev_warn(dev, "Firmware data not available\n"); 2138 ret = -EINVAL; 2139 goto exit; 2140 } 2141 2142 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL); 2143 if (!priv->fw_data) { 2144 ret = -ENOMEM; 2145 goto exit; 2146 } 2147 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header); 2148 2149 signature = le16_to_cpu(priv->fw_data->signature); 2150 switch (signature & 0xfff0) { 2151 case 0x92e0: 2152 case 0x92c0: 2153 case 0x88e0: 2154 case 0x88c0: 2155 case 0x5300: 2156 case 0x2300: 2157 case 0x88f0: 2158 case 0x10b0: 2159 case 0x92f0: 2160 break; 2161 default: 2162 ret = -EINVAL; 2163 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n", 2164 __func__, signature); 2165 } 2166 2167 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n", 2168 le16_to_cpu(priv->fw_data->major_version), 2169 priv->fw_data->minor_version, signature); 2170 2171 exit: 2172 release_firmware(fw); 2173 return ret; 2174 } 2175 2176 void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv) 2177 { 2178 u16 val16; 2179 int i = 100; 2180 2181 /* Inform 8051 to perform reset */ 2182 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20); 2183 2184 for (i = 100; i > 0; i--) { 2185 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2186 2187 if (!(val16 & SYS_FUNC_CPU_ENABLE)) { 2188 dev_dbg(&priv->udev->dev, 2189 "%s: Firmware self reset success!\n", __func__); 2190 break; 2191 } 2192 udelay(50); 2193 } 2194 2195 if (!i) { 2196 /* Force firmware reset */ 2197 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2198 val16 &= ~SYS_FUNC_CPU_ENABLE; 2199 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 2200 } 2201 } 2202 2203 static int 2204 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv) 2205 { 2206 const struct rtl8xxxu_reg8val *array = priv->fops->mactable; 2207 int i, ret; 2208 u16 reg; 2209 u8 val; 2210 2211 for (i = 0; ; i++) { 2212 reg = array[i].reg; 2213 val = array[i].val; 2214 2215 if (reg == 0xffff && val == 0xff) 2216 break; 2217 2218 ret = rtl8xxxu_write8(priv, reg, val); 2219 if (ret != 1) { 2220 dev_warn(&priv->udev->dev, 2221 "Failed to initialize MAC " 2222 "(reg: %04x, val %02x)\n", reg, val); 2223 return -EAGAIN; 2224 } 2225 } 2226 2227 switch (priv->rtl_chip) { 2228 case RTL8188C: 2229 case RTL8188R: 2230 case RTL8191C: 2231 case RTL8192C: 2232 case RTL8723A: 2233 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a); 2234 break; 2235 case RTL8188E: 2236 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0707); 2237 break; 2238 default: 2239 break; 2240 } 2241 2242 return 0; 2243 } 2244 2245 int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv, 2246 const struct rtl8xxxu_reg32val *array) 2247 { 2248 int i, ret; 2249 u16 reg; 2250 u32 val; 2251 2252 for (i = 0; ; i++) { 2253 reg = array[i].reg; 2254 val = array[i].val; 2255 2256 if (reg == 0xffff && val == 0xffffffff) 2257 break; 2258 2259 ret = rtl8xxxu_write32(priv, reg, val); 2260 if (ret != sizeof(val)) { 2261 dev_warn(&priv->udev->dev, 2262 "Failed to initialize PHY\n"); 2263 return -EAGAIN; 2264 } 2265 udelay(1); 2266 } 2267 2268 return 0; 2269 } 2270 2271 void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv) 2272 { 2273 u8 val8, ldoa15, ldov12d, lpldo, ldohci12; 2274 u16 val16; 2275 u32 val32; 2276 2277 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); 2278 udelay(2); 2279 val8 |= AFE_PLL_320_ENABLE; 2280 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); 2281 udelay(2); 2282 2283 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff); 2284 udelay(2); 2285 2286 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2287 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB; 2288 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 2289 2290 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); 2291 val32 &= ~AFE_XTAL_RF_GATE; 2292 if (priv->has_bluetooth) 2293 val32 &= ~AFE_XTAL_BT_GATE; 2294 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); 2295 2296 /* 6. 0x1f[7:0] = 0x07 */ 2297 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; 2298 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); 2299 2300 if (priv->hi_pa) 2301 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table); 2302 else if (priv->tx_paths == 2) 2303 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table); 2304 else 2305 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table); 2306 2307 if (priv->rtl_chip == RTL8188R && priv->hi_pa && 2308 priv->vendor_umc && priv->chip_cut == 1) 2309 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50); 2310 2311 if (priv->hi_pa) 2312 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table); 2313 else 2314 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table); 2315 2316 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF; 2317 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT); 2318 ldohci12 = 0x57; 2319 lpldo = 1; 2320 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15; 2321 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32); 2322 } 2323 2324 /* 2325 * Most of this is black magic retrieved from the old rtl8723au driver 2326 */ 2327 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv) 2328 { 2329 u32 val32; 2330 2331 priv->fops->init_phy_bb(priv); 2332 2333 if (priv->tx_paths == 1 && priv->rx_paths == 2) { 2334 /* 2335 * For 1T2R boards, patch the registers. 2336 * 2337 * It looks like 8191/2 1T2R boards use path B for TX 2338 */ 2339 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO); 2340 val32 &= ~(BIT(0) | BIT(1)); 2341 val32 |= BIT(1); 2342 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32); 2343 2344 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO); 2345 val32 &= ~0x300033; 2346 val32 |= 0x200022; 2347 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32); 2348 2349 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); 2350 val32 &= ~CCK0_AFE_RX_MASK; 2351 val32 &= 0x00ffffff; 2352 val32 |= 0x40000000; 2353 val32 |= CCK0_AFE_RX_ANT_B; 2354 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); 2355 2356 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 2357 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); 2358 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B | 2359 OFDM_RF_PATH_TX_B); 2360 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 2361 2362 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1); 2363 val32 &= ~(BIT(4) | BIT(5)); 2364 val32 |= BIT(4); 2365 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32); 2366 2367 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON); 2368 val32 &= ~(BIT(27) | BIT(26)); 2369 val32 |= BIT(27); 2370 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32); 2371 2372 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON); 2373 val32 &= ~(BIT(27) | BIT(26)); 2374 val32 |= BIT(27); 2375 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32); 2376 2377 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON); 2378 val32 &= ~(BIT(27) | BIT(26)); 2379 val32 |= BIT(27); 2380 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32); 2381 2382 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON); 2383 val32 &= ~(BIT(27) | BIT(26)); 2384 val32 |= BIT(27); 2385 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32); 2386 2387 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX); 2388 val32 &= ~(BIT(27) | BIT(26)); 2389 val32 |= BIT(27); 2390 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32); 2391 } 2392 2393 if (priv->fops->set_crystal_cap) 2394 priv->fops->set_crystal_cap(priv, priv->default_crystal_cap); 2395 2396 if (priv->rtl_chip == RTL8192E) 2397 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x000f81fb); 2398 2399 return 0; 2400 } 2401 2402 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv, 2403 const struct rtl8xxxu_rfregval *array, 2404 enum rtl8xxxu_rfpath path) 2405 { 2406 int i, ret; 2407 u8 reg; 2408 u32 val; 2409 2410 for (i = 0; ; i++) { 2411 reg = array[i].reg; 2412 val = array[i].val; 2413 2414 if (reg == 0xff && val == 0xffffffff) 2415 break; 2416 2417 switch (reg) { 2418 case 0xfe: 2419 msleep(50); 2420 continue; 2421 case 0xfd: 2422 mdelay(5); 2423 continue; 2424 case 0xfc: 2425 mdelay(1); 2426 continue; 2427 case 0xfb: 2428 udelay(50); 2429 continue; 2430 case 0xfa: 2431 udelay(5); 2432 continue; 2433 case 0xf9: 2434 udelay(1); 2435 continue; 2436 } 2437 2438 ret = rtl8xxxu_write_rfreg(priv, path, reg, val); 2439 if (ret) { 2440 dev_warn(&priv->udev->dev, 2441 "Failed to initialize RF\n"); 2442 return -EAGAIN; 2443 } 2444 udelay(1); 2445 } 2446 2447 return 0; 2448 } 2449 2450 int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv, 2451 const struct rtl8xxxu_rfregval *table, 2452 enum rtl8xxxu_rfpath path) 2453 { 2454 u32 val32; 2455 u16 val16, rfsi_rfenv; 2456 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2; 2457 2458 switch (path) { 2459 case RF_A: 2460 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL; 2461 reg_int_oe = REG_FPGA0_XA_RF_INT_OE; 2462 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2; 2463 break; 2464 case RF_B: 2465 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL; 2466 reg_int_oe = REG_FPGA0_XB_RF_INT_OE; 2467 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2; 2468 break; 2469 default: 2470 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n", 2471 __func__, path + 'A'); 2472 return -EINVAL; 2473 } 2474 /* For path B, use XB */ 2475 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl); 2476 rfsi_rfenv &= FPGA0_RF_RFENV; 2477 2478 /* 2479 * These two we might be able to optimize into one 2480 */ 2481 val32 = rtl8xxxu_read32(priv, reg_int_oe); 2482 val32 |= BIT(20); /* 0x10 << 16 */ 2483 rtl8xxxu_write32(priv, reg_int_oe, val32); 2484 udelay(1); 2485 2486 val32 = rtl8xxxu_read32(priv, reg_int_oe); 2487 val32 |= BIT(4); 2488 rtl8xxxu_write32(priv, reg_int_oe, val32); 2489 udelay(1); 2490 2491 /* 2492 * These two we might be able to optimize into one 2493 */ 2494 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); 2495 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN; 2496 rtl8xxxu_write32(priv, reg_hssi_parm2, val32); 2497 udelay(1); 2498 2499 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); 2500 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN; 2501 rtl8xxxu_write32(priv, reg_hssi_parm2, val32); 2502 udelay(1); 2503 2504 rtl8xxxu_init_rf_regs(priv, table, path); 2505 2506 /* For path B, use XB */ 2507 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl); 2508 val16 &= ~FPGA0_RF_RFENV; 2509 val16 |= rfsi_rfenv; 2510 rtl8xxxu_write16(priv, reg_sw_ctrl, val16); 2511 2512 return 0; 2513 } 2514 2515 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data) 2516 { 2517 int ret = -EBUSY; 2518 int count = 0; 2519 u32 value; 2520 2521 value = LLT_OP_WRITE | address << 8 | data; 2522 2523 rtl8xxxu_write32(priv, REG_LLT_INIT, value); 2524 2525 do { 2526 value = rtl8xxxu_read32(priv, REG_LLT_INIT); 2527 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) { 2528 ret = 0; 2529 break; 2530 } 2531 } while (count++ < 20); 2532 2533 return ret; 2534 } 2535 2536 int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv) 2537 { 2538 int ret; 2539 int i, last_entry; 2540 u8 last_tx_page; 2541 2542 last_tx_page = priv->fops->total_page_num; 2543 2544 if (priv->fops->last_llt_entry) 2545 last_entry = priv->fops->last_llt_entry; 2546 else 2547 last_entry = 255; 2548 2549 for (i = 0; i < last_tx_page; i++) { 2550 ret = rtl8xxxu_llt_write(priv, i, i + 1); 2551 if (ret) 2552 goto exit; 2553 } 2554 2555 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff); 2556 if (ret) 2557 goto exit; 2558 2559 /* Mark remaining pages as a ring buffer */ 2560 for (i = last_tx_page + 1; i < last_entry; i++) { 2561 ret = rtl8xxxu_llt_write(priv, i, (i + 1)); 2562 if (ret) 2563 goto exit; 2564 } 2565 2566 /* Let last entry point to the start entry of ring buffer */ 2567 ret = rtl8xxxu_llt_write(priv, last_entry, last_tx_page + 1); 2568 if (ret) 2569 goto exit; 2570 2571 exit: 2572 return ret; 2573 } 2574 2575 int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv) 2576 { 2577 u32 val32; 2578 int ret = 0; 2579 int i; 2580 2581 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT); 2582 val32 |= AUTO_LLT_INIT_LLT; 2583 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32); 2584 2585 for (i = 500; i; i--) { 2586 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT); 2587 if (!(val32 & AUTO_LLT_INIT_LLT)) 2588 break; 2589 usleep_range(2, 4); 2590 } 2591 2592 if (!i) { 2593 ret = -EBUSY; 2594 dev_warn(&priv->udev->dev, "LLT table init failed\n"); 2595 } 2596 2597 return ret; 2598 } 2599 2600 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv) 2601 { 2602 u16 val16, hi, lo; 2603 u16 hiq, mgq, bkq, beq, viq, voq; 2604 int hip, mgp, bkp, bep, vip, vop; 2605 int ret = 0; 2606 u32 val32; 2607 2608 switch (priv->ep_tx_count) { 2609 case 1: 2610 if (priv->ep_tx_high_queue) { 2611 hi = TRXDMA_QUEUE_HIGH; 2612 } else if (priv->ep_tx_low_queue) { 2613 hi = TRXDMA_QUEUE_LOW; 2614 } else if (priv->ep_tx_normal_queue) { 2615 hi = TRXDMA_QUEUE_NORMAL; 2616 } else { 2617 hi = 0; 2618 ret = -EINVAL; 2619 } 2620 2621 hiq = hi; 2622 mgq = hi; 2623 bkq = hi; 2624 beq = hi; 2625 viq = hi; 2626 voq = hi; 2627 2628 hip = 0; 2629 mgp = 0; 2630 bkp = 0; 2631 bep = 0; 2632 vip = 0; 2633 vop = 0; 2634 break; 2635 case 2: 2636 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) { 2637 hi = TRXDMA_QUEUE_HIGH; 2638 lo = TRXDMA_QUEUE_LOW; 2639 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) { 2640 hi = TRXDMA_QUEUE_NORMAL; 2641 lo = TRXDMA_QUEUE_LOW; 2642 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) { 2643 hi = TRXDMA_QUEUE_HIGH; 2644 lo = TRXDMA_QUEUE_NORMAL; 2645 } else { 2646 ret = -EINVAL; 2647 hi = 0; 2648 lo = 0; 2649 } 2650 2651 hiq = hi; 2652 mgq = hi; 2653 bkq = lo; 2654 beq = lo; 2655 viq = hi; 2656 voq = hi; 2657 2658 hip = 0; 2659 mgp = 0; 2660 bkp = 1; 2661 bep = 1; 2662 vip = 0; 2663 vop = 0; 2664 break; 2665 case 3: 2666 beq = TRXDMA_QUEUE_LOW; 2667 bkq = TRXDMA_QUEUE_LOW; 2668 viq = TRXDMA_QUEUE_NORMAL; 2669 voq = TRXDMA_QUEUE_HIGH; 2670 mgq = TRXDMA_QUEUE_HIGH; 2671 hiq = TRXDMA_QUEUE_HIGH; 2672 2673 hip = hiq ^ 3; 2674 mgp = mgq ^ 3; 2675 bkp = bkq ^ 3; 2676 bep = beq ^ 3; 2677 vip = viq ^ 3; 2678 vop = viq ^ 3; 2679 break; 2680 default: 2681 ret = -EINVAL; 2682 } 2683 2684 /* 2685 * None of the vendor drivers are configuring the beacon 2686 * queue here .... why? 2687 */ 2688 if (!ret) { 2689 /* Only RTL8192F seems to do it like this. */ 2690 if (priv->rtl_chip == RTL8192F) { 2691 val32 = rtl8xxxu_read32(priv, REG_TRXDMA_CTRL); 2692 val32 &= 0x7; 2693 val32 |= (voq << TRXDMA_CTRL_VOQ_SHIFT_8192F) | 2694 (viq << TRXDMA_CTRL_VIQ_SHIFT_8192F) | 2695 (beq << TRXDMA_CTRL_BEQ_SHIFT_8192F) | 2696 (bkq << TRXDMA_CTRL_BKQ_SHIFT_8192F) | 2697 (mgq << TRXDMA_CTRL_MGQ_SHIFT_8192F) | 2698 (hiq << TRXDMA_CTRL_HIQ_SHIFT_8192F); 2699 rtl8xxxu_write32(priv, REG_TRXDMA_CTRL, val32); 2700 } else { 2701 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL); 2702 val16 &= 0x7; 2703 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) | 2704 (viq << TRXDMA_CTRL_VIQ_SHIFT) | 2705 (beq << TRXDMA_CTRL_BEQ_SHIFT) | 2706 (bkq << TRXDMA_CTRL_BKQ_SHIFT) | 2707 (mgq << TRXDMA_CTRL_MGQ_SHIFT) | 2708 (hiq << TRXDMA_CTRL_HIQ_SHIFT); 2709 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16); 2710 } 2711 2712 priv->pipe_out[TXDESC_QUEUE_VO] = 2713 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]); 2714 priv->pipe_out[TXDESC_QUEUE_VI] = 2715 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]); 2716 priv->pipe_out[TXDESC_QUEUE_BE] = 2717 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]); 2718 priv->pipe_out[TXDESC_QUEUE_BK] = 2719 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]); 2720 priv->pipe_out[TXDESC_QUEUE_BEACON] = 2721 usb_sndbulkpipe(priv->udev, priv->out_ep[0]); 2722 priv->pipe_out[TXDESC_QUEUE_MGNT] = 2723 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]); 2724 priv->pipe_out[TXDESC_QUEUE_HIGH] = 2725 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]); 2726 priv->pipe_out[TXDESC_QUEUE_CMD] = 2727 usb_sndbulkpipe(priv->udev, priv->out_ep[0]); 2728 } 2729 2730 return ret; 2731 } 2732 2733 void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok, 2734 int result[][8], int candidate, bool tx_only) 2735 { 2736 u32 oldval, x, tx0_a, reg; 2737 int y, tx0_c; 2738 u32 val32; 2739 2740 if (!iqk_ok) 2741 return; 2742 2743 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); 2744 oldval = val32 >> 22; 2745 2746 x = result[candidate][0]; 2747 if ((x & 0x00000200) != 0) 2748 x = x | 0xfffffc00; 2749 tx0_a = (x * oldval) >> 8; 2750 2751 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); 2752 val32 &= ~0x3ff; 2753 val32 |= tx0_a; 2754 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); 2755 2756 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2757 val32 &= ~BIT(31); 2758 if ((x * oldval >> 7) & 0x1) 2759 val32 |= BIT(31); 2760 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2761 2762 y = result[candidate][1]; 2763 if ((y & 0x00000200) != 0) 2764 y = y | 0xfffffc00; 2765 tx0_c = (y * oldval) >> 8; 2766 2767 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE); 2768 val32 &= ~0xf0000000; 2769 val32 |= (((tx0_c & 0x3c0) >> 6) << 28); 2770 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32); 2771 2772 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); 2773 val32 &= ~0x003f0000; 2774 val32 |= ((tx0_c & 0x3f) << 16); 2775 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); 2776 2777 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2778 val32 &= ~BIT(29); 2779 if ((y * oldval >> 7) & 0x1) 2780 val32 |= BIT(29); 2781 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2782 2783 if (tx_only) { 2784 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__); 2785 return; 2786 } 2787 2788 reg = result[candidate][2]; 2789 2790 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); 2791 val32 &= ~0x3ff; 2792 val32 |= (reg & 0x3ff); 2793 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); 2794 2795 reg = result[candidate][3] & 0x3F; 2796 2797 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); 2798 val32 &= ~0xfc00; 2799 val32 |= ((reg << 10) & 0xfc00); 2800 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); 2801 2802 reg = (result[candidate][3] >> 6) & 0xF; 2803 2804 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA); 2805 val32 &= ~0xf0000000; 2806 val32 |= (reg << 28); 2807 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32); 2808 } 2809 2810 void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok, 2811 int result[][8], int candidate, bool tx_only) 2812 { 2813 u32 oldval, x, tx1_a, reg; 2814 int y, tx1_c; 2815 u32 val32; 2816 2817 if (!iqk_ok) 2818 return; 2819 2820 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); 2821 oldval = val32 >> 22; 2822 2823 x = result[candidate][4]; 2824 if ((x & 0x00000200) != 0) 2825 x = x | 0xfffffc00; 2826 tx1_a = (x * oldval) >> 8; 2827 2828 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); 2829 val32 &= ~0x3ff; 2830 val32 |= tx1_a; 2831 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); 2832 2833 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2834 val32 &= ~BIT(27); 2835 if ((x * oldval >> 7) & 0x1) 2836 val32 |= BIT(27); 2837 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2838 2839 y = result[candidate][5]; 2840 if ((y & 0x00000200) != 0) 2841 y = y | 0xfffffc00; 2842 tx1_c = (y * oldval) >> 8; 2843 2844 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE); 2845 val32 &= ~0xf0000000; 2846 val32 |= (((tx1_c & 0x3c0) >> 6) << 28); 2847 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32); 2848 2849 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); 2850 val32 &= ~0x003f0000; 2851 val32 |= ((tx1_c & 0x3f) << 16); 2852 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); 2853 2854 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2855 val32 &= ~BIT(25); 2856 if ((y * oldval >> 7) & 0x1) 2857 val32 |= BIT(25); 2858 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2859 2860 if (tx_only) { 2861 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__); 2862 return; 2863 } 2864 2865 reg = result[candidate][6]; 2866 2867 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); 2868 val32 &= ~0x3ff; 2869 val32 |= (reg & 0x3ff); 2870 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); 2871 2872 reg = result[candidate][7] & 0x3f; 2873 2874 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); 2875 val32 &= ~0xfc00; 2876 val32 |= ((reg << 10) & 0xfc00); 2877 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); 2878 2879 reg = (result[candidate][7] >> 6) & 0xf; 2880 2881 if (priv->rtl_chip == RTL8192F) { 2882 rtl8xxxu_write32_mask(priv, REG_RXIQB_EXT, 0x000000f0, reg); 2883 } else { 2884 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_RSSI_TABLE); 2885 val32 &= ~0x0000f000; 2886 val32 |= (reg << 12); 2887 rtl8xxxu_write32(priv, REG_OFDM0_AGC_RSSI_TABLE, val32); 2888 } 2889 } 2890 2891 #define MAX_TOLERANCE 5 2892 2893 bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv, 2894 int result[][8], int c1, int c2) 2895 { 2896 u32 i, j, diff, simubitmap, bound = 0; 2897 int candidate[2] = {-1, -1}; /* for path A and path B */ 2898 bool retval = true; 2899 2900 if (priv->tx_paths > 1) 2901 bound = 8; 2902 else 2903 bound = 4; 2904 2905 simubitmap = 0; 2906 2907 for (i = 0; i < bound; i++) { 2908 diff = (result[c1][i] > result[c2][i]) ? 2909 (result[c1][i] - result[c2][i]) : 2910 (result[c2][i] - result[c1][i]); 2911 if (diff > MAX_TOLERANCE) { 2912 if ((i == 2 || i == 6) && !simubitmap) { 2913 if (result[c1][i] + result[c1][i + 1] == 0) 2914 candidate[(i / 4)] = c2; 2915 else if (result[c2][i] + result[c2][i + 1] == 0) 2916 candidate[(i / 4)] = c1; 2917 else 2918 simubitmap = simubitmap | (1 << i); 2919 } else { 2920 simubitmap = simubitmap | (1 << i); 2921 } 2922 } 2923 } 2924 2925 if (simubitmap == 0) { 2926 for (i = 0; i < (bound / 4); i++) { 2927 if (candidate[i] >= 0) { 2928 for (j = i * 4; j < (i + 1) * 4 - 2; j++) 2929 result[3][j] = result[candidate[i]][j]; 2930 retval = false; 2931 } 2932 } 2933 return retval; 2934 } else if (!(simubitmap & 0x0f)) { 2935 /* path A OK */ 2936 for (i = 0; i < 4; i++) 2937 result[3][i] = result[c1][i]; 2938 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) { 2939 /* path B OK */ 2940 for (i = 4; i < 8; i++) 2941 result[3][i] = result[c1][i]; 2942 } 2943 2944 return false; 2945 } 2946 2947 bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv, 2948 int result[][8], int c1, int c2) 2949 { 2950 u32 i, j, diff, simubitmap, bound = 0; 2951 int candidate[2] = {-1, -1}; /* for path A and path B */ 2952 int tmp1, tmp2; 2953 bool retval = true; 2954 2955 if (priv->tx_paths > 1) 2956 bound = 8; 2957 else 2958 bound = 4; 2959 2960 simubitmap = 0; 2961 2962 for (i = 0; i < bound; i++) { 2963 if (i & 1) { 2964 if ((result[c1][i] & 0x00000200)) 2965 tmp1 = result[c1][i] | 0xfffffc00; 2966 else 2967 tmp1 = result[c1][i]; 2968 2969 if ((result[c2][i]& 0x00000200)) 2970 tmp2 = result[c2][i] | 0xfffffc00; 2971 else 2972 tmp2 = result[c2][i]; 2973 } else { 2974 tmp1 = result[c1][i]; 2975 tmp2 = result[c2][i]; 2976 } 2977 2978 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); 2979 2980 if (diff > MAX_TOLERANCE) { 2981 if ((i == 2 || i == 6) && !simubitmap) { 2982 if (result[c1][i] + result[c1][i + 1] == 0) 2983 candidate[(i / 4)] = c2; 2984 else if (result[c2][i] + result[c2][i + 1] == 0) 2985 candidate[(i / 4)] = c1; 2986 else 2987 simubitmap = simubitmap | (1 << i); 2988 } else { 2989 simubitmap = simubitmap | (1 << i); 2990 } 2991 } 2992 } 2993 2994 if (simubitmap == 0) { 2995 for (i = 0; i < (bound / 4); i++) { 2996 if (candidate[i] >= 0) { 2997 for (j = i * 4; j < (i + 1) * 4 - 2; j++) 2998 result[3][j] = result[candidate[i]][j]; 2999 retval = false; 3000 } 3001 } 3002 return retval; 3003 } else { 3004 if (!(simubitmap & 0x03)) { 3005 /* path A TX OK */ 3006 for (i = 0; i < 2; i++) 3007 result[3][i] = result[c1][i]; 3008 } 3009 3010 if (!(simubitmap & 0x0c)) { 3011 /* path A RX OK */ 3012 for (i = 2; i < 4; i++) 3013 result[3][i] = result[c1][i]; 3014 } 3015 3016 if (!(simubitmap & 0x30) && priv->tx_paths > 1) { 3017 /* path B TX OK */ 3018 for (i = 4; i < 6; i++) 3019 result[3][i] = result[c1][i]; 3020 } 3021 3022 if (!(simubitmap & 0xc0) && priv->tx_paths > 1) { 3023 /* path B RX OK */ 3024 for (i = 6; i < 8; i++) 3025 result[3][i] = result[c1][i]; 3026 } 3027 } 3028 3029 return false; 3030 } 3031 3032 void 3033 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup) 3034 { 3035 int i; 3036 3037 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++) 3038 backup[i] = rtl8xxxu_read8(priv, reg[i]); 3039 3040 backup[i] = rtl8xxxu_read32(priv, reg[i]); 3041 } 3042 3043 void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv, 3044 const u32 *reg, u32 *backup) 3045 { 3046 int i; 3047 3048 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++) 3049 rtl8xxxu_write8(priv, reg[i], backup[i]); 3050 3051 rtl8xxxu_write32(priv, reg[i], backup[i]); 3052 } 3053 3054 void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 3055 u32 *backup, int count) 3056 { 3057 int i; 3058 3059 for (i = 0; i < count; i++) 3060 backup[i] = rtl8xxxu_read32(priv, regs[i]); 3061 } 3062 3063 void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 3064 u32 *backup, int count) 3065 { 3066 int i; 3067 3068 for (i = 0; i < count; i++) 3069 rtl8xxxu_write32(priv, regs[i], backup[i]); 3070 } 3071 3072 3073 void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs, 3074 bool path_a_on) 3075 { 3076 u32 path_on; 3077 int i; 3078 3079 if (priv->tx_paths == 1) { 3080 path_on = priv->fops->adda_1t_path_on; 3081 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init); 3082 } else { 3083 path_on = path_a_on ? priv->fops->adda_2t_path_on_a : 3084 priv->fops->adda_2t_path_on_b; 3085 3086 rtl8xxxu_write32(priv, regs[0], path_on); 3087 } 3088 3089 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++) 3090 rtl8xxxu_write32(priv, regs[i], path_on); 3091 } 3092 3093 void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv, 3094 const u32 *regs, u32 *backup) 3095 { 3096 int i = 0; 3097 3098 rtl8xxxu_write8(priv, regs[i], 0x3f); 3099 3100 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++) 3101 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3))); 3102 3103 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5))); 3104 } 3105 3106 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv) 3107 { 3108 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32; 3109 int result = 0; 3110 3111 /* path-A IQK setting */ 3112 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f); 3113 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f); 3114 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102); 3115 3116 val32 = (priv->rf_paths > 1) ? 0x28160202 : 3117 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */ 3118 0x28160502; 3119 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32); 3120 3121 /* path-B IQK setting */ 3122 if (priv->rf_paths > 1) { 3123 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22); 3124 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22); 3125 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102); 3126 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202); 3127 } 3128 3129 /* LO calibration setting */ 3130 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1); 3131 3132 /* One shot, path A LOK & IQK */ 3133 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 3134 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 3135 3136 mdelay(1); 3137 3138 /* Check failed */ 3139 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 3140 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 3141 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 3142 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); 3143 3144 if (!(reg_eac & BIT(28)) && 3145 ((reg_e94 & 0x03ff0000) != 0x01420000) && 3146 ((reg_e9c & 0x03ff0000) != 0x00420000)) 3147 result |= 0x01; 3148 else /* If TX not OK, ignore RX */ 3149 goto out; 3150 3151 /* If TX is OK, check whether RX is OK */ 3152 if (!(reg_eac & BIT(27)) && 3153 ((reg_ea4 & 0x03ff0000) != 0x01320000) && 3154 ((reg_eac & 0x03ff0000) != 0x00360000)) 3155 result |= 0x02; 3156 else 3157 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n", 3158 __func__); 3159 out: 3160 return result; 3161 } 3162 3163 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv) 3164 { 3165 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc; 3166 int result = 0; 3167 3168 /* One shot, path B LOK & IQK */ 3169 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002); 3170 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000); 3171 3172 mdelay(1); 3173 3174 /* Check failed */ 3175 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 3176 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 3177 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 3178 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); 3179 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); 3180 3181 if (!(reg_eac & BIT(31)) && 3182 ((reg_eb4 & 0x03ff0000) != 0x01420000) && 3183 ((reg_ebc & 0x03ff0000) != 0x00420000)) 3184 result |= 0x01; 3185 else 3186 goto out; 3187 3188 if (!(reg_eac & BIT(30)) && 3189 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) && 3190 (((reg_ecc & 0x03ff0000) >> 16) != 0x36)) 3191 result |= 0x02; 3192 else 3193 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", 3194 __func__); 3195 out: 3196 return result; 3197 } 3198 3199 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, 3200 int result[][8], int t) 3201 { 3202 struct device *dev = &priv->udev->dev; 3203 u32 i, val32; 3204 int path_a_ok, path_b_ok; 3205 int retry = 2; 3206 static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { 3207 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, 3208 REG_RX_WAIT_CCA, REG_TX_CCK_RFON, 3209 REG_TX_CCK_BBON, REG_TX_OFDM_RFON, 3210 REG_TX_OFDM_BBON, REG_TX_TO_RX, 3211 REG_TX_TO_TX, REG_RX_CCK, 3212 REG_RX_OFDM, REG_RX_WAIT_RIFS, 3213 REG_RX_TO_RX, REG_STANDBY, 3214 REG_SLEEP, REG_PMPD_ANAEN 3215 }; 3216 static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { 3217 REG_TXPAUSE, REG_BEACON_CTRL, 3218 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG 3219 }; 3220 static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { 3221 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, 3222 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, 3223 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, 3224 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE 3225 }; 3226 3227 /* 3228 * Note: IQ calibration must be performed after loading 3229 * PHY_REG.txt , and radio_a, radio_b.txt 3230 */ 3231 3232 if (t == 0) { 3233 /* Save ADDA parameters, turn Path A ADDA on */ 3234 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, 3235 RTL8XXXU_ADDA_REGS); 3236 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 3237 rtl8xxxu_save_regs(priv, iqk_bb_regs, 3238 priv->bb_backup, RTL8XXXU_BB_REGS); 3239 } 3240 3241 rtl8xxxu_path_adda_on(priv, adda_regs, true); 3242 3243 if (t == 0) { 3244 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); 3245 if (val32 & FPGA0_HSSI_PARM1_PI) 3246 priv->pi_enabled = 1; 3247 } 3248 3249 if (!priv->pi_enabled) { 3250 /* Switch BB to PI mode to do IQ Calibration. */ 3251 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); 3252 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100); 3253 } 3254 3255 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 3256 val32 &= ~FPGA_RF_MODE_CCK; 3257 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 3258 3259 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); 3260 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); 3261 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); 3262 3263 if (!priv->no_pape) { 3264 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); 3265 val32 |= (FPGA0_RF_PAPE | 3266 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); 3267 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); 3268 } 3269 3270 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); 3271 val32 &= ~BIT(10); 3272 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); 3273 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); 3274 val32 &= ~BIT(10); 3275 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); 3276 3277 if (priv->tx_paths > 1) { 3278 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); 3279 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000); 3280 } 3281 3282 /* MAC settings */ 3283 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); 3284 3285 /* Page B init */ 3286 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000); 3287 3288 if (priv->tx_paths > 1) 3289 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000); 3290 3291 /* IQ calibration setting */ 3292 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); 3293 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 3294 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 3295 3296 for (i = 0; i < retry; i++) { 3297 path_a_ok = rtl8xxxu_iqk_path_a(priv); 3298 if (path_a_ok == 0x03) { 3299 val32 = rtl8xxxu_read32(priv, 3300 REG_TX_POWER_BEFORE_IQK_A); 3301 result[t][0] = (val32 >> 16) & 0x3ff; 3302 val32 = rtl8xxxu_read32(priv, 3303 REG_TX_POWER_AFTER_IQK_A); 3304 result[t][1] = (val32 >> 16) & 0x3ff; 3305 val32 = rtl8xxxu_read32(priv, 3306 REG_RX_POWER_BEFORE_IQK_A_2); 3307 result[t][2] = (val32 >> 16) & 0x3ff; 3308 val32 = rtl8xxxu_read32(priv, 3309 REG_RX_POWER_AFTER_IQK_A_2); 3310 result[t][3] = (val32 >> 16) & 0x3ff; 3311 break; 3312 } else if (i == (retry - 1) && path_a_ok == 0x01) { 3313 /* TX IQK OK */ 3314 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n", 3315 __func__); 3316 3317 val32 = rtl8xxxu_read32(priv, 3318 REG_TX_POWER_BEFORE_IQK_A); 3319 result[t][0] = (val32 >> 16) & 0x3ff; 3320 val32 = rtl8xxxu_read32(priv, 3321 REG_TX_POWER_AFTER_IQK_A); 3322 result[t][1] = (val32 >> 16) & 0x3ff; 3323 } 3324 } 3325 3326 if (!path_a_ok) 3327 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__); 3328 3329 if (priv->tx_paths > 1) { 3330 /* 3331 * Path A into standby 3332 */ 3333 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0); 3334 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); 3335 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); 3336 3337 /* Turn Path B ADDA on */ 3338 rtl8xxxu_path_adda_on(priv, adda_regs, false); 3339 3340 for (i = 0; i < retry; i++) { 3341 path_b_ok = rtl8xxxu_iqk_path_b(priv); 3342 if (path_b_ok == 0x03) { 3343 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 3344 result[t][4] = (val32 >> 16) & 0x3ff; 3345 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 3346 result[t][5] = (val32 >> 16) & 0x3ff; 3347 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); 3348 result[t][6] = (val32 >> 16) & 0x3ff; 3349 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); 3350 result[t][7] = (val32 >> 16) & 0x3ff; 3351 break; 3352 } else if (i == (retry - 1) && path_b_ok == 0x01) { 3353 /* TX IQK OK */ 3354 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 3355 result[t][4] = (val32 >> 16) & 0x3ff; 3356 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 3357 result[t][5] = (val32 >> 16) & 0x3ff; 3358 } 3359 } 3360 3361 if (!path_b_ok) 3362 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__); 3363 } 3364 3365 /* Back to BB mode, load original value */ 3366 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0); 3367 3368 if (t) { 3369 if (!priv->pi_enabled) { 3370 /* 3371 * Switch back BB to SI mode after finishing 3372 * IQ Calibration 3373 */ 3374 val32 = 0x01000000; 3375 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32); 3376 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32); 3377 } 3378 3379 /* Reload ADDA power saving parameters */ 3380 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, 3381 RTL8XXXU_ADDA_REGS); 3382 3383 /* Reload MAC parameters */ 3384 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 3385 3386 /* Reload BB parameters */ 3387 rtl8xxxu_restore_regs(priv, iqk_bb_regs, 3388 priv->bb_backup, RTL8XXXU_BB_REGS); 3389 3390 /* Restore RX initial gain */ 3391 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3); 3392 3393 if (priv->tx_paths > 1) { 3394 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 3395 0x00032ed3); 3396 } 3397 3398 /* Load 0xe30 IQC default value */ 3399 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); 3400 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); 3401 } 3402 } 3403 3404 void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start) 3405 { 3406 struct h2c_cmd h2c; 3407 3408 memset(&h2c, 0, sizeof(struct h2c_cmd)); 3409 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION; 3410 h2c.bt_wlan_calibration.data = start; 3411 3412 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration)); 3413 } 3414 3415 void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv) 3416 { 3417 struct device *dev = &priv->udev->dev; 3418 int result[4][8]; /* last is final result */ 3419 int i, candidate; 3420 bool path_a_ok, path_b_ok; 3421 u32 reg_e94, reg_e9c, reg_ea4, reg_eac; 3422 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; 3423 s32 reg_tmp = 0; 3424 bool simu; 3425 3426 memset(result, 0, sizeof(result)); 3427 candidate = -1; 3428 3429 path_a_ok = false; 3430 path_b_ok = false; 3431 3432 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 3433 3434 for (i = 0; i < 3; i++) { 3435 rtl8xxxu_phy_iqcalibrate(priv, result, i); 3436 3437 if (i == 1) { 3438 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1); 3439 if (simu) { 3440 candidate = 0; 3441 break; 3442 } 3443 } 3444 3445 if (i == 2) { 3446 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2); 3447 if (simu) { 3448 candidate = 0; 3449 break; 3450 } 3451 3452 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2); 3453 if (simu) { 3454 candidate = 1; 3455 } else { 3456 for (i = 0; i < 8; i++) 3457 reg_tmp += result[3][i]; 3458 3459 if (reg_tmp) 3460 candidate = 3; 3461 else 3462 candidate = -1; 3463 } 3464 } 3465 } 3466 3467 for (i = 0; i < 4; i++) { 3468 reg_e94 = result[i][0]; 3469 reg_e9c = result[i][1]; 3470 reg_ea4 = result[i][2]; 3471 reg_eac = result[i][3]; 3472 reg_eb4 = result[i][4]; 3473 reg_ebc = result[i][5]; 3474 reg_ec4 = result[i][6]; 3475 reg_ecc = result[i][7]; 3476 } 3477 3478 if (candidate >= 0) { 3479 reg_e94 = result[candidate][0]; 3480 priv->rege94 = reg_e94; 3481 reg_e9c = result[candidate][1]; 3482 priv->rege9c = reg_e9c; 3483 reg_ea4 = result[candidate][2]; 3484 reg_eac = result[candidate][3]; 3485 reg_eb4 = result[candidate][4]; 3486 priv->regeb4 = reg_eb4; 3487 reg_ebc = result[candidate][5]; 3488 priv->regebc = reg_ebc; 3489 reg_ec4 = result[candidate][6]; 3490 reg_ecc = result[candidate][7]; 3491 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); 3492 dev_dbg(dev, 3493 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n", 3494 __func__, reg_e94, reg_e9c, 3495 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); 3496 path_a_ok = true; 3497 path_b_ok = true; 3498 } else { 3499 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; 3500 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; 3501 } 3502 3503 if (reg_e94 && candidate >= 0) 3504 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, 3505 candidate, (reg_ea4 == 0)); 3506 3507 if (priv->tx_paths > 1 && reg_eb4) 3508 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, 3509 candidate, (reg_ec4 == 0)); 3510 3511 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, 3512 priv->bb_recovery_backup, RTL8XXXU_BB_REGS); 3513 } 3514 3515 void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv) 3516 { 3517 u32 val32; 3518 u32 rf_amode, rf_bmode = 0, lstf; 3519 3520 /* Check continuous TX and Packet TX */ 3521 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 3522 3523 if (lstf & OFDM_LSTF_MASK) { 3524 /* Disable all continuous TX */ 3525 val32 = lstf & ~OFDM_LSTF_MASK; 3526 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 3527 3528 /* Read original RF mode Path A */ 3529 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC); 3530 3531 /* Set RF mode to standby Path A */ 3532 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 3533 (rf_amode & 0x8ffff) | 0x10000); 3534 3535 /* Path-B */ 3536 if (priv->tx_paths > 1) { 3537 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B, 3538 RF6052_REG_AC); 3539 3540 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 3541 (rf_bmode & 0x8ffff) | 0x10000); 3542 } 3543 } else { 3544 /* Deal with Packet TX case */ 3545 /* block all queues */ 3546 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 3547 } 3548 3549 /* Start LC calibration */ 3550 if (priv->fops->has_s0s1) 3551 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0); 3552 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); 3553 val32 |= 0x08000; 3554 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); 3555 3556 msleep(100); 3557 3558 if (priv->fops->has_s0s1) 3559 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0); 3560 3561 /* Restore original parameters */ 3562 if (lstf & OFDM_LSTF_MASK) { 3563 /* Path-A */ 3564 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf); 3565 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode); 3566 3567 /* Path-B */ 3568 if (priv->tx_paths > 1) 3569 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 3570 rf_bmode); 3571 } else /* Deal with Packet TX case */ 3572 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); 3573 } 3574 3575 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv) 3576 { 3577 int i; 3578 u16 reg; 3579 3580 reg = REG_MACID; 3581 3582 for (i = 0; i < ETH_ALEN; i++) 3583 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]); 3584 3585 return 0; 3586 } 3587 3588 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid) 3589 { 3590 int i; 3591 u16 reg; 3592 3593 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid); 3594 3595 reg = REG_BSSID; 3596 3597 for (i = 0; i < ETH_ALEN; i++) 3598 rtl8xxxu_write8(priv, reg + i, bssid[i]); 3599 3600 return 0; 3601 } 3602 3603 static void 3604 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor) 3605 { 3606 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 }; 3607 u8 max_agg = 0xf; 3608 int i; 3609 3610 ampdu_factor = 1 << (ampdu_factor + 2); 3611 if (ampdu_factor > max_agg) 3612 ampdu_factor = max_agg; 3613 3614 for (i = 0; i < 4; i++) { 3615 if ((vals[i] & 0xf0) > (ampdu_factor << 4)) 3616 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4); 3617 3618 if ((vals[i] & 0x0f) > ampdu_factor) 3619 vals[i] = (vals[i] & 0xf0) | ampdu_factor; 3620 3621 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]); 3622 } 3623 } 3624 3625 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density) 3626 { 3627 u8 val8; 3628 3629 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE); 3630 val8 &= 0xf8; 3631 val8 |= density; 3632 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8); 3633 } 3634 3635 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv) 3636 { 3637 u8 val8; 3638 int count, ret = 0; 3639 3640 /* Start of rtl8723AU_card_enable_flow */ 3641 /* Act to Cardemu sequence*/ 3642 /* Turn off RF */ 3643 rtl8xxxu_write8(priv, REG_RF_CTRL, 0); 3644 3645 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */ 3646 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); 3647 val8 &= ~LEDCFG2_DPDT_SELECT; 3648 rtl8xxxu_write8(priv, REG_LEDCFG2, val8); 3649 3650 /* 0x0005[1] = 1 turn off MAC by HW state machine*/ 3651 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3652 val8 |= BIT(1); 3653 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3654 3655 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 3656 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3657 if ((val8 & BIT(1)) == 0) 3658 break; 3659 udelay(10); 3660 } 3661 3662 if (!count) { 3663 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", 3664 __func__); 3665 ret = -EBUSY; 3666 goto exit; 3667 } 3668 3669 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */ 3670 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); 3671 val8 |= SYS_ISO_ANALOG_IPS; 3672 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); 3673 3674 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/ 3675 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); 3676 val8 &= ~LDOA15_ENABLE; 3677 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); 3678 3679 exit: 3680 return ret; 3681 } 3682 3683 int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv) 3684 { 3685 u8 val8; 3686 u8 val32; 3687 int count, ret = 0; 3688 3689 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 3690 3691 /* 3692 * Poll - wait for RX packet to complete 3693 */ 3694 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 3695 val32 = rtl8xxxu_read32(priv, 0x5f8); 3696 if (!val32) 3697 break; 3698 udelay(10); 3699 } 3700 3701 if (!count) { 3702 dev_warn(&priv->udev->dev, 3703 "%s: RX poll timed out (0x05f8)\n", __func__); 3704 ret = -EBUSY; 3705 goto exit; 3706 } 3707 3708 /* Disable CCK and OFDM, clock gated */ 3709 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 3710 val8 &= ~SYS_FUNC_BBRSTB; 3711 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 3712 3713 udelay(2); 3714 3715 /* Reset baseband */ 3716 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 3717 val8 &= ~SYS_FUNC_BB_GLB_RSTN; 3718 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 3719 3720 /* Reset MAC TRX */ 3721 val8 = rtl8xxxu_read8(priv, REG_CR); 3722 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE; 3723 rtl8xxxu_write8(priv, REG_CR, val8); 3724 3725 /* Reset MAC TRX */ 3726 val8 = rtl8xxxu_read8(priv, REG_CR + 1); 3727 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */ 3728 rtl8xxxu_write8(priv, REG_CR + 1, val8); 3729 3730 /* Respond TX OK to scheduler */ 3731 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); 3732 val8 |= DUAL_TSF_TX_OK; 3733 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); 3734 3735 exit: 3736 return ret; 3737 } 3738 3739 void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv) 3740 { 3741 u8 val8; 3742 3743 /* Clear suspend enable and power down enable*/ 3744 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3745 val8 &= ~(BIT(3) | BIT(7)); 3746 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3747 3748 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ 3749 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); 3750 val8 &= ~BIT(0); 3751 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); 3752 3753 /* 0x04[12:11] = 11 enable WL suspend*/ 3754 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3755 val8 &= ~(BIT(3) | BIT(4)); 3756 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3757 } 3758 3759 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv) 3760 { 3761 u8 val8; 3762 3763 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */ 3764 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20); 3765 3766 /* 0x04[12:11] = 01 enable WL suspend */ 3767 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3768 val8 &= ~BIT(4); 3769 val8 |= BIT(3); 3770 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3771 3772 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3773 val8 |= BIT(7); 3774 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3775 3776 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */ 3777 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); 3778 val8 |= BIT(0); 3779 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); 3780 3781 return 0; 3782 } 3783 3784 int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv) 3785 { 3786 struct device *dev = &priv->udev->dev; 3787 u32 val32; 3788 int retry, retval; 3789 3790 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 3791 3792 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM); 3793 val32 |= RXPKT_NUM_RW_RELEASE_EN; 3794 rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32); 3795 3796 retry = 100; 3797 retval = -EBUSY; 3798 3799 do { 3800 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM); 3801 if (val32 & RXPKT_NUM_RXDMA_IDLE) { 3802 retval = 0; 3803 break; 3804 } 3805 } while (retry--); 3806 3807 rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0); 3808 rtl8xxxu_write32(priv, REG_RQPN, 0x80000000); 3809 mdelay(2); 3810 3811 if (!retry) 3812 dev_warn(dev, "Failed to flush FIFO\n"); 3813 3814 return retval; 3815 } 3816 3817 void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv) 3818 { 3819 /* Fix USB interface interference issue */ 3820 rtl8xxxu_write8(priv, 0xfe40, 0xe0); 3821 rtl8xxxu_write8(priv, 0xfe41, 0x8d); 3822 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3823 /* 3824 * This sets TXDMA_OFFSET_DROP_DATA_EN (bit 9) as well as bits 3825 * 8 and 5, for which I have found no documentation. 3826 */ 3827 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320); 3828 3829 /* 3830 * Solve too many protocol error on USB bus. 3831 * Can't do this for 8188/8192 UMC A cut parts 3832 */ 3833 if (!(!priv->chip_cut && priv->vendor_umc)) { 3834 rtl8xxxu_write8(priv, 0xfe40, 0xe6); 3835 rtl8xxxu_write8(priv, 0xfe41, 0x94); 3836 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3837 3838 rtl8xxxu_write8(priv, 0xfe40, 0xe0); 3839 rtl8xxxu_write8(priv, 0xfe41, 0x19); 3840 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3841 3842 rtl8xxxu_write8(priv, 0xfe40, 0xe5); 3843 rtl8xxxu_write8(priv, 0xfe41, 0x91); 3844 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3845 3846 rtl8xxxu_write8(priv, 0xfe40, 0xe2); 3847 rtl8xxxu_write8(priv, 0xfe41, 0x81); 3848 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3849 } 3850 } 3851 3852 void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv) 3853 { 3854 u32 val32; 3855 3856 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK); 3857 val32 |= TXDMA_OFFSET_DROP_DATA_EN; 3858 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32); 3859 } 3860 3861 void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv) 3862 { 3863 u8 val8; 3864 u16 val16; 3865 u32 val32; 3866 3867 /* 3868 * Workaround for 8188RU LNA power leakage problem. 3869 */ 3870 if (priv->rtl_chip == RTL8188R) { 3871 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM); 3872 val32 |= BIT(1); 3873 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32); 3874 } 3875 3876 rtl8xxxu_flush_fifo(priv); 3877 3878 rtl8xxxu_active_to_lps(priv); 3879 3880 /* Turn off RF */ 3881 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); 3882 3883 /* Reset Firmware if running in RAM */ 3884 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) 3885 rtl8xxxu_firmware_self_reset(priv); 3886 3887 /* Reset MCU */ 3888 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 3889 val16 &= ~SYS_FUNC_CPU_ENABLE; 3890 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 3891 3892 /* Reset MCU ready status */ 3893 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); 3894 3895 rtl8xxxu_active_to_emu(priv); 3896 rtl8xxxu_emu_to_disabled(priv); 3897 3898 /* Reset MCU IO Wrapper */ 3899 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 3900 val8 &= ~BIT(0); 3901 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 3902 3903 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 3904 val8 |= BIT(0); 3905 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 3906 3907 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */ 3908 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e); 3909 } 3910 3911 void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv, 3912 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5) 3913 { 3914 struct h2c_cmd h2c; 3915 3916 memset(&h2c, 0, sizeof(struct h2c_cmd)); 3917 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA; 3918 h2c.b_type_dma.data1 = arg1; 3919 h2c.b_type_dma.data2 = arg2; 3920 h2c.b_type_dma.data3 = arg3; 3921 h2c.b_type_dma.data4 = arg4; 3922 h2c.b_type_dma.data5 = arg5; 3923 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma)); 3924 } 3925 3926 void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv) 3927 { 3928 u32 val32; 3929 3930 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); 3931 val32 &= ~(BIT(22) | BIT(23)); 3932 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); 3933 } 3934 3935 static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv *priv) 3936 { 3937 struct rtl8xxxu_fileops *fops = priv->fops; 3938 u32 hq, lq, nq, eq, pubq; 3939 u32 val32; 3940 3941 hq = 0; 3942 lq = 0; 3943 nq = 0; 3944 eq = 0; 3945 pubq = 0; 3946 3947 if (priv->ep_tx_high_queue) 3948 hq = fops->page_num_hi; 3949 if (priv->ep_tx_low_queue) 3950 lq = fops->page_num_lo; 3951 if (priv->ep_tx_normal_queue) 3952 nq = fops->page_num_norm; 3953 3954 val32 = (nq << RQPN_NPQ_SHIFT) | (eq << RQPN_EPQ_SHIFT); 3955 rtl8xxxu_write32(priv, REG_RQPN_NPQ, val32); 3956 3957 pubq = fops->total_page_num - hq - lq - nq - 1; 3958 3959 val32 = RQPN_LOAD; 3960 val32 |= (hq << RQPN_HI_PQ_SHIFT); 3961 val32 |= (lq << RQPN_LO_PQ_SHIFT); 3962 val32 |= (pubq << RQPN_PUB_PQ_SHIFT); 3963 3964 rtl8xxxu_write32(priv, REG_RQPN, val32); 3965 } 3966 3967 void rtl8xxxu_init_burst(struct rtl8xxxu_priv *priv) 3968 { 3969 u8 val8; 3970 3971 /* 3972 * For USB high speed set 512B packets 3973 */ 3974 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B); 3975 u8p_replace_bits(&val8, 1, RXDMA_PRO_DMA_BURST_SIZE); 3976 u8p_replace_bits(&val8, 3, RXDMA_PRO_DMA_BURST_CNT); 3977 val8 |= RXDMA_PRO_DMA_MODE; 3978 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8); 3979 3980 /* 3981 * Enable single packet AMPDU 3982 */ 3983 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B); 3984 val8 |= HT_SINGLE_AMPDU_ENABLE; 3985 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8); 3986 3987 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, priv->fops->max_aggr_num); 3988 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 3989 priv->fops->ampdu_max_time); 3990 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff); 3991 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18); 3992 rtl8xxxu_write8(priv, REG_PIFS, 0x00); 3993 if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8710B || 3994 priv->rtl_chip == RTL8192F) { 3995 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, FWHW_TXQ_CTRL_AMPDU_RETRY); 3996 rtl8xxxu_write32(priv, REG_FAST_EDCA_CTRL, 0x03086666); 3997 } 3998 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, priv->fops->ustime_tsf_edca); 3999 rtl8xxxu_write8(priv, REG_USTIME_EDCA, priv->fops->ustime_tsf_edca); 4000 4001 /* to prevent mac is reseted by bus. */ 4002 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); 4003 val8 |= RSV_CTRL_WLOCK_1C | RSV_CTRL_DIS_PRST; 4004 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); 4005 } 4006 4007 static u8 rtl8xxxu_acquire_macid(struct rtl8xxxu_priv *priv) 4008 { 4009 u8 macid; 4010 4011 macid = find_first_zero_bit(priv->mac_id_map, RTL8XXXU_MAX_MAC_ID_NUM); 4012 if (macid < RTL8XXXU_MAX_MAC_ID_NUM) 4013 set_bit(macid, priv->mac_id_map); 4014 4015 return macid; 4016 } 4017 4018 static void rtl8xxxu_release_macid(struct rtl8xxxu_priv *priv, u8 macid) 4019 { 4020 clear_bit(macid, priv->mac_id_map); 4021 } 4022 4023 static inline u8 rtl8xxxu_get_macid(struct rtl8xxxu_priv *priv, 4024 struct ieee80211_sta *sta) 4025 { 4026 struct rtl8xxxu_sta_info *sta_info; 4027 4028 if (!priv->vif || priv->vif->type == NL80211_IFTYPE_STATION || !sta) 4029 return 0; 4030 4031 sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; 4032 return sta_info->macid; 4033 } 4034 4035 static int rtl8xxxu_init_device(struct ieee80211_hw *hw) 4036 { 4037 struct rtl8xxxu_priv *priv = hw->priv; 4038 struct device *dev = &priv->udev->dev; 4039 struct rtl8xxxu_fileops *fops = priv->fops; 4040 bool macpower; 4041 int ret; 4042 u8 val8; 4043 u16 val16; 4044 u32 val32; 4045 4046 /* Check if MAC is already powered on */ 4047 val8 = rtl8xxxu_read8(priv, REG_CR); 4048 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR); 4049 4050 /* 4051 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not 4052 * initialized. First MAC returns 0xea, second MAC returns 0x00 4053 */ 4054 if (val8 == 0xea || !(val16 & SYS_CLK_MAC_CLK_ENABLE)) 4055 macpower = false; 4056 else 4057 macpower = true; 4058 4059 if (fops->needs_full_init) 4060 macpower = false; 4061 4062 ret = fops->power_on(priv); 4063 if (ret < 0) { 4064 dev_warn(dev, "%s: Failed power on\n", __func__); 4065 goto exit; 4066 } 4067 4068 if (!macpower) 4069 rtl8xxxu_init_queue_reserved_page(priv); 4070 4071 ret = rtl8xxxu_init_queue_priority(priv); 4072 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret); 4073 if (ret) 4074 goto exit; 4075 4076 /* 4077 * Set RX page boundary 4078 */ 4079 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, fops->trxff_boundary); 4080 4081 ret = rtl8xxxu_download_firmware(priv); 4082 dev_dbg(dev, "%s: download_firmware %i\n", __func__, ret); 4083 if (ret) 4084 goto exit; 4085 ret = rtl8xxxu_start_firmware(priv); 4086 dev_dbg(dev, "%s: start_firmware %i\n", __func__, ret); 4087 if (ret) 4088 goto exit; 4089 4090 if (fops->phy_init_antenna_selection) 4091 fops->phy_init_antenna_selection(priv); 4092 4093 ret = rtl8xxxu_init_mac(priv); 4094 4095 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret); 4096 if (ret) 4097 goto exit; 4098 4099 ret = rtl8xxxu_init_phy_bb(priv); 4100 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret); 4101 if (ret) 4102 goto exit; 4103 4104 ret = fops->init_phy_rf(priv); 4105 if (ret) 4106 goto exit; 4107 4108 /* Mac APLL Setting */ 4109 if (priv->rtl_chip == RTL8192F) 4110 rtl8xxxu_write16_set(priv, REG_AFE_CTRL4, BIT(4) | BIT(15)); 4111 4112 /* RFSW Control - clear bit 14 ?? */ 4113 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E && 4114 priv->rtl_chip != RTL8188E && priv->rtl_chip != RTL8710B && 4115 priv->rtl_chip != RTL8192F) 4116 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003); 4117 4118 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW | 4119 FPGA0_RF_ANTSWB | 4120 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB) << FPGA0_RF_BD_CTRL_SHIFT); 4121 if (!priv->no_pape) { 4122 val32 |= (FPGA0_RF_PAPE | 4123 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); 4124 } 4125 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); 4126 4127 /* 0x860[6:5]= 00 - why? - this sets antenna B */ 4128 if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188E && 4129 priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192F) 4130 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210); 4131 4132 if (!macpower) { 4133 /* 4134 * Set TX buffer boundary 4135 */ 4136 val8 = fops->total_page_num + 1; 4137 4138 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8); 4139 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8); 4140 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8); 4141 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8); 4142 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8); 4143 } 4144 4145 /* 4146 * The vendor drivers set PBP for all devices, except 8192e. 4147 * There is no explanation for this in any of the sources. 4148 */ 4149 val8 = (fops->pbp_rx << PBP_PAGE_SIZE_RX_SHIFT) | 4150 (fops->pbp_tx << PBP_PAGE_SIZE_TX_SHIFT); 4151 if (priv->rtl_chip != RTL8192E) 4152 rtl8xxxu_write8(priv, REG_PBP, val8); 4153 4154 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower); 4155 if (!macpower) { 4156 ret = fops->llt_init(priv); 4157 if (ret) { 4158 dev_warn(dev, "%s: LLT table init failed\n", __func__); 4159 goto exit; 4160 } 4161 4162 /* 4163 * Chip specific quirks 4164 */ 4165 fops->usb_quirks(priv); 4166 4167 /* 4168 * Enable TX report and TX report timer for 8723bu/8188eu/... 4169 */ 4170 if (fops->has_tx_report) { 4171 /* 4172 * The RTL8188EU has two types of TX reports: 4173 * rpt_sel=1: 4174 * One report for one frame. We can use this for frames 4175 * with IEEE80211_TX_CTL_REQ_TX_STATUS. 4176 * rpt_sel=2: 4177 * One report for many frames transmitted over a period 4178 * of time. (This is what REG_TX_REPORT_TIME is for.) The 4179 * report includes the number of frames transmitted 4180 * successfully, and the number of unsuccessful 4181 * transmissions. We use this for software rate control. 4182 * 4183 * Bit 0 of REG_TX_REPORT_CTRL is required for both types. 4184 * Bit 1 (TX_REPORT_CTRL_TIMER_ENABLE) is required for 4185 * type 2. 4186 */ 4187 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); 4188 if (priv->rtl_chip == RTL8188E) 4189 val8 |= BIT(0); 4190 val8 |= TX_REPORT_CTRL_TIMER_ENABLE; 4191 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); 4192 /* Set MAX RPT MACID */ 4193 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02); 4194 /* TX report Timer. Unit: 32us */ 4195 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0); 4196 4197 /* tmp ps ? */ 4198 val8 = rtl8xxxu_read8(priv, 0xa3); 4199 val8 &= 0xf8; 4200 rtl8xxxu_write8(priv, 0xa3, val8); 4201 } 4202 4203 if (priv->rtl_chip == RTL8710B || priv->rtl_chip == RTL8192F) 4204 rtl8xxxu_write8(priv, REG_EARLY_MODE_CONTROL_8710B, 0); 4205 } 4206 4207 /* 4208 * Unit in 8 bytes. 4209 * Get Rx PHY status in order to report RSSI and others. 4210 */ 4211 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4); 4212 4213 if (priv->rtl_chip == RTL8192E) { 4214 rtl8xxxu_write32(priv, REG_HIMR0, 0x00); 4215 rtl8xxxu_write32(priv, REG_HIMR1, 0x00); 4216 } else if (priv->rtl_chip == RTL8188F) { 4217 rtl8xxxu_write32(priv, REG_HISR0, 0xffffffff); 4218 rtl8xxxu_write32(priv, REG_HISR1, 0xffffffff); 4219 } else if (priv->rtl_chip == RTL8188E) { 4220 rtl8xxxu_write32(priv, REG_HISR0, 0xffffffff); 4221 val32 = IMR0_PSTIMEOUT | IMR0_TBDER | IMR0_CPWM | IMR0_CPWM2; 4222 rtl8xxxu_write32(priv, REG_HIMR0, val32); 4223 val32 = IMR1_TXERR | IMR1_RXERR | IMR1_TXFOVW | IMR1_RXFOVW; 4224 rtl8xxxu_write32(priv, REG_HIMR1, val32); 4225 val8 = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION); 4226 val8 |= USB_SPEC_INT_BULK_SELECT; 4227 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, val8); 4228 } else if (priv->rtl_chip == RTL8710B) { 4229 rtl8xxxu_write32(priv, REG_HIMR0_8710B, 0); 4230 } else if (priv->rtl_chip != RTL8192F) { 4231 /* 4232 * Enable all interrupts - not obvious USB needs to do this 4233 */ 4234 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff); 4235 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff); 4236 } 4237 4238 rtl8xxxu_set_mac(priv); 4239 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION); 4240 4241 /* 4242 * Configure initial WMAC settings 4243 */ 4244 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST | 4245 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL | 4246 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC; 4247 rtl8xxxu_write32(priv, REG_RCR, val32); 4248 priv->regrcr = val32; 4249 4250 if (fops->init_reg_rxfltmap) { 4251 /* Accept all data frames */ 4252 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff); 4253 4254 /* 4255 * Since ADF is removed from RCR, ps-poll will not be indicate to driver, 4256 * RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. 4257 */ 4258 rtl8xxxu_write16(priv, REG_RXFLTMAP1, 0x400); 4259 4260 /* Accept all management frames */ 4261 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff); 4262 } else { 4263 /* 4264 * Accept all multicast 4265 */ 4266 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff); 4267 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff); 4268 } 4269 4270 /* 4271 * Init adaptive controls 4272 */ 4273 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 4274 val32 &= ~RESPONSE_RATE_BITMAP_ALL; 4275 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M; 4276 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 4277 4278 /* CCK = 0x0a, OFDM = 0x10 */ 4279 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10); 4280 rtl8xxxu_set_retry(priv, 0x30, 0x30); 4281 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10); 4282 4283 /* 4284 * Init EDCA 4285 */ 4286 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a); 4287 4288 /* Set CCK SIFS */ 4289 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a); 4290 4291 /* Set OFDM SIFS */ 4292 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a); 4293 4294 /* TXOP */ 4295 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b); 4296 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f); 4297 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324); 4298 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226); 4299 4300 /* Set data auto rate fallback retry count */ 4301 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000); 4302 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404); 4303 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201); 4304 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605); 4305 4306 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL); 4307 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY; 4308 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8); 4309 4310 /* Set ACK timeout */ 4311 rtl8xxxu_write8(priv, REG_ACKTO, 0x40); 4312 4313 /* 4314 * Initialize beacon parameters 4315 */ 4316 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8); 4317 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16); 4318 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404); 4319 if (priv->rtl_chip != RTL8188F && priv->rtl_chip != RTL8710B && 4320 priv->rtl_chip != RTL8192F) 4321 /* Firmware will control REG_DRVERLYINT when power saving is enable, */ 4322 /* so don't set this register on STA mode. */ 4323 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME); 4324 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME); 4325 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F); 4326 4327 /* 4328 * Initialize burst parameters 4329 */ 4330 if (priv->fops->init_burst) 4331 priv->fops->init_burst(priv); 4332 4333 if (fops->init_aggregation) 4334 fops->init_aggregation(priv); 4335 4336 if (fops->init_reg_pkt_life_time) { 4337 rtl8xxxu_write16(priv, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ 4338 rtl8xxxu_write16(priv, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ 4339 } 4340 4341 /* 4342 * Enable CCK and OFDM block 4343 */ 4344 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 4345 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM); 4346 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 4347 4348 /* 4349 * Invalidate all CAM entries - bit 30 is undocumented 4350 */ 4351 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30)); 4352 4353 /* 4354 * Start out with default power levels for channel 6, 20MHz 4355 */ 4356 fops->set_tx_power(priv, 1, false); 4357 4358 /* Let the 8051 take control of antenna setting */ 4359 if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188F && 4360 priv->rtl_chip != RTL8710B) { 4361 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); 4362 val8 |= LEDCFG2_DPDT_SELECT; 4363 rtl8xxxu_write8(priv, REG_LEDCFG2, val8); 4364 } 4365 4366 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff); 4367 4368 /* Disable BAR - not sure if this has any effect on USB */ 4369 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff); 4370 4371 if (priv->rtl_chip != RTL8188F && priv->rtl_chip != RTL8188E && 4372 priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192F) 4373 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0); 4374 4375 if (fops->init_statistics) 4376 fops->init_statistics(priv); 4377 4378 if (priv->rtl_chip == RTL8192E) { 4379 /* 4380 * 0x4c6[3] 1: RTS BW = Data BW 4381 * 0: RTS BW depends on CCA / secondary CCA result. 4382 */ 4383 val8 = rtl8xxxu_read8(priv, REG_QUEUE_CTRL); 4384 val8 &= ~BIT(3); 4385 rtl8xxxu_write8(priv, REG_QUEUE_CTRL, val8); 4386 /* 4387 * Reset USB mode switch setting 4388 */ 4389 rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00); 4390 } else if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8188E || 4391 priv->rtl_chip == RTL8192F) { 4392 /* 4393 * Init GPIO settings for 8188f, 8188e, 8192f 4394 */ 4395 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG); 4396 val8 &= ~GPIO_MUXCFG_IO_SEL_ENBT; 4397 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8); 4398 } 4399 4400 if (priv->rtl_chip == RTL8188F) 4401 /* CCK PD */ 4402 rtl8xxxu_write8(priv, REG_CCK_PD_THRESH, CCK_PD_TYPE1_LV1_TH); 4403 4404 fops->phy_lc_calibrate(priv); 4405 4406 fops->phy_iq_calibrate(priv); 4407 4408 /* 4409 * This should enable thermal meter 4410 */ 4411 if (fops->gen2_thermal_meter) { 4412 if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8710B) { 4413 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B); 4414 val32 |= 0x30000; 4415 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B, val32); 4416 } else { 4417 rtl8xxxu_write_rfreg(priv, 4418 RF_A, RF6052_REG_T_METER_8723B, 0x37cf8); 4419 } 4420 } else { 4421 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60); 4422 } 4423 4424 /* Set NAV_UPPER to 30000us */ 4425 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT); 4426 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8); 4427 4428 if (priv->rtl_chip == RTL8723A) { 4429 /* 4430 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test, 4431 * but we need to find root cause. 4432 * This is 8723au only. 4433 */ 4434 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 4435 if ((val32 & 0xff000000) != 0x83000000) { 4436 val32 |= FPGA_RF_MODE_CCK; 4437 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 4438 } 4439 } else if (priv->rtl_chip == RTL8192E || priv->rtl_chip == RTL8188E) { 4440 rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00); 4441 } 4442 4443 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL); 4444 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK; 4445 /* ack for xmit mgmt frames. */ 4446 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32); 4447 4448 if (priv->rtl_chip == RTL8192E) { 4449 /* 4450 * Fix LDPC rx hang issue. 4451 */ 4452 val32 = rtl8xxxu_read32(priv, REG_AFE_MISC); 4453 rtl8xxxu_write8(priv, REG_8192E_LDOV12_CTRL, 0x75); 4454 val32 &= 0xfff00fff; 4455 val32 |= 0x0007e000; 4456 rtl8xxxu_write32(priv, REG_AFE_MISC, val32); 4457 4458 /* 4459 * 0x824[9] = 0x82C[9] = 0xA80[7] those registers setting 4460 * should be equal or CCK RSSI report may be incorrect 4461 */ 4462 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2); 4463 priv->cck_agc_report_type = 4464 u32_get_bits(val32, FPGA0_HSSI_PARM2_CCK_HIGH_PWR); 4465 4466 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_HSSI_PARM2); 4467 if (priv->cck_agc_report_type != 4468 u32_get_bits(val32, FPGA0_HSSI_PARM2_CCK_HIGH_PWR)) { 4469 if (priv->cck_agc_report_type) 4470 val32 |= FPGA0_HSSI_PARM2_CCK_HIGH_PWR; 4471 else 4472 val32 &= ~FPGA0_HSSI_PARM2_CCK_HIGH_PWR; 4473 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM2, val32); 4474 } 4475 4476 val32 = rtl8xxxu_read32(priv, REG_AGC_RPT); 4477 if (priv->cck_agc_report_type) 4478 val32 |= AGC_RPT_CCK; 4479 else 4480 val32 &= ~AGC_RPT_CCK; 4481 rtl8xxxu_write32(priv, REG_AGC_RPT, val32); 4482 } 4483 4484 if (priv->rtl_chip == RTL8710B) { 4485 /* 4486 * 0x76D[5:4] is Port0,Port1 Enable Bit. 4487 * This is only for 8710B, 2b'00 for MP and 2b'11 for Normal Driver 4488 */ 4489 val8 = rtl8xxxu_read8(priv, REG_PORT_CONTROL_8710B); 4490 val8 |= BIT(5) | BIT(4); 4491 rtl8xxxu_write8(priv, REG_PORT_CONTROL_8710B, val8); 4492 4493 /* Set 0x5c[8] and [2:0] = 1, LDO mode */ 4494 val32 = rtl8xxxu_read32(priv, REG_WL_RF_PSS_8710B); 4495 val32 |= 0x107; 4496 rtl8xxxu_write32(priv, REG_WL_RF_PSS_8710B, val32); 4497 } 4498 4499 val32 = rtl8xxxu_read32(priv, 0xa9c); 4500 priv->cck_new_agc = u32_get_bits(val32, BIT(17)); 4501 4502 /* Initialise the center frequency offset tracking */ 4503 if (priv->fops->set_crystal_cap) { 4504 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); 4505 priv->cfo_tracking.atc_status = val32 & CFO_TRACKING_ATC_STATUS; 4506 priv->cfo_tracking.adjust = true; 4507 priv->cfo_tracking.crystal_cap = priv->default_crystal_cap; 4508 } 4509 4510 if (priv->rtl_chip == RTL8188E) 4511 rtl8188e_ra_info_init_all(&priv->ra_info); 4512 4513 set_bit(RTL8XXXU_BC_MC_MACID, priv->mac_id_map); 4514 4515 exit: 4516 return ret; 4517 } 4518 4519 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv, 4520 struct ieee80211_key_conf *key, const u8 *mac) 4521 { 4522 u32 cmd, val32, addr, ctrl; 4523 int j, i, tmp_debug; 4524 4525 tmp_debug = rtl8xxxu_debug; 4526 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY) 4527 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE; 4528 4529 /* 4530 * This is a bit of a hack - the lower bits of the cipher 4531 * suite selector happens to match the cipher index in the CAM 4532 */ 4533 addr = key->keyidx << CAM_CMD_KEY_SHIFT; 4534 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID; 4535 4536 for (j = 5; j >= 0; j--) { 4537 switch (j) { 4538 case 0: 4539 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24); 4540 break; 4541 case 1: 4542 val32 = mac[2] | (mac[3] << 8) | 4543 (mac[4] << 16) | (mac[5] << 24); 4544 break; 4545 default: 4546 i = (j - 2) << 2; 4547 val32 = key->key[i] | (key->key[i + 1] << 8) | 4548 key->key[i + 2] << 16 | key->key[i + 3] << 24; 4549 break; 4550 } 4551 4552 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32); 4553 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j); 4554 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd); 4555 udelay(100); 4556 } 4557 4558 rtl8xxxu_debug = tmp_debug; 4559 } 4560 4561 static 4562 int rtl8xxxu_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) 4563 { 4564 struct rtl8xxxu_priv *priv = hw->priv; 4565 4566 *tx_ant = BIT(priv->tx_paths) - 1; 4567 *rx_ant = BIT(priv->rx_paths) - 1; 4568 4569 return 0; 4570 } 4571 4572 static int rtl8xxxu_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, 4573 bool set) 4574 { 4575 struct rtl8xxxu_priv *priv = hw->priv; 4576 4577 schedule_work(&priv->update_beacon_work); 4578 4579 return 0; 4580 } 4581 4582 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw, 4583 struct ieee80211_vif *vif, const u8 *mac) 4584 { 4585 struct rtl8xxxu_priv *priv = hw->priv; 4586 u8 val8; 4587 4588 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 4589 val8 |= BEACON_DISABLE_TSF_UPDATE; 4590 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 4591 } 4592 4593 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw, 4594 struct ieee80211_vif *vif) 4595 { 4596 struct rtl8xxxu_priv *priv = hw->priv; 4597 u8 val8; 4598 4599 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 4600 val8 &= ~BEACON_DISABLE_TSF_UPDATE; 4601 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 4602 } 4603 4604 void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv, 4605 u32 ramask, u8 rateid, int sgi, int txbw_40mhz, 4606 u8 macid) 4607 { 4608 struct h2c_cmd h2c; 4609 4610 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4611 4612 h2c.ramask.cmd = H2C_SET_RATE_MASK; 4613 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff); 4614 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16); 4615 4616 h2c.ramask.arg = 0x80; 4617 if (sgi) 4618 h2c.ramask.arg |= 0x20; 4619 4620 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n", 4621 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask)); 4622 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.ramask)); 4623 } 4624 4625 void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv, 4626 u32 ramask, u8 rateid, int sgi, int txbw_40mhz, 4627 u8 macid) 4628 { 4629 struct h2c_cmd h2c; 4630 u8 bw; 4631 4632 if (txbw_40mhz) 4633 bw = RTL8XXXU_CHANNEL_WIDTH_40; 4634 else 4635 bw = RTL8XXXU_CHANNEL_WIDTH_20; 4636 4637 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4638 4639 h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID; 4640 h2c.b_macid_cfg.ramask0 = ramask & 0xff; 4641 h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff; 4642 h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff; 4643 h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff; 4644 h2c.b_macid_cfg.macid = macid; 4645 4646 h2c.b_macid_cfg.data1 = rateid; 4647 if (sgi) 4648 h2c.b_macid_cfg.data1 |= BIT(7); 4649 4650 h2c.b_macid_cfg.data2 = bw; 4651 4652 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, rateid %02x, sgi %d, size %zi\n", 4653 __func__, ramask, rateid, sgi, sizeof(h2c.b_macid_cfg)); 4654 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg)); 4655 } 4656 4657 void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv, 4658 u8 macid, u8 role, bool connect) 4659 { 4660 struct h2c_cmd h2c; 4661 4662 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4663 4664 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT; 4665 4666 if (connect) 4667 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT; 4668 else 4669 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT; 4670 4671 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss)); 4672 } 4673 4674 void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv, 4675 u8 macid, u8 role, bool connect) 4676 { 4677 /* 4678 * The firmware turns on the rate control when it knows it's 4679 * connected to a network. 4680 */ 4681 struct h2c_cmd h2c; 4682 4683 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4684 4685 h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT; 4686 if (connect) 4687 h2c.media_status_rpt.parm |= BIT(0); 4688 else 4689 h2c.media_status_rpt.parm &= ~BIT(0); 4690 4691 h2c.media_status_rpt.parm |= ((role << 4) & 0xf0); 4692 h2c.media_status_rpt.macid = macid; 4693 4694 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt)); 4695 } 4696 4697 void rtl8xxxu_gen1_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi) 4698 { 4699 struct h2c_cmd h2c; 4700 const int h2c_size = 4; 4701 4702 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4703 4704 h2c.rssi_report.cmd = H2C_SET_RSSI; 4705 h2c.rssi_report.macid = macid; 4706 h2c.rssi_report.rssi = rssi; 4707 4708 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, h2c_size); 4709 } 4710 4711 void rtl8xxxu_gen2_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi) 4712 { 4713 struct h2c_cmd h2c; 4714 int h2c_size = sizeof(h2c.rssi_report); 4715 4716 if (priv->rtl_chip == RTL8723B) 4717 h2c_size = 4; 4718 4719 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4720 4721 h2c.rssi_report.cmd = H2C_8723B_RSSI_SETTING; 4722 h2c.rssi_report.macid = macid; 4723 h2c.rssi_report.rssi = rssi; 4724 4725 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, h2c_size); 4726 } 4727 4728 void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv) 4729 { 4730 u8 agg_ctrl, usb_spec, page_thresh, timeout; 4731 4732 usb_spec = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION); 4733 usb_spec &= ~USB_SPEC_USB_AGG_ENABLE; 4734 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, usb_spec); 4735 4736 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); 4737 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; 4738 4739 if (!rtl8xxxu_dma_aggregation) { 4740 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); 4741 return; 4742 } 4743 4744 agg_ctrl |= TRXDMA_CTRL_RXDMA_AGG_EN; 4745 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); 4746 4747 /* 4748 * The number of packets we can take looks to be buffer size / 512 4749 * which matches the 512 byte rounding we have to do when de-muxing 4750 * the packets. 4751 * 4752 * Sample numbers from the vendor driver: 4753 * USB High-Speed mode values: 4754 * RxAggBlockCount = 8 : 512 byte unit 4755 * RxAggBlockTimeout = 6 4756 * RxAggPageCount = 48 : 128 byte unit 4757 * RxAggPageTimeout = 4 or 6 (absolute time 34ms/(2^6)) 4758 */ 4759 4760 page_thresh = (priv->fops->rx_agg_buf_size / 512); 4761 if (rtl8xxxu_dma_agg_pages >= 0) { 4762 if (rtl8xxxu_dma_agg_pages <= page_thresh) 4763 timeout = page_thresh; 4764 else if (rtl8xxxu_dma_agg_pages <= 6) 4765 dev_err(&priv->udev->dev, 4766 "%s: dma_agg_pages=%i too small, minimum is 6\n", 4767 __func__, rtl8xxxu_dma_agg_pages); 4768 else 4769 dev_err(&priv->udev->dev, 4770 "%s: dma_agg_pages=%i larger than limit %i\n", 4771 __func__, rtl8xxxu_dma_agg_pages, page_thresh); 4772 } 4773 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH, page_thresh); 4774 /* 4775 * REG_RXDMA_AGG_PG_TH + 1 seems to be the timeout register on 4776 * gen2 chips and rtl8188eu. The rtl8723au seems unhappy if we 4777 * don't set it, so better set both. 4778 */ 4779 timeout = 4; 4780 4781 if (rtl8xxxu_dma_agg_timeout >= 0) { 4782 if (rtl8xxxu_dma_agg_timeout <= 127) 4783 timeout = rtl8xxxu_dma_agg_timeout; 4784 else 4785 dev_err(&priv->udev->dev, 4786 "%s: Invalid dma_agg_timeout: %i\n", 4787 __func__, rtl8xxxu_dma_agg_timeout); 4788 } 4789 4790 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH + 1, timeout); 4791 rtl8xxxu_write8(priv, REG_USB_DMA_AGG_TO, timeout); 4792 priv->rx_buf_aggregation = 1; 4793 } 4794 4795 static const struct ieee80211_rate rtl8xxxu_legacy_ratetable[] = { 4796 {.bitrate = 10, .hw_value = 0x00,}, 4797 {.bitrate = 20, .hw_value = 0x01,}, 4798 {.bitrate = 55, .hw_value = 0x02,}, 4799 {.bitrate = 110, .hw_value = 0x03,}, 4800 {.bitrate = 60, .hw_value = 0x04,}, 4801 {.bitrate = 90, .hw_value = 0x05,}, 4802 {.bitrate = 120, .hw_value = 0x06,}, 4803 {.bitrate = 180, .hw_value = 0x07,}, 4804 {.bitrate = 240, .hw_value = 0x08,}, 4805 {.bitrate = 360, .hw_value = 0x09,}, 4806 {.bitrate = 480, .hw_value = 0x0a,}, 4807 {.bitrate = 540, .hw_value = 0x0b,}, 4808 }; 4809 4810 static void rtl8xxxu_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss) 4811 { 4812 if (rate <= DESC_RATE_54M) 4813 return; 4814 4815 if (rate >= DESC_RATE_MCS0 && rate <= DESC_RATE_MCS15) { 4816 if (rate < DESC_RATE_MCS8) 4817 *nss = 1; 4818 else 4819 *nss = 2; 4820 *mcs = rate - DESC_RATE_MCS0; 4821 } 4822 } 4823 4824 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg) 4825 { 4826 struct ieee80211_hw *hw = priv->hw; 4827 u32 val32; 4828 u8 rate_idx = 0; 4829 4830 rate_cfg &= RESPONSE_RATE_BITMAP_ALL; 4831 4832 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 4833 if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ) 4834 val32 &= RESPONSE_RATE_RRSR_INIT_5G; 4835 else 4836 val32 &= RESPONSE_RATE_RRSR_INIT_2G; 4837 val32 |= rate_cfg; 4838 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 4839 4840 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg); 4841 4842 while (rate_cfg) { 4843 rate_cfg = (rate_cfg >> 1); 4844 rate_idx++; 4845 } 4846 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx); 4847 } 4848 4849 static u16 4850 rtl8xxxu_wireless_mode(struct ieee80211_hw *hw, struct ieee80211_sta *sta) 4851 { 4852 u16 network_type = WIRELESS_MODE_UNKNOWN; 4853 4854 if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ) { 4855 if (sta->deflink.vht_cap.vht_supported) 4856 network_type = WIRELESS_MODE_AC; 4857 else if (sta->deflink.ht_cap.ht_supported) 4858 network_type = WIRELESS_MODE_N_5G; 4859 4860 network_type |= WIRELESS_MODE_A; 4861 } else { 4862 if (sta->deflink.vht_cap.vht_supported) 4863 network_type = WIRELESS_MODE_AC; 4864 else if (sta->deflink.ht_cap.ht_supported) 4865 network_type = WIRELESS_MODE_N_24G; 4866 4867 if (sta->deflink.supp_rates[0] <= 0xf) 4868 network_type |= WIRELESS_MODE_B; 4869 else if (sta->deflink.supp_rates[0] & 0xf) 4870 network_type |= (WIRELESS_MODE_B | WIRELESS_MODE_G); 4871 else 4872 network_type |= WIRELESS_MODE_G; 4873 } 4874 4875 return network_type; 4876 } 4877 4878 static void rtl8xxxu_set_aifs(struct rtl8xxxu_priv *priv, u8 slot_time) 4879 { 4880 u32 reg_edca_param[IEEE80211_NUM_ACS] = { 4881 [IEEE80211_AC_VO] = REG_EDCA_VO_PARAM, 4882 [IEEE80211_AC_VI] = REG_EDCA_VI_PARAM, 4883 [IEEE80211_AC_BE] = REG_EDCA_BE_PARAM, 4884 [IEEE80211_AC_BK] = REG_EDCA_BK_PARAM, 4885 }; 4886 u32 val32; 4887 u16 wireless_mode = 0; 4888 u8 aifs, aifsn, sifs; 4889 int i; 4890 4891 if (priv->vif) { 4892 struct ieee80211_sta *sta; 4893 4894 rcu_read_lock(); 4895 sta = ieee80211_find_sta(priv->vif, priv->vif->bss_conf.bssid); 4896 if (sta) 4897 wireless_mode = rtl8xxxu_wireless_mode(priv->hw, sta); 4898 rcu_read_unlock(); 4899 } 4900 4901 if (priv->hw->conf.chandef.chan->band == NL80211_BAND_5GHZ || 4902 (wireless_mode & WIRELESS_MODE_N_24G)) 4903 sifs = 16; 4904 else 4905 sifs = 10; 4906 4907 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 4908 val32 = rtl8xxxu_read32(priv, reg_edca_param[i]); 4909 4910 /* It was set in conf_tx. */ 4911 aifsn = val32 & 0xff; 4912 4913 /* aifsn not set yet or already fixed */ 4914 if (aifsn < 2 || aifsn > 15) 4915 continue; 4916 4917 aifs = aifsn * slot_time + sifs; 4918 4919 val32 &= ~0xff; 4920 val32 |= aifs; 4921 rtl8xxxu_write32(priv, reg_edca_param[i], val32); 4922 } 4923 } 4924 4925 void rtl8xxxu_update_ra_report(struct rtl8xxxu_ra_report *rarpt, 4926 u8 rate, u8 sgi, u8 bw) 4927 { 4928 u8 mcs, nss; 4929 4930 rarpt->txrate.flags = 0; 4931 4932 if (rate <= DESC_RATE_54M) { 4933 rarpt->txrate.legacy = rtl8xxxu_legacy_ratetable[rate].bitrate; 4934 } else { 4935 rtl8xxxu_desc_to_mcsrate(rate, &mcs, &nss); 4936 rarpt->txrate.flags |= RATE_INFO_FLAGS_MCS; 4937 4938 rarpt->txrate.mcs = mcs; 4939 rarpt->txrate.nss = nss; 4940 4941 if (sgi) 4942 rarpt->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 4943 4944 rarpt->txrate.bw = bw; 4945 } 4946 4947 rarpt->bit_rate = cfg80211_calculate_bitrate(&rarpt->txrate); 4948 rarpt->desc_rate = rate; 4949 } 4950 4951 static void 4952 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 4953 struct ieee80211_bss_conf *bss_conf, u64 changed) 4954 { 4955 struct rtl8xxxu_priv *priv = hw->priv; 4956 struct device *dev = &priv->udev->dev; 4957 struct ieee80211_sta *sta; 4958 struct rtl8xxxu_ra_report *rarpt; 4959 u32 val32; 4960 u8 val8; 4961 4962 rarpt = &priv->ra_report; 4963 4964 if (changed & BSS_CHANGED_ASSOC) { 4965 dev_dbg(dev, "Changed ASSOC: %i!\n", vif->cfg.assoc); 4966 4967 rtl8xxxu_set_linktype(priv, vif->type); 4968 4969 if (vif->cfg.assoc) { 4970 u32 ramask; 4971 int sgi = 0; 4972 u8 highest_rate; 4973 u8 bw; 4974 4975 rcu_read_lock(); 4976 sta = ieee80211_find_sta(vif, bss_conf->bssid); 4977 if (!sta) { 4978 dev_info(dev, "%s: ASSOC no sta found\n", 4979 __func__); 4980 rcu_read_unlock(); 4981 goto error; 4982 } 4983 4984 if (sta->deflink.ht_cap.ht_supported) 4985 dev_info(dev, "%s: HT supported\n", __func__); 4986 if (sta->deflink.vht_cap.vht_supported) 4987 dev_info(dev, "%s: VHT supported\n", __func__); 4988 4989 /* TODO: Set bits 28-31 for rate adaptive id */ 4990 ramask = (sta->deflink.supp_rates[0] & 0xfff) | 4991 sta->deflink.ht_cap.mcs.rx_mask[0] << 12 | 4992 sta->deflink.ht_cap.mcs.rx_mask[1] << 20; 4993 if (sta->deflink.ht_cap.cap & 4994 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)) 4995 sgi = 1; 4996 4997 highest_rate = fls(ramask) - 1; 4998 if (rtl8xxxu_ht40_2g && 4999 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)) 5000 bw = RATE_INFO_BW_40; 5001 else 5002 bw = RATE_INFO_BW_20; 5003 rcu_read_unlock(); 5004 5005 rtl8xxxu_update_ra_report(rarpt, highest_rate, sgi, bw); 5006 5007 priv->vif = vif; 5008 priv->rssi_level = RTL8XXXU_RATR_STA_INIT; 5009 5010 priv->fops->update_rate_mask(priv, ramask, 0, sgi, 5011 bw == RATE_INFO_BW_40, 0); 5012 5013 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff); 5014 5015 rtl8xxxu_stop_tx_beacon(priv); 5016 5017 /* joinbss sequence */ 5018 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT, 5019 0xc000 | vif->cfg.aid); 5020 5021 priv->fops->report_connect(priv, 0, H2C_MACID_ROLE_AP, true); 5022 } else { 5023 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 5024 val8 |= BEACON_DISABLE_TSF_UPDATE; 5025 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 5026 5027 priv->fops->report_connect(priv, 0, H2C_MACID_ROLE_AP, false); 5028 } 5029 } 5030 5031 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 5032 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n", 5033 bss_conf->use_short_preamble); 5034 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 5035 if (bss_conf->use_short_preamble) 5036 val32 |= RSR_ACK_SHORT_PREAMBLE; 5037 else 5038 val32 &= ~RSR_ACK_SHORT_PREAMBLE; 5039 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 5040 } 5041 5042 if (changed & BSS_CHANGED_ERP_SLOT) { 5043 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n", 5044 bss_conf->use_short_slot); 5045 5046 if (bss_conf->use_short_slot) 5047 val8 = 9; 5048 else 5049 val8 = 20; 5050 rtl8xxxu_write8(priv, REG_SLOT, val8); 5051 5052 rtl8xxxu_set_aifs(priv, val8); 5053 } 5054 5055 if (changed & BSS_CHANGED_BSSID) { 5056 dev_dbg(dev, "Changed BSSID!\n"); 5057 rtl8xxxu_set_bssid(priv, bss_conf->bssid); 5058 } 5059 5060 if (changed & BSS_CHANGED_BASIC_RATES) { 5061 dev_dbg(dev, "Changed BASIC_RATES!\n"); 5062 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates); 5063 } 5064 5065 if (changed & BSS_CHANGED_BEACON_ENABLED) { 5066 if (bss_conf->enable_beacon) 5067 rtl8xxxu_start_tx_beacon(priv); 5068 else 5069 rtl8xxxu_stop_tx_beacon(priv); 5070 } 5071 5072 if (changed & BSS_CHANGED_BEACON) 5073 schedule_work(&priv->update_beacon_work); 5074 5075 error: 5076 return; 5077 } 5078 5079 static int rtl8xxxu_start_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 5080 struct ieee80211_bss_conf *link_conf) 5081 { 5082 struct rtl8xxxu_priv *priv = hw->priv; 5083 struct device *dev = &priv->udev->dev; 5084 5085 dev_dbg(dev, "Start AP mode\n"); 5086 rtl8xxxu_set_bssid(priv, vif->bss_conf.bssid); 5087 rtl8xxxu_write16(priv, REG_BCN_INTERVAL, vif->bss_conf.beacon_int); 5088 priv->fops->report_connect(priv, RTL8XXXU_BC_MC_MACID, 0, true); 5089 5090 return 0; 5091 } 5092 5093 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue) 5094 { 5095 u32 rtlqueue; 5096 5097 switch (queue) { 5098 case IEEE80211_AC_VO: 5099 rtlqueue = TXDESC_QUEUE_VO; 5100 break; 5101 case IEEE80211_AC_VI: 5102 rtlqueue = TXDESC_QUEUE_VI; 5103 break; 5104 case IEEE80211_AC_BE: 5105 rtlqueue = TXDESC_QUEUE_BE; 5106 break; 5107 case IEEE80211_AC_BK: 5108 rtlqueue = TXDESC_QUEUE_BK; 5109 break; 5110 default: 5111 rtlqueue = TXDESC_QUEUE_BE; 5112 } 5113 5114 return rtlqueue; 5115 } 5116 5117 static u32 rtl8xxxu_queue_select(struct ieee80211_hdr *hdr, struct sk_buff *skb) 5118 { 5119 u32 queue; 5120 5121 if (unlikely(ieee80211_is_beacon(hdr->frame_control))) 5122 queue = TXDESC_QUEUE_BEACON; 5123 else if (ieee80211_is_mgmt(hdr->frame_control)) 5124 queue = TXDESC_QUEUE_MGNT; 5125 else 5126 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb)); 5127 5128 return queue; 5129 } 5130 5131 /* 5132 * Despite newer chips 8723b/8812/8821 having a larger TX descriptor 5133 * format. The descriptor checksum is still only calculated over the 5134 * initial 32 bytes of the descriptor! 5135 */ 5136 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc) 5137 { 5138 __le16 *ptr = (__le16 *)tx_desc; 5139 u16 csum = 0; 5140 int i; 5141 5142 /* 5143 * Clear csum field before calculation, as the csum field is 5144 * in the middle of the struct. 5145 */ 5146 tx_desc->csum = cpu_to_le16(0); 5147 5148 for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++) 5149 csum = csum ^ le16_to_cpu(ptr[i]); 5150 5151 tx_desc->csum |= cpu_to_le16(csum); 5152 } 5153 5154 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv) 5155 { 5156 struct rtl8xxxu_tx_urb *tx_urb, *tmp; 5157 unsigned long flags; 5158 5159 spin_lock_irqsave(&priv->tx_urb_lock, flags); 5160 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) { 5161 list_del(&tx_urb->list); 5162 priv->tx_urb_free_count--; 5163 usb_free_urb(&tx_urb->urb); 5164 } 5165 spin_unlock_irqrestore(&priv->tx_urb_lock, flags); 5166 } 5167 5168 static struct rtl8xxxu_tx_urb * 5169 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv) 5170 { 5171 struct rtl8xxxu_tx_urb *tx_urb; 5172 unsigned long flags; 5173 5174 spin_lock_irqsave(&priv->tx_urb_lock, flags); 5175 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list, 5176 struct rtl8xxxu_tx_urb, list); 5177 if (tx_urb) { 5178 list_del(&tx_urb->list); 5179 priv->tx_urb_free_count--; 5180 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER && 5181 !priv->tx_stopped) { 5182 priv->tx_stopped = true; 5183 ieee80211_stop_queues(priv->hw); 5184 } 5185 } 5186 5187 spin_unlock_irqrestore(&priv->tx_urb_lock, flags); 5188 5189 return tx_urb; 5190 } 5191 5192 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv, 5193 struct rtl8xxxu_tx_urb *tx_urb) 5194 { 5195 unsigned long flags; 5196 5197 INIT_LIST_HEAD(&tx_urb->list); 5198 5199 spin_lock_irqsave(&priv->tx_urb_lock, flags); 5200 5201 list_add(&tx_urb->list, &priv->tx_urb_free_list); 5202 priv->tx_urb_free_count++; 5203 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER && 5204 priv->tx_stopped) { 5205 priv->tx_stopped = false; 5206 ieee80211_wake_queues(priv->hw); 5207 } 5208 5209 spin_unlock_irqrestore(&priv->tx_urb_lock, flags); 5210 } 5211 5212 static void rtl8xxxu_tx_complete(struct urb *urb) 5213 { 5214 struct sk_buff *skb = (struct sk_buff *)urb->context; 5215 struct ieee80211_tx_info *tx_info; 5216 struct ieee80211_hw *hw; 5217 struct rtl8xxxu_priv *priv; 5218 struct rtl8xxxu_tx_urb *tx_urb = 5219 container_of(urb, struct rtl8xxxu_tx_urb, urb); 5220 5221 tx_info = IEEE80211_SKB_CB(skb); 5222 hw = tx_info->rate_driver_data[0]; 5223 priv = hw->priv; 5224 5225 skb_pull(skb, priv->fops->tx_desc_size); 5226 5227 ieee80211_tx_info_clear_status(tx_info); 5228 tx_info->status.rates[0].idx = -1; 5229 tx_info->status.rates[0].count = 0; 5230 5231 if (!urb->status) 5232 tx_info->flags |= IEEE80211_TX_STAT_ACK; 5233 5234 ieee80211_tx_status_irqsafe(hw, skb); 5235 5236 rtl8xxxu_free_tx_urb(priv, tx_urb); 5237 } 5238 5239 static void rtl8xxxu_dump_action(struct device *dev, 5240 struct ieee80211_hdr *hdr) 5241 { 5242 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr; 5243 u16 cap, timeout; 5244 5245 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION)) 5246 return; 5247 5248 switch (mgmt->u.action.u.addba_resp.action_code) { 5249 case WLAN_ACTION_ADDBA_RESP: 5250 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab); 5251 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout); 5252 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: " 5253 "timeout %i, tid %02x, buf_size %02x, policy %02x, " 5254 "status %02x\n", 5255 timeout, 5256 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2, 5257 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6, 5258 (cap >> 1) & 0x1, 5259 le16_to_cpu(mgmt->u.action.u.addba_resp.status)); 5260 break; 5261 case WLAN_ACTION_ADDBA_REQ: 5262 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab); 5263 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout); 5264 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: " 5265 "timeout %i, tid %02x, buf_size %02x, policy %02x\n", 5266 timeout, 5267 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2, 5268 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6, 5269 (cap >> 1) & 0x1); 5270 break; 5271 default: 5272 dev_info(dev, "action frame %02x\n", 5273 mgmt->u.action.u.addba_resp.action_code); 5274 break; 5275 } 5276 } 5277 5278 /* 5279 * Fill in v1 (gen1) specific TX descriptor bits. 5280 * This format is used on 8188cu/8192cu/8723au 5281 */ 5282 void 5283 rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 5284 struct ieee80211_tx_info *tx_info, 5285 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 5286 bool short_preamble, bool ampdu_enable, u32 rts_rate, 5287 u8 macid) 5288 { 5289 struct rtl8xxxu_priv *priv = hw->priv; 5290 struct device *dev = &priv->udev->dev; 5291 u8 *qc = ieee80211_get_qos_ctl(hdr); 5292 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; 5293 u32 rate = 0; 5294 u16 seq_number; 5295 5296 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) 5297 dev_info(dev, "%s: TX rate: %d, pkt size %u\n", 5298 __func__, rate, le16_to_cpu(tx_desc->pkt_size)); 5299 5300 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 5301 5302 tx_desc->txdw5 = cpu_to_le32(rate); 5303 5304 if (ieee80211_is_data(hdr->frame_control)) 5305 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00); 5306 5307 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT); 5308 5309 if (ampdu_enable && test_bit(tid, priv->tid_tx_operational)) 5310 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE); 5311 else 5312 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK); 5313 5314 if (ieee80211_is_mgmt(hdr->frame_control)) { 5315 tx_desc->txdw5 = cpu_to_le32(rate); 5316 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE); 5317 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT); 5318 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE); 5319 } 5320 5321 if (ieee80211_is_data_qos(hdr->frame_control)) 5322 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS); 5323 5324 if (short_preamble) 5325 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE); 5326 5327 if (sgi) 5328 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI); 5329 5330 /* 5331 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled 5332 */ 5333 tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT); 5334 if (ampdu_enable || tx_info->control.use_rts) { 5335 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE); 5336 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); 5337 } else if (tx_info->control.use_cts_prot) { 5338 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE); 5339 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); 5340 } 5341 } 5342 5343 /* 5344 * Fill in v2 (gen2) specific TX descriptor bits. 5345 * This format is used on 8192eu/8723bu 5346 */ 5347 void 5348 rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 5349 struct ieee80211_tx_info *tx_info, 5350 struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi, 5351 bool short_preamble, bool ampdu_enable, u32 rts_rate, 5352 u8 macid) 5353 { 5354 struct rtl8xxxu_priv *priv = hw->priv; 5355 struct device *dev = &priv->udev->dev; 5356 struct rtl8xxxu_txdesc40 *tx_desc40; 5357 u8 *qc = ieee80211_get_qos_ctl(hdr); 5358 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; 5359 u32 rate = 0; 5360 u16 seq_number; 5361 5362 tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc32; 5363 5364 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) 5365 dev_info(dev, "%s: TX rate: %d, pkt size %u\n", 5366 __func__, rate, le16_to_cpu(tx_desc40->pkt_size)); 5367 5368 tx_desc40->txdw1 |= cpu_to_le32(macid << TXDESC40_MACID_SHIFT); 5369 5370 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 5371 5372 tx_desc40->txdw4 = cpu_to_le32(rate); 5373 if (ieee80211_is_data(hdr->frame_control)) { 5374 tx_desc40->txdw4 |= cpu_to_le32(0x1f << 5375 TXDESC40_DATA_RATE_FB_SHIFT); 5376 } 5377 5378 tx_desc40->txdw9 = cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT); 5379 5380 if (ampdu_enable && test_bit(tid, priv->tid_tx_operational)) 5381 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE); 5382 else 5383 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK); 5384 5385 if (ieee80211_is_mgmt(hdr->frame_control)) { 5386 tx_desc40->txdw4 = cpu_to_le32(rate); 5387 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_USE_DRIVER_RATE); 5388 tx_desc40->txdw4 |= 5389 cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT); 5390 tx_desc40->txdw4 |= cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE); 5391 } 5392 5393 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) 5394 tx_desc40->txdw8 |= cpu_to_le32(TXDESC40_HW_SEQ_ENABLE); 5395 5396 if (short_preamble) 5397 tx_desc40->txdw5 |= cpu_to_le32(TXDESC40_SHORT_PREAMBLE); 5398 5399 tx_desc40->txdw4 |= cpu_to_le32(rts_rate << TXDESC40_RTS_RATE_SHIFT); 5400 5401 /* 5402 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled 5403 */ 5404 if (ampdu_enable || tx_info->control.use_rts) { 5405 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE); 5406 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE); 5407 } else if (tx_info->control.use_cts_prot) { 5408 /* 5409 * For some reason the vendor driver doesn't set 5410 * TXDESC40_HW_RTS_ENABLE for CTS to SELF 5411 */ 5412 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_CTS_SELF_ENABLE); 5413 } 5414 } 5415 5416 /* 5417 * Fill in v3 (gen1) specific TX descriptor bits. 5418 * This format is a hybrid between the v1 and v2 formats, only seen 5419 * on 8188eu devices so far. 5420 */ 5421 void 5422 rtl8xxxu_fill_txdesc_v3(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 5423 struct ieee80211_tx_info *tx_info, 5424 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 5425 bool short_preamble, bool ampdu_enable, u32 rts_rate, 5426 u8 macid) 5427 { 5428 struct rtl8xxxu_priv *priv = hw->priv; 5429 struct device *dev = &priv->udev->dev; 5430 struct rtl8xxxu_ra_info *ra = &priv->ra_info; 5431 u8 *qc = ieee80211_get_qos_ctl(hdr); 5432 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; 5433 u32 rate = 0; 5434 u16 seq_number; 5435 5436 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 5437 5438 if (ieee80211_is_data(hdr->frame_control)) { 5439 rate = ra->decision_rate; 5440 tx_desc->txdw5 = cpu_to_le32(rate); 5441 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE); 5442 tx_desc->txdw4 |= le32_encode_bits(ra->pt_stage, TXDESC32_PT_STAGE_MASK); 5443 /* Data/RTS rate FB limit */ 5444 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00); 5445 } 5446 5447 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) 5448 dev_info(dev, "%s: TX rate: %d, pkt size %d\n", 5449 __func__, rate, le16_to_cpu(tx_desc->pkt_size)); 5450 5451 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT); 5452 5453 if (ampdu_enable && test_bit(tid, priv->tid_tx_operational)) 5454 tx_desc->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE); 5455 else 5456 tx_desc->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK); 5457 5458 if (ieee80211_is_mgmt(hdr->frame_control)) { 5459 tx_desc->txdw5 = cpu_to_le32(rate); 5460 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE); 5461 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT); 5462 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE); 5463 } 5464 5465 if (ieee80211_is_data_qos(hdr->frame_control)) { 5466 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS); 5467 5468 if (conf_is_ht40(&hw->conf)) { 5469 tx_desc->txdw4 |= cpu_to_le32(TXDESC_DATA_BW); 5470 5471 if (conf_is_ht40_minus(&hw->conf)) 5472 tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_UPPER); 5473 else 5474 tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_LOWER); 5475 } 5476 } 5477 5478 if (short_preamble) 5479 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE); 5480 5481 if (sgi && ra->rate_sgi) 5482 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI); 5483 5484 /* 5485 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled 5486 */ 5487 tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT); 5488 if (ampdu_enable || tx_info->control.use_rts) { 5489 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE); 5490 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); 5491 } else if (tx_info->control.use_cts_prot) { 5492 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE); 5493 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); 5494 } 5495 5496 tx_desc->txdw2 |= cpu_to_le32(TXDESC_ANTENNA_SELECT_A | 5497 TXDESC_ANTENNA_SELECT_B); 5498 tx_desc->txdw7 |= cpu_to_le16(TXDESC_ANTENNA_SELECT_C >> 16); 5499 } 5500 5501 static void rtl8xxxu_tx(struct ieee80211_hw *hw, 5502 struct ieee80211_tx_control *control, 5503 struct sk_buff *skb) 5504 { 5505 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 5506 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 5507 struct rtl8xxxu_priv *priv = hw->priv; 5508 struct rtl8xxxu_txdesc32 *tx_desc; 5509 struct rtl8xxxu_tx_urb *tx_urb; 5510 struct ieee80211_sta *sta = NULL; 5511 struct ieee80211_vif *vif = tx_info->control.vif; 5512 struct device *dev = &priv->udev->dev; 5513 u32 queue, rts_rate; 5514 u16 pktlen = skb->len; 5515 int tx_desc_size = priv->fops->tx_desc_size; 5516 u8 macid; 5517 int ret; 5518 bool ampdu_enable, sgi = false, short_preamble = false; 5519 5520 if (skb_headroom(skb) < tx_desc_size) { 5521 dev_warn(dev, 5522 "%s: Not enough headroom (%i) for tx descriptor\n", 5523 __func__, skb_headroom(skb)); 5524 goto error; 5525 } 5526 5527 if (unlikely(skb->len > (65535 - tx_desc_size))) { 5528 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n", 5529 __func__, skb->len); 5530 goto error; 5531 } 5532 5533 tx_urb = rtl8xxxu_alloc_tx_urb(priv); 5534 if (!tx_urb) { 5535 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__); 5536 goto error; 5537 } 5538 5539 if (ieee80211_is_action(hdr->frame_control)) 5540 rtl8xxxu_dump_action(dev, hdr); 5541 5542 tx_info->rate_driver_data[0] = hw; 5543 5544 if (control && control->sta) 5545 sta = control->sta; 5546 5547 queue = rtl8xxxu_queue_select(hdr, skb); 5548 5549 tx_desc = skb_push(skb, tx_desc_size); 5550 5551 memset(tx_desc, 0, tx_desc_size); 5552 tx_desc->pkt_size = cpu_to_le16(pktlen); 5553 tx_desc->pkt_offset = tx_desc_size; 5554 5555 /* These bits mean different things to the RTL8192F. */ 5556 if (priv->rtl_chip != RTL8192F) 5557 tx_desc->txdw0 = 5558 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT; 5559 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) || 5560 is_broadcast_ether_addr(ieee80211_get_DA(hdr))) 5561 tx_desc->txdw0 |= TXDESC_BROADMULTICAST; 5562 5563 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT); 5564 5565 if (tx_info->control.hw_key) { 5566 switch (tx_info->control.hw_key->cipher) { 5567 case WLAN_CIPHER_SUITE_WEP40: 5568 case WLAN_CIPHER_SUITE_WEP104: 5569 case WLAN_CIPHER_SUITE_TKIP: 5570 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4); 5571 break; 5572 case WLAN_CIPHER_SUITE_CCMP: 5573 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES); 5574 break; 5575 default: 5576 break; 5577 } 5578 } 5579 5580 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */ 5581 ampdu_enable = false; 5582 if (ieee80211_is_data_qos(hdr->frame_control) && sta) { 5583 if (sta->deflink.ht_cap.ht_supported) { 5584 u32 ampdu, val32; 5585 u8 *qc = ieee80211_get_qos_ctl(hdr); 5586 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; 5587 5588 ampdu = (u32)sta->deflink.ht_cap.ampdu_density; 5589 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT; 5590 tx_desc->txdw2 |= cpu_to_le32(val32); 5591 5592 ampdu_enable = true; 5593 5594 if (!test_bit(tid, priv->tx_aggr_started) && 5595 !(skb->protocol == cpu_to_be16(ETH_P_PAE))) 5596 if (!ieee80211_start_tx_ba_session(sta, tid, 0)) 5597 set_bit(tid, priv->tx_aggr_started); 5598 } 5599 } 5600 5601 if (ieee80211_is_data_qos(hdr->frame_control) && 5602 sta && sta->deflink.ht_cap.cap & 5603 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)) 5604 sgi = true; 5605 5606 if (sta && vif && vif->bss_conf.use_short_preamble) 5607 short_preamble = true; 5608 5609 if (skb->len > hw->wiphy->rts_threshold) 5610 tx_info->control.use_rts = true; 5611 5612 if (sta && vif && vif->bss_conf.use_cts_prot) 5613 tx_info->control.use_cts_prot = true; 5614 5615 if (ampdu_enable || tx_info->control.use_rts || 5616 tx_info->control.use_cts_prot) 5617 rts_rate = DESC_RATE_24M; 5618 else 5619 rts_rate = 0; 5620 5621 macid = rtl8xxxu_get_macid(priv, sta); 5622 priv->fops->fill_txdesc(hw, hdr, tx_info, tx_desc, sgi, short_preamble, 5623 ampdu_enable, rts_rate, macid); 5624 5625 rtl8xxxu_calc_tx_desc_csum(tx_desc); 5626 5627 /* avoid zero checksum make tx hang */ 5628 if (priv->rtl_chip == RTL8710B || priv->rtl_chip == RTL8192F) 5629 tx_desc->csum = ~tx_desc->csum; 5630 5631 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue], 5632 skb->data, skb->len, rtl8xxxu_tx_complete, skb); 5633 5634 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor); 5635 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC); 5636 if (ret) { 5637 usb_unanchor_urb(&tx_urb->urb); 5638 rtl8xxxu_free_tx_urb(priv, tx_urb); 5639 goto error; 5640 } 5641 return; 5642 error: 5643 dev_kfree_skb(skb); 5644 } 5645 5646 static void rtl8xxxu_send_beacon_frame(struct ieee80211_hw *hw, 5647 struct ieee80211_vif *vif) 5648 { 5649 struct rtl8xxxu_priv *priv = hw->priv; 5650 struct sk_buff *skb = ieee80211_beacon_get(hw, vif, 0); 5651 struct device *dev = &priv->udev->dev; 5652 int retry; 5653 u8 val8; 5654 5655 /* BCN_VALID, write 1 to clear, cleared by SW */ 5656 val8 = rtl8xxxu_read8(priv, REG_TDECTRL + 2); 5657 val8 |= BIT_BCN_VALID >> 16; 5658 rtl8xxxu_write8(priv, REG_TDECTRL + 2, val8); 5659 5660 /* SW_BCN_SEL - Port0 */ 5661 val8 = rtl8xxxu_read8(priv, REG_DWBCN1_CTRL_8723B + 2); 5662 val8 &= ~(BIT_SW_BCN_SEL >> 16); 5663 rtl8xxxu_write8(priv, REG_DWBCN1_CTRL_8723B + 2, val8); 5664 5665 if (skb) 5666 rtl8xxxu_tx(hw, NULL, skb); 5667 5668 retry = 100; 5669 do { 5670 val8 = rtl8xxxu_read8(priv, REG_TDECTRL + 2); 5671 if (val8 & (BIT_BCN_VALID >> 16)) 5672 break; 5673 usleep_range(10, 20); 5674 } while (--retry); 5675 5676 if (!retry) 5677 dev_err(dev, "%s: Failed to read beacon valid bit\n", __func__); 5678 } 5679 5680 static void rtl8xxxu_update_beacon_work_callback(struct work_struct *work) 5681 { 5682 struct rtl8xxxu_priv *priv = 5683 container_of(work, struct rtl8xxxu_priv, update_beacon_work); 5684 struct ieee80211_hw *hw = priv->hw; 5685 struct ieee80211_vif *vif = priv->vif; 5686 5687 if (!vif) { 5688 WARN_ONCE(true, "no vif to update beacon\n"); 5689 return; 5690 } 5691 5692 rtl8xxxu_send_beacon_frame(hw, vif); 5693 } 5694 5695 void rtl8723au_rx_parse_phystats(struct rtl8xxxu_priv *priv, 5696 struct ieee80211_rx_status *rx_status, 5697 struct rtl8723au_phy_stats *phy_stats, 5698 u32 rxmcs, struct ieee80211_hdr *hdr, 5699 bool crc_icv_err) 5700 { 5701 if (phy_stats->sgi_en) 5702 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 5703 5704 if (rxmcs < DESC_RATE_6M) { 5705 /* 5706 * Handle PHY stats for CCK rates 5707 */ 5708 rx_status->signal = priv->fops->cck_rssi(priv, phy_stats); 5709 } else { 5710 bool parse_cfo = priv->fops->set_crystal_cap && 5711 priv->vif && 5712 priv->vif->type == NL80211_IFTYPE_STATION && 5713 priv->vif->cfg.assoc && 5714 !crc_icv_err && 5715 !ieee80211_is_ctl(hdr->frame_control) && 5716 ether_addr_equal(priv->vif->bss_conf.bssid, hdr->addr2); 5717 5718 if (parse_cfo) { 5719 priv->cfo_tracking.cfo_tail[0] = phy_stats->path_cfotail[0]; 5720 priv->cfo_tracking.cfo_tail[1] = phy_stats->path_cfotail[1]; 5721 5722 priv->cfo_tracking.packet_count++; 5723 } 5724 5725 rx_status->signal = 5726 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110; 5727 } 5728 } 5729 5730 static void jaguar2_rx_parse_phystats_type0(struct rtl8xxxu_priv *priv, 5731 struct ieee80211_rx_status *rx_status, 5732 struct jaguar2_phy_stats_type0 *phy_stats0, 5733 u32 rxmcs, struct ieee80211_hdr *hdr, 5734 bool crc_icv_err) 5735 { 5736 s8 rx_power = phy_stats0->pwdb - 110; 5737 5738 if (!priv->cck_new_agc) 5739 rx_power = priv->fops->cck_rssi(priv, (struct rtl8723au_phy_stats *)phy_stats0); 5740 5741 rx_status->signal = rx_power; 5742 } 5743 5744 static void jaguar2_rx_parse_phystats_type1(struct rtl8xxxu_priv *priv, 5745 struct ieee80211_rx_status *rx_status, 5746 struct jaguar2_phy_stats_type1 *phy_stats1, 5747 u32 rxmcs, struct ieee80211_hdr *hdr, 5748 bool crc_icv_err) 5749 { 5750 bool parse_cfo = priv->fops->set_crystal_cap && 5751 priv->vif && 5752 priv->vif->type == NL80211_IFTYPE_STATION && 5753 priv->vif->cfg.assoc && 5754 !crc_icv_err && 5755 !ieee80211_is_ctl(hdr->frame_control) && 5756 ether_addr_equal(priv->vif->bss_conf.bssid, hdr->addr2); 5757 u8 pwdb_max = 0; 5758 int rx_path; 5759 5760 if (parse_cfo) { 5761 /* Only path-A and path-B have CFO tail and short CFO */ 5762 priv->cfo_tracking.cfo_tail[RF_A] = phy_stats1->cfo_tail[RF_A]; 5763 priv->cfo_tracking.cfo_tail[RF_B] = phy_stats1->cfo_tail[RF_B]; 5764 5765 priv->cfo_tracking.packet_count++; 5766 } 5767 5768 for (rx_path = 0; rx_path < priv->rx_paths; rx_path++) 5769 pwdb_max = max(pwdb_max, phy_stats1->pwdb[rx_path]); 5770 5771 rx_status->signal = pwdb_max - 110; 5772 } 5773 5774 static void jaguar2_rx_parse_phystats_type2(struct rtl8xxxu_priv *priv, 5775 struct ieee80211_rx_status *rx_status, 5776 struct jaguar2_phy_stats_type2 *phy_stats2, 5777 u32 rxmcs, struct ieee80211_hdr *hdr, 5778 bool crc_icv_err) 5779 { 5780 u8 pwdb_max = 0; 5781 int rx_path; 5782 5783 for (rx_path = 0; rx_path < priv->rx_paths; rx_path++) 5784 pwdb_max = max(pwdb_max, phy_stats2->pwdb[rx_path]); 5785 5786 rx_status->signal = pwdb_max - 110; 5787 } 5788 5789 void jaguar2_rx_parse_phystats(struct rtl8xxxu_priv *priv, 5790 struct ieee80211_rx_status *rx_status, 5791 struct rtl8723au_phy_stats *phy_stats, 5792 u32 rxmcs, struct ieee80211_hdr *hdr, 5793 bool crc_icv_err) 5794 { 5795 struct jaguar2_phy_stats_type0 *phy_stats0 = (struct jaguar2_phy_stats_type0 *)phy_stats; 5796 struct jaguar2_phy_stats_type1 *phy_stats1 = (struct jaguar2_phy_stats_type1 *)phy_stats; 5797 struct jaguar2_phy_stats_type2 *phy_stats2 = (struct jaguar2_phy_stats_type2 *)phy_stats; 5798 5799 switch (phy_stats0->page_num) { 5800 case 0: 5801 /* CCK */ 5802 jaguar2_rx_parse_phystats_type0(priv, rx_status, phy_stats0, 5803 rxmcs, hdr, crc_icv_err); 5804 break; 5805 case 1: 5806 /* OFDM */ 5807 jaguar2_rx_parse_phystats_type1(priv, rx_status, phy_stats1, 5808 rxmcs, hdr, crc_icv_err); 5809 break; 5810 case 2: 5811 /* Also OFDM but different (how?) */ 5812 jaguar2_rx_parse_phystats_type2(priv, rx_status, phy_stats2, 5813 rxmcs, hdr, crc_icv_err); 5814 break; 5815 default: 5816 return; 5817 } 5818 } 5819 5820 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv) 5821 { 5822 struct rtl8xxxu_rx_urb *rx_urb, *tmp; 5823 unsigned long flags; 5824 5825 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5826 5827 list_for_each_entry_safe(rx_urb, tmp, 5828 &priv->rx_urb_pending_list, list) { 5829 list_del(&rx_urb->list); 5830 priv->rx_urb_pending_count--; 5831 usb_free_urb(&rx_urb->urb); 5832 } 5833 5834 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5835 } 5836 5837 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv, 5838 struct rtl8xxxu_rx_urb *rx_urb) 5839 { 5840 struct sk_buff *skb; 5841 unsigned long flags; 5842 int pending = 0; 5843 5844 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5845 5846 if (!priv->shutdown) { 5847 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list); 5848 priv->rx_urb_pending_count++; 5849 pending = priv->rx_urb_pending_count; 5850 } else { 5851 skb = (struct sk_buff *)rx_urb->urb.context; 5852 dev_kfree_skb_irq(skb); 5853 usb_free_urb(&rx_urb->urb); 5854 } 5855 5856 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5857 5858 if (pending > RTL8XXXU_RX_URB_PENDING_WATER) 5859 schedule_work(&priv->rx_urb_wq); 5860 } 5861 5862 static void rtl8xxxu_rx_urb_work(struct work_struct *work) 5863 { 5864 struct rtl8xxxu_priv *priv; 5865 struct rtl8xxxu_rx_urb *rx_urb, *tmp; 5866 struct list_head local; 5867 struct sk_buff *skb; 5868 unsigned long flags; 5869 int ret; 5870 5871 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq); 5872 INIT_LIST_HEAD(&local); 5873 5874 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5875 5876 list_splice_init(&priv->rx_urb_pending_list, &local); 5877 priv->rx_urb_pending_count = 0; 5878 5879 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5880 5881 list_for_each_entry_safe(rx_urb, tmp, &local, list) { 5882 list_del_init(&rx_urb->list); 5883 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb); 5884 /* 5885 * If out of memory or temporary error, put it back on the 5886 * queue and try again. Otherwise the device is dead/gone 5887 * and we should drop it. 5888 */ 5889 switch (ret) { 5890 case 0: 5891 break; 5892 case -ENOMEM: 5893 case -EAGAIN: 5894 rtl8xxxu_queue_rx_urb(priv, rx_urb); 5895 break; 5896 default: 5897 dev_warn(&priv->udev->dev, 5898 "failed to requeue urb with error %i\n", ret); 5899 skb = (struct sk_buff *)rx_urb->urb.context; 5900 dev_kfree_skb(skb); 5901 usb_free_urb(&rx_urb->urb); 5902 } 5903 } 5904 } 5905 5906 /* 5907 * The RTL8723BU/RTL8192EU vendor driver use coexistence table type 5908 * 0-7 to represent writing different combinations of register values 5909 * to REG_BT_COEX_TABLEs. It's for different kinds of coexistence use 5910 * cases which Realtek doesn't provide detail for these settings. Keep 5911 * this aligned with vendor driver for easier maintenance. 5912 */ 5913 static 5914 void rtl8723bu_set_coex_with_type(struct rtl8xxxu_priv *priv, u8 type) 5915 { 5916 switch (type) { 5917 case 0: 5918 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); 5919 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555); 5920 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5921 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5922 break; 5923 case 1: 5924 case 3: 5925 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); 5926 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a); 5927 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5928 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5929 break; 5930 case 2: 5931 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a); 5932 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a); 5933 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5934 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5935 break; 5936 case 4: 5937 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a); 5938 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaa5a5a); 5939 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5940 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5941 break; 5942 case 5: 5943 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a); 5944 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaa5a5a5a); 5945 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5946 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5947 break; 5948 case 6: 5949 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); 5950 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa); 5951 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5952 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5953 break; 5954 case 7: 5955 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0xaaaaaaaa); 5956 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa); 5957 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5958 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5959 break; 5960 default: 5961 break; 5962 } 5963 } 5964 5965 static 5966 void rtl8723bu_update_bt_link_info(struct rtl8xxxu_priv *priv, u8 bt_info) 5967 { 5968 struct rtl8xxxu_btcoex *btcoex = &priv->bt_coex; 5969 5970 if (bt_info & BT_INFO_8723B_1ANT_B_INQ_PAGE) 5971 btcoex->c2h_bt_inquiry = true; 5972 else 5973 btcoex->c2h_bt_inquiry = false; 5974 5975 if (!(bt_info & BT_INFO_8723B_1ANT_B_CONNECTION)) { 5976 btcoex->bt_status = BT_8723B_1ANT_STATUS_NON_CONNECTED_IDLE; 5977 btcoex->has_sco = false; 5978 btcoex->has_hid = false; 5979 btcoex->has_pan = false; 5980 btcoex->has_a2dp = false; 5981 } else { 5982 if ((bt_info & 0x1f) == BT_INFO_8723B_1ANT_B_CONNECTION) 5983 btcoex->bt_status = BT_8723B_1ANT_STATUS_CONNECTED_IDLE; 5984 else if ((bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) || 5985 (bt_info & BT_INFO_8723B_1ANT_B_SCO_BUSY)) 5986 btcoex->bt_status = BT_8723B_1ANT_STATUS_SCO_BUSY; 5987 else if (bt_info & BT_INFO_8723B_1ANT_B_ACL_BUSY) 5988 btcoex->bt_status = BT_8723B_1ANT_STATUS_ACL_BUSY; 5989 else 5990 btcoex->bt_status = BT_8723B_1ANT_STATUS_MAX; 5991 5992 if (bt_info & BT_INFO_8723B_1ANT_B_FTP) 5993 btcoex->has_pan = true; 5994 else 5995 btcoex->has_pan = false; 5996 5997 if (bt_info & BT_INFO_8723B_1ANT_B_A2DP) 5998 btcoex->has_a2dp = true; 5999 else 6000 btcoex->has_a2dp = false; 6001 6002 if (bt_info & BT_INFO_8723B_1ANT_B_HID) 6003 btcoex->has_hid = true; 6004 else 6005 btcoex->has_hid = false; 6006 6007 if (bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) 6008 btcoex->has_sco = true; 6009 else 6010 btcoex->has_sco = false; 6011 } 6012 6013 if (!btcoex->has_a2dp && !btcoex->has_sco && 6014 !btcoex->has_pan && btcoex->has_hid) 6015 btcoex->hid_only = true; 6016 else 6017 btcoex->hid_only = false; 6018 6019 if (!btcoex->has_sco && !btcoex->has_pan && 6020 !btcoex->has_hid && btcoex->has_a2dp) 6021 btcoex->has_a2dp = true; 6022 else 6023 btcoex->has_a2dp = false; 6024 6025 if (btcoex->bt_status == BT_8723B_1ANT_STATUS_SCO_BUSY || 6026 btcoex->bt_status == BT_8723B_1ANT_STATUS_ACL_BUSY) 6027 btcoex->bt_busy = true; 6028 else 6029 btcoex->bt_busy = false; 6030 } 6031 6032 static 6033 void rtl8723bu_handle_bt_inquiry(struct rtl8xxxu_priv *priv) 6034 { 6035 struct ieee80211_vif *vif; 6036 struct rtl8xxxu_btcoex *btcoex; 6037 bool wifi_connected; 6038 6039 vif = priv->vif; 6040 btcoex = &priv->bt_coex; 6041 wifi_connected = (vif && vif->cfg.assoc); 6042 6043 if (!wifi_connected) { 6044 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); 6045 rtl8723bu_set_coex_with_type(priv, 0); 6046 } else if (btcoex->has_sco || btcoex->has_hid || btcoex->has_a2dp) { 6047 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, 0x3, 0x11, 0x11); 6048 rtl8723bu_set_coex_with_type(priv, 4); 6049 } else if (btcoex->has_pan) { 6050 rtl8723bu_set_ps_tdma(priv, 0x61, 0x3f, 0x3, 0x11, 0x11); 6051 rtl8723bu_set_coex_with_type(priv, 4); 6052 } else { 6053 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); 6054 rtl8723bu_set_coex_with_type(priv, 7); 6055 } 6056 } 6057 6058 static 6059 void rtl8723bu_handle_bt_info(struct rtl8xxxu_priv *priv) 6060 { 6061 struct ieee80211_vif *vif; 6062 struct rtl8xxxu_btcoex *btcoex; 6063 bool wifi_connected; 6064 6065 vif = priv->vif; 6066 btcoex = &priv->bt_coex; 6067 wifi_connected = (vif && vif->cfg.assoc); 6068 6069 if (wifi_connected) { 6070 u32 val32 = 0; 6071 u32 high_prio_tx = 0, high_prio_rx = 0; 6072 6073 val32 = rtl8xxxu_read32(priv, 0x770); 6074 high_prio_tx = val32 & 0x0000ffff; 6075 high_prio_rx = (val32 & 0xffff0000) >> 16; 6076 6077 if (btcoex->bt_busy) { 6078 if (btcoex->hid_only) { 6079 rtl8723bu_set_ps_tdma(priv, 0x61, 0x20, 6080 0x3, 0x11, 0x11); 6081 rtl8723bu_set_coex_with_type(priv, 5); 6082 } else if (btcoex->a2dp_only) { 6083 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, 6084 0x3, 0x11, 0x11); 6085 rtl8723bu_set_coex_with_type(priv, 4); 6086 } else if ((btcoex->has_a2dp && btcoex->has_pan) || 6087 (btcoex->has_hid && btcoex->has_a2dp && 6088 btcoex->has_pan)) { 6089 rtl8723bu_set_ps_tdma(priv, 0x51, 0x21, 6090 0x3, 0x10, 0x10); 6091 rtl8723bu_set_coex_with_type(priv, 4); 6092 } else if (btcoex->has_hid && btcoex->has_a2dp) { 6093 rtl8723bu_set_ps_tdma(priv, 0x51, 0x21, 6094 0x3, 0x10, 0x10); 6095 rtl8723bu_set_coex_with_type(priv, 3); 6096 } else { 6097 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, 6098 0x3, 0x11, 0x11); 6099 rtl8723bu_set_coex_with_type(priv, 4); 6100 } 6101 } else { 6102 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); 6103 if (high_prio_tx + high_prio_rx <= 60) 6104 rtl8723bu_set_coex_with_type(priv, 2); 6105 else 6106 rtl8723bu_set_coex_with_type(priv, 7); 6107 } 6108 } else { 6109 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); 6110 rtl8723bu_set_coex_with_type(priv, 0); 6111 } 6112 } 6113 6114 static void rtl8xxxu_c2hcmd_callback(struct work_struct *work) 6115 { 6116 struct rtl8xxxu_priv *priv; 6117 struct rtl8723bu_c2h *c2h; 6118 struct sk_buff *skb = NULL; 6119 u8 bt_info = 0; 6120 struct rtl8xxxu_btcoex *btcoex; 6121 struct rtl8xxxu_ra_report *rarpt; 6122 u8 bw; 6123 6124 priv = container_of(work, struct rtl8xxxu_priv, c2hcmd_work); 6125 btcoex = &priv->bt_coex; 6126 rarpt = &priv->ra_report; 6127 6128 while (!skb_queue_empty(&priv->c2hcmd_queue)) { 6129 skb = skb_dequeue(&priv->c2hcmd_queue); 6130 6131 c2h = (struct rtl8723bu_c2h *)skb->data; 6132 6133 switch (c2h->id) { 6134 case C2H_8723B_BT_INFO: 6135 bt_info = c2h->bt_info.bt_info; 6136 6137 rtl8723bu_update_bt_link_info(priv, bt_info); 6138 if (btcoex->c2h_bt_inquiry) { 6139 rtl8723bu_handle_bt_inquiry(priv); 6140 break; 6141 } 6142 rtl8723bu_handle_bt_info(priv); 6143 break; 6144 case C2H_8723B_RA_REPORT: 6145 bw = rarpt->txrate.bw; 6146 6147 if (skb->len >= offsetofend(typeof(*c2h), ra_report.bw)) { 6148 if (c2h->ra_report.bw == RTL8XXXU_CHANNEL_WIDTH_40) 6149 bw = RATE_INFO_BW_40; 6150 else 6151 bw = RATE_INFO_BW_20; 6152 } 6153 6154 rtl8xxxu_update_ra_report(rarpt, c2h->ra_report.rate, 6155 c2h->ra_report.sgi, bw); 6156 break; 6157 default: 6158 break; 6159 } 6160 6161 dev_kfree_skb(skb); 6162 } 6163 } 6164 6165 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv, 6166 struct sk_buff *skb) 6167 { 6168 struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data; 6169 struct device *dev = &priv->udev->dev; 6170 int len; 6171 6172 len = skb->len - 2; 6173 6174 dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n", 6175 c2h->id, c2h->seq, len, c2h->bt_info.response_source); 6176 6177 switch(c2h->id) { 6178 case C2H_8723B_BT_INFO: 6179 if (c2h->bt_info.response_source > 6180 BT_INFO_SRC_8723B_BT_ACTIVE_SEND) 6181 dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n"); 6182 else 6183 dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n"); 6184 6185 if (c2h->bt_info.bt_has_reset) 6186 dev_dbg(dev, "BT has been reset\n"); 6187 if (c2h->bt_info.tx_rx_mask) 6188 dev_dbg(dev, "BT TRx mask\n"); 6189 6190 break; 6191 case C2H_8723B_BT_MP_INFO: 6192 dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n", 6193 c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status); 6194 break; 6195 case C2H_8723B_RA_REPORT: 6196 dev_dbg(dev, 6197 "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n", 6198 c2h->ra_report.rate, c2h->ra_report.sgi, 6199 c2h->ra_report.macid, c2h->ra_report.noisy_state); 6200 break; 6201 default: 6202 dev_info(dev, "Unhandled C2H event %02x seq %02x\n", 6203 c2h->id, c2h->seq); 6204 print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE, 6205 16, 1, c2h->raw.payload, len, false); 6206 break; 6207 } 6208 6209 skb_queue_tail(&priv->c2hcmd_queue, skb); 6210 6211 schedule_work(&priv->c2hcmd_work); 6212 } 6213 6214 static void rtl8188e_c2hcmd_callback(struct work_struct *work) 6215 { 6216 struct rtl8xxxu_priv *priv = container_of(work, struct rtl8xxxu_priv, c2hcmd_work); 6217 struct device *dev = &priv->udev->dev; 6218 struct sk_buff *skb = NULL; 6219 struct rtl8xxxu_rxdesc16 *rx_desc; 6220 6221 while (!skb_queue_empty(&priv->c2hcmd_queue)) { 6222 skb = skb_dequeue(&priv->c2hcmd_queue); 6223 6224 rx_desc = (struct rtl8xxxu_rxdesc16 *)(skb->data - sizeof(struct rtl8xxxu_rxdesc16)); 6225 6226 switch (rx_desc->rpt_sel) { 6227 case 1: 6228 dev_dbg(dev, "C2H TX report type 1\n"); 6229 6230 break; 6231 case 2: 6232 dev_dbg(dev, "C2H TX report type 2\n"); 6233 6234 rtl8188e_handle_ra_tx_report2(priv, skb); 6235 6236 break; 6237 case 3: 6238 dev_dbg(dev, "C2H USB interrupt report\n"); 6239 6240 break; 6241 default: 6242 dev_warn(dev, "%s: rpt_sel should not be %d\n", 6243 __func__, rx_desc->rpt_sel); 6244 6245 break; 6246 } 6247 6248 dev_kfree_skb(skb); 6249 } 6250 } 6251 6252 int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb) 6253 { 6254 struct ieee80211_hw *hw = priv->hw; 6255 struct ieee80211_rx_status *rx_status; 6256 struct rtl8xxxu_rxdesc16 *rx_desc; 6257 struct rtl8723au_phy_stats *phy_stats; 6258 struct sk_buff *next_skb = NULL; 6259 __le32 *_rx_desc_le; 6260 u32 *_rx_desc; 6261 int drvinfo_sz, desc_shift; 6262 int i, pkt_cnt, pkt_len, urb_len, pkt_offset; 6263 6264 urb_len = skb->len; 6265 pkt_cnt = 0; 6266 6267 if (urb_len < sizeof(struct rtl8xxxu_rxdesc16)) { 6268 kfree_skb(skb); 6269 return RX_TYPE_ERROR; 6270 } 6271 6272 do { 6273 rx_desc = (struct rtl8xxxu_rxdesc16 *)skb->data; 6274 _rx_desc_le = (__le32 *)skb->data; 6275 _rx_desc = (u32 *)skb->data; 6276 6277 for (i = 0; 6278 i < (sizeof(struct rtl8xxxu_rxdesc16) / sizeof(u32)); i++) 6279 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]); 6280 6281 /* 6282 * Only read pkt_cnt from the header if we're parsing the 6283 * first packet 6284 */ 6285 if (!pkt_cnt) 6286 pkt_cnt = rx_desc->pkt_cnt; 6287 pkt_len = rx_desc->pktlen; 6288 6289 drvinfo_sz = rx_desc->drvinfo_sz * 8; 6290 desc_shift = rx_desc->shift; 6291 pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift + 6292 sizeof(struct rtl8xxxu_rxdesc16), 128); 6293 6294 /* 6295 * Only clone the skb if there's enough data at the end to 6296 * at least cover the rx descriptor 6297 */ 6298 if (pkt_cnt > 1 && 6299 urb_len >= (pkt_offset + sizeof(struct rtl8xxxu_rxdesc16))) 6300 next_skb = skb_clone(skb, GFP_ATOMIC); 6301 6302 rx_status = IEEE80211_SKB_RXCB(skb); 6303 memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); 6304 6305 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc16)); 6306 6307 if (rx_desc->rpt_sel) { 6308 skb_queue_tail(&priv->c2hcmd_queue, skb); 6309 schedule_work(&priv->c2hcmd_work); 6310 } else { 6311 phy_stats = (struct rtl8723au_phy_stats *)skb->data; 6312 6313 skb_pull(skb, drvinfo_sz + desc_shift); 6314 6315 skb_trim(skb, pkt_len); 6316 6317 if (rx_desc->phy_stats) 6318 priv->fops->parse_phystats( 6319 priv, rx_status, phy_stats, 6320 rx_desc->rxmcs, 6321 (struct ieee80211_hdr *)skb->data, 6322 rx_desc->crc32 || rx_desc->icverr); 6323 6324 rx_status->mactime = rx_desc->tsfl; 6325 rx_status->flag |= RX_FLAG_MACTIME_START; 6326 6327 if (!rx_desc->swdec) 6328 rx_status->flag |= RX_FLAG_DECRYPTED; 6329 if (rx_desc->crc32) 6330 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 6331 if (rx_desc->bw) 6332 rx_status->bw = RATE_INFO_BW_40; 6333 6334 if (rx_desc->rxht) { 6335 rx_status->encoding = RX_ENC_HT; 6336 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0; 6337 } else { 6338 rx_status->rate_idx = rx_desc->rxmcs; 6339 } 6340 6341 rx_status->freq = hw->conf.chandef.chan->center_freq; 6342 rx_status->band = hw->conf.chandef.chan->band; 6343 6344 ieee80211_rx_irqsafe(hw, skb); 6345 } 6346 6347 skb = next_skb; 6348 if (skb) 6349 skb_pull(next_skb, pkt_offset); 6350 6351 pkt_cnt--; 6352 urb_len -= pkt_offset; 6353 next_skb = NULL; 6354 } while (skb && pkt_cnt > 0 && 6355 urb_len >= sizeof(struct rtl8xxxu_rxdesc16)); 6356 6357 return RX_TYPE_DATA_PKT; 6358 } 6359 6360 int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb) 6361 { 6362 struct ieee80211_hw *hw = priv->hw; 6363 struct ieee80211_rx_status *rx_status; 6364 struct rtl8xxxu_rxdesc24 *rx_desc; 6365 struct rtl8723au_phy_stats *phy_stats; 6366 struct sk_buff *next_skb = NULL; 6367 __le32 *_rx_desc_le; 6368 u32 *_rx_desc; 6369 int drvinfo_sz, desc_shift; 6370 int i, pkt_len, urb_len, pkt_offset; 6371 6372 urb_len = skb->len; 6373 6374 if (urb_len < sizeof(struct rtl8xxxu_rxdesc24)) { 6375 kfree_skb(skb); 6376 return RX_TYPE_ERROR; 6377 } 6378 6379 do { 6380 rx_desc = (struct rtl8xxxu_rxdesc24 *)skb->data; 6381 _rx_desc_le = (__le32 *)skb->data; 6382 _rx_desc = (u32 *)skb->data; 6383 6384 for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++) 6385 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]); 6386 6387 pkt_len = rx_desc->pktlen; 6388 6389 drvinfo_sz = rx_desc->drvinfo_sz * 8; 6390 desc_shift = rx_desc->shift; 6391 pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift + 6392 sizeof(struct rtl8xxxu_rxdesc24), 8); 6393 6394 /* 6395 * Only clone the skb if there's enough data at the end to 6396 * at least cover the rx descriptor 6397 */ 6398 if (urb_len >= (pkt_offset + sizeof(struct rtl8xxxu_rxdesc24))) 6399 next_skb = skb_clone(skb, GFP_ATOMIC); 6400 6401 rx_status = IEEE80211_SKB_RXCB(skb); 6402 memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); 6403 6404 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24)); 6405 6406 phy_stats = (struct rtl8723au_phy_stats *)skb->data; 6407 6408 skb_pull(skb, drvinfo_sz + desc_shift); 6409 6410 skb_trim(skb, pkt_len); 6411 6412 if (rx_desc->rpt_sel) { 6413 struct device *dev = &priv->udev->dev; 6414 dev_dbg(dev, "%s: C2H packet\n", __func__); 6415 rtl8723bu_handle_c2h(priv, skb); 6416 } else { 6417 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 6418 6419 if (rx_desc->phy_stats) 6420 priv->fops->parse_phystats(priv, rx_status, phy_stats, 6421 rx_desc->rxmcs, hdr, 6422 rx_desc->crc32 || rx_desc->icverr); 6423 6424 rx_status->mactime = rx_desc->tsfl; 6425 rx_status->flag |= RX_FLAG_MACTIME_START; 6426 6427 if (!rx_desc->swdec) 6428 rx_status->flag |= RX_FLAG_DECRYPTED; 6429 if (rx_desc->crc32) 6430 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 6431 if (rx_desc->bw) 6432 rx_status->bw = RATE_INFO_BW_40; 6433 6434 if (rx_desc->rxmcs >= DESC_RATE_MCS0) { 6435 rx_status->encoding = RX_ENC_HT; 6436 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0; 6437 } else { 6438 rx_status->rate_idx = rx_desc->rxmcs; 6439 } 6440 6441 rx_status->freq = hw->conf.chandef.chan->center_freq; 6442 rx_status->band = hw->conf.chandef.chan->band; 6443 6444 ieee80211_rx_irqsafe(hw, skb); 6445 } 6446 6447 skb = next_skb; 6448 if (skb) 6449 skb_pull(next_skb, pkt_offset); 6450 6451 urb_len -= pkt_offset; 6452 next_skb = NULL; 6453 } while (skb && urb_len >= sizeof(struct rtl8xxxu_rxdesc24)); 6454 6455 return RX_TYPE_DATA_PKT; 6456 } 6457 6458 static void rtl8xxxu_rx_complete(struct urb *urb) 6459 { 6460 struct rtl8xxxu_rx_urb *rx_urb = 6461 container_of(urb, struct rtl8xxxu_rx_urb, urb); 6462 struct ieee80211_hw *hw = rx_urb->hw; 6463 struct rtl8xxxu_priv *priv = hw->priv; 6464 struct sk_buff *skb = (struct sk_buff *)urb->context; 6465 struct device *dev = &priv->udev->dev; 6466 6467 skb_put(skb, urb->actual_length); 6468 6469 if (urb->status == 0) { 6470 priv->fops->parse_rx_desc(priv, skb); 6471 6472 skb = NULL; 6473 rx_urb->urb.context = NULL; 6474 rtl8xxxu_queue_rx_urb(priv, rx_urb); 6475 } else { 6476 dev_dbg(dev, "%s: status %i\n", __func__, urb->status); 6477 goto cleanup; 6478 } 6479 return; 6480 6481 cleanup: 6482 usb_free_urb(urb); 6483 dev_kfree_skb(skb); 6484 } 6485 6486 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv, 6487 struct rtl8xxxu_rx_urb *rx_urb) 6488 { 6489 struct rtl8xxxu_fileops *fops = priv->fops; 6490 struct sk_buff *skb; 6491 int skb_size; 6492 int ret, rx_desc_sz; 6493 6494 rx_desc_sz = fops->rx_desc_size; 6495 6496 if (priv->rx_buf_aggregation && fops->rx_agg_buf_size) { 6497 skb_size = fops->rx_agg_buf_size; 6498 skb_size += (rx_desc_sz + sizeof(struct rtl8723au_phy_stats)); 6499 } else { 6500 skb_size = IEEE80211_MAX_FRAME_LEN; 6501 } 6502 6503 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL); 6504 if (!skb) 6505 return -ENOMEM; 6506 6507 memset(skb->data, 0, rx_desc_sz); 6508 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data, 6509 skb_size, rtl8xxxu_rx_complete, skb); 6510 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor); 6511 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC); 6512 if (ret) 6513 usb_unanchor_urb(&rx_urb->urb); 6514 return ret; 6515 } 6516 6517 static void rtl8xxxu_int_complete(struct urb *urb) 6518 { 6519 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context; 6520 struct device *dev = &priv->udev->dev; 6521 int ret; 6522 6523 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_INTERRUPT) 6524 dev_dbg(dev, "%s: status %i\n", __func__, urb->status); 6525 if (urb->status == 0) { 6526 usb_anchor_urb(urb, &priv->int_anchor); 6527 ret = usb_submit_urb(urb, GFP_ATOMIC); 6528 if (ret) 6529 usb_unanchor_urb(urb); 6530 } else { 6531 dev_dbg(dev, "%s: Error %i\n", __func__, urb->status); 6532 } 6533 } 6534 6535 6536 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw) 6537 { 6538 struct rtl8xxxu_priv *priv = hw->priv; 6539 struct urb *urb; 6540 u32 val32; 6541 int ret; 6542 6543 urb = usb_alloc_urb(0, GFP_KERNEL); 6544 if (!urb) 6545 return -ENOMEM; 6546 6547 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt, 6548 priv->int_buf, USB_INTR_CONTENT_LENGTH, 6549 rtl8xxxu_int_complete, priv, 1); 6550 usb_anchor_urb(urb, &priv->int_anchor); 6551 ret = usb_submit_urb(urb, GFP_KERNEL); 6552 if (ret) { 6553 usb_unanchor_urb(urb); 6554 goto error; 6555 } 6556 6557 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR); 6558 val32 |= USB_HIMR_CPWM; 6559 rtl8xxxu_write32(priv, REG_USB_HIMR, val32); 6560 6561 error: 6562 usb_free_urb(urb); 6563 return ret; 6564 } 6565 6566 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw, 6567 struct ieee80211_vif *vif) 6568 { 6569 struct rtl8xxxu_priv *priv = hw->priv; 6570 int ret; 6571 u8 val8; 6572 6573 if (!priv->vif) 6574 priv->vif = vif; 6575 else 6576 return -EOPNOTSUPP; 6577 6578 switch (vif->type) { 6579 case NL80211_IFTYPE_STATION: 6580 rtl8xxxu_stop_tx_beacon(priv); 6581 6582 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 6583 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE | 6584 BEACON_DISABLE_TSF_UPDATE; 6585 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 6586 ret = 0; 6587 break; 6588 case NL80211_IFTYPE_AP: 6589 rtl8xxxu_write8(priv, REG_BEACON_CTRL, 6590 BEACON_DISABLE_TSF_UPDATE | BEACON_CTRL_MBSSID); 6591 rtl8xxxu_write8(priv, REG_ATIMWND, 0x0c); /* 12ms */ 6592 rtl8xxxu_write16(priv, REG_TSFTR_SYN_OFFSET, 0x7fff); /* ~32ms */ 6593 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, DUAL_TSF_RESET_TSF0); 6594 6595 /* enable BCN0 function */ 6596 rtl8xxxu_write8(priv, REG_BEACON_CTRL, 6597 BEACON_DISABLE_TSF_UPDATE | 6598 BEACON_FUNCTION_ENABLE | BEACON_CTRL_MBSSID | 6599 BEACON_CTRL_TX_BEACON_RPT); 6600 6601 /* select BCN on port 0 */ 6602 val8 = rtl8xxxu_read8(priv, REG_CCK_CHECK); 6603 val8 &= ~BIT_BCN_PORT_SEL; 6604 rtl8xxxu_write8(priv, REG_CCK_CHECK, val8); 6605 6606 ret = 0; 6607 break; 6608 default: 6609 ret = -EOPNOTSUPP; 6610 } 6611 6612 rtl8xxxu_set_linktype(priv, vif->type); 6613 ether_addr_copy(priv->mac_addr, vif->addr); 6614 rtl8xxxu_set_mac(priv); 6615 6616 return ret; 6617 } 6618 6619 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw, 6620 struct ieee80211_vif *vif) 6621 { 6622 struct rtl8xxxu_priv *priv = hw->priv; 6623 6624 dev_dbg(&priv->udev->dev, "%s\n", __func__); 6625 6626 if (priv->vif) 6627 priv->vif = NULL; 6628 } 6629 6630 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed) 6631 { 6632 struct rtl8xxxu_priv *priv = hw->priv; 6633 struct device *dev = &priv->udev->dev; 6634 int ret = 0, channel; 6635 bool ht40; 6636 6637 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL) 6638 dev_info(dev, 6639 "%s: channel: %i (changed %08x chandef.width %02x)\n", 6640 __func__, hw->conf.chandef.chan->hw_value, 6641 changed, hw->conf.chandef.width); 6642 6643 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { 6644 switch (hw->conf.chandef.width) { 6645 case NL80211_CHAN_WIDTH_20_NOHT: 6646 case NL80211_CHAN_WIDTH_20: 6647 ht40 = false; 6648 break; 6649 case NL80211_CHAN_WIDTH_40: 6650 ht40 = true; 6651 break; 6652 default: 6653 ret = -ENOTSUPP; 6654 goto exit; 6655 } 6656 6657 channel = hw->conf.chandef.chan->hw_value; 6658 6659 priv->fops->set_tx_power(priv, channel, ht40); 6660 6661 priv->fops->config_channel(hw); 6662 } 6663 6664 exit: 6665 return ret; 6666 } 6667 6668 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw, 6669 struct ieee80211_vif *vif, 6670 unsigned int link_id, u16 queue, 6671 const struct ieee80211_tx_queue_params *param) 6672 { 6673 struct rtl8xxxu_priv *priv = hw->priv; 6674 struct device *dev = &priv->udev->dev; 6675 u32 val32; 6676 u8 aifs, acm_ctrl, acm_bit; 6677 6678 aifs = param->aifs; 6679 6680 val32 = aifs | 6681 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT | 6682 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT | 6683 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT; 6684 6685 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL); 6686 dev_dbg(dev, 6687 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n", 6688 __func__, queue, val32, param->acm, acm_ctrl); 6689 6690 switch (queue) { 6691 case IEEE80211_AC_VO: 6692 acm_bit = ACM_HW_CTRL_VO; 6693 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32); 6694 break; 6695 case IEEE80211_AC_VI: 6696 acm_bit = ACM_HW_CTRL_VI; 6697 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32); 6698 break; 6699 case IEEE80211_AC_BE: 6700 acm_bit = ACM_HW_CTRL_BE; 6701 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32); 6702 break; 6703 case IEEE80211_AC_BK: 6704 acm_bit = ACM_HW_CTRL_BK; 6705 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32); 6706 break; 6707 default: 6708 acm_bit = 0; 6709 break; 6710 } 6711 6712 if (param->acm) 6713 acm_ctrl |= acm_bit; 6714 else 6715 acm_ctrl &= ~acm_bit; 6716 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl); 6717 6718 return 0; 6719 } 6720 6721 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw, 6722 unsigned int changed_flags, 6723 unsigned int *total_flags, u64 multicast) 6724 { 6725 struct rtl8xxxu_priv *priv = hw->priv; 6726 u32 rcr = priv->regrcr; 6727 6728 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n", 6729 __func__, changed_flags, *total_flags); 6730 6731 /* 6732 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR) 6733 */ 6734 6735 if (*total_flags & FIF_FCSFAIL) 6736 rcr |= RCR_ACCEPT_CRC32; 6737 else 6738 rcr &= ~RCR_ACCEPT_CRC32; 6739 6740 /* 6741 * FIF_PLCPFAIL not supported? 6742 */ 6743 6744 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) 6745 rcr &= ~(RCR_CHECK_BSSID_BEACON | RCR_CHECK_BSSID_MATCH); 6746 else 6747 rcr |= RCR_CHECK_BSSID_BEACON | RCR_CHECK_BSSID_MATCH; 6748 6749 if (priv->vif && priv->vif->type == NL80211_IFTYPE_AP) 6750 rcr &= ~RCR_CHECK_BSSID_MATCH; 6751 6752 if (*total_flags & FIF_CONTROL) 6753 rcr |= RCR_ACCEPT_CTRL_FRAME; 6754 else 6755 rcr &= ~RCR_ACCEPT_CTRL_FRAME; 6756 6757 if (*total_flags & FIF_OTHER_BSS) 6758 rcr |= RCR_ACCEPT_AP; 6759 else 6760 rcr &= ~RCR_ACCEPT_AP; 6761 6762 if (*total_flags & FIF_PSPOLL) 6763 rcr |= RCR_ACCEPT_PM; 6764 else 6765 rcr &= ~RCR_ACCEPT_PM; 6766 6767 /* 6768 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted 6769 */ 6770 6771 rtl8xxxu_write32(priv, REG_RCR, rcr); 6772 priv->regrcr = rcr; 6773 6774 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC | 6775 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL | 6776 FIF_PROBE_REQ); 6777 } 6778 6779 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts) 6780 { 6781 if (rts > 2347 && rts != (u32)-1) 6782 return -EINVAL; 6783 6784 return 0; 6785 } 6786 6787 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 6788 struct ieee80211_vif *vif, 6789 struct ieee80211_sta *sta, 6790 struct ieee80211_key_conf *key) 6791 { 6792 struct rtl8xxxu_priv *priv = hw->priv; 6793 struct device *dev = &priv->udev->dev; 6794 u8 mac_addr[ETH_ALEN]; 6795 u8 val8; 6796 u16 val16; 6797 u32 val32; 6798 int retval = -EOPNOTSUPP; 6799 6800 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n", 6801 __func__, cmd, key->cipher, key->keyidx); 6802 6803 if (vif->type != NL80211_IFTYPE_STATION) 6804 return -EOPNOTSUPP; 6805 6806 if (key->keyidx > 3) 6807 return -EOPNOTSUPP; 6808 6809 switch (key->cipher) { 6810 case WLAN_CIPHER_SUITE_WEP40: 6811 case WLAN_CIPHER_SUITE_WEP104: 6812 6813 break; 6814 case WLAN_CIPHER_SUITE_CCMP: 6815 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; 6816 break; 6817 case WLAN_CIPHER_SUITE_TKIP: 6818 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 6819 break; 6820 default: 6821 return -EOPNOTSUPP; 6822 } 6823 6824 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { 6825 dev_dbg(dev, "%s: pairwise key\n", __func__); 6826 ether_addr_copy(mac_addr, sta->addr); 6827 } else { 6828 dev_dbg(dev, "%s: group key\n", __func__); 6829 eth_broadcast_addr(mac_addr); 6830 } 6831 6832 val16 = rtl8xxxu_read16(priv, REG_CR); 6833 val16 |= CR_SECURITY_ENABLE; 6834 rtl8xxxu_write16(priv, REG_CR, val16); 6835 6836 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY | 6837 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY; 6838 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY; 6839 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8); 6840 6841 switch (cmd) { 6842 case SET_KEY: 6843 key->hw_key_idx = key->keyidx; 6844 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 6845 rtl8xxxu_cam_write(priv, key, mac_addr); 6846 retval = 0; 6847 break; 6848 case DISABLE_KEY: 6849 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000); 6850 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE | 6851 key->keyidx << CAM_CMD_KEY_SHIFT; 6852 rtl8xxxu_write32(priv, REG_CAM_CMD, val32); 6853 retval = 0; 6854 break; 6855 default: 6856 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd); 6857 } 6858 6859 return retval; 6860 } 6861 6862 static int 6863 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 6864 struct ieee80211_ampdu_params *params) 6865 { 6866 struct rtl8xxxu_priv *priv = hw->priv; 6867 struct device *dev = &priv->udev->dev; 6868 u8 ampdu_factor, ampdu_density; 6869 struct ieee80211_sta *sta = params->sta; 6870 u16 tid = params->tid; 6871 enum ieee80211_ampdu_mlme_action action = params->action; 6872 6873 switch (action) { 6874 case IEEE80211_AMPDU_TX_START: 6875 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__); 6876 ampdu_factor = sta->deflink.ht_cap.ampdu_factor; 6877 ampdu_density = sta->deflink.ht_cap.ampdu_density; 6878 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor); 6879 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density); 6880 dev_dbg(dev, 6881 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n", 6882 ampdu_factor, ampdu_density); 6883 return IEEE80211_AMPDU_TX_START_IMMEDIATE; 6884 case IEEE80211_AMPDU_TX_STOP_CONT: 6885 case IEEE80211_AMPDU_TX_STOP_FLUSH: 6886 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 6887 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP\n", __func__); 6888 rtl8xxxu_set_ampdu_factor(priv, 0); 6889 rtl8xxxu_set_ampdu_min_space(priv, 0); 6890 clear_bit(tid, priv->tx_aggr_started); 6891 clear_bit(tid, priv->tid_tx_operational); 6892 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 6893 break; 6894 case IEEE80211_AMPDU_TX_OPERATIONAL: 6895 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_OPERATIONAL\n", __func__); 6896 set_bit(tid, priv->tid_tx_operational); 6897 break; 6898 case IEEE80211_AMPDU_RX_START: 6899 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__); 6900 break; 6901 case IEEE80211_AMPDU_RX_STOP: 6902 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__); 6903 break; 6904 default: 6905 break; 6906 } 6907 return 0; 6908 } 6909 6910 static void 6911 rtl8xxxu_sta_statistics(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 6912 struct ieee80211_sta *sta, struct station_info *sinfo) 6913 { 6914 struct rtl8xxxu_priv *priv = hw->priv; 6915 6916 sinfo->txrate = priv->ra_report.txrate; 6917 sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE); 6918 } 6919 6920 static u8 rtl8xxxu_signal_to_snr(int signal) 6921 { 6922 if (signal < RTL8XXXU_NOISE_FLOOR_MIN) 6923 signal = RTL8XXXU_NOISE_FLOOR_MIN; 6924 else if (signal > 0) 6925 signal = 0; 6926 return (u8)(signal - RTL8XXXU_NOISE_FLOOR_MIN); 6927 } 6928 6929 static void rtl8xxxu_refresh_rate_mask(struct rtl8xxxu_priv *priv, 6930 int signal, struct ieee80211_sta *sta, 6931 bool force) 6932 { 6933 struct ieee80211_hw *hw = priv->hw; 6934 u16 wireless_mode; 6935 u8 rssi_level, ratr_idx; 6936 u8 txbw_40mhz; 6937 u8 snr, snr_thresh_high, snr_thresh_low; 6938 u8 go_up_gap = 5; 6939 u8 macid = rtl8xxxu_get_macid(priv, sta); 6940 6941 rssi_level = priv->rssi_level; 6942 snr = rtl8xxxu_signal_to_snr(signal); 6943 snr_thresh_high = RTL8XXXU_SNR_THRESH_HIGH; 6944 snr_thresh_low = RTL8XXXU_SNR_THRESH_LOW; 6945 txbw_40mhz = (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) ? 1 : 0; 6946 6947 switch (rssi_level) { 6948 case RTL8XXXU_RATR_STA_MID: 6949 snr_thresh_high += go_up_gap; 6950 break; 6951 case RTL8XXXU_RATR_STA_LOW: 6952 snr_thresh_high += go_up_gap; 6953 snr_thresh_low += go_up_gap; 6954 break; 6955 default: 6956 break; 6957 } 6958 6959 if (snr > snr_thresh_high) 6960 rssi_level = RTL8XXXU_RATR_STA_HIGH; 6961 else if (snr > snr_thresh_low) 6962 rssi_level = RTL8XXXU_RATR_STA_MID; 6963 else 6964 rssi_level = RTL8XXXU_RATR_STA_LOW; 6965 6966 if (rssi_level != priv->rssi_level || force) { 6967 int sgi = 0; 6968 u32 rate_bitmap = 0; 6969 6970 rcu_read_lock(); 6971 rate_bitmap = (sta->deflink.supp_rates[0] & 0xfff) | 6972 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12) | 6973 (sta->deflink.ht_cap.mcs.rx_mask[1] << 20); 6974 if (sta->deflink.ht_cap.cap & 6975 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)) 6976 sgi = 1; 6977 rcu_read_unlock(); 6978 6979 wireless_mode = rtl8xxxu_wireless_mode(hw, sta); 6980 switch (wireless_mode) { 6981 case WIRELESS_MODE_B: 6982 ratr_idx = RATEID_IDX_B; 6983 if (rate_bitmap & 0x0000000c) 6984 rate_bitmap &= 0x0000000d; 6985 else 6986 rate_bitmap &= 0x0000000f; 6987 break; 6988 case WIRELESS_MODE_A: 6989 case WIRELESS_MODE_G: 6990 ratr_idx = RATEID_IDX_G; 6991 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) 6992 rate_bitmap &= 0x00000f00; 6993 else 6994 rate_bitmap &= 0x00000ff0; 6995 break; 6996 case (WIRELESS_MODE_B | WIRELESS_MODE_G): 6997 ratr_idx = RATEID_IDX_BG; 6998 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) 6999 rate_bitmap &= 0x00000f00; 7000 else if (rssi_level == RTL8XXXU_RATR_STA_MID) 7001 rate_bitmap &= 0x00000ff0; 7002 else 7003 rate_bitmap &= 0x00000ff5; 7004 break; 7005 case WIRELESS_MODE_N_24G: 7006 case WIRELESS_MODE_N_5G: 7007 case (WIRELESS_MODE_G | WIRELESS_MODE_N_24G): 7008 case (WIRELESS_MODE_A | WIRELESS_MODE_N_5G): 7009 if (priv->tx_paths == 2 && priv->rx_paths == 2) 7010 ratr_idx = RATEID_IDX_GN_N2SS; 7011 else 7012 ratr_idx = RATEID_IDX_GN_N1SS; 7013 break; 7014 case (WIRELESS_MODE_B | WIRELESS_MODE_G | WIRELESS_MODE_N_24G): 7015 case (WIRELESS_MODE_B | WIRELESS_MODE_N_24G): 7016 if (txbw_40mhz) { 7017 if (priv->tx_paths == 2 && priv->rx_paths == 2) 7018 ratr_idx = RATEID_IDX_BGN_40M_2SS; 7019 else 7020 ratr_idx = RATEID_IDX_BGN_40M_1SS; 7021 } else { 7022 if (priv->tx_paths == 2 && priv->rx_paths == 2) 7023 ratr_idx = RATEID_IDX_BGN_20M_2SS_BN; 7024 else 7025 ratr_idx = RATEID_IDX_BGN_20M_1SS_BN; 7026 } 7027 7028 if (priv->tx_paths == 2 && priv->rx_paths == 2) { 7029 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) { 7030 rate_bitmap &= 0x0f8f0000; 7031 } else if (rssi_level == RTL8XXXU_RATR_STA_MID) { 7032 rate_bitmap &= 0x0f8ff000; 7033 } else { 7034 if (txbw_40mhz) 7035 rate_bitmap &= 0x0f8ff015; 7036 else 7037 rate_bitmap &= 0x0f8ff005; 7038 } 7039 } else { 7040 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) { 7041 rate_bitmap &= 0x000f0000; 7042 } else if (rssi_level == RTL8XXXU_RATR_STA_MID) { 7043 rate_bitmap &= 0x000ff000; 7044 } else { 7045 if (txbw_40mhz) 7046 rate_bitmap &= 0x000ff015; 7047 else 7048 rate_bitmap &= 0x000ff005; 7049 } 7050 } 7051 break; 7052 default: 7053 ratr_idx = RATEID_IDX_BGN_40M_2SS; 7054 rate_bitmap &= 0x0fffffff; 7055 break; 7056 } 7057 7058 priv->rssi_level = rssi_level; 7059 priv->fops->update_rate_mask(priv, rate_bitmap, ratr_idx, sgi, txbw_40mhz, macid); 7060 } 7061 } 7062 7063 static void rtl8xxxu_set_atc_status(struct rtl8xxxu_priv *priv, bool atc_status) 7064 { 7065 struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; 7066 u32 val32; 7067 7068 if (atc_status == cfo->atc_status) 7069 return; 7070 7071 cfo->atc_status = atc_status; 7072 7073 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); 7074 if (atc_status) 7075 val32 |= CFO_TRACKING_ATC_STATUS; 7076 else 7077 val32 &= ~CFO_TRACKING_ATC_STATUS; 7078 rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); 7079 } 7080 7081 /* Central frequency offset correction */ 7082 static void rtl8xxxu_track_cfo(struct rtl8xxxu_priv *priv) 7083 { 7084 struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; 7085 int cfo_khz_a, cfo_khz_b, cfo_average; 7086 int crystal_cap; 7087 7088 if (!priv->vif || !priv->vif->cfg.assoc) { 7089 /* Reset */ 7090 cfo->adjust = true; 7091 7092 if (cfo->crystal_cap > priv->default_crystal_cap) 7093 priv->fops->set_crystal_cap(priv, cfo->crystal_cap - 1); 7094 else if (cfo->crystal_cap < priv->default_crystal_cap) 7095 priv->fops->set_crystal_cap(priv, cfo->crystal_cap + 1); 7096 7097 rtl8xxxu_set_atc_status(priv, true); 7098 7099 return; 7100 } 7101 7102 if (cfo->packet_count == cfo->packet_count_pre) 7103 /* No new information. */ 7104 return; 7105 7106 cfo->packet_count_pre = cfo->packet_count; 7107 7108 /* CFO_tail[1:0] is S(8,7), (num_subcarrier>>7) x 312.5K = CFO value(K Hz) */ 7109 cfo_khz_a = (int)((cfo->cfo_tail[0] * 3125) / 10) >> 7; 7110 cfo_khz_b = (int)((cfo->cfo_tail[1] * 3125) / 10) >> 7; 7111 7112 if (priv->tx_paths == 1) 7113 cfo_average = cfo_khz_a; 7114 else 7115 cfo_average = (cfo_khz_a + cfo_khz_b) / 2; 7116 7117 dev_dbg(&priv->udev->dev, "cfo_average: %d\n", cfo_average); 7118 7119 if (cfo->adjust) { 7120 if (abs(cfo_average) < CFO_TH_XTAL_LOW) 7121 cfo->adjust = false; 7122 } else { 7123 if (abs(cfo_average) > CFO_TH_XTAL_HIGH) 7124 cfo->adjust = true; 7125 } 7126 7127 /* 7128 * TODO: We should return here only if bluetooth is enabled. 7129 * See the vendor drivers for how to determine that. 7130 */ 7131 if (priv->has_bluetooth) 7132 return; 7133 7134 if (!cfo->adjust) 7135 return; 7136 7137 crystal_cap = cfo->crystal_cap; 7138 7139 if (cfo_average > CFO_TH_XTAL_LOW) 7140 crystal_cap++; 7141 else if (cfo_average < -CFO_TH_XTAL_LOW) 7142 crystal_cap--; 7143 7144 crystal_cap = clamp(crystal_cap, 0, 0x3f); 7145 7146 priv->fops->set_crystal_cap(priv, crystal_cap); 7147 7148 rtl8xxxu_set_atc_status(priv, abs(cfo_average) >= CFO_TH_ATC); 7149 } 7150 7151 static void rtl8xxxu_watchdog_callback(struct work_struct *work) 7152 { 7153 struct ieee80211_vif *vif; 7154 struct rtl8xxxu_priv *priv; 7155 7156 priv = container_of(work, struct rtl8xxxu_priv, ra_watchdog.work); 7157 vif = priv->vif; 7158 7159 if (vif && vif->type == NL80211_IFTYPE_STATION) { 7160 int signal; 7161 struct ieee80211_sta *sta; 7162 7163 rcu_read_lock(); 7164 sta = ieee80211_find_sta(vif, vif->bss_conf.bssid); 7165 if (!sta) { 7166 struct device *dev = &priv->udev->dev; 7167 7168 dev_dbg(dev, "%s: no sta found\n", __func__); 7169 rcu_read_unlock(); 7170 goto out; 7171 } 7172 rcu_read_unlock(); 7173 7174 signal = ieee80211_ave_rssi(vif); 7175 7176 priv->fops->report_rssi(priv, 0, 7177 rtl8xxxu_signal_to_snr(signal)); 7178 7179 if (priv->fops->set_crystal_cap) 7180 rtl8xxxu_track_cfo(priv); 7181 7182 rtl8xxxu_refresh_rate_mask(priv, signal, sta, false); 7183 } 7184 7185 out: 7186 schedule_delayed_work(&priv->ra_watchdog, 2 * HZ); 7187 } 7188 7189 static int rtl8xxxu_start(struct ieee80211_hw *hw) 7190 { 7191 struct rtl8xxxu_priv *priv = hw->priv; 7192 struct rtl8xxxu_rx_urb *rx_urb; 7193 struct rtl8xxxu_tx_urb *tx_urb; 7194 struct sk_buff *skb; 7195 unsigned long flags; 7196 int ret, i; 7197 7198 ret = 0; 7199 7200 init_usb_anchor(&priv->rx_anchor); 7201 init_usb_anchor(&priv->tx_anchor); 7202 init_usb_anchor(&priv->int_anchor); 7203 7204 priv->fops->enable_rf(priv); 7205 if (priv->usb_interrupts) { 7206 ret = rtl8xxxu_submit_int_urb(hw); 7207 if (ret) 7208 goto exit; 7209 } 7210 7211 for (i = 0; i < RTL8XXXU_TX_URBS; i++) { 7212 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL); 7213 if (!tx_urb) { 7214 if (!i) 7215 ret = -ENOMEM; 7216 7217 goto error_out; 7218 } 7219 usb_init_urb(&tx_urb->urb); 7220 INIT_LIST_HEAD(&tx_urb->list); 7221 tx_urb->hw = hw; 7222 list_add(&tx_urb->list, &priv->tx_urb_free_list); 7223 priv->tx_urb_free_count++; 7224 } 7225 7226 priv->tx_stopped = false; 7227 7228 spin_lock_irqsave(&priv->rx_urb_lock, flags); 7229 priv->shutdown = false; 7230 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 7231 7232 for (i = 0; i < RTL8XXXU_RX_URBS; i++) { 7233 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL); 7234 if (!rx_urb) { 7235 if (!i) 7236 ret = -ENOMEM; 7237 7238 goto error_out; 7239 } 7240 usb_init_urb(&rx_urb->urb); 7241 INIT_LIST_HEAD(&rx_urb->list); 7242 rx_urb->hw = hw; 7243 7244 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb); 7245 if (ret) { 7246 if (ret != -ENOMEM) { 7247 skb = (struct sk_buff *)rx_urb->urb.context; 7248 dev_kfree_skb(skb); 7249 } 7250 rtl8xxxu_queue_rx_urb(priv, rx_urb); 7251 } 7252 } 7253 7254 schedule_delayed_work(&priv->ra_watchdog, 2 * HZ); 7255 exit: 7256 /* 7257 * Accept all data and mgmt frames 7258 */ 7259 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff); 7260 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff); 7261 7262 rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1, 7263 OFDM0_X_AGC_CORE1_IGI_MASK, 0x1e); 7264 7265 return ret; 7266 7267 error_out: 7268 rtl8xxxu_free_tx_resources(priv); 7269 /* 7270 * Disable all data and mgmt frames 7271 */ 7272 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); 7273 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000); 7274 7275 return ret; 7276 } 7277 7278 static void rtl8xxxu_stop(struct ieee80211_hw *hw) 7279 { 7280 struct rtl8xxxu_priv *priv = hw->priv; 7281 unsigned long flags; 7282 7283 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 7284 7285 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000); 7286 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); 7287 7288 spin_lock_irqsave(&priv->rx_urb_lock, flags); 7289 priv->shutdown = true; 7290 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 7291 7292 usb_kill_anchored_urbs(&priv->rx_anchor); 7293 usb_kill_anchored_urbs(&priv->tx_anchor); 7294 if (priv->usb_interrupts) 7295 usb_kill_anchored_urbs(&priv->int_anchor); 7296 7297 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 7298 7299 priv->fops->disable_rf(priv); 7300 7301 /* 7302 * Disable interrupts 7303 */ 7304 if (priv->usb_interrupts) 7305 rtl8xxxu_write32(priv, REG_USB_HIMR, 0); 7306 7307 cancel_delayed_work_sync(&priv->ra_watchdog); 7308 7309 rtl8xxxu_free_rx_resources(priv); 7310 rtl8xxxu_free_tx_resources(priv); 7311 } 7312 7313 static int rtl8xxxu_sta_add(struct ieee80211_hw *hw, 7314 struct ieee80211_vif *vif, 7315 struct ieee80211_sta *sta) 7316 { 7317 struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; 7318 struct rtl8xxxu_priv *priv = hw->priv; 7319 7320 if (vif->type == NL80211_IFTYPE_AP) { 7321 sta_info->macid = rtl8xxxu_acquire_macid(priv); 7322 if (sta_info->macid >= RTL8XXXU_MAX_MAC_ID_NUM) 7323 return -ENOSPC; 7324 7325 rtl8xxxu_refresh_rate_mask(priv, 0, sta, true); 7326 priv->fops->report_connect(priv, sta_info->macid, H2C_MACID_ROLE_STA, true); 7327 } 7328 7329 return 0; 7330 } 7331 7332 static int rtl8xxxu_sta_remove(struct ieee80211_hw *hw, 7333 struct ieee80211_vif *vif, 7334 struct ieee80211_sta *sta) 7335 { 7336 struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; 7337 struct rtl8xxxu_priv *priv = hw->priv; 7338 7339 if (vif->type == NL80211_IFTYPE_AP) 7340 rtl8xxxu_release_macid(priv, sta_info->macid); 7341 7342 return 0; 7343 } 7344 7345 static const struct ieee80211_ops rtl8xxxu_ops = { 7346 .tx = rtl8xxxu_tx, 7347 .wake_tx_queue = ieee80211_handle_wake_tx_queue, 7348 .add_interface = rtl8xxxu_add_interface, 7349 .remove_interface = rtl8xxxu_remove_interface, 7350 .config = rtl8xxxu_config, 7351 .conf_tx = rtl8xxxu_conf_tx, 7352 .bss_info_changed = rtl8xxxu_bss_info_changed, 7353 .start_ap = rtl8xxxu_start_ap, 7354 .configure_filter = rtl8xxxu_configure_filter, 7355 .set_rts_threshold = rtl8xxxu_set_rts_threshold, 7356 .start = rtl8xxxu_start, 7357 .stop = rtl8xxxu_stop, 7358 .sw_scan_start = rtl8xxxu_sw_scan_start, 7359 .sw_scan_complete = rtl8xxxu_sw_scan_complete, 7360 .set_key = rtl8xxxu_set_key, 7361 .ampdu_action = rtl8xxxu_ampdu_action, 7362 .sta_statistics = rtl8xxxu_sta_statistics, 7363 .get_antenna = rtl8xxxu_get_antenna, 7364 .set_tim = rtl8xxxu_set_tim, 7365 .sta_add = rtl8xxxu_sta_add, 7366 .sta_remove = rtl8xxxu_sta_remove, 7367 }; 7368 7369 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv, 7370 struct usb_interface *interface) 7371 { 7372 struct usb_interface_descriptor *interface_desc; 7373 struct usb_host_interface *host_interface; 7374 struct usb_endpoint_descriptor *endpoint; 7375 struct device *dev = &priv->udev->dev; 7376 int i, j = 0, endpoints; 7377 u8 dir, xtype, num; 7378 int ret = 0; 7379 7380 host_interface = interface->cur_altsetting; 7381 interface_desc = &host_interface->desc; 7382 endpoints = interface_desc->bNumEndpoints; 7383 7384 for (i = 0; i < endpoints; i++) { 7385 endpoint = &host_interface->endpoint[i].desc; 7386 7387 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK; 7388 num = usb_endpoint_num(endpoint); 7389 xtype = usb_endpoint_type(endpoint); 7390 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 7391 dev_dbg(dev, 7392 "%s: endpoint: dir %02x, # %02x, type %02x\n", 7393 __func__, dir, num, xtype); 7394 if (usb_endpoint_dir_in(endpoint) && 7395 usb_endpoint_xfer_bulk(endpoint)) { 7396 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 7397 dev_dbg(dev, "%s: in endpoint num %i\n", 7398 __func__, num); 7399 7400 if (priv->pipe_in) { 7401 dev_warn(dev, 7402 "%s: Too many IN pipes\n", __func__); 7403 ret = -EINVAL; 7404 goto exit; 7405 } 7406 7407 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num); 7408 } 7409 7410 if (usb_endpoint_dir_in(endpoint) && 7411 usb_endpoint_xfer_int(endpoint)) { 7412 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 7413 dev_dbg(dev, "%s: interrupt endpoint num %i\n", 7414 __func__, num); 7415 7416 if (priv->pipe_interrupt) { 7417 dev_warn(dev, "%s: Too many INTERRUPT pipes\n", 7418 __func__); 7419 ret = -EINVAL; 7420 goto exit; 7421 } 7422 7423 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num); 7424 } 7425 7426 if (usb_endpoint_dir_out(endpoint) && 7427 usb_endpoint_xfer_bulk(endpoint)) { 7428 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 7429 dev_dbg(dev, "%s: out endpoint num %i\n", 7430 __func__, num); 7431 if (j >= RTL8XXXU_OUT_ENDPOINTS) { 7432 dev_warn(dev, 7433 "%s: Too many OUT pipes\n", __func__); 7434 ret = -EINVAL; 7435 goto exit; 7436 } 7437 priv->out_ep[j++] = num; 7438 } 7439 } 7440 exit: 7441 priv->nr_out_eps = j; 7442 return ret; 7443 } 7444 7445 static void rtl8xxxu_init_led(struct rtl8xxxu_priv *priv) 7446 { 7447 struct led_classdev *led = &priv->led_cdev; 7448 7449 if (!priv->fops->led_classdev_brightness_set) 7450 return; 7451 7452 led->brightness_set_blocking = priv->fops->led_classdev_brightness_set; 7453 7454 snprintf(priv->led_name, sizeof(priv->led_name), 7455 "rtl8xxxu-usb%s", dev_name(&priv->udev->dev)); 7456 led->name = priv->led_name; 7457 led->max_brightness = RTL8XXXU_HW_LED_CONTROL; 7458 7459 if (led_classdev_register(&priv->udev->dev, led)) 7460 return; 7461 7462 priv->led_registered = true; 7463 7464 led->brightness = led->max_brightness; 7465 priv->fops->led_classdev_brightness_set(led, led->brightness); 7466 } 7467 7468 static void rtl8xxxu_deinit_led(struct rtl8xxxu_priv *priv) 7469 { 7470 struct led_classdev *led = &priv->led_cdev; 7471 7472 if (!priv->led_registered) 7473 return; 7474 7475 priv->fops->led_classdev_brightness_set(led, LED_OFF); 7476 led_classdev_unregister(led); 7477 } 7478 7479 static int rtl8xxxu_probe(struct usb_interface *interface, 7480 const struct usb_device_id *id) 7481 { 7482 struct rtl8xxxu_priv *priv; 7483 struct ieee80211_hw *hw; 7484 struct usb_device *udev; 7485 struct ieee80211_supported_band *sband; 7486 int ret; 7487 int untested = 1; 7488 7489 udev = usb_get_dev(interface_to_usbdev(interface)); 7490 7491 switch (id->idVendor) { 7492 case USB_VENDOR_ID_REALTEK: 7493 switch(id->idProduct) { 7494 case 0x1724: 7495 case 0x8176: 7496 case 0x8178: 7497 case 0x817f: 7498 case 0x818b: 7499 case 0xf179: 7500 case 0x8179: 7501 case 0xb711: 7502 case 0xf192: 7503 untested = 0; 7504 break; 7505 } 7506 break; 7507 case 0x7392: 7508 if (id->idProduct == 0x7811 || id->idProduct == 0xa611 || id->idProduct == 0xb811) 7509 untested = 0; 7510 break; 7511 case 0x050d: 7512 if (id->idProduct == 0x1004) 7513 untested = 0; 7514 break; 7515 case 0x20f4: 7516 if (id->idProduct == 0x648b) 7517 untested = 0; 7518 break; 7519 case 0x2001: 7520 if (id->idProduct == 0x3308) 7521 untested = 0; 7522 break; 7523 case 0x2357: 7524 if (id->idProduct == 0x0109) 7525 untested = 0; 7526 break; 7527 case 0x0b05: 7528 if (id->idProduct == 0x18f1) 7529 untested = 0; 7530 break; 7531 default: 7532 break; 7533 } 7534 7535 if (untested) { 7536 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE; 7537 dev_info(&udev->dev, 7538 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n", 7539 id->idVendor, id->idProduct); 7540 dev_info(&udev->dev, 7541 "Please report results to Jes.Sorensen@gmail.com\n"); 7542 } 7543 7544 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops); 7545 if (!hw) { 7546 ret = -ENOMEM; 7547 goto err_put_dev; 7548 } 7549 7550 priv = hw->priv; 7551 priv->hw = hw; 7552 priv->udev = udev; 7553 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info; 7554 mutex_init(&priv->usb_buf_mutex); 7555 mutex_init(&priv->syson_indirect_access_mutex); 7556 mutex_init(&priv->h2c_mutex); 7557 INIT_LIST_HEAD(&priv->tx_urb_free_list); 7558 spin_lock_init(&priv->tx_urb_lock); 7559 INIT_LIST_HEAD(&priv->rx_urb_pending_list); 7560 spin_lock_init(&priv->rx_urb_lock); 7561 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work); 7562 INIT_DELAYED_WORK(&priv->ra_watchdog, rtl8xxxu_watchdog_callback); 7563 INIT_WORK(&priv->update_beacon_work, rtl8xxxu_update_beacon_work_callback); 7564 skb_queue_head_init(&priv->c2hcmd_queue); 7565 7566 usb_set_intfdata(interface, hw); 7567 7568 ret = rtl8xxxu_parse_usb(priv, interface); 7569 if (ret) 7570 goto err_set_intfdata; 7571 7572 ret = priv->fops->identify_chip(priv); 7573 if (ret) { 7574 dev_err(&udev->dev, "Fatal - failed to identify chip\n"); 7575 goto err_set_intfdata; 7576 } 7577 7578 hw->wiphy->available_antennas_tx = BIT(priv->tx_paths) - 1; 7579 hw->wiphy->available_antennas_rx = BIT(priv->rx_paths) - 1; 7580 7581 if (priv->rtl_chip == RTL8188E) 7582 INIT_WORK(&priv->c2hcmd_work, rtl8188e_c2hcmd_callback); 7583 else 7584 INIT_WORK(&priv->c2hcmd_work, rtl8xxxu_c2hcmd_callback); 7585 7586 ret = priv->fops->read_efuse(priv); 7587 if (ret) { 7588 dev_err(&udev->dev, "Fatal - failed to read EFuse\n"); 7589 goto err_set_intfdata; 7590 } 7591 7592 ret = priv->fops->parse_efuse(priv); 7593 if (ret) { 7594 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n"); 7595 goto err_set_intfdata; 7596 } 7597 7598 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) 7599 rtl8xxxu_dump_efuse(priv); 7600 7601 rtl8xxxu_print_chipinfo(priv); 7602 7603 ret = priv->fops->load_firmware(priv); 7604 if (ret) { 7605 dev_err(&udev->dev, "Fatal - failed to load firmware\n"); 7606 goto err_set_intfdata; 7607 } 7608 7609 ret = rtl8xxxu_init_device(hw); 7610 if (ret) 7611 goto err_set_intfdata; 7612 7613 hw->wiphy->max_scan_ssids = 1; 7614 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; 7615 if (priv->fops->max_macid_num) 7616 hw->wiphy->max_ap_assoc_sta = priv->fops->max_macid_num - 1; 7617 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); 7618 if (priv->fops->supports_ap) 7619 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP); 7620 hw->queues = 4; 7621 7622 sband = &rtl8xxxu_supported_band; 7623 sband->ht_cap.ht_supported = true; 7624 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 7625 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16; 7626 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40; 7627 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs)); 7628 sband->ht_cap.mcs.rx_mask[0] = 0xff; 7629 sband->ht_cap.mcs.rx_mask[4] = 0x01; 7630 if (priv->rf_paths > 1) { 7631 sband->ht_cap.mcs.rx_mask[1] = 0xff; 7632 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40; 7633 } 7634 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 7635 /* 7636 * Some APs will negotiate HT20_40 in a noisy environment leading 7637 * to miserable performance. Rather than defaulting to this, only 7638 * enable it if explicitly requested at module load time. 7639 */ 7640 if (rtl8xxxu_ht40_2g) { 7641 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n"); 7642 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; 7643 } 7644 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 7645 7646 hw->wiphy->rts_threshold = 2347; 7647 7648 SET_IEEE80211_DEV(priv->hw, &interface->dev); 7649 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr); 7650 7651 hw->extra_tx_headroom = priv->fops->tx_desc_size; 7652 ieee80211_hw_set(hw, SIGNAL_DBM); 7653 7654 /* 7655 * The firmware handles rate control, except for RTL8188EU, 7656 * where we handle the rate control in the driver. 7657 */ 7658 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 7659 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 7660 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 7661 7662 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); 7663 7664 ret = ieee80211_register_hw(priv->hw); 7665 if (ret) { 7666 dev_err(&udev->dev, "%s: Failed to register: %i\n", 7667 __func__, ret); 7668 goto err_set_intfdata; 7669 } 7670 7671 rtl8xxxu_init_led(priv); 7672 7673 return 0; 7674 7675 err_set_intfdata: 7676 usb_set_intfdata(interface, NULL); 7677 7678 kfree(priv->fw_data); 7679 mutex_destroy(&priv->usb_buf_mutex); 7680 mutex_destroy(&priv->syson_indirect_access_mutex); 7681 mutex_destroy(&priv->h2c_mutex); 7682 7683 ieee80211_free_hw(hw); 7684 err_put_dev: 7685 usb_put_dev(udev); 7686 7687 return ret; 7688 } 7689 7690 static void rtl8xxxu_disconnect(struct usb_interface *interface) 7691 { 7692 struct rtl8xxxu_priv *priv; 7693 struct ieee80211_hw *hw; 7694 7695 hw = usb_get_intfdata(interface); 7696 priv = hw->priv; 7697 7698 rtl8xxxu_deinit_led(priv); 7699 7700 ieee80211_unregister_hw(hw); 7701 7702 priv->fops->power_off(priv); 7703 7704 usb_set_intfdata(interface, NULL); 7705 7706 dev_info(&priv->udev->dev, "disconnecting\n"); 7707 7708 kfree(priv->fw_data); 7709 mutex_destroy(&priv->usb_buf_mutex); 7710 mutex_destroy(&priv->syson_indirect_access_mutex); 7711 mutex_destroy(&priv->h2c_mutex); 7712 7713 if (priv->udev->state != USB_STATE_NOTATTACHED) { 7714 dev_info(&priv->udev->dev, 7715 "Device still attached, trying to reset\n"); 7716 usb_reset_device(priv->udev); 7717 } 7718 usb_put_dev(priv->udev); 7719 ieee80211_free_hw(hw); 7720 } 7721 7722 static const struct usb_device_id dev_table[] = { 7723 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff), 7724 .driver_info = (unsigned long)&rtl8723au_fops}, 7725 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff), 7726 .driver_info = (unsigned long)&rtl8723au_fops}, 7727 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff), 7728 .driver_info = (unsigned long)&rtl8723au_fops}, 7729 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff), 7730 .driver_info = (unsigned long)&rtl8192eu_fops}, 7731 /* TP-Link TL-WN822N v4 */ 7732 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0108, 0xff, 0xff, 0xff), 7733 .driver_info = (unsigned long)&rtl8192eu_fops}, 7734 /* D-Link DWA-131 rev E1, tested by David Patiño */ 7735 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3319, 0xff, 0xff, 0xff), 7736 .driver_info = (unsigned long)&rtl8192eu_fops}, 7737 /* Tested by Myckel Habets */ 7738 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0109, 0xff, 0xff, 0xff), 7739 .driver_info = (unsigned long)&rtl8192eu_fops}, 7740 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff), 7741 .driver_info = (unsigned long)&rtl8723bu_fops}, 7742 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xa611, 0xff, 0xff, 0xff), 7743 .driver_info = (unsigned long)&rtl8723bu_fops}, 7744 /* RTL8188FU */ 7745 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xf179, 0xff, 0xff, 0xff), 7746 .driver_info = (unsigned long)&rtl8188fu_fops}, 7747 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8179, 0xff, 0xff, 0xff), 7748 .driver_info = (unsigned long)&rtl8188eu_fops}, 7749 /* Tested by Hans de Goede - rtl8188etv */ 7750 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0179, 0xff, 0xff, 0xff), 7751 .driver_info = (unsigned long)&rtl8188eu_fops}, 7752 /* Sitecom rtl8188eus */ 7753 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0076, 0xff, 0xff, 0xff), 7754 .driver_info = (unsigned long)&rtl8188eu_fops}, 7755 /* D-Link USB-GO-N150 */ 7756 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3311, 0xff, 0xff, 0xff), 7757 .driver_info = (unsigned long)&rtl8188eu_fops}, 7758 /* D-Link DWA-125 REV D1 */ 7759 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330f, 0xff, 0xff, 0xff), 7760 .driver_info = (unsigned long)&rtl8188eu_fops}, 7761 /* D-Link DWA-123 REV D1 */ 7762 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3310, 0xff, 0xff, 0xff), 7763 .driver_info = (unsigned long)&rtl8188eu_fops}, 7764 /* D-Link DWA-121 rev B1 */ 7765 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x331b, 0xff, 0xff, 0xff), 7766 .driver_info = (unsigned long)&rtl8188eu_fops}, 7767 /* Abocom - Abocom */ 7768 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8179, 0xff, 0xff, 0xff), 7769 .driver_info = (unsigned long)&rtl8188eu_fops}, 7770 /* Elecom WDC-150SU2M */ 7771 {USB_DEVICE_AND_INTERFACE_INFO(0x056e, 0x4008, 0xff, 0xff, 0xff), 7772 .driver_info = (unsigned long)&rtl8188eu_fops}, 7773 /* TP-Link TL-WN722N v2 */ 7774 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x010c, 0xff, 0xff, 0xff), 7775 .driver_info = (unsigned long)&rtl8188eu_fops}, 7776 /* TP-Link TL-WN727N v5.21 */ 7777 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0111, 0xff, 0xff, 0xff), 7778 .driver_info = (unsigned long)&rtl8188eu_fops}, 7779 /* MERCUSYS MW150US v2 */ 7780 {USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0102, 0xff, 0xff, 0xff), 7781 .driver_info = (unsigned long)&rtl8188eu_fops}, 7782 /* ASUS USB-N10 Nano B1 */ 7783 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x18f0, 0xff, 0xff, 0xff), 7784 .driver_info = (unsigned long)&rtl8188eu_fops}, 7785 /* Edimax EW-7811Un V2 */ 7786 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xb811, 0xff, 0xff, 0xff), 7787 .driver_info = (unsigned long)&rtl8188eu_fops}, 7788 /* Rosewill USB-N150 Nano */ 7789 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xffef, 0xff, 0xff, 0xff), 7790 .driver_info = (unsigned long)&rtl8188eu_fops}, 7791 /* RTL8710BU aka RTL8188GU (not to be confused with RTL8188GTVU) */ 7792 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb711, 0xff, 0xff, 0xff), 7793 .driver_info = (unsigned long)&rtl8710bu_fops}, 7794 /* TOTOLINK N150UA V5 / N150UA-B */ 7795 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2005, 0xff, 0xff, 0xff), 7796 .driver_info = (unsigned long)&rtl8710bu_fops}, 7797 /* Comfast CF-826F */ 7798 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xf192, 0xff, 0xff, 0xff), 7799 .driver_info = (unsigned long)&rtl8192fu_fops}, 7800 /* Asus USB-N13 rev C1 */ 7801 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x18f1, 0xff, 0xff, 0xff), 7802 .driver_info = (unsigned long)&rtl8192fu_fops}, 7803 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xb722, 0xff, 0xff, 0xff), 7804 .driver_info = (unsigned long)&rtl8192fu_fops}, 7805 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x318b, 0xff, 0xff, 0xff), 7806 .driver_info = (unsigned long)&rtl8192fu_fops}, 7807 #ifdef CONFIG_RTL8XXXU_UNTESTED 7808 /* Still supported by rtlwifi */ 7809 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff), 7810 .driver_info = (unsigned long)&rtl8192cu_fops}, 7811 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff), 7812 .driver_info = (unsigned long)&rtl8192cu_fops}, 7813 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff), 7814 .driver_info = (unsigned long)&rtl8192cu_fops}, 7815 /* Tested by Larry Finger */ 7816 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff), 7817 .driver_info = (unsigned long)&rtl8192cu_fops}, 7818 /* Tested by Andrea Merello */ 7819 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff), 7820 .driver_info = (unsigned long)&rtl8192cu_fops}, 7821 /* Tested by Jocelyn Mayer */ 7822 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff), 7823 .driver_info = (unsigned long)&rtl8192cu_fops}, 7824 /* Tested by Stefano Bravi */ 7825 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff), 7826 .driver_info = (unsigned long)&rtl8192cu_fops}, 7827 /* Currently untested 8188 series devices */ 7828 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x018a, 0xff, 0xff, 0xff), 7829 .driver_info = (unsigned long)&rtl8192cu_fops}, 7830 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff), 7831 .driver_info = (unsigned long)&rtl8192cu_fops}, 7832 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff), 7833 .driver_info = (unsigned long)&rtl8192cu_fops}, 7834 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff), 7835 .driver_info = (unsigned long)&rtl8192cu_fops}, 7836 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff), 7837 .driver_info = (unsigned long)&rtl8192cu_fops}, 7838 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff), 7839 .driver_info = (unsigned long)&rtl8192cu_fops}, 7840 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff), 7841 .driver_info = (unsigned long)&rtl8192cu_fops}, 7842 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff), 7843 .driver_info = (unsigned long)&rtl8192cu_fops}, 7844 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff), 7845 .driver_info = (unsigned long)&rtl8192cu_fops}, 7846 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff), 7847 .driver_info = (unsigned long)&rtl8192cu_fops}, 7848 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff), 7849 .driver_info = (unsigned long)&rtl8192cu_fops}, 7850 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff), 7851 .driver_info = (unsigned long)&rtl8192cu_fops}, 7852 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff), 7853 .driver_info = (unsigned long)&rtl8192cu_fops}, 7854 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff), 7855 .driver_info = (unsigned long)&rtl8192cu_fops}, 7856 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff), 7857 .driver_info = (unsigned long)&rtl8192cu_fops}, 7858 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff), 7859 .driver_info = (unsigned long)&rtl8192cu_fops}, 7860 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff), 7861 .driver_info = (unsigned long)&rtl8192cu_fops}, 7862 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff), 7863 .driver_info = (unsigned long)&rtl8192cu_fops}, 7864 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff), 7865 .driver_info = (unsigned long)&rtl8192cu_fops}, 7866 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff), 7867 .driver_info = (unsigned long)&rtl8192cu_fops}, 7868 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff), 7869 .driver_info = (unsigned long)&rtl8192cu_fops}, 7870 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff), 7871 .driver_info = (unsigned long)&rtl8192cu_fops}, 7872 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff), 7873 .driver_info = (unsigned long)&rtl8192cu_fops}, 7874 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff), 7875 .driver_info = (unsigned long)&rtl8192cu_fops}, 7876 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff), 7877 .driver_info = (unsigned long)&rtl8192cu_fops}, 7878 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff), 7879 .driver_info = (unsigned long)&rtl8192cu_fops}, 7880 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff), 7881 .driver_info = (unsigned long)&rtl8192cu_fops}, 7882 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff), 7883 .driver_info = (unsigned long)&rtl8192cu_fops}, 7884 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff), 7885 .driver_info = (unsigned long)&rtl8192cu_fops}, 7886 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff), 7887 .driver_info = (unsigned long)&rtl8192cu_fops}, 7888 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff), 7889 .driver_info = (unsigned long)&rtl8192cu_fops}, 7890 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff), 7891 .driver_info = (unsigned long)&rtl8192cu_fops}, 7892 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff), 7893 .driver_info = (unsigned long)&rtl8192cu_fops}, 7894 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff), 7895 .driver_info = (unsigned long)&rtl8192cu_fops}, 7896 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff), 7897 .driver_info = (unsigned long)&rtl8192cu_fops}, 7898 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff), 7899 .driver_info = (unsigned long)&rtl8192cu_fops}, 7900 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff), 7901 .driver_info = (unsigned long)&rtl8192cu_fops}, 7902 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff), 7903 .driver_info = (unsigned long)&rtl8192cu_fops}, 7904 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff), 7905 .driver_info = (unsigned long)&rtl8192cu_fops}, 7906 /* Currently untested 8192 series devices */ 7907 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff), 7908 .driver_info = (unsigned long)&rtl8192cu_fops}, 7909 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff), 7910 .driver_info = (unsigned long)&rtl8192cu_fops}, 7911 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff), 7912 .driver_info = (unsigned long)&rtl8192cu_fops}, 7913 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff), 7914 .driver_info = (unsigned long)&rtl8192cu_fops}, 7915 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff), 7916 .driver_info = (unsigned long)&rtl8192cu_fops}, 7917 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff), 7918 .driver_info = (unsigned long)&rtl8192cu_fops}, 7919 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff), 7920 .driver_info = (unsigned long)&rtl8192cu_fops}, 7921 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff), 7922 .driver_info = (unsigned long)&rtl8192cu_fops}, 7923 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff), 7924 .driver_info = (unsigned long)&rtl8192cu_fops}, 7925 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff), 7926 .driver_info = (unsigned long)&rtl8192cu_fops}, 7927 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff), 7928 .driver_info = (unsigned long)&rtl8192cu_fops}, 7929 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff), 7930 .driver_info = (unsigned long)&rtl8192cu_fops}, 7931 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff), 7932 .driver_info = (unsigned long)&rtl8192cu_fops}, 7933 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff), 7934 .driver_info = (unsigned long)&rtl8192cu_fops}, 7935 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff), 7936 .driver_info = (unsigned long)&rtl8192cu_fops}, 7937 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff), 7938 .driver_info = (unsigned long)&rtl8192cu_fops}, 7939 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff), 7940 .driver_info = (unsigned long)&rtl8192cu_fops}, 7941 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff), 7942 .driver_info = (unsigned long)&rtl8192cu_fops}, 7943 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff), 7944 .driver_info = (unsigned long)&rtl8192cu_fops}, 7945 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff), 7946 .driver_info = (unsigned long)&rtl8192cu_fops}, 7947 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff), 7948 .driver_info = (unsigned long)&rtl8192cu_fops}, 7949 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff), 7950 .driver_info = (unsigned long)&rtl8192cu_fops}, 7951 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff), 7952 .driver_info = (unsigned long)&rtl8192cu_fops}, 7953 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff), 7954 .driver_info = (unsigned long)&rtl8192cu_fops}, 7955 /* found in rtl8192eu vendor driver */ 7956 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0107, 0xff, 0xff, 0xff), 7957 .driver_info = (unsigned long)&rtl8192eu_fops}, 7958 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab33, 0xff, 0xff, 0xff), 7959 .driver_info = (unsigned long)&rtl8192eu_fops}, 7960 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818c, 0xff, 0xff, 0xff), 7961 .driver_info = (unsigned long)&rtl8192eu_fops}, 7962 /* D-Link DWA-131 rev C1 */ 7963 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3312, 0xff, 0xff, 0xff), 7964 .driver_info = (unsigned long)&rtl8192eu_fops}, 7965 /* TP-Link TL-WN8200ND V2 */ 7966 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0126, 0xff, 0xff, 0xff), 7967 .driver_info = (unsigned long)&rtl8192eu_fops}, 7968 /* Mercusys MW300UM */ 7969 {USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0100, 0xff, 0xff, 0xff), 7970 .driver_info = (unsigned long)&rtl8192eu_fops}, 7971 /* Mercusys MW300UH */ 7972 {USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0104, 0xff, 0xff, 0xff), 7973 .driver_info = (unsigned long)&rtl8192eu_fops}, 7974 #endif 7975 { } 7976 }; 7977 7978 static struct usb_driver rtl8xxxu_driver = { 7979 .name = DRIVER_NAME, 7980 .probe = rtl8xxxu_probe, 7981 .disconnect = rtl8xxxu_disconnect, 7982 .id_table = dev_table, 7983 .no_dynamic_id = 1, 7984 .disable_hub_initiated_lpm = 1, 7985 }; 7986 7987 MODULE_DEVICE_TABLE(usb, dev_table); 7988 7989 module_usb_driver(rtl8xxxu_driver); 7990