1 /* 2 * RTL8XXXU mac80211 USB driver 3 * 4 * Copyright (c) 2014 - 2016 Jes Sorensen <Jes.Sorensen@redhat.com> 5 * 6 * Portions, notably calibration code: 7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 8 * 9 * This driver was written as a replacement for the vendor provided 10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in 11 * their programming interface, I have started adding support for 12 * additional 8xxx chips like the 8192cu, 8188cus, etc. 13 * 14 * This program is free software; you can redistribute it and/or modify it 15 * under the terms of version 2 of the GNU General Public License as 16 * published by the Free Software Foundation. 17 * 18 * This program is distributed in the hope that it will be useful, but WITHOUT 19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 21 * more details. 22 */ 23 24 #include <linux/init.h> 25 #include <linux/kernel.h> 26 #include <linux/sched.h> 27 #include <linux/errno.h> 28 #include <linux/slab.h> 29 #include <linux/module.h> 30 #include <linux/spinlock.h> 31 #include <linux/list.h> 32 #include <linux/usb.h> 33 #include <linux/netdevice.h> 34 #include <linux/etherdevice.h> 35 #include <linux/ethtool.h> 36 #include <linux/wireless.h> 37 #include <linux/firmware.h> 38 #include <linux/moduleparam.h> 39 #include <net/mac80211.h> 40 #include "rtl8xxxu.h" 41 #include "rtl8xxxu_regs.h" 42 43 #define DRIVER_NAME "rtl8xxxu" 44 45 int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE; 46 static bool rtl8xxxu_ht40_2g; 47 static bool rtl8xxxu_dma_aggregation; 48 static int rtl8xxxu_dma_agg_timeout = -1; 49 static int rtl8xxxu_dma_agg_pages = -1; 50 51 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>"); 52 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver"); 53 MODULE_LICENSE("GPL"); 54 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin"); 55 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin"); 56 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin"); 57 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin"); 58 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin"); 59 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin"); 60 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin"); 61 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin"); 62 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin"); 63 64 module_param_named(debug, rtl8xxxu_debug, int, 0600); 65 MODULE_PARM_DESC(debug, "Set debug mask"); 66 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600); 67 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band"); 68 module_param_named(dma_aggregation, rtl8xxxu_dma_aggregation, bool, 0600); 69 MODULE_PARM_DESC(dma_aggregation, "Enable DMA packet aggregation"); 70 module_param_named(dma_agg_timeout, rtl8xxxu_dma_agg_timeout, int, 0600); 71 MODULE_PARM_DESC(dma_agg_timeout, "Set DMA aggregation timeout (range 1-127)"); 72 module_param_named(dma_agg_pages, rtl8xxxu_dma_agg_pages, int, 0600); 73 MODULE_PARM_DESC(dma_agg_pages, "Set DMA aggregation pages (range 1-127, 0 to disable)"); 74 75 #define USB_VENDOR_ID_REALTEK 0x0bda 76 #define RTL8XXXU_RX_URBS 32 77 #define RTL8XXXU_RX_URB_PENDING_WATER 8 78 #define RTL8XXXU_TX_URBS 64 79 #define RTL8XXXU_TX_URB_LOW_WATER 25 80 #define RTL8XXXU_TX_URB_HIGH_WATER 32 81 82 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv, 83 struct rtl8xxxu_rx_urb *rx_urb); 84 85 static struct ieee80211_rate rtl8xxxu_rates[] = { 86 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 }, 87 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 }, 88 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 }, 89 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 }, 90 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 }, 91 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 }, 92 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 }, 93 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 }, 94 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 }, 95 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 }, 96 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 }, 97 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 }, 98 }; 99 100 static struct ieee80211_channel rtl8xxxu_channels_2g[] = { 101 { .band = NL80211_BAND_2GHZ, .center_freq = 2412, 102 .hw_value = 1, .max_power = 30 }, 103 { .band = NL80211_BAND_2GHZ, .center_freq = 2417, 104 .hw_value = 2, .max_power = 30 }, 105 { .band = NL80211_BAND_2GHZ, .center_freq = 2422, 106 .hw_value = 3, .max_power = 30 }, 107 { .band = NL80211_BAND_2GHZ, .center_freq = 2427, 108 .hw_value = 4, .max_power = 30 }, 109 { .band = NL80211_BAND_2GHZ, .center_freq = 2432, 110 .hw_value = 5, .max_power = 30 }, 111 { .band = NL80211_BAND_2GHZ, .center_freq = 2437, 112 .hw_value = 6, .max_power = 30 }, 113 { .band = NL80211_BAND_2GHZ, .center_freq = 2442, 114 .hw_value = 7, .max_power = 30 }, 115 { .band = NL80211_BAND_2GHZ, .center_freq = 2447, 116 .hw_value = 8, .max_power = 30 }, 117 { .band = NL80211_BAND_2GHZ, .center_freq = 2452, 118 .hw_value = 9, .max_power = 30 }, 119 { .band = NL80211_BAND_2GHZ, .center_freq = 2457, 120 .hw_value = 10, .max_power = 30 }, 121 { .band = NL80211_BAND_2GHZ, .center_freq = 2462, 122 .hw_value = 11, .max_power = 30 }, 123 { .band = NL80211_BAND_2GHZ, .center_freq = 2467, 124 .hw_value = 12, .max_power = 30 }, 125 { .band = NL80211_BAND_2GHZ, .center_freq = 2472, 126 .hw_value = 13, .max_power = 30 }, 127 { .band = NL80211_BAND_2GHZ, .center_freq = 2484, 128 .hw_value = 14, .max_power = 30 } 129 }; 130 131 static struct ieee80211_supported_band rtl8xxxu_supported_band = { 132 .channels = rtl8xxxu_channels_2g, 133 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g), 134 .bitrates = rtl8xxxu_rates, 135 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates), 136 }; 137 138 struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[] = { 139 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00}, 140 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, 141 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00}, 142 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05}, 143 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01}, 144 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f}, 145 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72}, 146 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08}, 147 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, 148 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, 149 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, 150 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, 151 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, 152 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, 153 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16}, 154 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00}, 155 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02}, 156 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, 157 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, 158 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, 159 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, 160 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff}, 161 }; 162 163 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = { 164 {0x800, 0x80040000}, {0x804, 0x00000003}, 165 {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, 166 {0x810, 0x10001331}, {0x814, 0x020c3d10}, 167 {0x818, 0x02200385}, {0x81c, 0x00000000}, 168 {0x820, 0x01000100}, {0x824, 0x00390004}, 169 {0x828, 0x00000000}, {0x82c, 0x00000000}, 170 {0x830, 0x00000000}, {0x834, 0x00000000}, 171 {0x838, 0x00000000}, {0x83c, 0x00000000}, 172 {0x840, 0x00010000}, {0x844, 0x00000000}, 173 {0x848, 0x00000000}, {0x84c, 0x00000000}, 174 {0x850, 0x00000000}, {0x854, 0x00000000}, 175 {0x858, 0x569a569a}, {0x85c, 0x001b25a4}, 176 {0x860, 0x66f60110}, {0x864, 0x061f0130}, 177 {0x868, 0x00000000}, {0x86c, 0x32323200}, 178 {0x870, 0x07000760}, {0x874, 0x22004000}, 179 {0x878, 0x00000808}, {0x87c, 0x00000000}, 180 {0x880, 0xc0083070}, {0x884, 0x000004d5}, 181 {0x888, 0x00000000}, {0x88c, 0xccc000c0}, 182 {0x890, 0x00000800}, {0x894, 0xfffffffe}, 183 {0x898, 0x40302010}, {0x89c, 0x00706050}, 184 {0x900, 0x00000000}, {0x904, 0x00000023}, 185 {0x908, 0x00000000}, {0x90c, 0x81121111}, 186 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c}, 187 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f}, 188 {0xa10, 0x9500bb78}, {0xa14, 0x11144028}, 189 {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, 190 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, 191 {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, 192 {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, 193 {0xa78, 0x00000900}, 194 {0xc00, 0x48071d40}, {0xc04, 0x03a05611}, 195 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, 196 {0xc10, 0x08800000}, {0xc14, 0x40000100}, 197 {0xc18, 0x08800000}, {0xc1c, 0x40000100}, 198 {0xc20, 0x00000000}, {0xc24, 0x00000000}, 199 {0xc28, 0x00000000}, {0xc2c, 0x00000000}, 200 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af}, 201 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, 202 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, 203 {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, 204 {0xc50, 0x69543420}, {0xc54, 0x43bc0094}, 205 {0xc58, 0x69543420}, {0xc5c, 0x433c0094}, 206 {0xc60, 0x00000000}, {0xc64, 0x7112848b}, 207 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, 208 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db}, 209 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612}, 210 {0xc80, 0x40000100}, {0xc84, 0x20f60000}, 211 {0xc88, 0x40000100}, {0xc8c, 0x20200000}, 212 {0xc90, 0x00121820}, {0xc94, 0x00000000}, 213 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, 214 {0xca0, 0x00000000}, {0xca4, 0x00000080}, 215 {0xca8, 0x00000000}, {0xcac, 0x00000000}, 216 {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, 217 {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, 218 {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, 219 {0xcc8, 0x00000000}, {0xccc, 0x00000000}, 220 {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, 221 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, 222 {0xce0, 0x00222222}, {0xce4, 0x00000000}, 223 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, 224 {0xd00, 0x00080740}, {0xd04, 0x00020401}, 225 {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, 226 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, 227 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975}, 228 {0xd30, 0x00000000}, {0xd34, 0x80608000}, 229 {0xd38, 0x00000000}, {0xd3c, 0x00027293}, 230 {0xd40, 0x00000000}, {0xd44, 0x00000000}, 231 {0xd48, 0x00000000}, {0xd4c, 0x00000000}, 232 {0xd50, 0x6437140a}, {0xd54, 0x00000000}, 233 {0xd58, 0x00000000}, {0xd5c, 0x30032064}, 234 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, 235 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, 236 {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, 237 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a}, 238 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a}, 239 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a}, 240 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a}, 241 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, 242 {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, 243 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, 244 {0xe44, 0x01004800}, {0xe48, 0xfb000000}, 245 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, 246 {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, 247 {0xe5c, 0x28160d05}, {0xe60, 0x00000008}, 248 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0}, 249 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0}, 250 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0}, 251 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0}, 252 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0}, 253 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0}, 254 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0}, 255 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0}, 256 {0xf14, 0x00000003}, {0xf4c, 0x00000000}, 257 {0xf00, 0x00000300}, 258 {0xffff, 0xffffffff}, 259 }; 260 261 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = { 262 {0x024, 0x0011800f}, {0x028, 0x00ffdb83}, 263 {0x800, 0x80040002}, {0x804, 0x00000003}, 264 {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, 265 {0x810, 0x10000330}, {0x814, 0x020c3d10}, 266 {0x818, 0x02200385}, {0x81c, 0x00000000}, 267 {0x820, 0x01000100}, {0x824, 0x00390004}, 268 {0x828, 0x01000100}, {0x82c, 0x00390004}, 269 {0x830, 0x27272727}, {0x834, 0x27272727}, 270 {0x838, 0x27272727}, {0x83c, 0x27272727}, 271 {0x840, 0x00010000}, {0x844, 0x00010000}, 272 {0x848, 0x27272727}, {0x84c, 0x27272727}, 273 {0x850, 0x00000000}, {0x854, 0x00000000}, 274 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4}, 275 {0x860, 0x66e60230}, {0x864, 0x061f0130}, 276 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27}, 277 {0x870, 0x07000700}, {0x874, 0x22184000}, 278 {0x878, 0x08080808}, {0x87c, 0x00000000}, 279 {0x880, 0xc0083070}, {0x884, 0x000004d5}, 280 {0x888, 0x00000000}, {0x88c, 0xcc0000c0}, 281 {0x890, 0x00000800}, {0x894, 0xfffffffe}, 282 {0x898, 0x40302010}, {0x89c, 0x00706050}, 283 {0x900, 0x00000000}, {0x904, 0x00000023}, 284 {0x908, 0x00000000}, {0x90c, 0x81121313}, 285 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c}, 286 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f}, 287 {0xa10, 0x9500bb78}, {0xa14, 0x11144028}, 288 {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, 289 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, 290 {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, 291 {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, 292 {0xc00, 0x48071d40}, {0xc04, 0x03a05633}, 293 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, 294 {0xc10, 0x08800000}, {0xc14, 0x40000100}, 295 {0xc18, 0x08800000}, {0xc1c, 0x40000100}, 296 {0xc20, 0x00000000}, {0xc24, 0x00000000}, 297 {0xc28, 0x00000000}, {0xc2c, 0x00000000}, 298 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf}, 299 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, 300 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, 301 {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, 302 {0xc50, 0x69543420}, {0xc54, 0x43bc0094}, 303 {0xc58, 0x69543420}, {0xc5c, 0x433c0094}, 304 {0xc60, 0x00000000}, {0xc64, 0x5116848b}, 305 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, 306 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b}, 307 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612}, 308 {0xc80, 0x40000100}, {0xc84, 0x20f60000}, 309 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000}, 310 {0xc90, 0x00121820}, {0xc94, 0x00000000}, 311 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, 312 {0xca0, 0x00000000}, {0xca4, 0x00000080}, 313 {0xca8, 0x00000000}, {0xcac, 0x00000000}, 314 {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, 315 {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, 316 {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, 317 {0xcc8, 0x00000000}, {0xccc, 0x00000000}, 318 {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, 319 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, 320 {0xce0, 0x00222222}, {0xce4, 0x00000000}, 321 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, 322 {0xd00, 0x00080740}, {0xd04, 0x00020403}, 323 {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, 324 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, 325 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975}, 326 {0xd30, 0x00000000}, {0xd34, 0x80608000}, 327 {0xd38, 0x00000000}, {0xd3c, 0x00027293}, 328 {0xd40, 0x00000000}, {0xd44, 0x00000000}, 329 {0xd48, 0x00000000}, {0xd4c, 0x00000000}, 330 {0xd50, 0x6437140a}, {0xd54, 0x00000000}, 331 {0xd58, 0x00000000}, {0xd5c, 0x30032064}, 332 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, 333 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, 334 {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, 335 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a}, 336 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a}, 337 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a}, 338 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a}, 339 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, 340 {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, 341 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, 342 {0xe44, 0x01004800}, {0xe48, 0xfb000000}, 343 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, 344 {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, 345 {0xe5c, 0x28160d05}, {0xe60, 0x00000010}, 346 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4}, 347 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4}, 348 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4}, 349 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4}, 350 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4}, 351 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4}, 352 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4}, 353 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4}, 354 {0xf14, 0x00000003}, {0xf4c, 0x00000000}, 355 {0xf00, 0x00000300}, 356 {0xffff, 0xffffffff}, 357 }; 358 359 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = { 360 {0x024, 0x0011800f}, {0x028, 0x00ffdb83}, 361 {0x040, 0x000c0004}, {0x800, 0x80040000}, 362 {0x804, 0x00000001}, {0x808, 0x0000fc00}, 363 {0x80c, 0x0000000a}, {0x810, 0x10005388}, 364 {0x814, 0x020c3d10}, {0x818, 0x02200385}, 365 {0x81c, 0x00000000}, {0x820, 0x01000100}, 366 {0x824, 0x00390204}, {0x828, 0x00000000}, 367 {0x82c, 0x00000000}, {0x830, 0x00000000}, 368 {0x834, 0x00000000}, {0x838, 0x00000000}, 369 {0x83c, 0x00000000}, {0x840, 0x00010000}, 370 {0x844, 0x00000000}, {0x848, 0x00000000}, 371 {0x84c, 0x00000000}, {0x850, 0x00000000}, 372 {0x854, 0x00000000}, {0x858, 0x569a569a}, 373 {0x85c, 0x001b25a4}, {0x860, 0x66e60230}, 374 {0x864, 0x061f0130}, {0x868, 0x00000000}, 375 {0x86c, 0x20202000}, {0x870, 0x03000300}, 376 {0x874, 0x22004000}, {0x878, 0x00000808}, 377 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070}, 378 {0x884, 0x000004d5}, {0x888, 0x00000000}, 379 {0x88c, 0xccc000c0}, {0x890, 0x00000800}, 380 {0x894, 0xfffffffe}, {0x898, 0x40302010}, 381 {0x89c, 0x00706050}, {0x900, 0x00000000}, 382 {0x904, 0x00000023}, {0x908, 0x00000000}, 383 {0x90c, 0x81121111}, {0xa00, 0x00d047c8}, 384 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300}, 385 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78}, 386 {0xa14, 0x11144028}, {0xa18, 0x00881117}, 387 {0xa1c, 0x89140f00}, {0xa20, 0x15160000}, 388 {0xa24, 0x070b0f12}, {0xa28, 0x00000104}, 389 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00}, 390 {0xa74, 0x00000007}, {0xc00, 0x48071d40}, 391 {0xc04, 0x03a05611}, {0xc08, 0x000000e4}, 392 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000}, 393 {0xc14, 0x40000100}, {0xc18, 0x08800000}, 394 {0xc1c, 0x40000100}, {0xc20, 0x00000000}, 395 {0xc24, 0x00000000}, {0xc28, 0x00000000}, 396 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44}, 397 {0xc34, 0x469652cf}, {0xc38, 0x49795994}, 398 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f}, 399 {0xc44, 0x000100b7}, {0xc48, 0xec020107}, 400 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e}, 401 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f}, 402 {0xc5c, 0x433c0094}, {0xc60, 0x00000000}, 403 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff}, 404 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d}, 405 {0xc74, 0x018610db}, {0xc78, 0x0000001f}, 406 {0xc7c, 0x00b91612}, {0xc80, 0x24000090}, 407 {0xc84, 0x20f60000}, {0xc88, 0x24000090}, 408 {0xc8c, 0x20200000}, {0xc90, 0x00121820}, 409 {0xc94, 0x00000000}, {0xc98, 0x00121820}, 410 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000}, 411 {0xca4, 0x00000080}, {0xca8, 0x00000000}, 412 {0xcac, 0x00000000}, {0xcb0, 0x00000000}, 413 {0xcb4, 0x00000000}, {0xcb8, 0x00000000}, 414 {0xcbc, 0x28000000}, {0xcc0, 0x00000000}, 415 {0xcc4, 0x00000000}, {0xcc8, 0x00000000}, 416 {0xccc, 0x00000000}, {0xcd0, 0x00000000}, 417 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427}, 418 {0xcdc, 0x00766932}, {0xce0, 0x00222222}, 419 {0xce4, 0x00000000}, {0xce8, 0x37644302}, 420 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740}, 421 {0xd04, 0x00020401}, {0xd08, 0x0000907f}, 422 {0xd0c, 0x20010201}, {0xd10, 0xa0633333}, 423 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b}, 424 {0xd2c, 0xcc979975}, {0xd30, 0x00000000}, 425 {0xd34, 0x80608000}, {0xd38, 0x00000000}, 426 {0xd3c, 0x00027293}, {0xd40, 0x00000000}, 427 {0xd44, 0x00000000}, {0xd48, 0x00000000}, 428 {0xd4c, 0x00000000}, {0xd50, 0x6437140a}, 429 {0xd54, 0x00000000}, {0xd58, 0x00000000}, 430 {0xd5c, 0x30032064}, {0xd60, 0x4653de68}, 431 {0xd64, 0x04518a3c}, {0xd68, 0x00002101}, 432 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e}, 433 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24}, 434 {0xe00, 0x24242424}, {0xe04, 0x24242424}, 435 {0xe08, 0x03902024}, {0xe10, 0x24242424}, 436 {0xe14, 0x24242424}, {0xe18, 0x24242424}, 437 {0xe1c, 0x24242424}, {0xe28, 0x00000000}, 438 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f}, 439 {0xe38, 0x02140102}, {0xe3c, 0x681604c2}, 440 {0xe40, 0x01007c00}, {0xe44, 0x01004800}, 441 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1}, 442 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f}, 443 {0xe58, 0x02140102}, {0xe5c, 0x28160d05}, 444 {0xe60, 0x00000008}, {0xe68, 0x001b25a4}, 445 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0}, 446 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0}, 447 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0}, 448 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0}, 449 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0}, 450 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0}, 451 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0}, 452 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448}, 453 {0xf14, 0x00000003}, {0xf4c, 0x00000000}, 454 {0xf00, 0x00000300}, 455 {0xffff, 0xffffffff}, 456 }; 457 458 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = { 459 {0xc78, 0x7b000001}, {0xc78, 0x7b010001}, 460 {0xc78, 0x7b020001}, {0xc78, 0x7b030001}, 461 {0xc78, 0x7b040001}, {0xc78, 0x7b050001}, 462 {0xc78, 0x7a060001}, {0xc78, 0x79070001}, 463 {0xc78, 0x78080001}, {0xc78, 0x77090001}, 464 {0xc78, 0x760a0001}, {0xc78, 0x750b0001}, 465 {0xc78, 0x740c0001}, {0xc78, 0x730d0001}, 466 {0xc78, 0x720e0001}, {0xc78, 0x710f0001}, 467 {0xc78, 0x70100001}, {0xc78, 0x6f110001}, 468 {0xc78, 0x6e120001}, {0xc78, 0x6d130001}, 469 {0xc78, 0x6c140001}, {0xc78, 0x6b150001}, 470 {0xc78, 0x6a160001}, {0xc78, 0x69170001}, 471 {0xc78, 0x68180001}, {0xc78, 0x67190001}, 472 {0xc78, 0x661a0001}, {0xc78, 0x651b0001}, 473 {0xc78, 0x641c0001}, {0xc78, 0x631d0001}, 474 {0xc78, 0x621e0001}, {0xc78, 0x611f0001}, 475 {0xc78, 0x60200001}, {0xc78, 0x49210001}, 476 {0xc78, 0x48220001}, {0xc78, 0x47230001}, 477 {0xc78, 0x46240001}, {0xc78, 0x45250001}, 478 {0xc78, 0x44260001}, {0xc78, 0x43270001}, 479 {0xc78, 0x42280001}, {0xc78, 0x41290001}, 480 {0xc78, 0x402a0001}, {0xc78, 0x262b0001}, 481 {0xc78, 0x252c0001}, {0xc78, 0x242d0001}, 482 {0xc78, 0x232e0001}, {0xc78, 0x222f0001}, 483 {0xc78, 0x21300001}, {0xc78, 0x20310001}, 484 {0xc78, 0x06320001}, {0xc78, 0x05330001}, 485 {0xc78, 0x04340001}, {0xc78, 0x03350001}, 486 {0xc78, 0x02360001}, {0xc78, 0x01370001}, 487 {0xc78, 0x00380001}, {0xc78, 0x00390001}, 488 {0xc78, 0x003a0001}, {0xc78, 0x003b0001}, 489 {0xc78, 0x003c0001}, {0xc78, 0x003d0001}, 490 {0xc78, 0x003e0001}, {0xc78, 0x003f0001}, 491 {0xc78, 0x7b400001}, {0xc78, 0x7b410001}, 492 {0xc78, 0x7b420001}, {0xc78, 0x7b430001}, 493 {0xc78, 0x7b440001}, {0xc78, 0x7b450001}, 494 {0xc78, 0x7a460001}, {0xc78, 0x79470001}, 495 {0xc78, 0x78480001}, {0xc78, 0x77490001}, 496 {0xc78, 0x764a0001}, {0xc78, 0x754b0001}, 497 {0xc78, 0x744c0001}, {0xc78, 0x734d0001}, 498 {0xc78, 0x724e0001}, {0xc78, 0x714f0001}, 499 {0xc78, 0x70500001}, {0xc78, 0x6f510001}, 500 {0xc78, 0x6e520001}, {0xc78, 0x6d530001}, 501 {0xc78, 0x6c540001}, {0xc78, 0x6b550001}, 502 {0xc78, 0x6a560001}, {0xc78, 0x69570001}, 503 {0xc78, 0x68580001}, {0xc78, 0x67590001}, 504 {0xc78, 0x665a0001}, {0xc78, 0x655b0001}, 505 {0xc78, 0x645c0001}, {0xc78, 0x635d0001}, 506 {0xc78, 0x625e0001}, {0xc78, 0x615f0001}, 507 {0xc78, 0x60600001}, {0xc78, 0x49610001}, 508 {0xc78, 0x48620001}, {0xc78, 0x47630001}, 509 {0xc78, 0x46640001}, {0xc78, 0x45650001}, 510 {0xc78, 0x44660001}, {0xc78, 0x43670001}, 511 {0xc78, 0x42680001}, {0xc78, 0x41690001}, 512 {0xc78, 0x406a0001}, {0xc78, 0x266b0001}, 513 {0xc78, 0x256c0001}, {0xc78, 0x246d0001}, 514 {0xc78, 0x236e0001}, {0xc78, 0x226f0001}, 515 {0xc78, 0x21700001}, {0xc78, 0x20710001}, 516 {0xc78, 0x06720001}, {0xc78, 0x05730001}, 517 {0xc78, 0x04740001}, {0xc78, 0x03750001}, 518 {0xc78, 0x02760001}, {0xc78, 0x01770001}, 519 {0xc78, 0x00780001}, {0xc78, 0x00790001}, 520 {0xc78, 0x007a0001}, {0xc78, 0x007b0001}, 521 {0xc78, 0x007c0001}, {0xc78, 0x007d0001}, 522 {0xc78, 0x007e0001}, {0xc78, 0x007f0001}, 523 {0xc78, 0x3800001e}, {0xc78, 0x3801001e}, 524 {0xc78, 0x3802001e}, {0xc78, 0x3803001e}, 525 {0xc78, 0x3804001e}, {0xc78, 0x3805001e}, 526 {0xc78, 0x3806001e}, {0xc78, 0x3807001e}, 527 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e}, 528 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e}, 529 {0xc78, 0x440c001e}, {0xc78, 0x480d001e}, 530 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e}, 531 {0xc78, 0x5210001e}, {0xc78, 0x5611001e}, 532 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e}, 533 {0xc78, 0x6014001e}, {0xc78, 0x6015001e}, 534 {0xc78, 0x6016001e}, {0xc78, 0x6217001e}, 535 {0xc78, 0x6218001e}, {0xc78, 0x6219001e}, 536 {0xc78, 0x621a001e}, {0xc78, 0x621b001e}, 537 {0xc78, 0x621c001e}, {0xc78, 0x621d001e}, 538 {0xc78, 0x621e001e}, {0xc78, 0x621f001e}, 539 {0xffff, 0xffffffff} 540 }; 541 542 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = { 543 {0xc78, 0x7b000001}, {0xc78, 0x7b010001}, 544 {0xc78, 0x7b020001}, {0xc78, 0x7b030001}, 545 {0xc78, 0x7b040001}, {0xc78, 0x7b050001}, 546 {0xc78, 0x7b060001}, {0xc78, 0x7b070001}, 547 {0xc78, 0x7b080001}, {0xc78, 0x7a090001}, 548 {0xc78, 0x790a0001}, {0xc78, 0x780b0001}, 549 {0xc78, 0x770c0001}, {0xc78, 0x760d0001}, 550 {0xc78, 0x750e0001}, {0xc78, 0x740f0001}, 551 {0xc78, 0x73100001}, {0xc78, 0x72110001}, 552 {0xc78, 0x71120001}, {0xc78, 0x70130001}, 553 {0xc78, 0x6f140001}, {0xc78, 0x6e150001}, 554 {0xc78, 0x6d160001}, {0xc78, 0x6c170001}, 555 {0xc78, 0x6b180001}, {0xc78, 0x6a190001}, 556 {0xc78, 0x691a0001}, {0xc78, 0x681b0001}, 557 {0xc78, 0x671c0001}, {0xc78, 0x661d0001}, 558 {0xc78, 0x651e0001}, {0xc78, 0x641f0001}, 559 {0xc78, 0x63200001}, {0xc78, 0x62210001}, 560 {0xc78, 0x61220001}, {0xc78, 0x60230001}, 561 {0xc78, 0x46240001}, {0xc78, 0x45250001}, 562 {0xc78, 0x44260001}, {0xc78, 0x43270001}, 563 {0xc78, 0x42280001}, {0xc78, 0x41290001}, 564 {0xc78, 0x402a0001}, {0xc78, 0x262b0001}, 565 {0xc78, 0x252c0001}, {0xc78, 0x242d0001}, 566 {0xc78, 0x232e0001}, {0xc78, 0x222f0001}, 567 {0xc78, 0x21300001}, {0xc78, 0x20310001}, 568 {0xc78, 0x06320001}, {0xc78, 0x05330001}, 569 {0xc78, 0x04340001}, {0xc78, 0x03350001}, 570 {0xc78, 0x02360001}, {0xc78, 0x01370001}, 571 {0xc78, 0x00380001}, {0xc78, 0x00390001}, 572 {0xc78, 0x003a0001}, {0xc78, 0x003b0001}, 573 {0xc78, 0x003c0001}, {0xc78, 0x003d0001}, 574 {0xc78, 0x003e0001}, {0xc78, 0x003f0001}, 575 {0xc78, 0x7b400001}, {0xc78, 0x7b410001}, 576 {0xc78, 0x7b420001}, {0xc78, 0x7b430001}, 577 {0xc78, 0x7b440001}, {0xc78, 0x7b450001}, 578 {0xc78, 0x7b460001}, {0xc78, 0x7b470001}, 579 {0xc78, 0x7b480001}, {0xc78, 0x7a490001}, 580 {0xc78, 0x794a0001}, {0xc78, 0x784b0001}, 581 {0xc78, 0x774c0001}, {0xc78, 0x764d0001}, 582 {0xc78, 0x754e0001}, {0xc78, 0x744f0001}, 583 {0xc78, 0x73500001}, {0xc78, 0x72510001}, 584 {0xc78, 0x71520001}, {0xc78, 0x70530001}, 585 {0xc78, 0x6f540001}, {0xc78, 0x6e550001}, 586 {0xc78, 0x6d560001}, {0xc78, 0x6c570001}, 587 {0xc78, 0x6b580001}, {0xc78, 0x6a590001}, 588 {0xc78, 0x695a0001}, {0xc78, 0x685b0001}, 589 {0xc78, 0x675c0001}, {0xc78, 0x665d0001}, 590 {0xc78, 0x655e0001}, {0xc78, 0x645f0001}, 591 {0xc78, 0x63600001}, {0xc78, 0x62610001}, 592 {0xc78, 0x61620001}, {0xc78, 0x60630001}, 593 {0xc78, 0x46640001}, {0xc78, 0x45650001}, 594 {0xc78, 0x44660001}, {0xc78, 0x43670001}, 595 {0xc78, 0x42680001}, {0xc78, 0x41690001}, 596 {0xc78, 0x406a0001}, {0xc78, 0x266b0001}, 597 {0xc78, 0x256c0001}, {0xc78, 0x246d0001}, 598 {0xc78, 0x236e0001}, {0xc78, 0x226f0001}, 599 {0xc78, 0x21700001}, {0xc78, 0x20710001}, 600 {0xc78, 0x06720001}, {0xc78, 0x05730001}, 601 {0xc78, 0x04740001}, {0xc78, 0x03750001}, 602 {0xc78, 0x02760001}, {0xc78, 0x01770001}, 603 {0xc78, 0x00780001}, {0xc78, 0x00790001}, 604 {0xc78, 0x007a0001}, {0xc78, 0x007b0001}, 605 {0xc78, 0x007c0001}, {0xc78, 0x007d0001}, 606 {0xc78, 0x007e0001}, {0xc78, 0x007f0001}, 607 {0xc78, 0x3800001e}, {0xc78, 0x3801001e}, 608 {0xc78, 0x3802001e}, {0xc78, 0x3803001e}, 609 {0xc78, 0x3804001e}, {0xc78, 0x3805001e}, 610 {0xc78, 0x3806001e}, {0xc78, 0x3807001e}, 611 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e}, 612 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e}, 613 {0xc78, 0x440c001e}, {0xc78, 0x480d001e}, 614 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e}, 615 {0xc78, 0x5210001e}, {0xc78, 0x5611001e}, 616 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e}, 617 {0xc78, 0x6014001e}, {0xc78, 0x6015001e}, 618 {0xc78, 0x6016001e}, {0xc78, 0x6217001e}, 619 {0xc78, 0x6218001e}, {0xc78, 0x6219001e}, 620 {0xc78, 0x621a001e}, {0xc78, 0x621b001e}, 621 {0xc78, 0x621c001e}, {0xc78, 0x621d001e}, 622 {0xc78, 0x621e001e}, {0xc78, 0x621f001e}, 623 {0xffff, 0xffffffff} 624 }; 625 626 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = { 627 { /* RF_A */ 628 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1, 629 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2, 630 .lssiparm = REG_FPGA0_XA_LSSI_PARM, 631 .hspiread = REG_HSPI_XA_READBACK, 632 .lssiread = REG_FPGA0_XA_LSSI_READBACK, 633 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL, 634 }, 635 { /* RF_B */ 636 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1, 637 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2, 638 .lssiparm = REG_FPGA0_XB_LSSI_PARM, 639 .hspiread = REG_HSPI_XB_READBACK, 640 .lssiread = REG_FPGA0_XB_LSSI_READBACK, 641 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL, 642 }, 643 }; 644 645 const u32 rtl8xxxu_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = { 646 REG_OFDM0_XA_RX_IQ_IMBALANCE, 647 REG_OFDM0_XB_RX_IQ_IMBALANCE, 648 REG_OFDM0_ENERGY_CCA_THRES, 649 REG_OFDM0_AGCR_SSI_TABLE, 650 REG_OFDM0_XA_TX_IQ_IMBALANCE, 651 REG_OFDM0_XB_TX_IQ_IMBALANCE, 652 REG_OFDM0_XC_TX_AFE, 653 REG_OFDM0_XD_TX_AFE, 654 REG_OFDM0_RX_IQ_EXT_ANTA 655 }; 656 657 u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr) 658 { 659 struct usb_device *udev = priv->udev; 660 int len; 661 u8 data; 662 663 mutex_lock(&priv->usb_buf_mutex); 664 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 665 REALTEK_USB_CMD_REQ, REALTEK_USB_READ, 666 addr, 0, &priv->usb_buf.val8, sizeof(u8), 667 RTW_USB_CONTROL_MSG_TIMEOUT); 668 data = priv->usb_buf.val8; 669 mutex_unlock(&priv->usb_buf_mutex); 670 671 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) 672 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n", 673 __func__, addr, data, len); 674 return data; 675 } 676 677 u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr) 678 { 679 struct usb_device *udev = priv->udev; 680 int len; 681 u16 data; 682 683 mutex_lock(&priv->usb_buf_mutex); 684 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 685 REALTEK_USB_CMD_REQ, REALTEK_USB_READ, 686 addr, 0, &priv->usb_buf.val16, sizeof(u16), 687 RTW_USB_CONTROL_MSG_TIMEOUT); 688 data = le16_to_cpu(priv->usb_buf.val16); 689 mutex_unlock(&priv->usb_buf_mutex); 690 691 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) 692 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n", 693 __func__, addr, data, len); 694 return data; 695 } 696 697 u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr) 698 { 699 struct usb_device *udev = priv->udev; 700 int len; 701 u32 data; 702 703 mutex_lock(&priv->usb_buf_mutex); 704 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 705 REALTEK_USB_CMD_REQ, REALTEK_USB_READ, 706 addr, 0, &priv->usb_buf.val32, sizeof(u32), 707 RTW_USB_CONTROL_MSG_TIMEOUT); 708 data = le32_to_cpu(priv->usb_buf.val32); 709 mutex_unlock(&priv->usb_buf_mutex); 710 711 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) 712 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n", 713 __func__, addr, data, len); 714 return data; 715 } 716 717 int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val) 718 { 719 struct usb_device *udev = priv->udev; 720 int ret; 721 722 mutex_lock(&priv->usb_buf_mutex); 723 priv->usb_buf.val8 = val; 724 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 725 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 726 addr, 0, &priv->usb_buf.val8, sizeof(u8), 727 RTW_USB_CONTROL_MSG_TIMEOUT); 728 729 mutex_unlock(&priv->usb_buf_mutex); 730 731 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) 732 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n", 733 __func__, addr, val); 734 return ret; 735 } 736 737 int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val) 738 { 739 struct usb_device *udev = priv->udev; 740 int ret; 741 742 mutex_lock(&priv->usb_buf_mutex); 743 priv->usb_buf.val16 = cpu_to_le16(val); 744 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 745 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 746 addr, 0, &priv->usb_buf.val16, sizeof(u16), 747 RTW_USB_CONTROL_MSG_TIMEOUT); 748 mutex_unlock(&priv->usb_buf_mutex); 749 750 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) 751 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n", 752 __func__, addr, val); 753 return ret; 754 } 755 756 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val) 757 { 758 struct usb_device *udev = priv->udev; 759 int ret; 760 761 mutex_lock(&priv->usb_buf_mutex); 762 priv->usb_buf.val32 = cpu_to_le32(val); 763 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 764 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 765 addr, 0, &priv->usb_buf.val32, sizeof(u32), 766 RTW_USB_CONTROL_MSG_TIMEOUT); 767 mutex_unlock(&priv->usb_buf_mutex); 768 769 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) 770 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n", 771 __func__, addr, val); 772 return ret; 773 } 774 775 static int 776 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len) 777 { 778 struct usb_device *udev = priv->udev; 779 int blocksize = priv->fops->writeN_block_size; 780 int ret, i, count, remainder; 781 782 count = len / blocksize; 783 remainder = len % blocksize; 784 785 for (i = 0; i < count; i++) { 786 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 787 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 788 addr, 0, buf, blocksize, 789 RTW_USB_CONTROL_MSG_TIMEOUT); 790 if (ret != blocksize) 791 goto write_error; 792 793 addr += blocksize; 794 buf += blocksize; 795 } 796 797 if (remainder) { 798 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 799 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 800 addr, 0, buf, remainder, 801 RTW_USB_CONTROL_MSG_TIMEOUT); 802 if (ret != remainder) 803 goto write_error; 804 } 805 806 return len; 807 808 write_error: 809 dev_info(&udev->dev, 810 "%s: Failed to write block at addr: %04x size: %04x\n", 811 __func__, addr, blocksize); 812 return -EAGAIN; 813 } 814 815 u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv, 816 enum rtl8xxxu_rfpath path, u8 reg) 817 { 818 u32 hssia, val32, retval; 819 820 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2); 821 if (path != RF_A) 822 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2); 823 else 824 val32 = hssia; 825 826 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK; 827 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT); 828 val32 |= FPGA0_HSSI_PARM2_EDGE_READ; 829 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ; 830 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); 831 832 udelay(10); 833 834 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32); 835 udelay(100); 836 837 hssia |= FPGA0_HSSI_PARM2_EDGE_READ; 838 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); 839 udelay(10); 840 841 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1); 842 if (val32 & FPGA0_HSSI_PARM1_PI) 843 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread); 844 else 845 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread); 846 847 retval &= 0xfffff; 848 849 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ) 850 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n", 851 __func__, reg, retval); 852 return retval; 853 } 854 855 /* 856 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can 857 * have write issues in high temperature conditions. We may have to 858 * retry writing them. 859 */ 860 int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv, 861 enum rtl8xxxu_rfpath path, u8 reg, u32 data) 862 { 863 int ret, retval; 864 u32 dataaddr, val32; 865 866 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE) 867 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n", 868 __func__, reg, data); 869 870 data &= FPGA0_LSSI_PARM_DATA_MASK; 871 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data; 872 873 if (priv->rtl_chip == RTL8192E) { 874 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 875 val32 &= ~0x20000; 876 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 877 } 878 879 /* Use XB for path B */ 880 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr); 881 if (ret != sizeof(dataaddr)) 882 retval = -EIO; 883 else 884 retval = 0; 885 886 udelay(1); 887 888 if (priv->rtl_chip == RTL8192E) { 889 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 890 val32 |= 0x20000; 891 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 892 } 893 894 return retval; 895 } 896 897 int 898 rtl8xxxu_gen1_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len) 899 { 900 struct device *dev = &priv->udev->dev; 901 int mbox_nr, retry, retval = 0; 902 int mbox_reg, mbox_ext_reg; 903 u8 val8; 904 905 mutex_lock(&priv->h2c_mutex); 906 907 mbox_nr = priv->next_mbox; 908 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4); 909 mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2); 910 911 /* 912 * MBOX ready? 913 */ 914 retry = 100; 915 do { 916 val8 = rtl8xxxu_read8(priv, REG_HMTFR); 917 if (!(val8 & BIT(mbox_nr))) 918 break; 919 } while (retry--); 920 921 if (!retry) { 922 dev_info(dev, "%s: Mailbox busy\n", __func__); 923 retval = -EBUSY; 924 goto error; 925 } 926 927 /* 928 * Need to swap as it's being swapped again by rtl8xxxu_write16/32() 929 */ 930 if (len > sizeof(u32)) { 931 rtl8xxxu_write16(priv, mbox_ext_reg, le16_to_cpu(h2c->raw.ext)); 932 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 933 dev_info(dev, "H2C_EXT %04x\n", 934 le16_to_cpu(h2c->raw.ext)); 935 } 936 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data)); 937 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 938 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data)); 939 940 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX; 941 942 error: 943 mutex_unlock(&priv->h2c_mutex); 944 return retval; 945 } 946 947 int 948 rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len) 949 { 950 struct device *dev = &priv->udev->dev; 951 int mbox_nr, retry, retval = 0; 952 int mbox_reg, mbox_ext_reg; 953 u8 val8; 954 955 mutex_lock(&priv->h2c_mutex); 956 957 mbox_nr = priv->next_mbox; 958 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4); 959 mbox_ext_reg = REG_HMBOX_EXT0_8723B + (mbox_nr * 4); 960 961 /* 962 * MBOX ready? 963 */ 964 retry = 100; 965 do { 966 val8 = rtl8xxxu_read8(priv, REG_HMTFR); 967 if (!(val8 & BIT(mbox_nr))) 968 break; 969 } while (retry--); 970 971 if (!retry) { 972 dev_info(dev, "%s: Mailbox busy\n", __func__); 973 retval = -EBUSY; 974 goto error; 975 } 976 977 /* 978 * Need to swap as it's being swapped again by rtl8xxxu_write16/32() 979 */ 980 if (len > sizeof(u32)) { 981 rtl8xxxu_write32(priv, mbox_ext_reg, 982 le32_to_cpu(h2c->raw_wide.ext)); 983 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 984 dev_info(dev, "H2C_EXT %08x\n", 985 le32_to_cpu(h2c->raw_wide.ext)); 986 } 987 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data)); 988 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 989 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data)); 990 991 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX; 992 993 error: 994 mutex_unlock(&priv->h2c_mutex); 995 return retval; 996 } 997 998 void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv) 999 { 1000 u8 val8; 1001 u32 val32; 1002 1003 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL); 1004 val8 |= BIT(0) | BIT(3); 1005 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8); 1006 1007 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); 1008 val32 &= ~(BIT(4) | BIT(5)); 1009 val32 |= BIT(3); 1010 if (priv->rf_paths == 2) { 1011 val32 &= ~(BIT(20) | BIT(21)); 1012 val32 |= BIT(19); 1013 } 1014 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); 1015 1016 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1017 val32 &= ~OFDM_RF_PATH_TX_MASK; 1018 if (priv->tx_paths == 2) 1019 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B; 1020 else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C) 1021 val32 |= OFDM_RF_PATH_TX_B; 1022 else 1023 val32 |= OFDM_RF_PATH_TX_A; 1024 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1025 1026 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1027 val32 &= ~FPGA_RF_MODE_JAPAN; 1028 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1029 1030 if (priv->rf_paths == 2) 1031 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0); 1032 else 1033 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0); 1034 1035 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95); 1036 if (priv->rf_paths == 2) 1037 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95); 1038 1039 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); 1040 } 1041 1042 void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv) 1043 { 1044 u8 sps0; 1045 u32 val32; 1046 1047 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL); 1048 1049 /* RF RX code for preamble power saving */ 1050 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); 1051 val32 &= ~(BIT(3) | BIT(4) | BIT(5)); 1052 if (priv->rf_paths == 2) 1053 val32 &= ~(BIT(19) | BIT(20) | BIT(21)); 1054 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); 1055 1056 /* Disable TX for four paths */ 1057 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1058 val32 &= ~OFDM_RF_PATH_TX_MASK; 1059 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1060 1061 /* Enable power saving */ 1062 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1063 val32 |= FPGA_RF_MODE_JAPAN; 1064 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1065 1066 /* AFE control register to power down bits [30:22] */ 1067 if (priv->rf_paths == 2) 1068 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0); 1069 else 1070 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0); 1071 1072 /* Power down RF module */ 1073 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); 1074 if (priv->rf_paths == 2) 1075 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0); 1076 1077 sps0 &= ~(BIT(0) | BIT(3)); 1078 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0); 1079 } 1080 1081 static void rtl8xxxu_stop_tx_beacon(struct rtl8xxxu_priv *priv) 1082 { 1083 u8 val8; 1084 1085 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2); 1086 val8 &= ~BIT(6); 1087 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8); 1088 1089 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64); 1090 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2); 1091 val8 &= ~BIT(0); 1092 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8); 1093 } 1094 1095 1096 /* 1097 * The rtl8723a has 3 channel groups for it's efuse settings. It only 1098 * supports the 2.4GHz band, so channels 1 - 14: 1099 * group 0: channels 1 - 3 1100 * group 1: channels 4 - 9 1101 * group 2: channels 10 - 14 1102 * 1103 * Note: We index from 0 in the code 1104 */ 1105 static int rtl8xxxu_gen1_channel_to_group(int channel) 1106 { 1107 int group; 1108 1109 if (channel < 4) 1110 group = 0; 1111 else if (channel < 10) 1112 group = 1; 1113 else 1114 group = 2; 1115 1116 return group; 1117 } 1118 1119 /* 1120 * Valid for rtl8723bu and rtl8192eu 1121 */ 1122 int rtl8xxxu_gen2_channel_to_group(int channel) 1123 { 1124 int group; 1125 1126 if (channel < 3) 1127 group = 0; 1128 else if (channel < 6) 1129 group = 1; 1130 else if (channel < 9) 1131 group = 2; 1132 else if (channel < 12) 1133 group = 3; 1134 else 1135 group = 4; 1136 1137 return group; 1138 } 1139 1140 void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw) 1141 { 1142 struct rtl8xxxu_priv *priv = hw->priv; 1143 u32 val32, rsr; 1144 u8 val8, opmode; 1145 bool ht = true; 1146 int sec_ch_above, channel; 1147 int i; 1148 1149 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE); 1150 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 1151 channel = hw->conf.chandef.chan->hw_value; 1152 1153 switch (hw->conf.chandef.width) { 1154 case NL80211_CHAN_WIDTH_20_NOHT: 1155 ht = false; 1156 case NL80211_CHAN_WIDTH_20: 1157 opmode |= BW_OPMODE_20MHZ; 1158 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); 1159 1160 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1161 val32 &= ~FPGA_RF_MODE; 1162 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1163 1164 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1165 val32 &= ~FPGA_RF_MODE; 1166 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1167 1168 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); 1169 val32 |= FPGA0_ANALOG2_20MHZ; 1170 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); 1171 break; 1172 case NL80211_CHAN_WIDTH_40: 1173 if (hw->conf.chandef.center_freq1 > 1174 hw->conf.chandef.chan->center_freq) { 1175 sec_ch_above = 1; 1176 channel += 2; 1177 } else { 1178 sec_ch_above = 0; 1179 channel -= 2; 1180 } 1181 1182 opmode &= ~BW_OPMODE_20MHZ; 1183 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); 1184 rsr &= ~RSR_RSC_BANDWIDTH_40M; 1185 if (sec_ch_above) 1186 rsr |= RSR_RSC_UPPER_SUB_CHANNEL; 1187 else 1188 rsr |= RSR_RSC_LOWER_SUB_CHANNEL; 1189 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr); 1190 1191 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1192 val32 |= FPGA_RF_MODE; 1193 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1194 1195 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1196 val32 |= FPGA_RF_MODE; 1197 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1198 1199 /* 1200 * Set Control channel to upper or lower. These settings 1201 * are required only for 40MHz 1202 */ 1203 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); 1204 val32 &= ~CCK0_SIDEBAND; 1205 if (!sec_ch_above) 1206 val32 |= CCK0_SIDEBAND; 1207 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); 1208 1209 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 1210 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ 1211 if (sec_ch_above) 1212 val32 |= OFDM_LSTF_PRIME_CH_LOW; 1213 else 1214 val32 |= OFDM_LSTF_PRIME_CH_HIGH; 1215 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 1216 1217 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); 1218 val32 &= ~FPGA0_ANALOG2_20MHZ; 1219 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); 1220 1221 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 1222 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); 1223 if (sec_ch_above) 1224 val32 |= FPGA0_PS_UPPER_CHANNEL; 1225 else 1226 val32 |= FPGA0_PS_LOWER_CHANNEL; 1227 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 1228 break; 1229 1230 default: 1231 break; 1232 } 1233 1234 for (i = RF_A; i < priv->rf_paths; i++) { 1235 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1236 val32 &= ~MODE_AG_CHANNEL_MASK; 1237 val32 |= channel; 1238 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1239 } 1240 1241 if (ht) 1242 val8 = 0x0e; 1243 else 1244 val8 = 0x0a; 1245 1246 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8); 1247 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8); 1248 1249 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808); 1250 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a); 1251 1252 for (i = RF_A; i < priv->rf_paths; i++) { 1253 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1254 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) 1255 val32 &= ~MODE_AG_CHANNEL_20MHZ; 1256 else 1257 val32 |= MODE_AG_CHANNEL_20MHZ; 1258 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1259 } 1260 } 1261 1262 void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw) 1263 { 1264 struct rtl8xxxu_priv *priv = hw->priv; 1265 u32 val32, rsr; 1266 u8 val8, subchannel; 1267 u16 rf_mode_bw; 1268 bool ht = true; 1269 int sec_ch_above, channel; 1270 int i; 1271 1272 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL); 1273 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK; 1274 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 1275 channel = hw->conf.chandef.chan->hw_value; 1276 1277 /* Hack */ 1278 subchannel = 0; 1279 1280 switch (hw->conf.chandef.width) { 1281 case NL80211_CHAN_WIDTH_20_NOHT: 1282 ht = false; 1283 case NL80211_CHAN_WIDTH_20: 1284 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20; 1285 subchannel = 0; 1286 1287 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1288 val32 &= ~FPGA_RF_MODE; 1289 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1290 1291 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1292 val32 &= ~FPGA_RF_MODE; 1293 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1294 1295 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); 1296 val32 &= ~(BIT(30) | BIT(31)); 1297 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); 1298 1299 break; 1300 case NL80211_CHAN_WIDTH_40: 1301 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40; 1302 1303 if (hw->conf.chandef.center_freq1 > 1304 hw->conf.chandef.chan->center_freq) { 1305 sec_ch_above = 1; 1306 channel += 2; 1307 } else { 1308 sec_ch_above = 0; 1309 channel -= 2; 1310 } 1311 1312 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1313 val32 |= FPGA_RF_MODE; 1314 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1315 1316 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1317 val32 |= FPGA_RF_MODE; 1318 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1319 1320 /* 1321 * Set Control channel to upper or lower. These settings 1322 * are required only for 40MHz 1323 */ 1324 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); 1325 val32 &= ~CCK0_SIDEBAND; 1326 if (!sec_ch_above) 1327 val32 |= CCK0_SIDEBAND; 1328 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); 1329 1330 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 1331 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ 1332 if (sec_ch_above) 1333 val32 |= OFDM_LSTF_PRIME_CH_LOW; 1334 else 1335 val32 |= OFDM_LSTF_PRIME_CH_HIGH; 1336 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 1337 1338 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 1339 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); 1340 if (sec_ch_above) 1341 val32 |= FPGA0_PS_UPPER_CHANNEL; 1342 else 1343 val32 |= FPGA0_PS_LOWER_CHANNEL; 1344 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 1345 break; 1346 case NL80211_CHAN_WIDTH_80: 1347 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80; 1348 break; 1349 default: 1350 break; 1351 } 1352 1353 for (i = RF_A; i < priv->rf_paths; i++) { 1354 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1355 val32 &= ~MODE_AG_CHANNEL_MASK; 1356 val32 |= channel; 1357 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1358 } 1359 1360 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw); 1361 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel); 1362 1363 if (ht) 1364 val8 = 0x0e; 1365 else 1366 val8 = 0x0a; 1367 1368 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8); 1369 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8); 1370 1371 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808); 1372 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a); 1373 1374 for (i = RF_A; i < priv->rf_paths; i++) { 1375 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1376 val32 &= ~MODE_AG_BW_MASK; 1377 switch(hw->conf.chandef.width) { 1378 case NL80211_CHAN_WIDTH_80: 1379 val32 |= MODE_AG_BW_80MHZ_8723B; 1380 break; 1381 case NL80211_CHAN_WIDTH_40: 1382 val32 |= MODE_AG_BW_40MHZ_8723B; 1383 break; 1384 default: 1385 val32 |= MODE_AG_BW_20MHZ_8723B; 1386 break; 1387 } 1388 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1389 } 1390 } 1391 1392 void 1393 rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) 1394 { 1395 struct rtl8xxxu_power_base *power_base = priv->power_base; 1396 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS]; 1397 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS]; 1398 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b; 1399 u8 val8; 1400 int group, i; 1401 1402 group = rtl8xxxu_gen1_channel_to_group(channel); 1403 1404 cck[0] = priv->cck_tx_power_index_A[group] - 1; 1405 cck[1] = priv->cck_tx_power_index_B[group] - 1; 1406 1407 if (priv->hi_pa) { 1408 if (cck[0] > 0x20) 1409 cck[0] = 0x20; 1410 if (cck[1] > 0x20) 1411 cck[1] = 0x20; 1412 } 1413 1414 ofdm[0] = priv->ht40_1s_tx_power_index_A[group]; 1415 ofdm[1] = priv->ht40_1s_tx_power_index_B[group]; 1416 if (ofdm[0]) 1417 ofdm[0] -= 1; 1418 if (ofdm[1]) 1419 ofdm[1] -= 1; 1420 1421 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a; 1422 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b; 1423 1424 mcsbase[0] = ofdm[0]; 1425 mcsbase[1] = ofdm[1]; 1426 if (!ht40) { 1427 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a; 1428 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b; 1429 } 1430 1431 if (priv->tx_paths > 1) { 1432 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a) 1433 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a; 1434 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b) 1435 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b; 1436 } 1437 1438 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL) 1439 dev_info(&priv->udev->dev, 1440 "%s: Setting TX power CCK A: %02x, " 1441 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n", 1442 __func__, cck[0], cck[1], ofdm[0], ofdm[1]); 1443 1444 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) { 1445 if (cck[i] > RF6052_MAX_TX_PWR) 1446 cck[i] = RF6052_MAX_TX_PWR; 1447 if (ofdm[i] > RF6052_MAX_TX_PWR) 1448 ofdm[i] = RF6052_MAX_TX_PWR; 1449 } 1450 1451 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); 1452 val32 &= 0xffff00ff; 1453 val32 |= (cck[0] << 8); 1454 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); 1455 1456 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); 1457 val32 &= 0xff; 1458 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24)); 1459 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); 1460 1461 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); 1462 val32 &= 0xffffff00; 1463 val32 |= cck[1]; 1464 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); 1465 1466 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32); 1467 val32 &= 0xff; 1468 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24)); 1469 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32); 1470 1471 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 | 1472 ofdmbase[0] << 16 | ofdmbase[0] << 24; 1473 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 | 1474 ofdmbase[1] << 16 | ofdmbase[1] << 24; 1475 1476 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, 1477 ofdm_a + power_base->reg_0e00); 1478 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, 1479 ofdm_b + power_base->reg_0830); 1480 1481 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, 1482 ofdm_a + power_base->reg_0e04); 1483 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, 1484 ofdm_b + power_base->reg_0834); 1485 1486 mcs_a = mcsbase[0] | mcsbase[0] << 8 | 1487 mcsbase[0] << 16 | mcsbase[0] << 24; 1488 mcs_b = mcsbase[1] | mcsbase[1] << 8 | 1489 mcsbase[1] << 16 | mcsbase[1] << 24; 1490 1491 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, 1492 mcs_a + power_base->reg_0e10); 1493 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, 1494 mcs_b + power_base->reg_083c); 1495 1496 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, 1497 mcs_a + power_base->reg_0e14); 1498 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, 1499 mcs_b + power_base->reg_0848); 1500 1501 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, 1502 mcs_a + power_base->reg_0e18); 1503 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, 1504 mcs_b + power_base->reg_084c); 1505 1506 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, 1507 mcs_a + power_base->reg_0e1c); 1508 for (i = 0; i < 3; i++) { 1509 if (i != 2) 1510 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0; 1511 else 1512 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0; 1513 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8); 1514 } 1515 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, 1516 mcs_b + power_base->reg_0868); 1517 for (i = 0; i < 3; i++) { 1518 if (i != 2) 1519 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0; 1520 else 1521 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0; 1522 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8); 1523 } 1524 } 1525 1526 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv, 1527 enum nl80211_iftype linktype) 1528 { 1529 u8 val8; 1530 1531 val8 = rtl8xxxu_read8(priv, REG_MSR); 1532 val8 &= ~MSR_LINKTYPE_MASK; 1533 1534 switch (linktype) { 1535 case NL80211_IFTYPE_UNSPECIFIED: 1536 val8 |= MSR_LINKTYPE_NONE; 1537 break; 1538 case NL80211_IFTYPE_ADHOC: 1539 val8 |= MSR_LINKTYPE_ADHOC; 1540 break; 1541 case NL80211_IFTYPE_STATION: 1542 val8 |= MSR_LINKTYPE_STATION; 1543 break; 1544 case NL80211_IFTYPE_AP: 1545 val8 |= MSR_LINKTYPE_AP; 1546 break; 1547 default: 1548 goto out; 1549 } 1550 1551 rtl8xxxu_write8(priv, REG_MSR, val8); 1552 out: 1553 return; 1554 } 1555 1556 static void 1557 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry) 1558 { 1559 u16 val16; 1560 1561 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) & 1562 RETRY_LIMIT_SHORT_MASK) | 1563 ((long_retry << RETRY_LIMIT_LONG_SHIFT) & 1564 RETRY_LIMIT_LONG_MASK); 1565 1566 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16); 1567 } 1568 1569 static void 1570 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm) 1571 { 1572 u16 val16; 1573 1574 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) | 1575 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK); 1576 1577 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16); 1578 } 1579 1580 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv) 1581 { 1582 struct device *dev = &priv->udev->dev; 1583 char *cut; 1584 1585 switch (priv->chip_cut) { 1586 case 0: 1587 cut = "A"; 1588 break; 1589 case 1: 1590 cut = "B"; 1591 break; 1592 case 2: 1593 cut = "C"; 1594 break; 1595 case 3: 1596 cut = "D"; 1597 break; 1598 case 4: 1599 cut = "E"; 1600 break; 1601 default: 1602 cut = "unknown"; 1603 } 1604 1605 dev_info(dev, 1606 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n", 1607 priv->chip_name, cut, priv->chip_vendor, priv->tx_paths, 1608 priv->rx_paths, priv->ep_tx_count, priv->has_wifi, 1609 priv->has_bluetooth, priv->has_gps, priv->hi_pa); 1610 1611 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr); 1612 } 1613 1614 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv) 1615 { 1616 struct device *dev = &priv->udev->dev; 1617 u32 val32, bonding; 1618 u16 val16; 1619 1620 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG); 1621 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >> 1622 SYS_CFG_CHIP_VERSION_SHIFT; 1623 if (val32 & SYS_CFG_TRP_VAUX_EN) { 1624 dev_info(dev, "Unsupported test chip\n"); 1625 return -ENOTSUPP; 1626 } 1627 1628 if (val32 & SYS_CFG_BT_FUNC) { 1629 if (priv->chip_cut >= 3) { 1630 sprintf(priv->chip_name, "8723BU"); 1631 priv->rtl_chip = RTL8723B; 1632 } else { 1633 sprintf(priv->chip_name, "8723AU"); 1634 priv->usb_interrupts = 1; 1635 priv->rtl_chip = RTL8723A; 1636 } 1637 1638 priv->rf_paths = 1; 1639 priv->rx_paths = 1; 1640 priv->tx_paths = 1; 1641 1642 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); 1643 if (val32 & MULTI_WIFI_FUNC_EN) 1644 priv->has_wifi = 1; 1645 if (val32 & MULTI_BT_FUNC_EN) 1646 priv->has_bluetooth = 1; 1647 if (val32 & MULTI_GPS_FUNC_EN) 1648 priv->has_gps = 1; 1649 priv->is_multi_func = 1; 1650 } else if (val32 & SYS_CFG_TYPE_ID) { 1651 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM); 1652 bonding &= HPON_FSM_BONDING_MASK; 1653 if (priv->fops->tx_desc_size == 1654 sizeof(struct rtl8xxxu_txdesc40)) { 1655 if (bonding == HPON_FSM_BONDING_1T2R) { 1656 sprintf(priv->chip_name, "8191EU"); 1657 priv->rf_paths = 2; 1658 priv->rx_paths = 2; 1659 priv->tx_paths = 1; 1660 priv->rtl_chip = RTL8191E; 1661 } else { 1662 sprintf(priv->chip_name, "8192EU"); 1663 priv->rf_paths = 2; 1664 priv->rx_paths = 2; 1665 priv->tx_paths = 2; 1666 priv->rtl_chip = RTL8192E; 1667 } 1668 } else if (bonding == HPON_FSM_BONDING_1T2R) { 1669 sprintf(priv->chip_name, "8191CU"); 1670 priv->rf_paths = 2; 1671 priv->rx_paths = 2; 1672 priv->tx_paths = 1; 1673 priv->usb_interrupts = 1; 1674 priv->rtl_chip = RTL8191C; 1675 } else { 1676 sprintf(priv->chip_name, "8192CU"); 1677 priv->rf_paths = 2; 1678 priv->rx_paths = 2; 1679 priv->tx_paths = 2; 1680 priv->usb_interrupts = 1; 1681 priv->rtl_chip = RTL8192C; 1682 } 1683 priv->has_wifi = 1; 1684 } else { 1685 sprintf(priv->chip_name, "8188CU"); 1686 priv->rf_paths = 1; 1687 priv->rx_paths = 1; 1688 priv->tx_paths = 1; 1689 priv->rtl_chip = RTL8188C; 1690 priv->usb_interrupts = 1; 1691 priv->has_wifi = 1; 1692 } 1693 1694 switch (priv->rtl_chip) { 1695 case RTL8188E: 1696 case RTL8192E: 1697 case RTL8723B: 1698 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) { 1699 case SYS_CFG_VENDOR_ID_TSMC: 1700 sprintf(priv->chip_vendor, "TSMC"); 1701 break; 1702 case SYS_CFG_VENDOR_ID_SMIC: 1703 sprintf(priv->chip_vendor, "SMIC"); 1704 priv->vendor_smic = 1; 1705 break; 1706 case SYS_CFG_VENDOR_ID_UMC: 1707 sprintf(priv->chip_vendor, "UMC"); 1708 priv->vendor_umc = 1; 1709 break; 1710 default: 1711 sprintf(priv->chip_vendor, "unknown"); 1712 } 1713 break; 1714 default: 1715 if (val32 & SYS_CFG_VENDOR_ID) { 1716 sprintf(priv->chip_vendor, "UMC"); 1717 priv->vendor_umc = 1; 1718 } else { 1719 sprintf(priv->chip_vendor, "TSMC"); 1720 } 1721 } 1722 1723 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); 1724 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28; 1725 1726 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX); 1727 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) { 1728 priv->ep_tx_high_queue = 1; 1729 priv->ep_tx_count++; 1730 } 1731 1732 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) { 1733 priv->ep_tx_normal_queue = 1; 1734 priv->ep_tx_count++; 1735 } 1736 1737 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) { 1738 priv->ep_tx_low_queue = 1; 1739 priv->ep_tx_count++; 1740 } 1741 1742 /* 1743 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX 1744 */ 1745 if (!priv->ep_tx_count) { 1746 switch (priv->nr_out_eps) { 1747 case 4: 1748 case 3: 1749 priv->ep_tx_low_queue = 1; 1750 priv->ep_tx_count++; 1751 case 2: 1752 priv->ep_tx_normal_queue = 1; 1753 priv->ep_tx_count++; 1754 case 1: 1755 priv->ep_tx_high_queue = 1; 1756 priv->ep_tx_count++; 1757 break; 1758 default: 1759 dev_info(dev, "Unsupported USB TX end-points\n"); 1760 return -ENOTSUPP; 1761 } 1762 } 1763 1764 return 0; 1765 } 1766 1767 static int 1768 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data) 1769 { 1770 int i; 1771 u8 val8; 1772 u32 val32; 1773 1774 /* Write Address */ 1775 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff); 1776 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2); 1777 val8 &= 0xfc; 1778 val8 |= (offset >> 8) & 0x03; 1779 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8); 1780 1781 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3); 1782 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f); 1783 1784 /* Poll for data read */ 1785 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); 1786 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) { 1787 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); 1788 if (val32 & BIT(31)) 1789 break; 1790 } 1791 1792 if (i == RTL8XXXU_MAX_REG_POLL) 1793 return -EIO; 1794 1795 udelay(50); 1796 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); 1797 1798 *data = val32 & 0xff; 1799 return 0; 1800 } 1801 1802 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv) 1803 { 1804 struct device *dev = &priv->udev->dev; 1805 int i, ret = 0; 1806 u8 val8, word_mask, header, extheader; 1807 u16 val16, efuse_addr, offset; 1808 u32 val32; 1809 1810 val16 = rtl8xxxu_read16(priv, REG_9346CR); 1811 if (val16 & EEPROM_ENABLE) 1812 priv->has_eeprom = 1; 1813 if (val16 & EEPROM_BOOT) 1814 priv->boot_eeprom = 1; 1815 1816 if (priv->is_multi_func) { 1817 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST); 1818 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT; 1819 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32); 1820 } 1821 1822 dev_dbg(dev, "Booting from %s\n", 1823 priv->boot_eeprom ? "EEPROM" : "EFUSE"); 1824 1825 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE); 1826 1827 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */ 1828 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL); 1829 if (!(val16 & SYS_ISO_PWC_EV12V)) { 1830 val16 |= SYS_ISO_PWC_EV12V; 1831 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16); 1832 } 1833 /* Reset: 0x0000[28], default valid */ 1834 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1835 if (!(val16 & SYS_FUNC_ELDR)) { 1836 val16 |= SYS_FUNC_ELDR; 1837 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 1838 } 1839 1840 /* 1841 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid 1842 */ 1843 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR); 1844 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) { 1845 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M); 1846 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16); 1847 } 1848 1849 /* Default value is 0xff */ 1850 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN); 1851 1852 efuse_addr = 0; 1853 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) { 1854 u16 map_addr; 1855 1856 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header); 1857 if (ret || header == 0xff) 1858 goto exit; 1859 1860 if ((header & 0x1f) == 0x0f) { /* extended header */ 1861 offset = (header & 0xe0) >> 5; 1862 1863 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, 1864 &extheader); 1865 if (ret) 1866 goto exit; 1867 /* All words disabled */ 1868 if ((extheader & 0x0f) == 0x0f) 1869 continue; 1870 1871 offset |= ((extheader & 0xf0) >> 1); 1872 word_mask = extheader & 0x0f; 1873 } else { 1874 offset = (header >> 4) & 0x0f; 1875 word_mask = header & 0x0f; 1876 } 1877 1878 /* Get word enable value from PG header */ 1879 1880 /* We have 8 bits to indicate validity */ 1881 map_addr = offset * 8; 1882 if (map_addr >= EFUSE_MAP_LEN) { 1883 dev_warn(dev, "%s: Illegal map_addr (%04x), " 1884 "efuse corrupt!\n", 1885 __func__, map_addr); 1886 ret = -EINVAL; 1887 goto exit; 1888 } 1889 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { 1890 /* Check word enable condition in the section */ 1891 if (word_mask & BIT(i)) { 1892 map_addr += 2; 1893 continue; 1894 } 1895 1896 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8); 1897 if (ret) 1898 goto exit; 1899 priv->efuse_wifi.raw[map_addr++] = val8; 1900 1901 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8); 1902 if (ret) 1903 goto exit; 1904 priv->efuse_wifi.raw[map_addr++] = val8; 1905 } 1906 } 1907 1908 exit: 1909 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE); 1910 1911 return ret; 1912 } 1913 1914 void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv) 1915 { 1916 u8 val8; 1917 u16 sys_func; 1918 1919 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 1920 val8 &= ~BIT(0); 1921 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 1922 1923 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1924 sys_func &= ~SYS_FUNC_CPU_ENABLE; 1925 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); 1926 1927 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 1928 val8 |= BIT(0); 1929 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 1930 1931 sys_func |= SYS_FUNC_CPU_ENABLE; 1932 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); 1933 } 1934 1935 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv) 1936 { 1937 struct device *dev = &priv->udev->dev; 1938 int ret = 0, i; 1939 u32 val32; 1940 1941 /* Poll checksum report */ 1942 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) { 1943 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); 1944 if (val32 & MCU_FW_DL_CSUM_REPORT) 1945 break; 1946 } 1947 1948 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) { 1949 dev_warn(dev, "Firmware checksum poll timed out\n"); 1950 ret = -EAGAIN; 1951 goto exit; 1952 } 1953 1954 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); 1955 val32 |= MCU_FW_DL_READY; 1956 val32 &= ~MCU_WINT_INIT_READY; 1957 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32); 1958 1959 /* 1960 * Reset the 8051 in order for the firmware to start running, 1961 * otherwise it won't come up on the 8192eu 1962 */ 1963 priv->fops->reset_8051(priv); 1964 1965 /* Wait for firmware to become ready */ 1966 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) { 1967 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); 1968 if (val32 & MCU_WINT_INIT_READY) 1969 break; 1970 1971 udelay(100); 1972 } 1973 1974 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) { 1975 dev_warn(dev, "Firmware failed to start\n"); 1976 ret = -EAGAIN; 1977 goto exit; 1978 } 1979 1980 /* 1981 * Init H2C command 1982 */ 1983 if (priv->rtl_chip == RTL8723B) 1984 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f); 1985 exit: 1986 return ret; 1987 } 1988 1989 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv) 1990 { 1991 int pages, remainder, i, ret; 1992 u8 val8; 1993 u16 val16; 1994 u32 val32; 1995 u8 *fwptr; 1996 1997 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1); 1998 val8 |= 4; 1999 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8); 2000 2001 /* 8051 enable */ 2002 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2003 val16 |= SYS_FUNC_CPU_ENABLE; 2004 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 2005 2006 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL); 2007 if (val8 & MCU_FW_RAM_SEL) { 2008 pr_info("do the RAM reset\n"); 2009 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); 2010 priv->fops->reset_8051(priv); 2011 } 2012 2013 /* MCU firmware download enable */ 2014 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL); 2015 val8 |= MCU_FW_DL_ENABLE; 2016 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8); 2017 2018 /* 8051 reset */ 2019 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); 2020 val32 &= ~BIT(19); 2021 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32); 2022 2023 /* Reset firmware download checksum */ 2024 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL); 2025 val8 |= MCU_FW_DL_CSUM_REPORT; 2026 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8); 2027 2028 pages = priv->fw_size / RTL_FW_PAGE_SIZE; 2029 remainder = priv->fw_size % RTL_FW_PAGE_SIZE; 2030 2031 fwptr = priv->fw_data->data; 2032 2033 for (i = 0; i < pages; i++) { 2034 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8; 2035 val8 |= i; 2036 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8); 2037 2038 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS, 2039 fwptr, RTL_FW_PAGE_SIZE); 2040 if (ret != RTL_FW_PAGE_SIZE) { 2041 ret = -EAGAIN; 2042 goto fw_abort; 2043 } 2044 2045 fwptr += RTL_FW_PAGE_SIZE; 2046 } 2047 2048 if (remainder) { 2049 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8; 2050 val8 |= i; 2051 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8); 2052 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS, 2053 fwptr, remainder); 2054 if (ret != remainder) { 2055 ret = -EAGAIN; 2056 goto fw_abort; 2057 } 2058 } 2059 2060 ret = 0; 2061 fw_abort: 2062 /* MCU firmware download disable */ 2063 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL); 2064 val16 &= ~MCU_FW_DL_ENABLE; 2065 rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16); 2066 2067 return ret; 2068 } 2069 2070 int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name) 2071 { 2072 struct device *dev = &priv->udev->dev; 2073 const struct firmware *fw; 2074 int ret = 0; 2075 u16 signature; 2076 2077 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name); 2078 if (request_firmware(&fw, fw_name, &priv->udev->dev)) { 2079 dev_warn(dev, "request_firmware(%s) failed\n", fw_name); 2080 ret = -EAGAIN; 2081 goto exit; 2082 } 2083 if (!fw) { 2084 dev_warn(dev, "Firmware data not available\n"); 2085 ret = -EINVAL; 2086 goto exit; 2087 } 2088 2089 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL); 2090 if (!priv->fw_data) { 2091 ret = -ENOMEM; 2092 goto exit; 2093 } 2094 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header); 2095 2096 signature = le16_to_cpu(priv->fw_data->signature); 2097 switch (signature & 0xfff0) { 2098 case 0x92e0: 2099 case 0x92c0: 2100 case 0x88c0: 2101 case 0x5300: 2102 case 0x2300: 2103 break; 2104 default: 2105 ret = -EINVAL; 2106 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n", 2107 __func__, signature); 2108 } 2109 2110 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n", 2111 le16_to_cpu(priv->fw_data->major_version), 2112 priv->fw_data->minor_version, signature); 2113 2114 exit: 2115 release_firmware(fw); 2116 return ret; 2117 } 2118 2119 void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv) 2120 { 2121 u16 val16; 2122 int i = 100; 2123 2124 /* Inform 8051 to perform reset */ 2125 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20); 2126 2127 for (i = 100; i > 0; i--) { 2128 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2129 2130 if (!(val16 & SYS_FUNC_CPU_ENABLE)) { 2131 dev_dbg(&priv->udev->dev, 2132 "%s: Firmware self reset success!\n", __func__); 2133 break; 2134 } 2135 udelay(50); 2136 } 2137 2138 if (!i) { 2139 /* Force firmware reset */ 2140 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2141 val16 &= ~SYS_FUNC_CPU_ENABLE; 2142 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 2143 } 2144 } 2145 2146 static int 2147 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv) 2148 { 2149 struct rtl8xxxu_reg8val *array = priv->fops->mactable; 2150 int i, ret; 2151 u16 reg; 2152 u8 val; 2153 2154 for (i = 0; ; i++) { 2155 reg = array[i].reg; 2156 val = array[i].val; 2157 2158 if (reg == 0xffff && val == 0xff) 2159 break; 2160 2161 ret = rtl8xxxu_write8(priv, reg, val); 2162 if (ret != 1) { 2163 dev_warn(&priv->udev->dev, 2164 "Failed to initialize MAC " 2165 "(reg: %04x, val %02x)\n", reg, val); 2166 return -EAGAIN; 2167 } 2168 } 2169 2170 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E) 2171 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a); 2172 2173 return 0; 2174 } 2175 2176 int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv, 2177 struct rtl8xxxu_reg32val *array) 2178 { 2179 int i, ret; 2180 u16 reg; 2181 u32 val; 2182 2183 for (i = 0; ; i++) { 2184 reg = array[i].reg; 2185 val = array[i].val; 2186 2187 if (reg == 0xffff && val == 0xffffffff) 2188 break; 2189 2190 ret = rtl8xxxu_write32(priv, reg, val); 2191 if (ret != sizeof(val)) { 2192 dev_warn(&priv->udev->dev, 2193 "Failed to initialize PHY\n"); 2194 return -EAGAIN; 2195 } 2196 udelay(1); 2197 } 2198 2199 return 0; 2200 } 2201 2202 void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv) 2203 { 2204 u8 val8, ldoa15, ldov12d, lpldo, ldohci12; 2205 u16 val16; 2206 u32 val32; 2207 2208 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); 2209 udelay(2); 2210 val8 |= AFE_PLL_320_ENABLE; 2211 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); 2212 udelay(2); 2213 2214 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff); 2215 udelay(2); 2216 2217 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2218 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB; 2219 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 2220 2221 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); 2222 val32 &= ~AFE_XTAL_RF_GATE; 2223 if (priv->has_bluetooth) 2224 val32 &= ~AFE_XTAL_BT_GATE; 2225 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); 2226 2227 /* 6. 0x1f[7:0] = 0x07 */ 2228 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; 2229 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); 2230 2231 if (priv->hi_pa) 2232 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table); 2233 else if (priv->tx_paths == 2) 2234 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table); 2235 else 2236 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table); 2237 2238 if (priv->rtl_chip == RTL8188R && priv->hi_pa && 2239 priv->vendor_umc && priv->chip_cut == 1) 2240 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50); 2241 2242 if (priv->hi_pa) 2243 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table); 2244 else 2245 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table); 2246 2247 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF; 2248 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT); 2249 ldohci12 = 0x57; 2250 lpldo = 1; 2251 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15; 2252 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32); 2253 } 2254 2255 /* 2256 * Most of this is black magic retrieved from the old rtl8723au driver 2257 */ 2258 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv) 2259 { 2260 u8 val8; 2261 u32 val32; 2262 2263 priv->fops->init_phy_bb(priv); 2264 2265 if (priv->tx_paths == 1 && priv->rx_paths == 2) { 2266 /* 2267 * For 1T2R boards, patch the registers. 2268 * 2269 * It looks like 8191/2 1T2R boards use path B for TX 2270 */ 2271 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO); 2272 val32 &= ~(BIT(0) | BIT(1)); 2273 val32 |= BIT(1); 2274 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32); 2275 2276 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO); 2277 val32 &= ~0x300033; 2278 val32 |= 0x200022; 2279 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32); 2280 2281 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); 2282 val32 &= ~CCK0_AFE_RX_MASK; 2283 val32 &= 0x00ffffff; 2284 val32 |= 0x40000000; 2285 val32 |= CCK0_AFE_RX_ANT_B; 2286 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); 2287 2288 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 2289 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); 2290 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B | 2291 OFDM_RF_PATH_TX_B); 2292 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 2293 2294 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1); 2295 val32 &= ~(BIT(4) | BIT(5)); 2296 val32 |= BIT(4); 2297 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32); 2298 2299 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON); 2300 val32 &= ~(BIT(27) | BIT(26)); 2301 val32 |= BIT(27); 2302 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32); 2303 2304 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON); 2305 val32 &= ~(BIT(27) | BIT(26)); 2306 val32 |= BIT(27); 2307 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32); 2308 2309 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON); 2310 val32 &= ~(BIT(27) | BIT(26)); 2311 val32 |= BIT(27); 2312 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32); 2313 2314 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON); 2315 val32 &= ~(BIT(27) | BIT(26)); 2316 val32 |= BIT(27); 2317 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32); 2318 2319 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX); 2320 val32 &= ~(BIT(27) | BIT(26)); 2321 val32 |= BIT(27); 2322 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32); 2323 } 2324 2325 if (priv->has_xtalk) { 2326 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL); 2327 2328 val8 = priv->xtalk; 2329 val32 &= 0xff000fff; 2330 val32 |= ((val8 | (val8 << 6)) << 12); 2331 2332 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32); 2333 } 2334 2335 if (priv->rtl_chip == RTL8192E) 2336 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x000f81fb); 2337 2338 return 0; 2339 } 2340 2341 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv, 2342 struct rtl8xxxu_rfregval *array, 2343 enum rtl8xxxu_rfpath path) 2344 { 2345 int i, ret; 2346 u8 reg; 2347 u32 val; 2348 2349 for (i = 0; ; i++) { 2350 reg = array[i].reg; 2351 val = array[i].val; 2352 2353 if (reg == 0xff && val == 0xffffffff) 2354 break; 2355 2356 switch (reg) { 2357 case 0xfe: 2358 msleep(50); 2359 continue; 2360 case 0xfd: 2361 mdelay(5); 2362 continue; 2363 case 0xfc: 2364 mdelay(1); 2365 continue; 2366 case 0xfb: 2367 udelay(50); 2368 continue; 2369 case 0xfa: 2370 udelay(5); 2371 continue; 2372 case 0xf9: 2373 udelay(1); 2374 continue; 2375 } 2376 2377 ret = rtl8xxxu_write_rfreg(priv, path, reg, val); 2378 if (ret) { 2379 dev_warn(&priv->udev->dev, 2380 "Failed to initialize RF\n"); 2381 return -EAGAIN; 2382 } 2383 udelay(1); 2384 } 2385 2386 return 0; 2387 } 2388 2389 int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv, 2390 struct rtl8xxxu_rfregval *table, 2391 enum rtl8xxxu_rfpath path) 2392 { 2393 u32 val32; 2394 u16 val16, rfsi_rfenv; 2395 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2; 2396 2397 switch (path) { 2398 case RF_A: 2399 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL; 2400 reg_int_oe = REG_FPGA0_XA_RF_INT_OE; 2401 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2; 2402 break; 2403 case RF_B: 2404 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL; 2405 reg_int_oe = REG_FPGA0_XB_RF_INT_OE; 2406 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2; 2407 break; 2408 default: 2409 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n", 2410 __func__, path + 'A'); 2411 return -EINVAL; 2412 } 2413 /* For path B, use XB */ 2414 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl); 2415 rfsi_rfenv &= FPGA0_RF_RFENV; 2416 2417 /* 2418 * These two we might be able to optimize into one 2419 */ 2420 val32 = rtl8xxxu_read32(priv, reg_int_oe); 2421 val32 |= BIT(20); /* 0x10 << 16 */ 2422 rtl8xxxu_write32(priv, reg_int_oe, val32); 2423 udelay(1); 2424 2425 val32 = rtl8xxxu_read32(priv, reg_int_oe); 2426 val32 |= BIT(4); 2427 rtl8xxxu_write32(priv, reg_int_oe, val32); 2428 udelay(1); 2429 2430 /* 2431 * These two we might be able to optimize into one 2432 */ 2433 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); 2434 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN; 2435 rtl8xxxu_write32(priv, reg_hssi_parm2, val32); 2436 udelay(1); 2437 2438 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); 2439 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN; 2440 rtl8xxxu_write32(priv, reg_hssi_parm2, val32); 2441 udelay(1); 2442 2443 rtl8xxxu_init_rf_regs(priv, table, path); 2444 2445 /* For path B, use XB */ 2446 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl); 2447 val16 &= ~FPGA0_RF_RFENV; 2448 val16 |= rfsi_rfenv; 2449 rtl8xxxu_write16(priv, reg_sw_ctrl, val16); 2450 2451 return 0; 2452 } 2453 2454 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data) 2455 { 2456 int ret = -EBUSY; 2457 int count = 0; 2458 u32 value; 2459 2460 value = LLT_OP_WRITE | address << 8 | data; 2461 2462 rtl8xxxu_write32(priv, REG_LLT_INIT, value); 2463 2464 do { 2465 value = rtl8xxxu_read32(priv, REG_LLT_INIT); 2466 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) { 2467 ret = 0; 2468 break; 2469 } 2470 } while (count++ < 20); 2471 2472 return ret; 2473 } 2474 2475 int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page) 2476 { 2477 int ret; 2478 int i; 2479 2480 for (i = 0; i < last_tx_page; i++) { 2481 ret = rtl8xxxu_llt_write(priv, i, i + 1); 2482 if (ret) 2483 goto exit; 2484 } 2485 2486 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff); 2487 if (ret) 2488 goto exit; 2489 2490 /* Mark remaining pages as a ring buffer */ 2491 for (i = last_tx_page + 1; i < 0xff; i++) { 2492 ret = rtl8xxxu_llt_write(priv, i, (i + 1)); 2493 if (ret) 2494 goto exit; 2495 } 2496 2497 /* Let last entry point to the start entry of ring buffer */ 2498 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1); 2499 if (ret) 2500 goto exit; 2501 2502 exit: 2503 return ret; 2504 } 2505 2506 int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page) 2507 { 2508 u32 val32; 2509 int ret = 0; 2510 int i; 2511 2512 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT); 2513 val32 |= AUTO_LLT_INIT_LLT; 2514 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32); 2515 2516 for (i = 500; i; i--) { 2517 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT); 2518 if (!(val32 & AUTO_LLT_INIT_LLT)) 2519 break; 2520 usleep_range(2, 4); 2521 } 2522 2523 if (!i) { 2524 ret = -EBUSY; 2525 dev_warn(&priv->udev->dev, "LLT table init failed\n"); 2526 } 2527 2528 return ret; 2529 } 2530 2531 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv) 2532 { 2533 u16 val16, hi, lo; 2534 u16 hiq, mgq, bkq, beq, viq, voq; 2535 int hip, mgp, bkp, bep, vip, vop; 2536 int ret = 0; 2537 2538 switch (priv->ep_tx_count) { 2539 case 1: 2540 if (priv->ep_tx_high_queue) { 2541 hi = TRXDMA_QUEUE_HIGH; 2542 } else if (priv->ep_tx_low_queue) { 2543 hi = TRXDMA_QUEUE_LOW; 2544 } else if (priv->ep_tx_normal_queue) { 2545 hi = TRXDMA_QUEUE_NORMAL; 2546 } else { 2547 hi = 0; 2548 ret = -EINVAL; 2549 } 2550 2551 hiq = hi; 2552 mgq = hi; 2553 bkq = hi; 2554 beq = hi; 2555 viq = hi; 2556 voq = hi; 2557 2558 hip = 0; 2559 mgp = 0; 2560 bkp = 0; 2561 bep = 0; 2562 vip = 0; 2563 vop = 0; 2564 break; 2565 case 2: 2566 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) { 2567 hi = TRXDMA_QUEUE_HIGH; 2568 lo = TRXDMA_QUEUE_LOW; 2569 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) { 2570 hi = TRXDMA_QUEUE_NORMAL; 2571 lo = TRXDMA_QUEUE_LOW; 2572 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) { 2573 hi = TRXDMA_QUEUE_HIGH; 2574 lo = TRXDMA_QUEUE_NORMAL; 2575 } else { 2576 ret = -EINVAL; 2577 hi = 0; 2578 lo = 0; 2579 } 2580 2581 hiq = hi; 2582 mgq = hi; 2583 bkq = lo; 2584 beq = lo; 2585 viq = hi; 2586 voq = hi; 2587 2588 hip = 0; 2589 mgp = 0; 2590 bkp = 1; 2591 bep = 1; 2592 vip = 0; 2593 vop = 0; 2594 break; 2595 case 3: 2596 beq = TRXDMA_QUEUE_LOW; 2597 bkq = TRXDMA_QUEUE_LOW; 2598 viq = TRXDMA_QUEUE_NORMAL; 2599 voq = TRXDMA_QUEUE_HIGH; 2600 mgq = TRXDMA_QUEUE_HIGH; 2601 hiq = TRXDMA_QUEUE_HIGH; 2602 2603 hip = hiq ^ 3; 2604 mgp = mgq ^ 3; 2605 bkp = bkq ^ 3; 2606 bep = beq ^ 3; 2607 vip = viq ^ 3; 2608 vop = viq ^ 3; 2609 break; 2610 default: 2611 ret = -EINVAL; 2612 } 2613 2614 /* 2615 * None of the vendor drivers are configuring the beacon 2616 * queue here .... why? 2617 */ 2618 if (!ret) { 2619 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL); 2620 val16 &= 0x7; 2621 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) | 2622 (viq << TRXDMA_CTRL_VIQ_SHIFT) | 2623 (beq << TRXDMA_CTRL_BEQ_SHIFT) | 2624 (bkq << TRXDMA_CTRL_BKQ_SHIFT) | 2625 (mgq << TRXDMA_CTRL_MGQ_SHIFT) | 2626 (hiq << TRXDMA_CTRL_HIQ_SHIFT); 2627 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16); 2628 2629 priv->pipe_out[TXDESC_QUEUE_VO] = 2630 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]); 2631 priv->pipe_out[TXDESC_QUEUE_VI] = 2632 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]); 2633 priv->pipe_out[TXDESC_QUEUE_BE] = 2634 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]); 2635 priv->pipe_out[TXDESC_QUEUE_BK] = 2636 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]); 2637 priv->pipe_out[TXDESC_QUEUE_BEACON] = 2638 usb_sndbulkpipe(priv->udev, priv->out_ep[0]); 2639 priv->pipe_out[TXDESC_QUEUE_MGNT] = 2640 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]); 2641 priv->pipe_out[TXDESC_QUEUE_HIGH] = 2642 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]); 2643 priv->pipe_out[TXDESC_QUEUE_CMD] = 2644 usb_sndbulkpipe(priv->udev, priv->out_ep[0]); 2645 } 2646 2647 return ret; 2648 } 2649 2650 void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok, 2651 int result[][8], int candidate, bool tx_only) 2652 { 2653 u32 oldval, x, tx0_a, reg; 2654 int y, tx0_c; 2655 u32 val32; 2656 2657 if (!iqk_ok) 2658 return; 2659 2660 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); 2661 oldval = val32 >> 22; 2662 2663 x = result[candidate][0]; 2664 if ((x & 0x00000200) != 0) 2665 x = x | 0xfffffc00; 2666 tx0_a = (x * oldval) >> 8; 2667 2668 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); 2669 val32 &= ~0x3ff; 2670 val32 |= tx0_a; 2671 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); 2672 2673 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2674 val32 &= ~BIT(31); 2675 if ((x * oldval >> 7) & 0x1) 2676 val32 |= BIT(31); 2677 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2678 2679 y = result[candidate][1]; 2680 if ((y & 0x00000200) != 0) 2681 y = y | 0xfffffc00; 2682 tx0_c = (y * oldval) >> 8; 2683 2684 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE); 2685 val32 &= ~0xf0000000; 2686 val32 |= (((tx0_c & 0x3c0) >> 6) << 28); 2687 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32); 2688 2689 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); 2690 val32 &= ~0x003f0000; 2691 val32 |= ((tx0_c & 0x3f) << 16); 2692 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); 2693 2694 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2695 val32 &= ~BIT(29); 2696 if ((y * oldval >> 7) & 0x1) 2697 val32 |= BIT(29); 2698 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2699 2700 if (tx_only) { 2701 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__); 2702 return; 2703 } 2704 2705 reg = result[candidate][2]; 2706 2707 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); 2708 val32 &= ~0x3ff; 2709 val32 |= (reg & 0x3ff); 2710 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); 2711 2712 reg = result[candidate][3] & 0x3F; 2713 2714 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); 2715 val32 &= ~0xfc00; 2716 val32 |= ((reg << 10) & 0xfc00); 2717 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); 2718 2719 reg = (result[candidate][3] >> 6) & 0xF; 2720 2721 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA); 2722 val32 &= ~0xf0000000; 2723 val32 |= (reg << 28); 2724 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32); 2725 } 2726 2727 void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok, 2728 int result[][8], int candidate, bool tx_only) 2729 { 2730 u32 oldval, x, tx1_a, reg; 2731 int y, tx1_c; 2732 u32 val32; 2733 2734 if (!iqk_ok) 2735 return; 2736 2737 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); 2738 oldval = val32 >> 22; 2739 2740 x = result[candidate][4]; 2741 if ((x & 0x00000200) != 0) 2742 x = x | 0xfffffc00; 2743 tx1_a = (x * oldval) >> 8; 2744 2745 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); 2746 val32 &= ~0x3ff; 2747 val32 |= tx1_a; 2748 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); 2749 2750 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2751 val32 &= ~BIT(27); 2752 if ((x * oldval >> 7) & 0x1) 2753 val32 |= BIT(27); 2754 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2755 2756 y = result[candidate][5]; 2757 if ((y & 0x00000200) != 0) 2758 y = y | 0xfffffc00; 2759 tx1_c = (y * oldval) >> 8; 2760 2761 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE); 2762 val32 &= ~0xf0000000; 2763 val32 |= (((tx1_c & 0x3c0) >> 6) << 28); 2764 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32); 2765 2766 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); 2767 val32 &= ~0x003f0000; 2768 val32 |= ((tx1_c & 0x3f) << 16); 2769 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); 2770 2771 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2772 val32 &= ~BIT(25); 2773 if ((y * oldval >> 7) & 0x1) 2774 val32 |= BIT(25); 2775 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2776 2777 if (tx_only) { 2778 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__); 2779 return; 2780 } 2781 2782 reg = result[candidate][6]; 2783 2784 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); 2785 val32 &= ~0x3ff; 2786 val32 |= (reg & 0x3ff); 2787 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); 2788 2789 reg = result[candidate][7] & 0x3f; 2790 2791 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); 2792 val32 &= ~0xfc00; 2793 val32 |= ((reg << 10) & 0xfc00); 2794 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); 2795 2796 reg = (result[candidate][7] >> 6) & 0xf; 2797 2798 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE); 2799 val32 &= ~0x0000f000; 2800 val32 |= (reg << 12); 2801 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32); 2802 } 2803 2804 #define MAX_TOLERANCE 5 2805 2806 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv, 2807 int result[][8], int c1, int c2) 2808 { 2809 u32 i, j, diff, simubitmap, bound = 0; 2810 int candidate[2] = {-1, -1}; /* for path A and path B */ 2811 bool retval = true; 2812 2813 if (priv->tx_paths > 1) 2814 bound = 8; 2815 else 2816 bound = 4; 2817 2818 simubitmap = 0; 2819 2820 for (i = 0; i < bound; i++) { 2821 diff = (result[c1][i] > result[c2][i]) ? 2822 (result[c1][i] - result[c2][i]) : 2823 (result[c2][i] - result[c1][i]); 2824 if (diff > MAX_TOLERANCE) { 2825 if ((i == 2 || i == 6) && !simubitmap) { 2826 if (result[c1][i] + result[c1][i + 1] == 0) 2827 candidate[(i / 4)] = c2; 2828 else if (result[c2][i] + result[c2][i + 1] == 0) 2829 candidate[(i / 4)] = c1; 2830 else 2831 simubitmap = simubitmap | (1 << i); 2832 } else { 2833 simubitmap = simubitmap | (1 << i); 2834 } 2835 } 2836 } 2837 2838 if (simubitmap == 0) { 2839 for (i = 0; i < (bound / 4); i++) { 2840 if (candidate[i] >= 0) { 2841 for (j = i * 4; j < (i + 1) * 4 - 2; j++) 2842 result[3][j] = result[candidate[i]][j]; 2843 retval = false; 2844 } 2845 } 2846 return retval; 2847 } else if (!(simubitmap & 0x0f)) { 2848 /* path A OK */ 2849 for (i = 0; i < 4; i++) 2850 result[3][i] = result[c1][i]; 2851 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) { 2852 /* path B OK */ 2853 for (i = 4; i < 8; i++) 2854 result[3][i] = result[c1][i]; 2855 } 2856 2857 return false; 2858 } 2859 2860 bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv, 2861 int result[][8], int c1, int c2) 2862 { 2863 u32 i, j, diff, simubitmap, bound = 0; 2864 int candidate[2] = {-1, -1}; /* for path A and path B */ 2865 int tmp1, tmp2; 2866 bool retval = true; 2867 2868 if (priv->tx_paths > 1) 2869 bound = 8; 2870 else 2871 bound = 4; 2872 2873 simubitmap = 0; 2874 2875 for (i = 0; i < bound; i++) { 2876 if (i & 1) { 2877 if ((result[c1][i] & 0x00000200)) 2878 tmp1 = result[c1][i] | 0xfffffc00; 2879 else 2880 tmp1 = result[c1][i]; 2881 2882 if ((result[c2][i]& 0x00000200)) 2883 tmp2 = result[c2][i] | 0xfffffc00; 2884 else 2885 tmp2 = result[c2][i]; 2886 } else { 2887 tmp1 = result[c1][i]; 2888 tmp2 = result[c2][i]; 2889 } 2890 2891 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); 2892 2893 if (diff > MAX_TOLERANCE) { 2894 if ((i == 2 || i == 6) && !simubitmap) { 2895 if (result[c1][i] + result[c1][i + 1] == 0) 2896 candidate[(i / 4)] = c2; 2897 else if (result[c2][i] + result[c2][i + 1] == 0) 2898 candidate[(i / 4)] = c1; 2899 else 2900 simubitmap = simubitmap | (1 << i); 2901 } else { 2902 simubitmap = simubitmap | (1 << i); 2903 } 2904 } 2905 } 2906 2907 if (simubitmap == 0) { 2908 for (i = 0; i < (bound / 4); i++) { 2909 if (candidate[i] >= 0) { 2910 for (j = i * 4; j < (i + 1) * 4 - 2; j++) 2911 result[3][j] = result[candidate[i]][j]; 2912 retval = false; 2913 } 2914 } 2915 return retval; 2916 } else { 2917 if (!(simubitmap & 0x03)) { 2918 /* path A TX OK */ 2919 for (i = 0; i < 2; i++) 2920 result[3][i] = result[c1][i]; 2921 } 2922 2923 if (!(simubitmap & 0x0c)) { 2924 /* path A RX OK */ 2925 for (i = 2; i < 4; i++) 2926 result[3][i] = result[c1][i]; 2927 } 2928 2929 if (!(simubitmap & 0x30) && priv->tx_paths > 1) { 2930 /* path B RX OK */ 2931 for (i = 4; i < 6; i++) 2932 result[3][i] = result[c1][i]; 2933 } 2934 2935 if (!(simubitmap & 0x30) && priv->tx_paths > 1) { 2936 /* path B RX OK */ 2937 for (i = 6; i < 8; i++) 2938 result[3][i] = result[c1][i]; 2939 } 2940 } 2941 2942 return false; 2943 } 2944 2945 void 2946 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup) 2947 { 2948 int i; 2949 2950 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++) 2951 backup[i] = rtl8xxxu_read8(priv, reg[i]); 2952 2953 backup[i] = rtl8xxxu_read32(priv, reg[i]); 2954 } 2955 2956 void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv, 2957 const u32 *reg, u32 *backup) 2958 { 2959 int i; 2960 2961 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++) 2962 rtl8xxxu_write8(priv, reg[i], backup[i]); 2963 2964 rtl8xxxu_write32(priv, reg[i], backup[i]); 2965 } 2966 2967 void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 2968 u32 *backup, int count) 2969 { 2970 int i; 2971 2972 for (i = 0; i < count; i++) 2973 backup[i] = rtl8xxxu_read32(priv, regs[i]); 2974 } 2975 2976 void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 2977 u32 *backup, int count) 2978 { 2979 int i; 2980 2981 for (i = 0; i < count; i++) 2982 rtl8xxxu_write32(priv, regs[i], backup[i]); 2983 } 2984 2985 2986 void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs, 2987 bool path_a_on) 2988 { 2989 u32 path_on; 2990 int i; 2991 2992 if (priv->tx_paths == 1) { 2993 path_on = priv->fops->adda_1t_path_on; 2994 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init); 2995 } else { 2996 path_on = path_a_on ? priv->fops->adda_2t_path_on_a : 2997 priv->fops->adda_2t_path_on_b; 2998 2999 rtl8xxxu_write32(priv, regs[0], path_on); 3000 } 3001 3002 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++) 3003 rtl8xxxu_write32(priv, regs[i], path_on); 3004 } 3005 3006 void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv, 3007 const u32 *regs, u32 *backup) 3008 { 3009 int i = 0; 3010 3011 rtl8xxxu_write8(priv, regs[i], 0x3f); 3012 3013 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++) 3014 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3))); 3015 3016 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5))); 3017 } 3018 3019 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv) 3020 { 3021 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32; 3022 int result = 0; 3023 3024 /* path-A IQK setting */ 3025 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f); 3026 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f); 3027 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102); 3028 3029 val32 = (priv->rf_paths > 1) ? 0x28160202 : 3030 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */ 3031 0x28160502; 3032 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32); 3033 3034 /* path-B IQK setting */ 3035 if (priv->rf_paths > 1) { 3036 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22); 3037 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22); 3038 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102); 3039 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202); 3040 } 3041 3042 /* LO calibration setting */ 3043 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1); 3044 3045 /* One shot, path A LOK & IQK */ 3046 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 3047 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 3048 3049 mdelay(1); 3050 3051 /* Check failed */ 3052 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 3053 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 3054 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 3055 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); 3056 3057 if (!(reg_eac & BIT(28)) && 3058 ((reg_e94 & 0x03ff0000) != 0x01420000) && 3059 ((reg_e9c & 0x03ff0000) != 0x00420000)) 3060 result |= 0x01; 3061 else /* If TX not OK, ignore RX */ 3062 goto out; 3063 3064 /* If TX is OK, check whether RX is OK */ 3065 if (!(reg_eac & BIT(27)) && 3066 ((reg_ea4 & 0x03ff0000) != 0x01320000) && 3067 ((reg_eac & 0x03ff0000) != 0x00360000)) 3068 result |= 0x02; 3069 else 3070 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n", 3071 __func__); 3072 out: 3073 return result; 3074 } 3075 3076 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv) 3077 { 3078 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc; 3079 int result = 0; 3080 3081 /* One shot, path B LOK & IQK */ 3082 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002); 3083 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000); 3084 3085 mdelay(1); 3086 3087 /* Check failed */ 3088 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 3089 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 3090 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 3091 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); 3092 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); 3093 3094 if (!(reg_eac & BIT(31)) && 3095 ((reg_eb4 & 0x03ff0000) != 0x01420000) && 3096 ((reg_ebc & 0x03ff0000) != 0x00420000)) 3097 result |= 0x01; 3098 else 3099 goto out; 3100 3101 if (!(reg_eac & BIT(30)) && 3102 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) && 3103 (((reg_ecc & 0x03ff0000) >> 16) != 0x36)) 3104 result |= 0x02; 3105 else 3106 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", 3107 __func__); 3108 out: 3109 return result; 3110 } 3111 3112 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, 3113 int result[][8], int t) 3114 { 3115 struct device *dev = &priv->udev->dev; 3116 u32 i, val32; 3117 int path_a_ok, path_b_ok; 3118 int retry = 2; 3119 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { 3120 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, 3121 REG_RX_WAIT_CCA, REG_TX_CCK_RFON, 3122 REG_TX_CCK_BBON, REG_TX_OFDM_RFON, 3123 REG_TX_OFDM_BBON, REG_TX_TO_RX, 3124 REG_TX_TO_TX, REG_RX_CCK, 3125 REG_RX_OFDM, REG_RX_WAIT_RIFS, 3126 REG_RX_TO_RX, REG_STANDBY, 3127 REG_SLEEP, REG_PMPD_ANAEN 3128 }; 3129 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { 3130 REG_TXPAUSE, REG_BEACON_CTRL, 3131 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG 3132 }; 3133 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { 3134 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, 3135 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, 3136 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, 3137 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE 3138 }; 3139 3140 /* 3141 * Note: IQ calibration must be performed after loading 3142 * PHY_REG.txt , and radio_a, radio_b.txt 3143 */ 3144 3145 if (t == 0) { 3146 /* Save ADDA parameters, turn Path A ADDA on */ 3147 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, 3148 RTL8XXXU_ADDA_REGS); 3149 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 3150 rtl8xxxu_save_regs(priv, iqk_bb_regs, 3151 priv->bb_backup, RTL8XXXU_BB_REGS); 3152 } 3153 3154 rtl8xxxu_path_adda_on(priv, adda_regs, true); 3155 3156 if (t == 0) { 3157 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); 3158 if (val32 & FPGA0_HSSI_PARM1_PI) 3159 priv->pi_enabled = 1; 3160 } 3161 3162 if (!priv->pi_enabled) { 3163 /* Switch BB to PI mode to do IQ Calibration. */ 3164 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); 3165 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100); 3166 } 3167 3168 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 3169 val32 &= ~FPGA_RF_MODE_CCK; 3170 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 3171 3172 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); 3173 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); 3174 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); 3175 3176 if (!priv->no_pape) { 3177 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); 3178 val32 |= (FPGA0_RF_PAPE | 3179 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); 3180 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); 3181 } 3182 3183 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); 3184 val32 &= ~BIT(10); 3185 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); 3186 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); 3187 val32 &= ~BIT(10); 3188 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); 3189 3190 if (priv->tx_paths > 1) { 3191 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); 3192 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000); 3193 } 3194 3195 /* MAC settings */ 3196 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); 3197 3198 /* Page B init */ 3199 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000); 3200 3201 if (priv->tx_paths > 1) 3202 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000); 3203 3204 /* IQ calibration setting */ 3205 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); 3206 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 3207 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 3208 3209 for (i = 0; i < retry; i++) { 3210 path_a_ok = rtl8xxxu_iqk_path_a(priv); 3211 if (path_a_ok == 0x03) { 3212 val32 = rtl8xxxu_read32(priv, 3213 REG_TX_POWER_BEFORE_IQK_A); 3214 result[t][0] = (val32 >> 16) & 0x3ff; 3215 val32 = rtl8xxxu_read32(priv, 3216 REG_TX_POWER_AFTER_IQK_A); 3217 result[t][1] = (val32 >> 16) & 0x3ff; 3218 val32 = rtl8xxxu_read32(priv, 3219 REG_RX_POWER_BEFORE_IQK_A_2); 3220 result[t][2] = (val32 >> 16) & 0x3ff; 3221 val32 = rtl8xxxu_read32(priv, 3222 REG_RX_POWER_AFTER_IQK_A_2); 3223 result[t][3] = (val32 >> 16) & 0x3ff; 3224 break; 3225 } else if (i == (retry - 1) && path_a_ok == 0x01) { 3226 /* TX IQK OK */ 3227 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n", 3228 __func__); 3229 3230 val32 = rtl8xxxu_read32(priv, 3231 REG_TX_POWER_BEFORE_IQK_A); 3232 result[t][0] = (val32 >> 16) & 0x3ff; 3233 val32 = rtl8xxxu_read32(priv, 3234 REG_TX_POWER_AFTER_IQK_A); 3235 result[t][1] = (val32 >> 16) & 0x3ff; 3236 } 3237 } 3238 3239 if (!path_a_ok) 3240 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__); 3241 3242 if (priv->tx_paths > 1) { 3243 /* 3244 * Path A into standby 3245 */ 3246 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0); 3247 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); 3248 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); 3249 3250 /* Turn Path B ADDA on */ 3251 rtl8xxxu_path_adda_on(priv, adda_regs, false); 3252 3253 for (i = 0; i < retry; i++) { 3254 path_b_ok = rtl8xxxu_iqk_path_b(priv); 3255 if (path_b_ok == 0x03) { 3256 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 3257 result[t][4] = (val32 >> 16) & 0x3ff; 3258 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 3259 result[t][5] = (val32 >> 16) & 0x3ff; 3260 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); 3261 result[t][6] = (val32 >> 16) & 0x3ff; 3262 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); 3263 result[t][7] = (val32 >> 16) & 0x3ff; 3264 break; 3265 } else if (i == (retry - 1) && path_b_ok == 0x01) { 3266 /* TX IQK OK */ 3267 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 3268 result[t][4] = (val32 >> 16) & 0x3ff; 3269 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 3270 result[t][5] = (val32 >> 16) & 0x3ff; 3271 } 3272 } 3273 3274 if (!path_b_ok) 3275 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__); 3276 } 3277 3278 /* Back to BB mode, load original value */ 3279 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0); 3280 3281 if (t) { 3282 if (!priv->pi_enabled) { 3283 /* 3284 * Switch back BB to SI mode after finishing 3285 * IQ Calibration 3286 */ 3287 val32 = 0x01000000; 3288 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32); 3289 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32); 3290 } 3291 3292 /* Reload ADDA power saving parameters */ 3293 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, 3294 RTL8XXXU_ADDA_REGS); 3295 3296 /* Reload MAC parameters */ 3297 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 3298 3299 /* Reload BB parameters */ 3300 rtl8xxxu_restore_regs(priv, iqk_bb_regs, 3301 priv->bb_backup, RTL8XXXU_BB_REGS); 3302 3303 /* Restore RX initial gain */ 3304 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3); 3305 3306 if (priv->tx_paths > 1) { 3307 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 3308 0x00032ed3); 3309 } 3310 3311 /* Load 0xe30 IQC default value */ 3312 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); 3313 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); 3314 } 3315 } 3316 3317 void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start) 3318 { 3319 struct h2c_cmd h2c; 3320 3321 memset(&h2c, 0, sizeof(struct h2c_cmd)); 3322 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION; 3323 h2c.bt_wlan_calibration.data = start; 3324 3325 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration)); 3326 } 3327 3328 void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv) 3329 { 3330 struct device *dev = &priv->udev->dev; 3331 int result[4][8]; /* last is final result */ 3332 int i, candidate; 3333 bool path_a_ok, path_b_ok; 3334 u32 reg_e94, reg_e9c, reg_ea4, reg_eac; 3335 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; 3336 s32 reg_tmp = 0; 3337 bool simu; 3338 3339 memset(result, 0, sizeof(result)); 3340 candidate = -1; 3341 3342 path_a_ok = false; 3343 path_b_ok = false; 3344 3345 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 3346 3347 for (i = 0; i < 3; i++) { 3348 rtl8xxxu_phy_iqcalibrate(priv, result, i); 3349 3350 if (i == 1) { 3351 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1); 3352 if (simu) { 3353 candidate = 0; 3354 break; 3355 } 3356 } 3357 3358 if (i == 2) { 3359 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2); 3360 if (simu) { 3361 candidate = 0; 3362 break; 3363 } 3364 3365 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2); 3366 if (simu) { 3367 candidate = 1; 3368 } else { 3369 for (i = 0; i < 8; i++) 3370 reg_tmp += result[3][i]; 3371 3372 if (reg_tmp) 3373 candidate = 3; 3374 else 3375 candidate = -1; 3376 } 3377 } 3378 } 3379 3380 for (i = 0; i < 4; i++) { 3381 reg_e94 = result[i][0]; 3382 reg_e9c = result[i][1]; 3383 reg_ea4 = result[i][2]; 3384 reg_eac = result[i][3]; 3385 reg_eb4 = result[i][4]; 3386 reg_ebc = result[i][5]; 3387 reg_ec4 = result[i][6]; 3388 reg_ecc = result[i][7]; 3389 } 3390 3391 if (candidate >= 0) { 3392 reg_e94 = result[candidate][0]; 3393 priv->rege94 = reg_e94; 3394 reg_e9c = result[candidate][1]; 3395 priv->rege9c = reg_e9c; 3396 reg_ea4 = result[candidate][2]; 3397 reg_eac = result[candidate][3]; 3398 reg_eb4 = result[candidate][4]; 3399 priv->regeb4 = reg_eb4; 3400 reg_ebc = result[candidate][5]; 3401 priv->regebc = reg_ebc; 3402 reg_ec4 = result[candidate][6]; 3403 reg_ecc = result[candidate][7]; 3404 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); 3405 dev_dbg(dev, 3406 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x " 3407 "ecc=%x\n ", __func__, reg_e94, reg_e9c, 3408 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); 3409 path_a_ok = true; 3410 path_b_ok = true; 3411 } else { 3412 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; 3413 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; 3414 } 3415 3416 if (reg_e94 && candidate >= 0) 3417 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, 3418 candidate, (reg_ea4 == 0)); 3419 3420 if (priv->tx_paths > 1 && reg_eb4) 3421 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, 3422 candidate, (reg_ec4 == 0)); 3423 3424 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, 3425 priv->bb_recovery_backup, RTL8XXXU_BB_REGS); 3426 } 3427 3428 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv) 3429 { 3430 u32 val32; 3431 u32 rf_amode, rf_bmode = 0, lstf; 3432 3433 /* Check continuous TX and Packet TX */ 3434 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 3435 3436 if (lstf & OFDM_LSTF_MASK) { 3437 /* Disable all continuous TX */ 3438 val32 = lstf & ~OFDM_LSTF_MASK; 3439 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 3440 3441 /* Read original RF mode Path A */ 3442 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC); 3443 3444 /* Set RF mode to standby Path A */ 3445 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 3446 (rf_amode & 0x8ffff) | 0x10000); 3447 3448 /* Path-B */ 3449 if (priv->tx_paths > 1) { 3450 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B, 3451 RF6052_REG_AC); 3452 3453 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 3454 (rf_bmode & 0x8ffff) | 0x10000); 3455 } 3456 } else { 3457 /* Deal with Packet TX case */ 3458 /* block all queues */ 3459 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 3460 } 3461 3462 /* Start LC calibration */ 3463 if (priv->fops->has_s0s1) 3464 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0); 3465 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); 3466 val32 |= 0x08000; 3467 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); 3468 3469 msleep(100); 3470 3471 if (priv->fops->has_s0s1) 3472 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0); 3473 3474 /* Restore original parameters */ 3475 if (lstf & OFDM_LSTF_MASK) { 3476 /* Path-A */ 3477 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf); 3478 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode); 3479 3480 /* Path-B */ 3481 if (priv->tx_paths > 1) 3482 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 3483 rf_bmode); 3484 } else /* Deal with Packet TX case */ 3485 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); 3486 } 3487 3488 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv) 3489 { 3490 int i; 3491 u16 reg; 3492 3493 reg = REG_MACID; 3494 3495 for (i = 0; i < ETH_ALEN; i++) 3496 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]); 3497 3498 return 0; 3499 } 3500 3501 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid) 3502 { 3503 int i; 3504 u16 reg; 3505 3506 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid); 3507 3508 reg = REG_BSSID; 3509 3510 for (i = 0; i < ETH_ALEN; i++) 3511 rtl8xxxu_write8(priv, reg + i, bssid[i]); 3512 3513 return 0; 3514 } 3515 3516 static void 3517 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor) 3518 { 3519 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 }; 3520 u8 max_agg = 0xf; 3521 int i; 3522 3523 ampdu_factor = 1 << (ampdu_factor + 2); 3524 if (ampdu_factor > max_agg) 3525 ampdu_factor = max_agg; 3526 3527 for (i = 0; i < 4; i++) { 3528 if ((vals[i] & 0xf0) > (ampdu_factor << 4)) 3529 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4); 3530 3531 if ((vals[i] & 0x0f) > ampdu_factor) 3532 vals[i] = (vals[i] & 0xf0) | ampdu_factor; 3533 3534 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]); 3535 } 3536 } 3537 3538 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density) 3539 { 3540 u8 val8; 3541 3542 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE); 3543 val8 &= 0xf8; 3544 val8 |= density; 3545 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8); 3546 } 3547 3548 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv) 3549 { 3550 u8 val8; 3551 int count, ret = 0; 3552 3553 /* Start of rtl8723AU_card_enable_flow */ 3554 /* Act to Cardemu sequence*/ 3555 /* Turn off RF */ 3556 rtl8xxxu_write8(priv, REG_RF_CTRL, 0); 3557 3558 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */ 3559 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); 3560 val8 &= ~LEDCFG2_DPDT_SELECT; 3561 rtl8xxxu_write8(priv, REG_LEDCFG2, val8); 3562 3563 /* 0x0005[1] = 1 turn off MAC by HW state machine*/ 3564 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3565 val8 |= BIT(1); 3566 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3567 3568 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 3569 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3570 if ((val8 & BIT(1)) == 0) 3571 break; 3572 udelay(10); 3573 } 3574 3575 if (!count) { 3576 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", 3577 __func__); 3578 ret = -EBUSY; 3579 goto exit; 3580 } 3581 3582 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */ 3583 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); 3584 val8 |= SYS_ISO_ANALOG_IPS; 3585 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); 3586 3587 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/ 3588 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); 3589 val8 &= ~LDOA15_ENABLE; 3590 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); 3591 3592 exit: 3593 return ret; 3594 } 3595 3596 int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv) 3597 { 3598 u8 val8; 3599 u8 val32; 3600 int count, ret = 0; 3601 3602 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 3603 3604 /* 3605 * Poll - wait for RX packet to complete 3606 */ 3607 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 3608 val32 = rtl8xxxu_read32(priv, 0x5f8); 3609 if (!val32) 3610 break; 3611 udelay(10); 3612 } 3613 3614 if (!count) { 3615 dev_warn(&priv->udev->dev, 3616 "%s: RX poll timed out (0x05f8)\n", __func__); 3617 ret = -EBUSY; 3618 goto exit; 3619 } 3620 3621 /* Disable CCK and OFDM, clock gated */ 3622 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 3623 val8 &= ~SYS_FUNC_BBRSTB; 3624 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 3625 3626 udelay(2); 3627 3628 /* Reset baseband */ 3629 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 3630 val8 &= ~SYS_FUNC_BB_GLB_RSTN; 3631 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 3632 3633 /* Reset MAC TRX */ 3634 val8 = rtl8xxxu_read8(priv, REG_CR); 3635 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE; 3636 rtl8xxxu_write8(priv, REG_CR, val8); 3637 3638 /* Reset MAC TRX */ 3639 val8 = rtl8xxxu_read8(priv, REG_CR + 1); 3640 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */ 3641 rtl8xxxu_write8(priv, REG_CR + 1, val8); 3642 3643 /* Respond TX OK to scheduler */ 3644 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); 3645 val8 |= DUAL_TSF_TX_OK; 3646 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); 3647 3648 exit: 3649 return ret; 3650 } 3651 3652 void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv) 3653 { 3654 u8 val8; 3655 3656 /* Clear suspend enable and power down enable*/ 3657 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3658 val8 &= ~(BIT(3) | BIT(7)); 3659 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3660 3661 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ 3662 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); 3663 val8 &= ~BIT(0); 3664 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); 3665 3666 /* 0x04[12:11] = 11 enable WL suspend*/ 3667 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3668 val8 &= ~(BIT(3) | BIT(4)); 3669 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3670 } 3671 3672 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv) 3673 { 3674 u8 val8; 3675 3676 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */ 3677 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20); 3678 3679 /* 0x04[12:11] = 01 enable WL suspend */ 3680 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3681 val8 &= ~BIT(4); 3682 val8 |= BIT(3); 3683 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3684 3685 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3686 val8 |= BIT(7); 3687 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3688 3689 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */ 3690 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); 3691 val8 |= BIT(0); 3692 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); 3693 3694 return 0; 3695 } 3696 3697 int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv) 3698 { 3699 struct device *dev = &priv->udev->dev; 3700 u32 val32; 3701 int retry, retval; 3702 3703 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 3704 3705 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM); 3706 val32 |= RXPKT_NUM_RW_RELEASE_EN; 3707 rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32); 3708 3709 retry = 100; 3710 retval = -EBUSY; 3711 3712 do { 3713 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM); 3714 if (val32 & RXPKT_NUM_RXDMA_IDLE) { 3715 retval = 0; 3716 break; 3717 } 3718 } while (retry--); 3719 3720 rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0); 3721 rtl8xxxu_write32(priv, REG_RQPN, 0x80000000); 3722 mdelay(2); 3723 3724 if (!retry) 3725 dev_warn(dev, "Failed to flush FIFO\n"); 3726 3727 return retval; 3728 } 3729 3730 void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv) 3731 { 3732 /* Fix USB interface interference issue */ 3733 rtl8xxxu_write8(priv, 0xfe40, 0xe0); 3734 rtl8xxxu_write8(priv, 0xfe41, 0x8d); 3735 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3736 /* 3737 * This sets TXDMA_OFFSET_DROP_DATA_EN (bit 9) as well as bits 3738 * 8 and 5, for which I have found no documentation. 3739 */ 3740 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320); 3741 3742 /* 3743 * Solve too many protocol error on USB bus. 3744 * Can't do this for 8188/8192 UMC A cut parts 3745 */ 3746 if (!(!priv->chip_cut && priv->vendor_umc)) { 3747 rtl8xxxu_write8(priv, 0xfe40, 0xe6); 3748 rtl8xxxu_write8(priv, 0xfe41, 0x94); 3749 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3750 3751 rtl8xxxu_write8(priv, 0xfe40, 0xe0); 3752 rtl8xxxu_write8(priv, 0xfe41, 0x19); 3753 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3754 3755 rtl8xxxu_write8(priv, 0xfe40, 0xe5); 3756 rtl8xxxu_write8(priv, 0xfe41, 0x91); 3757 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3758 3759 rtl8xxxu_write8(priv, 0xfe40, 0xe2); 3760 rtl8xxxu_write8(priv, 0xfe41, 0x81); 3761 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3762 } 3763 } 3764 3765 void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv) 3766 { 3767 u32 val32; 3768 3769 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK); 3770 val32 |= TXDMA_OFFSET_DROP_DATA_EN; 3771 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32); 3772 } 3773 3774 void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv) 3775 { 3776 u8 val8; 3777 u16 val16; 3778 u32 val32; 3779 3780 /* 3781 * Workaround for 8188RU LNA power leakage problem. 3782 */ 3783 if (priv->rtl_chip == RTL8188R) { 3784 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM); 3785 val32 |= BIT(1); 3786 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32); 3787 } 3788 3789 rtl8xxxu_flush_fifo(priv); 3790 3791 rtl8xxxu_active_to_lps(priv); 3792 3793 /* Turn off RF */ 3794 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); 3795 3796 /* Reset Firmware if running in RAM */ 3797 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) 3798 rtl8xxxu_firmware_self_reset(priv); 3799 3800 /* Reset MCU */ 3801 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 3802 val16 &= ~SYS_FUNC_CPU_ENABLE; 3803 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 3804 3805 /* Reset MCU ready status */ 3806 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); 3807 3808 rtl8xxxu_active_to_emu(priv); 3809 rtl8xxxu_emu_to_disabled(priv); 3810 3811 /* Reset MCU IO Wrapper */ 3812 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 3813 val8 &= ~BIT(0); 3814 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 3815 3816 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 3817 val8 |= BIT(0); 3818 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 3819 3820 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */ 3821 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e); 3822 } 3823 3824 #ifdef NEED_PS_TDMA 3825 static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv, 3826 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5) 3827 { 3828 struct h2c_cmd h2c; 3829 3830 memset(&h2c, 0, sizeof(struct h2c_cmd)); 3831 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA; 3832 h2c.b_type_dma.data1 = arg1; 3833 h2c.b_type_dma.data2 = arg2; 3834 h2c.b_type_dma.data3 = arg3; 3835 h2c.b_type_dma.data4 = arg4; 3836 h2c.b_type_dma.data5 = arg5; 3837 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma)); 3838 } 3839 #endif 3840 3841 void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv) 3842 { 3843 u32 val32; 3844 3845 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); 3846 val32 &= ~(BIT(22) | BIT(23)); 3847 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); 3848 } 3849 3850 static void rtl8xxxu_old_init_queue_reserved_page(struct rtl8xxxu_priv *priv) 3851 { 3852 u8 val8; 3853 u32 val32; 3854 3855 if (priv->ep_tx_normal_queue) 3856 val8 = TX_PAGE_NUM_NORM_PQ; 3857 else 3858 val8 = 0; 3859 3860 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8); 3861 3862 val32 = (TX_PAGE_NUM_PUBQ << RQPN_PUB_PQ_SHIFT) | RQPN_LOAD; 3863 3864 if (priv->ep_tx_high_queue) 3865 val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT); 3866 if (priv->ep_tx_low_queue) 3867 val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT); 3868 3869 rtl8xxxu_write32(priv, REG_RQPN, val32); 3870 } 3871 3872 static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv *priv) 3873 { 3874 struct rtl8xxxu_fileops *fops = priv->fops; 3875 u32 hq, lq, nq, eq, pubq; 3876 u32 val32; 3877 3878 hq = 0; 3879 lq = 0; 3880 nq = 0; 3881 eq = 0; 3882 pubq = 0; 3883 3884 if (priv->ep_tx_high_queue) 3885 hq = fops->page_num_hi; 3886 if (priv->ep_tx_low_queue) 3887 lq = fops->page_num_lo; 3888 if (priv->ep_tx_normal_queue) 3889 nq = fops->page_num_norm; 3890 3891 val32 = (nq << RQPN_NPQ_SHIFT) | (eq << RQPN_EPQ_SHIFT); 3892 rtl8xxxu_write32(priv, REG_RQPN_NPQ, val32); 3893 3894 pubq = fops->total_page_num - hq - lq - nq; 3895 3896 val32 = RQPN_LOAD; 3897 val32 |= (hq << RQPN_HI_PQ_SHIFT); 3898 val32 |= (lq << RQPN_LO_PQ_SHIFT); 3899 val32 |= (pubq << RQPN_PUB_PQ_SHIFT); 3900 3901 rtl8xxxu_write32(priv, REG_RQPN, val32); 3902 } 3903 3904 static int rtl8xxxu_init_device(struct ieee80211_hw *hw) 3905 { 3906 struct rtl8xxxu_priv *priv = hw->priv; 3907 struct device *dev = &priv->udev->dev; 3908 bool macpower; 3909 int ret; 3910 u8 val8; 3911 u16 val16; 3912 u32 val32; 3913 3914 /* Check if MAC is already powered on */ 3915 val8 = rtl8xxxu_read8(priv, REG_CR); 3916 3917 /* 3918 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not 3919 * initialized. First MAC returns 0xea, second MAC returns 0x00 3920 */ 3921 if (val8 == 0xea) 3922 macpower = false; 3923 else 3924 macpower = true; 3925 3926 ret = priv->fops->power_on(priv); 3927 if (ret < 0) { 3928 dev_warn(dev, "%s: Failed power on\n", __func__); 3929 goto exit; 3930 } 3931 3932 if (!macpower) { 3933 if (priv->fops->total_page_num) 3934 rtl8xxxu_init_queue_reserved_page(priv); 3935 else 3936 rtl8xxxu_old_init_queue_reserved_page(priv); 3937 } 3938 3939 ret = rtl8xxxu_init_queue_priority(priv); 3940 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret); 3941 if (ret) 3942 goto exit; 3943 3944 /* 3945 * Set RX page boundary 3946 */ 3947 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, priv->fops->trxff_boundary); 3948 3949 ret = rtl8xxxu_download_firmware(priv); 3950 dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret); 3951 if (ret) 3952 goto exit; 3953 ret = rtl8xxxu_start_firmware(priv); 3954 dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret); 3955 if (ret) 3956 goto exit; 3957 3958 if (priv->fops->phy_init_antenna_selection) 3959 priv->fops->phy_init_antenna_selection(priv); 3960 3961 ret = rtl8xxxu_init_mac(priv); 3962 3963 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret); 3964 if (ret) 3965 goto exit; 3966 3967 ret = rtl8xxxu_init_phy_bb(priv); 3968 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret); 3969 if (ret) 3970 goto exit; 3971 3972 ret = priv->fops->init_phy_rf(priv); 3973 if (ret) 3974 goto exit; 3975 3976 /* RFSW Control - clear bit 14 ?? */ 3977 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E) 3978 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003); 3979 3980 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW | 3981 FPGA0_RF_ANTSWB | 3982 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB) << FPGA0_RF_BD_CTRL_SHIFT); 3983 if (!priv->no_pape) { 3984 val32 |= (FPGA0_RF_PAPE | 3985 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); 3986 } 3987 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); 3988 3989 /* 0x860[6:5]= 00 - why? - this sets antenna B */ 3990 if (priv->rtl_chip != RTL8192E) 3991 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210); 3992 3993 if (!macpower) { 3994 /* 3995 * Set TX buffer boundary 3996 */ 3997 if (priv->rtl_chip == RTL8192E) 3998 val8 = TX_TOTAL_PAGE_NUM_8192E + 1; 3999 else 4000 val8 = TX_TOTAL_PAGE_NUM + 1; 4001 4002 if (priv->rtl_chip == RTL8723B) 4003 val8 -= 1; 4004 4005 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8); 4006 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8); 4007 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8); 4008 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8); 4009 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8); 4010 } 4011 4012 /* 4013 * The vendor drivers set PBP for all devices, except 8192e. 4014 * There is no explanation for this in any of the sources. 4015 */ 4016 val8 = (priv->fops->pbp_rx << PBP_PAGE_SIZE_RX_SHIFT) | 4017 (priv->fops->pbp_tx << PBP_PAGE_SIZE_TX_SHIFT); 4018 if (priv->rtl_chip != RTL8192E) 4019 rtl8xxxu_write8(priv, REG_PBP, val8); 4020 4021 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower); 4022 if (!macpower) { 4023 ret = priv->fops->llt_init(priv, TX_TOTAL_PAGE_NUM); 4024 if (ret) { 4025 dev_warn(dev, "%s: LLT table init failed\n", __func__); 4026 goto exit; 4027 } 4028 4029 /* 4030 * Chip specific quirks 4031 */ 4032 priv->fops->usb_quirks(priv); 4033 4034 /* 4035 * Presumably this is for 8188EU as well 4036 * Enable TX report and TX report timer 4037 */ 4038 if (priv->rtl_chip == RTL8723B) { 4039 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); 4040 val8 |= TX_REPORT_CTRL_TIMER_ENABLE; 4041 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); 4042 /* Set MAX RPT MACID */ 4043 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02); 4044 /* TX report Timer. Unit: 32us */ 4045 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0); 4046 4047 /* tmp ps ? */ 4048 val8 = rtl8xxxu_read8(priv, 0xa3); 4049 val8 &= 0xf8; 4050 rtl8xxxu_write8(priv, 0xa3, val8); 4051 } 4052 } 4053 4054 /* 4055 * Unit in 8 bytes, not obvious what it is used for 4056 */ 4057 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4); 4058 4059 if (priv->rtl_chip == RTL8192E) { 4060 rtl8xxxu_write32(priv, REG_HIMR0, 0x00); 4061 rtl8xxxu_write32(priv, REG_HIMR1, 0x00); 4062 } else { 4063 /* 4064 * Enable all interrupts - not obvious USB needs to do this 4065 */ 4066 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff); 4067 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff); 4068 } 4069 4070 rtl8xxxu_set_mac(priv); 4071 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION); 4072 4073 /* 4074 * Configure initial WMAC settings 4075 */ 4076 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST | 4077 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL | 4078 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC; 4079 rtl8xxxu_write32(priv, REG_RCR, val32); 4080 4081 /* 4082 * Accept all multicast 4083 */ 4084 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff); 4085 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff); 4086 4087 /* 4088 * Init adaptive controls 4089 */ 4090 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 4091 val32 &= ~RESPONSE_RATE_BITMAP_ALL; 4092 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M; 4093 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 4094 4095 /* CCK = 0x0a, OFDM = 0x10 */ 4096 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10); 4097 rtl8xxxu_set_retry(priv, 0x30, 0x30); 4098 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10); 4099 4100 /* 4101 * Init EDCA 4102 */ 4103 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a); 4104 4105 /* Set CCK SIFS */ 4106 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a); 4107 4108 /* Set OFDM SIFS */ 4109 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a); 4110 4111 /* TXOP */ 4112 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b); 4113 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f); 4114 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324); 4115 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226); 4116 4117 /* Set data auto rate fallback retry count */ 4118 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000); 4119 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404); 4120 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201); 4121 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605); 4122 4123 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL); 4124 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY; 4125 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8); 4126 4127 /* Set ACK timeout */ 4128 rtl8xxxu_write8(priv, REG_ACKTO, 0x40); 4129 4130 /* 4131 * Initialize beacon parameters 4132 */ 4133 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8); 4134 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16); 4135 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404); 4136 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME); 4137 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME); 4138 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F); 4139 4140 /* 4141 * Initialize burst parameters 4142 */ 4143 if (priv->rtl_chip == RTL8723B) { 4144 /* 4145 * For USB high speed set 512B packets 4146 */ 4147 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B); 4148 val8 &= ~(BIT(4) | BIT(5)); 4149 val8 |= BIT(4); 4150 val8 |= BIT(1) | BIT(2) | BIT(3); 4151 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8); 4152 4153 /* 4154 * For USB high speed set 512B packets 4155 */ 4156 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B); 4157 val8 |= BIT(7); 4158 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8); 4159 4160 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14); 4161 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 0x5e); 4162 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff); 4163 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18); 4164 rtl8xxxu_write8(priv, REG_PIFS, 0x00); 4165 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, 0x50); 4166 rtl8xxxu_write8(priv, REG_USTIME_EDCA, 0x50); 4167 4168 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); 4169 val8 |= BIT(5) | BIT(6); 4170 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); 4171 } 4172 4173 if (priv->fops->init_aggregation) 4174 priv->fops->init_aggregation(priv); 4175 4176 /* 4177 * Enable CCK and OFDM block 4178 */ 4179 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 4180 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM); 4181 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 4182 4183 /* 4184 * Invalidate all CAM entries - bit 30 is undocumented 4185 */ 4186 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30)); 4187 4188 /* 4189 * Start out with default power levels for channel 6, 20MHz 4190 */ 4191 priv->fops->set_tx_power(priv, 1, false); 4192 4193 /* Let the 8051 take control of antenna setting */ 4194 if (priv->rtl_chip != RTL8192E) { 4195 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); 4196 val8 |= LEDCFG2_DPDT_SELECT; 4197 rtl8xxxu_write8(priv, REG_LEDCFG2, val8); 4198 } 4199 4200 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff); 4201 4202 /* Disable BAR - not sure if this has any effect on USB */ 4203 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff); 4204 4205 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0); 4206 4207 if (priv->fops->init_statistics) 4208 priv->fops->init_statistics(priv); 4209 4210 if (priv->rtl_chip == RTL8192E) { 4211 /* 4212 * 0x4c6[3] 1: RTS BW = Data BW 4213 * 0: RTS BW depends on CCA / secondary CCA result. 4214 */ 4215 val8 = rtl8xxxu_read8(priv, REG_QUEUE_CTRL); 4216 val8 &= ~BIT(3); 4217 rtl8xxxu_write8(priv, REG_QUEUE_CTRL, val8); 4218 /* 4219 * Reset USB mode switch setting 4220 */ 4221 rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00); 4222 } 4223 4224 rtl8723a_phy_lc_calibrate(priv); 4225 4226 priv->fops->phy_iq_calibrate(priv); 4227 4228 /* 4229 * This should enable thermal meter 4230 */ 4231 if (priv->fops->tx_desc_size == sizeof(struct rtl8xxxu_txdesc40)) 4232 rtl8xxxu_write_rfreg(priv, 4233 RF_A, RF6052_REG_T_METER_8723B, 0x37cf8); 4234 else 4235 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60); 4236 4237 /* Set NAV_UPPER to 30000us */ 4238 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT); 4239 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8); 4240 4241 if (priv->rtl_chip == RTL8723A) { 4242 /* 4243 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test, 4244 * but we need to find root cause. 4245 * This is 8723au only. 4246 */ 4247 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 4248 if ((val32 & 0xff000000) != 0x83000000) { 4249 val32 |= FPGA_RF_MODE_CCK; 4250 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 4251 } 4252 } else if (priv->rtl_chip == RTL8192E) { 4253 rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00); 4254 } 4255 4256 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL); 4257 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK; 4258 /* ack for xmit mgmt frames. */ 4259 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32); 4260 4261 if (priv->rtl_chip == RTL8192E) { 4262 /* 4263 * Fix LDPC rx hang issue. 4264 */ 4265 val32 = rtl8xxxu_read32(priv, REG_AFE_MISC); 4266 rtl8xxxu_write8(priv, REG_8192E_LDOV12_CTRL, 0x75); 4267 val32 &= 0xfff00fff; 4268 val32 |= 0x0007e000; 4269 rtl8xxxu_write32(priv, REG_AFE_MISC, val32); 4270 } 4271 exit: 4272 return ret; 4273 } 4274 4275 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv, 4276 struct ieee80211_key_conf *key, const u8 *mac) 4277 { 4278 u32 cmd, val32, addr, ctrl; 4279 int j, i, tmp_debug; 4280 4281 tmp_debug = rtl8xxxu_debug; 4282 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY) 4283 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE; 4284 4285 /* 4286 * This is a bit of a hack - the lower bits of the cipher 4287 * suite selector happens to match the cipher index in the CAM 4288 */ 4289 addr = key->keyidx << CAM_CMD_KEY_SHIFT; 4290 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID; 4291 4292 for (j = 5; j >= 0; j--) { 4293 switch (j) { 4294 case 0: 4295 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24); 4296 break; 4297 case 1: 4298 val32 = mac[2] | (mac[3] << 8) | 4299 (mac[4] << 16) | (mac[5] << 24); 4300 break; 4301 default: 4302 i = (j - 2) << 2; 4303 val32 = key->key[i] | (key->key[i + 1] << 8) | 4304 key->key[i + 2] << 16 | key->key[i + 3] << 24; 4305 break; 4306 } 4307 4308 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32); 4309 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j); 4310 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd); 4311 udelay(100); 4312 } 4313 4314 rtl8xxxu_debug = tmp_debug; 4315 } 4316 4317 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw, 4318 struct ieee80211_vif *vif, const u8 *mac) 4319 { 4320 struct rtl8xxxu_priv *priv = hw->priv; 4321 u8 val8; 4322 4323 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 4324 val8 |= BEACON_DISABLE_TSF_UPDATE; 4325 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 4326 } 4327 4328 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw, 4329 struct ieee80211_vif *vif) 4330 { 4331 struct rtl8xxxu_priv *priv = hw->priv; 4332 u8 val8; 4333 4334 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 4335 val8 &= ~BEACON_DISABLE_TSF_UPDATE; 4336 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 4337 } 4338 4339 void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv, u32 ramask, int sgi) 4340 { 4341 struct h2c_cmd h2c; 4342 4343 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4344 4345 h2c.ramask.cmd = H2C_SET_RATE_MASK; 4346 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff); 4347 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16); 4348 4349 h2c.ramask.arg = 0x80; 4350 if (sgi) 4351 h2c.ramask.arg |= 0x20; 4352 4353 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n", 4354 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask)); 4355 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.ramask)); 4356 } 4357 4358 void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv, 4359 u32 ramask, int sgi) 4360 { 4361 struct h2c_cmd h2c; 4362 u8 bw = 0; 4363 4364 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4365 4366 h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID; 4367 h2c.b_macid_cfg.ramask0 = ramask & 0xff; 4368 h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff; 4369 h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff; 4370 h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff; 4371 4372 h2c.ramask.arg = 0x80; 4373 h2c.b_macid_cfg.data1 = 0; 4374 if (sgi) 4375 h2c.b_macid_cfg.data1 |= BIT(7); 4376 4377 h2c.b_macid_cfg.data2 = bw; 4378 4379 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n", 4380 __func__, ramask, h2c.ramask.arg, sizeof(h2c.b_macid_cfg)); 4381 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg)); 4382 } 4383 4384 void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv, 4385 u8 macid, bool connect) 4386 { 4387 struct h2c_cmd h2c; 4388 4389 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4390 4391 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT; 4392 4393 if (connect) 4394 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT; 4395 else 4396 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT; 4397 4398 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss)); 4399 } 4400 4401 void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv, 4402 u8 macid, bool connect) 4403 { 4404 struct h2c_cmd h2c; 4405 4406 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4407 4408 h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT; 4409 if (connect) 4410 h2c.media_status_rpt.parm |= BIT(0); 4411 else 4412 h2c.media_status_rpt.parm &= ~BIT(0); 4413 4414 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt)); 4415 } 4416 4417 void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv) 4418 { 4419 u8 agg_ctrl, usb_spec, page_thresh, timeout; 4420 4421 usb_spec = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION); 4422 usb_spec &= ~USB_SPEC_USB_AGG_ENABLE; 4423 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, usb_spec); 4424 4425 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); 4426 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; 4427 4428 if (!rtl8xxxu_dma_aggregation) { 4429 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); 4430 return; 4431 } 4432 4433 agg_ctrl |= TRXDMA_CTRL_RXDMA_AGG_EN; 4434 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); 4435 4436 /* 4437 * The number of packets we can take looks to be buffer size / 512 4438 * which matches the 512 byte rounding we have to do when de-muxing 4439 * the packets. 4440 * 4441 * Sample numbers from the vendor driver: 4442 * USB High-Speed mode values: 4443 * RxAggBlockCount = 8 : 512 byte unit 4444 * RxAggBlockTimeout = 6 4445 * RxAggPageCount = 48 : 128 byte unit 4446 * RxAggPageTimeout = 4 or 6 (absolute time 34ms/(2^6)) 4447 */ 4448 4449 page_thresh = (priv->fops->rx_agg_buf_size / 512); 4450 if (rtl8xxxu_dma_agg_pages >= 0) { 4451 if (rtl8xxxu_dma_agg_pages <= page_thresh) 4452 timeout = page_thresh; 4453 else if (rtl8xxxu_dma_agg_pages <= 6) 4454 dev_err(&priv->udev->dev, 4455 "%s: dma_agg_pages=%i too small, minium is 6\n", 4456 __func__, rtl8xxxu_dma_agg_pages); 4457 else 4458 dev_err(&priv->udev->dev, 4459 "%s: dma_agg_pages=%i larger than limit %i\n", 4460 __func__, rtl8xxxu_dma_agg_pages, page_thresh); 4461 } 4462 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH, page_thresh); 4463 /* 4464 * REG_RXDMA_AGG_PG_TH + 1 seems to be the timeout register on 4465 * gen2 chips and rtl8188eu. The rtl8723au seems unhappy if we 4466 * don't set it, so better set both. 4467 */ 4468 timeout = 4; 4469 4470 if (rtl8xxxu_dma_agg_timeout >= 0) { 4471 if (rtl8xxxu_dma_agg_timeout <= 127) 4472 timeout = rtl8xxxu_dma_agg_timeout; 4473 else 4474 dev_err(&priv->udev->dev, 4475 "%s: Invalid dma_agg_timeout: %i\n", 4476 __func__, rtl8xxxu_dma_agg_timeout); 4477 } 4478 4479 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH + 1, timeout); 4480 rtl8xxxu_write8(priv, REG_USB_DMA_AGG_TO, timeout); 4481 priv->rx_buf_aggregation = 1; 4482 } 4483 4484 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg) 4485 { 4486 u32 val32; 4487 u8 rate_idx = 0; 4488 4489 rate_cfg &= RESPONSE_RATE_BITMAP_ALL; 4490 4491 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 4492 val32 &= ~RESPONSE_RATE_BITMAP_ALL; 4493 val32 |= rate_cfg; 4494 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 4495 4496 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg); 4497 4498 while (rate_cfg) { 4499 rate_cfg = (rate_cfg >> 1); 4500 rate_idx++; 4501 } 4502 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx); 4503 } 4504 4505 static void 4506 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 4507 struct ieee80211_bss_conf *bss_conf, u32 changed) 4508 { 4509 struct rtl8xxxu_priv *priv = hw->priv; 4510 struct device *dev = &priv->udev->dev; 4511 struct ieee80211_sta *sta; 4512 u32 val32; 4513 u8 val8; 4514 4515 if (changed & BSS_CHANGED_ASSOC) { 4516 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc); 4517 4518 rtl8xxxu_set_linktype(priv, vif->type); 4519 4520 if (bss_conf->assoc) { 4521 u32 ramask; 4522 int sgi = 0; 4523 4524 rcu_read_lock(); 4525 sta = ieee80211_find_sta(vif, bss_conf->bssid); 4526 if (!sta) { 4527 dev_info(dev, "%s: ASSOC no sta found\n", 4528 __func__); 4529 rcu_read_unlock(); 4530 goto error; 4531 } 4532 4533 if (sta->ht_cap.ht_supported) 4534 dev_info(dev, "%s: HT supported\n", __func__); 4535 if (sta->vht_cap.vht_supported) 4536 dev_info(dev, "%s: VHT supported\n", __func__); 4537 4538 /* TODO: Set bits 28-31 for rate adaptive id */ 4539 ramask = (sta->supp_rates[0] & 0xfff) | 4540 sta->ht_cap.mcs.rx_mask[0] << 12 | 4541 sta->ht_cap.mcs.rx_mask[1] << 20; 4542 if (sta->ht_cap.cap & 4543 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)) 4544 sgi = 1; 4545 rcu_read_unlock(); 4546 4547 priv->fops->update_rate_mask(priv, ramask, sgi); 4548 4549 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff); 4550 4551 rtl8xxxu_stop_tx_beacon(priv); 4552 4553 /* joinbss sequence */ 4554 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT, 4555 0xc000 | bss_conf->aid); 4556 4557 priv->fops->report_connect(priv, 0, true); 4558 } else { 4559 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 4560 val8 |= BEACON_DISABLE_TSF_UPDATE; 4561 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 4562 4563 priv->fops->report_connect(priv, 0, false); 4564 } 4565 } 4566 4567 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 4568 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n", 4569 bss_conf->use_short_preamble); 4570 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 4571 if (bss_conf->use_short_preamble) 4572 val32 |= RSR_ACK_SHORT_PREAMBLE; 4573 else 4574 val32 &= ~RSR_ACK_SHORT_PREAMBLE; 4575 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 4576 } 4577 4578 if (changed & BSS_CHANGED_ERP_SLOT) { 4579 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n", 4580 bss_conf->use_short_slot); 4581 4582 if (bss_conf->use_short_slot) 4583 val8 = 9; 4584 else 4585 val8 = 20; 4586 rtl8xxxu_write8(priv, REG_SLOT, val8); 4587 } 4588 4589 if (changed & BSS_CHANGED_BSSID) { 4590 dev_dbg(dev, "Changed BSSID!\n"); 4591 rtl8xxxu_set_bssid(priv, bss_conf->bssid); 4592 } 4593 4594 if (changed & BSS_CHANGED_BASIC_RATES) { 4595 dev_dbg(dev, "Changed BASIC_RATES!\n"); 4596 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates); 4597 } 4598 error: 4599 return; 4600 } 4601 4602 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue) 4603 { 4604 u32 rtlqueue; 4605 4606 switch (queue) { 4607 case IEEE80211_AC_VO: 4608 rtlqueue = TXDESC_QUEUE_VO; 4609 break; 4610 case IEEE80211_AC_VI: 4611 rtlqueue = TXDESC_QUEUE_VI; 4612 break; 4613 case IEEE80211_AC_BE: 4614 rtlqueue = TXDESC_QUEUE_BE; 4615 break; 4616 case IEEE80211_AC_BK: 4617 rtlqueue = TXDESC_QUEUE_BK; 4618 break; 4619 default: 4620 rtlqueue = TXDESC_QUEUE_BE; 4621 } 4622 4623 return rtlqueue; 4624 } 4625 4626 static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb) 4627 { 4628 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 4629 u32 queue; 4630 4631 if (ieee80211_is_mgmt(hdr->frame_control)) 4632 queue = TXDESC_QUEUE_MGNT; 4633 else 4634 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb)); 4635 4636 return queue; 4637 } 4638 4639 /* 4640 * Despite newer chips 8723b/8812/8821 having a larger TX descriptor 4641 * format. The descriptor checksum is still only calculated over the 4642 * initial 32 bytes of the descriptor! 4643 */ 4644 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc) 4645 { 4646 __le16 *ptr = (__le16 *)tx_desc; 4647 u16 csum = 0; 4648 int i; 4649 4650 /* 4651 * Clear csum field before calculation, as the csum field is 4652 * in the middle of the struct. 4653 */ 4654 tx_desc->csum = cpu_to_le16(0); 4655 4656 for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++) 4657 csum = csum ^ le16_to_cpu(ptr[i]); 4658 4659 tx_desc->csum |= cpu_to_le16(csum); 4660 } 4661 4662 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv) 4663 { 4664 struct rtl8xxxu_tx_urb *tx_urb, *tmp; 4665 unsigned long flags; 4666 4667 spin_lock_irqsave(&priv->tx_urb_lock, flags); 4668 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) { 4669 list_del(&tx_urb->list); 4670 priv->tx_urb_free_count--; 4671 usb_free_urb(&tx_urb->urb); 4672 } 4673 spin_unlock_irqrestore(&priv->tx_urb_lock, flags); 4674 } 4675 4676 static struct rtl8xxxu_tx_urb * 4677 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv) 4678 { 4679 struct rtl8xxxu_tx_urb *tx_urb; 4680 unsigned long flags; 4681 4682 spin_lock_irqsave(&priv->tx_urb_lock, flags); 4683 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list, 4684 struct rtl8xxxu_tx_urb, list); 4685 if (tx_urb) { 4686 list_del(&tx_urb->list); 4687 priv->tx_urb_free_count--; 4688 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER && 4689 !priv->tx_stopped) { 4690 priv->tx_stopped = true; 4691 ieee80211_stop_queues(priv->hw); 4692 } 4693 } 4694 4695 spin_unlock_irqrestore(&priv->tx_urb_lock, flags); 4696 4697 return tx_urb; 4698 } 4699 4700 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv, 4701 struct rtl8xxxu_tx_urb *tx_urb) 4702 { 4703 unsigned long flags; 4704 4705 INIT_LIST_HEAD(&tx_urb->list); 4706 4707 spin_lock_irqsave(&priv->tx_urb_lock, flags); 4708 4709 list_add(&tx_urb->list, &priv->tx_urb_free_list); 4710 priv->tx_urb_free_count++; 4711 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER && 4712 priv->tx_stopped) { 4713 priv->tx_stopped = false; 4714 ieee80211_wake_queues(priv->hw); 4715 } 4716 4717 spin_unlock_irqrestore(&priv->tx_urb_lock, flags); 4718 } 4719 4720 static void rtl8xxxu_tx_complete(struct urb *urb) 4721 { 4722 struct sk_buff *skb = (struct sk_buff *)urb->context; 4723 struct ieee80211_tx_info *tx_info; 4724 struct ieee80211_hw *hw; 4725 struct rtl8xxxu_priv *priv; 4726 struct rtl8xxxu_tx_urb *tx_urb = 4727 container_of(urb, struct rtl8xxxu_tx_urb, urb); 4728 4729 tx_info = IEEE80211_SKB_CB(skb); 4730 hw = tx_info->rate_driver_data[0]; 4731 priv = hw->priv; 4732 4733 skb_pull(skb, priv->fops->tx_desc_size); 4734 4735 ieee80211_tx_info_clear_status(tx_info); 4736 tx_info->status.rates[0].idx = -1; 4737 tx_info->status.rates[0].count = 0; 4738 4739 if (!urb->status) 4740 tx_info->flags |= IEEE80211_TX_STAT_ACK; 4741 4742 ieee80211_tx_status_irqsafe(hw, skb); 4743 4744 rtl8xxxu_free_tx_urb(priv, tx_urb); 4745 } 4746 4747 static void rtl8xxxu_dump_action(struct device *dev, 4748 struct ieee80211_hdr *hdr) 4749 { 4750 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr; 4751 u16 cap, timeout; 4752 4753 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION)) 4754 return; 4755 4756 switch (mgmt->u.action.u.addba_resp.action_code) { 4757 case WLAN_ACTION_ADDBA_RESP: 4758 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab); 4759 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout); 4760 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: " 4761 "timeout %i, tid %02x, buf_size %02x, policy %02x, " 4762 "status %02x\n", 4763 timeout, 4764 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2, 4765 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6, 4766 (cap >> 1) & 0x1, 4767 le16_to_cpu(mgmt->u.action.u.addba_resp.status)); 4768 break; 4769 case WLAN_ACTION_ADDBA_REQ: 4770 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab); 4771 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout); 4772 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: " 4773 "timeout %i, tid %02x, buf_size %02x, policy %02x\n", 4774 timeout, 4775 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2, 4776 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6, 4777 (cap >> 1) & 0x1); 4778 break; 4779 default: 4780 dev_info(dev, "action frame %02x\n", 4781 mgmt->u.action.u.addba_resp.action_code); 4782 break; 4783 } 4784 } 4785 4786 static void rtl8xxxu_tx(struct ieee80211_hw *hw, 4787 struct ieee80211_tx_control *control, 4788 struct sk_buff *skb) 4789 { 4790 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 4791 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 4792 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info); 4793 struct rtl8xxxu_priv *priv = hw->priv; 4794 struct rtl8xxxu_txdesc32 *tx_desc; 4795 struct rtl8xxxu_txdesc40 *tx_desc40; 4796 struct rtl8xxxu_tx_urb *tx_urb; 4797 struct ieee80211_sta *sta = NULL; 4798 struct ieee80211_vif *vif = tx_info->control.vif; 4799 struct device *dev = &priv->udev->dev; 4800 u32 queue, rate; 4801 u16 pktlen = skb->len; 4802 u16 seq_number; 4803 u16 rate_flag = tx_info->control.rates[0].flags; 4804 int tx_desc_size = priv->fops->tx_desc_size; 4805 int ret; 4806 bool usedesc40, ampdu_enable; 4807 4808 if (skb_headroom(skb) < tx_desc_size) { 4809 dev_warn(dev, 4810 "%s: Not enough headroom (%i) for tx descriptor\n", 4811 __func__, skb_headroom(skb)); 4812 goto error; 4813 } 4814 4815 if (unlikely(skb->len > (65535 - tx_desc_size))) { 4816 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n", 4817 __func__, skb->len); 4818 goto error; 4819 } 4820 4821 tx_urb = rtl8xxxu_alloc_tx_urb(priv); 4822 if (!tx_urb) { 4823 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__); 4824 goto error; 4825 } 4826 4827 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) 4828 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n", 4829 __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen); 4830 4831 if (ieee80211_is_action(hdr->frame_control)) 4832 rtl8xxxu_dump_action(dev, hdr); 4833 4834 usedesc40 = (tx_desc_size == 40); 4835 tx_info->rate_driver_data[0] = hw; 4836 4837 if (control && control->sta) 4838 sta = control->sta; 4839 4840 tx_desc = (struct rtl8xxxu_txdesc32 *)skb_push(skb, tx_desc_size); 4841 4842 memset(tx_desc, 0, tx_desc_size); 4843 tx_desc->pkt_size = cpu_to_le16(pktlen); 4844 tx_desc->pkt_offset = tx_desc_size; 4845 4846 tx_desc->txdw0 = 4847 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT; 4848 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) || 4849 is_broadcast_ether_addr(ieee80211_get_DA(hdr))) 4850 tx_desc->txdw0 |= TXDESC_BROADMULTICAST; 4851 4852 queue = rtl8xxxu_queue_select(hw, skb); 4853 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT); 4854 4855 if (tx_info->control.hw_key) { 4856 switch (tx_info->control.hw_key->cipher) { 4857 case WLAN_CIPHER_SUITE_WEP40: 4858 case WLAN_CIPHER_SUITE_WEP104: 4859 case WLAN_CIPHER_SUITE_TKIP: 4860 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4); 4861 break; 4862 case WLAN_CIPHER_SUITE_CCMP: 4863 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES); 4864 break; 4865 default: 4866 break; 4867 } 4868 } 4869 4870 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */ 4871 ampdu_enable = false; 4872 if (ieee80211_is_data_qos(hdr->frame_control) && sta) { 4873 if (sta->ht_cap.ht_supported) { 4874 u32 ampdu, val32; 4875 4876 ampdu = (u32)sta->ht_cap.ampdu_density; 4877 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT; 4878 tx_desc->txdw2 |= cpu_to_le32(val32); 4879 4880 ampdu_enable = true; 4881 } 4882 } 4883 4884 if (rate_flag & IEEE80211_TX_RC_MCS) 4885 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0; 4886 else 4887 rate = tx_rate->hw_value; 4888 4889 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 4890 if (!usedesc40) { 4891 tx_desc->txdw5 = cpu_to_le32(rate); 4892 4893 if (ieee80211_is_data(hdr->frame_control)) 4894 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00); 4895 4896 tx_desc->txdw3 = 4897 cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT); 4898 4899 if (ampdu_enable) 4900 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE); 4901 else 4902 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK); 4903 4904 if (ieee80211_is_mgmt(hdr->frame_control)) { 4905 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value); 4906 tx_desc->txdw4 |= 4907 cpu_to_le32(TXDESC32_USE_DRIVER_RATE); 4908 tx_desc->txdw5 |= 4909 cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT); 4910 tx_desc->txdw5 |= 4911 cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE); 4912 } 4913 4914 if (ieee80211_is_data_qos(hdr->frame_control)) 4915 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS); 4916 4917 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE || 4918 (sta && vif && vif->bss_conf.use_short_preamble)) 4919 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE); 4920 4921 if (rate_flag & IEEE80211_TX_RC_SHORT_GI || 4922 (ieee80211_is_data_qos(hdr->frame_control) && 4923 sta && sta->ht_cap.cap & 4924 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) { 4925 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI); 4926 } 4927 4928 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) { 4929 /* 4930 * Use RTS rate 24M - does the mac80211 tell 4931 * us which to use? 4932 */ 4933 tx_desc->txdw4 |= 4934 cpu_to_le32(DESC_RATE_24M << 4935 TXDESC32_RTS_RATE_SHIFT); 4936 tx_desc->txdw4 |= 4937 cpu_to_le32(TXDESC32_RTS_CTS_ENABLE); 4938 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); 4939 } 4940 } else { 4941 tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc; 4942 4943 tx_desc40->txdw4 = cpu_to_le32(rate); 4944 if (ieee80211_is_data(hdr->frame_control)) { 4945 tx_desc->txdw4 |= 4946 cpu_to_le32(0x1f << 4947 TXDESC40_DATA_RATE_FB_SHIFT); 4948 } 4949 4950 tx_desc40->txdw9 = 4951 cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT); 4952 4953 if (ampdu_enable) 4954 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE); 4955 else 4956 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK); 4957 4958 if (ieee80211_is_mgmt(hdr->frame_control)) { 4959 tx_desc40->txdw4 = cpu_to_le32(tx_rate->hw_value); 4960 tx_desc40->txdw3 |= 4961 cpu_to_le32(TXDESC40_USE_DRIVER_RATE); 4962 tx_desc40->txdw4 |= 4963 cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT); 4964 tx_desc40->txdw4 |= 4965 cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE); 4966 } 4967 4968 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE || 4969 (sta && vif && vif->bss_conf.use_short_preamble)) 4970 tx_desc40->txdw5 |= 4971 cpu_to_le32(TXDESC40_SHORT_PREAMBLE); 4972 4973 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) { 4974 /* 4975 * Use RTS rate 24M - does the mac80211 tell 4976 * us which to use? 4977 */ 4978 tx_desc->txdw4 |= 4979 cpu_to_le32(DESC_RATE_24M << 4980 TXDESC40_RTS_RATE_SHIFT); 4981 tx_desc->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE); 4982 tx_desc->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE); 4983 } 4984 } 4985 4986 rtl8xxxu_calc_tx_desc_csum(tx_desc); 4987 4988 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue], 4989 skb->data, skb->len, rtl8xxxu_tx_complete, skb); 4990 4991 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor); 4992 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC); 4993 if (ret) { 4994 usb_unanchor_urb(&tx_urb->urb); 4995 rtl8xxxu_free_tx_urb(priv, tx_urb); 4996 goto error; 4997 } 4998 return; 4999 error: 5000 dev_kfree_skb(skb); 5001 } 5002 5003 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv, 5004 struct ieee80211_rx_status *rx_status, 5005 struct rtl8723au_phy_stats *phy_stats, 5006 u32 rxmcs) 5007 { 5008 if (phy_stats->sgi_en) 5009 rx_status->flag |= RX_FLAG_SHORT_GI; 5010 5011 if (rxmcs < DESC_RATE_6M) { 5012 /* 5013 * Handle PHY stats for CCK rates 5014 */ 5015 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a; 5016 5017 switch (cck_agc_rpt & 0xc0) { 5018 case 0xc0: 5019 rx_status->signal = -46 - (cck_agc_rpt & 0x3e); 5020 break; 5021 case 0x80: 5022 rx_status->signal = -26 - (cck_agc_rpt & 0x3e); 5023 break; 5024 case 0x40: 5025 rx_status->signal = -12 - (cck_agc_rpt & 0x3e); 5026 break; 5027 case 0x00: 5028 rx_status->signal = 16 - (cck_agc_rpt & 0x3e); 5029 break; 5030 } 5031 } else { 5032 rx_status->signal = 5033 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110; 5034 } 5035 } 5036 5037 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv) 5038 { 5039 struct rtl8xxxu_rx_urb *rx_urb, *tmp; 5040 unsigned long flags; 5041 5042 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5043 5044 list_for_each_entry_safe(rx_urb, tmp, 5045 &priv->rx_urb_pending_list, list) { 5046 list_del(&rx_urb->list); 5047 priv->rx_urb_pending_count--; 5048 usb_free_urb(&rx_urb->urb); 5049 } 5050 5051 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5052 } 5053 5054 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv, 5055 struct rtl8xxxu_rx_urb *rx_urb) 5056 { 5057 struct sk_buff *skb; 5058 unsigned long flags; 5059 int pending = 0; 5060 5061 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5062 5063 if (!priv->shutdown) { 5064 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list); 5065 priv->rx_urb_pending_count++; 5066 pending = priv->rx_urb_pending_count; 5067 } else { 5068 skb = (struct sk_buff *)rx_urb->urb.context; 5069 dev_kfree_skb(skb); 5070 usb_free_urb(&rx_urb->urb); 5071 } 5072 5073 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5074 5075 if (pending > RTL8XXXU_RX_URB_PENDING_WATER) 5076 schedule_work(&priv->rx_urb_wq); 5077 } 5078 5079 static void rtl8xxxu_rx_urb_work(struct work_struct *work) 5080 { 5081 struct rtl8xxxu_priv *priv; 5082 struct rtl8xxxu_rx_urb *rx_urb, *tmp; 5083 struct list_head local; 5084 struct sk_buff *skb; 5085 unsigned long flags; 5086 int ret; 5087 5088 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq); 5089 INIT_LIST_HEAD(&local); 5090 5091 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5092 5093 list_splice_init(&priv->rx_urb_pending_list, &local); 5094 priv->rx_urb_pending_count = 0; 5095 5096 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5097 5098 list_for_each_entry_safe(rx_urb, tmp, &local, list) { 5099 list_del_init(&rx_urb->list); 5100 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb); 5101 /* 5102 * If out of memory or temporary error, put it back on the 5103 * queue and try again. Otherwise the device is dead/gone 5104 * and we should drop it. 5105 */ 5106 switch (ret) { 5107 case 0: 5108 break; 5109 case -ENOMEM: 5110 case -EAGAIN: 5111 rtl8xxxu_queue_rx_urb(priv, rx_urb); 5112 break; 5113 default: 5114 pr_info("failed to requeue urb %i\n", ret); 5115 skb = (struct sk_buff *)rx_urb->urb.context; 5116 dev_kfree_skb(skb); 5117 usb_free_urb(&rx_urb->urb); 5118 } 5119 } 5120 } 5121 5122 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv, 5123 struct sk_buff *skb) 5124 { 5125 struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data; 5126 struct device *dev = &priv->udev->dev; 5127 int len; 5128 5129 len = skb->len - 2; 5130 5131 dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n", 5132 c2h->id, c2h->seq, len, c2h->bt_info.response_source); 5133 5134 switch(c2h->id) { 5135 case C2H_8723B_BT_INFO: 5136 if (c2h->bt_info.response_source > 5137 BT_INFO_SRC_8723B_BT_ACTIVE_SEND) 5138 dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n"); 5139 else 5140 dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n"); 5141 5142 if (c2h->bt_info.bt_has_reset) 5143 dev_dbg(dev, "BT has been reset\n"); 5144 if (c2h->bt_info.tx_rx_mask) 5145 dev_dbg(dev, "BT TRx mask\n"); 5146 5147 break; 5148 case C2H_8723B_BT_MP_INFO: 5149 dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n", 5150 c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status); 5151 break; 5152 case C2H_8723B_RA_REPORT: 5153 dev_dbg(dev, 5154 "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n", 5155 c2h->ra_report.rate, c2h->ra_report.dummy0_0, 5156 c2h->ra_report.macid, c2h->ra_report.noisy_state); 5157 break; 5158 default: 5159 dev_info(dev, "Unhandled C2H event %02x seq %02x\n", 5160 c2h->id, c2h->seq); 5161 print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE, 5162 16, 1, c2h->raw.payload, len, false); 5163 break; 5164 } 5165 } 5166 5167 int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb) 5168 { 5169 struct ieee80211_hw *hw = priv->hw; 5170 struct ieee80211_rx_status *rx_status; 5171 struct rtl8xxxu_rxdesc16 *rx_desc; 5172 struct rtl8723au_phy_stats *phy_stats; 5173 struct sk_buff *next_skb = NULL; 5174 __le32 *_rx_desc_le; 5175 u32 *_rx_desc; 5176 int drvinfo_sz, desc_shift; 5177 int i, pkt_cnt, pkt_len, urb_len, pkt_offset; 5178 5179 urb_len = skb->len; 5180 pkt_cnt = 0; 5181 5182 do { 5183 rx_desc = (struct rtl8xxxu_rxdesc16 *)skb->data; 5184 _rx_desc_le = (__le32 *)skb->data; 5185 _rx_desc = (u32 *)skb->data; 5186 5187 for (i = 0; 5188 i < (sizeof(struct rtl8xxxu_rxdesc16) / sizeof(u32)); i++) 5189 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]); 5190 5191 /* 5192 * Only read pkt_cnt from the header if we're parsing the 5193 * first packet 5194 */ 5195 if (!pkt_cnt) 5196 pkt_cnt = rx_desc->pkt_cnt; 5197 pkt_len = rx_desc->pktlen; 5198 5199 drvinfo_sz = rx_desc->drvinfo_sz * 8; 5200 desc_shift = rx_desc->shift; 5201 pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift + 5202 sizeof(struct rtl8xxxu_rxdesc16), 128); 5203 5204 if (pkt_cnt > 1) 5205 next_skb = skb_clone(skb, GFP_ATOMIC); 5206 5207 rx_status = IEEE80211_SKB_RXCB(skb); 5208 memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); 5209 5210 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc16)); 5211 5212 phy_stats = (struct rtl8723au_phy_stats *)skb->data; 5213 5214 skb_pull(skb, drvinfo_sz + desc_shift); 5215 5216 skb_trim(skb, pkt_len); 5217 5218 if (rx_desc->phy_stats) 5219 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats, 5220 rx_desc->rxmcs); 5221 5222 rx_status->mactime = le32_to_cpu(rx_desc->tsfl); 5223 rx_status->flag |= RX_FLAG_MACTIME_START; 5224 5225 if (!rx_desc->swdec) 5226 rx_status->flag |= RX_FLAG_DECRYPTED; 5227 if (rx_desc->crc32) 5228 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 5229 if (rx_desc->bw) 5230 rx_status->flag |= RX_FLAG_40MHZ; 5231 5232 if (rx_desc->rxht) { 5233 rx_status->flag |= RX_FLAG_HT; 5234 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0; 5235 } else { 5236 rx_status->rate_idx = rx_desc->rxmcs; 5237 } 5238 5239 rx_status->freq = hw->conf.chandef.chan->center_freq; 5240 rx_status->band = hw->conf.chandef.chan->band; 5241 5242 ieee80211_rx_irqsafe(hw, skb); 5243 5244 skb = next_skb; 5245 if (skb) 5246 skb_pull(next_skb, pkt_offset); 5247 5248 pkt_cnt--; 5249 urb_len -= pkt_offset; 5250 } while (skb && urb_len > 0 && pkt_cnt > 0); 5251 5252 return RX_TYPE_DATA_PKT; 5253 } 5254 5255 int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb) 5256 { 5257 struct ieee80211_hw *hw = priv->hw; 5258 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 5259 struct rtl8xxxu_rxdesc24 *rx_desc = 5260 (struct rtl8xxxu_rxdesc24 *)skb->data; 5261 struct rtl8723au_phy_stats *phy_stats; 5262 __le32 *_rx_desc_le = (__le32 *)skb->data; 5263 u32 *_rx_desc = (u32 *)skb->data; 5264 int drvinfo_sz, desc_shift; 5265 int i; 5266 5267 for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++) 5268 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]); 5269 5270 memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); 5271 5272 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24)); 5273 5274 phy_stats = (struct rtl8723au_phy_stats *)skb->data; 5275 5276 drvinfo_sz = rx_desc->drvinfo_sz * 8; 5277 desc_shift = rx_desc->shift; 5278 skb_pull(skb, drvinfo_sz + desc_shift); 5279 5280 if (rx_desc->rpt_sel) { 5281 struct device *dev = &priv->udev->dev; 5282 dev_dbg(dev, "%s: C2H packet\n", __func__); 5283 rtl8723bu_handle_c2h(priv, skb); 5284 dev_kfree_skb(skb); 5285 return RX_TYPE_C2H; 5286 } 5287 5288 if (rx_desc->phy_stats) 5289 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats, 5290 rx_desc->rxmcs); 5291 5292 rx_status->mactime = le32_to_cpu(rx_desc->tsfl); 5293 rx_status->flag |= RX_FLAG_MACTIME_START; 5294 5295 if (!rx_desc->swdec) 5296 rx_status->flag |= RX_FLAG_DECRYPTED; 5297 if (rx_desc->crc32) 5298 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 5299 if (rx_desc->bw) 5300 rx_status->flag |= RX_FLAG_40MHZ; 5301 5302 if (rx_desc->rxmcs >= DESC_RATE_MCS0) { 5303 rx_status->flag |= RX_FLAG_HT; 5304 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0; 5305 } else { 5306 rx_status->rate_idx = rx_desc->rxmcs; 5307 } 5308 5309 rx_status->freq = hw->conf.chandef.chan->center_freq; 5310 rx_status->band = hw->conf.chandef.chan->band; 5311 5312 ieee80211_rx_irqsafe(hw, skb); 5313 return RX_TYPE_DATA_PKT; 5314 } 5315 5316 static void rtl8xxxu_rx_complete(struct urb *urb) 5317 { 5318 struct rtl8xxxu_rx_urb *rx_urb = 5319 container_of(urb, struct rtl8xxxu_rx_urb, urb); 5320 struct ieee80211_hw *hw = rx_urb->hw; 5321 struct rtl8xxxu_priv *priv = hw->priv; 5322 struct sk_buff *skb = (struct sk_buff *)urb->context; 5323 struct device *dev = &priv->udev->dev; 5324 5325 skb_put(skb, urb->actual_length); 5326 5327 if (urb->status == 0) { 5328 priv->fops->parse_rx_desc(priv, skb); 5329 5330 skb = NULL; 5331 rx_urb->urb.context = NULL; 5332 rtl8xxxu_queue_rx_urb(priv, rx_urb); 5333 } else { 5334 dev_dbg(dev, "%s: status %i\n", __func__, urb->status); 5335 goto cleanup; 5336 } 5337 return; 5338 5339 cleanup: 5340 usb_free_urb(urb); 5341 dev_kfree_skb(skb); 5342 return; 5343 } 5344 5345 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv, 5346 struct rtl8xxxu_rx_urb *rx_urb) 5347 { 5348 struct rtl8xxxu_fileops *fops = priv->fops; 5349 struct sk_buff *skb; 5350 int skb_size; 5351 int ret, rx_desc_sz; 5352 5353 rx_desc_sz = fops->rx_desc_size; 5354 5355 if (priv->rx_buf_aggregation && fops->rx_agg_buf_size) { 5356 skb_size = fops->rx_agg_buf_size; 5357 skb_size += (rx_desc_sz + sizeof(struct rtl8723au_phy_stats)); 5358 } else { 5359 skb_size = IEEE80211_MAX_FRAME_LEN; 5360 } 5361 5362 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL); 5363 if (!skb) 5364 return -ENOMEM; 5365 5366 memset(skb->data, 0, rx_desc_sz); 5367 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data, 5368 skb_size, rtl8xxxu_rx_complete, skb); 5369 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor); 5370 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC); 5371 if (ret) 5372 usb_unanchor_urb(&rx_urb->urb); 5373 return ret; 5374 } 5375 5376 static void rtl8xxxu_int_complete(struct urb *urb) 5377 { 5378 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context; 5379 struct device *dev = &priv->udev->dev; 5380 int ret; 5381 5382 dev_dbg(dev, "%s: status %i\n", __func__, urb->status); 5383 if (urb->status == 0) { 5384 usb_anchor_urb(urb, &priv->int_anchor); 5385 ret = usb_submit_urb(urb, GFP_ATOMIC); 5386 if (ret) 5387 usb_unanchor_urb(urb); 5388 } else { 5389 dev_dbg(dev, "%s: Error %i\n", __func__, urb->status); 5390 } 5391 } 5392 5393 5394 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw) 5395 { 5396 struct rtl8xxxu_priv *priv = hw->priv; 5397 struct urb *urb; 5398 u32 val32; 5399 int ret; 5400 5401 urb = usb_alloc_urb(0, GFP_KERNEL); 5402 if (!urb) 5403 return -ENOMEM; 5404 5405 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt, 5406 priv->int_buf, USB_INTR_CONTENT_LENGTH, 5407 rtl8xxxu_int_complete, priv, 1); 5408 usb_anchor_urb(urb, &priv->int_anchor); 5409 ret = usb_submit_urb(urb, GFP_KERNEL); 5410 if (ret) { 5411 usb_unanchor_urb(urb); 5412 goto error; 5413 } 5414 5415 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR); 5416 val32 |= USB_HIMR_CPWM; 5417 rtl8xxxu_write32(priv, REG_USB_HIMR, val32); 5418 5419 error: 5420 return ret; 5421 } 5422 5423 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw, 5424 struct ieee80211_vif *vif) 5425 { 5426 struct rtl8xxxu_priv *priv = hw->priv; 5427 int ret; 5428 u8 val8; 5429 5430 switch (vif->type) { 5431 case NL80211_IFTYPE_STATION: 5432 rtl8xxxu_stop_tx_beacon(priv); 5433 5434 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 5435 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE | 5436 BEACON_DISABLE_TSF_UPDATE; 5437 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 5438 ret = 0; 5439 break; 5440 default: 5441 ret = -EOPNOTSUPP; 5442 } 5443 5444 rtl8xxxu_set_linktype(priv, vif->type); 5445 5446 return ret; 5447 } 5448 5449 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw, 5450 struct ieee80211_vif *vif) 5451 { 5452 struct rtl8xxxu_priv *priv = hw->priv; 5453 5454 dev_dbg(&priv->udev->dev, "%s\n", __func__); 5455 } 5456 5457 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed) 5458 { 5459 struct rtl8xxxu_priv *priv = hw->priv; 5460 struct device *dev = &priv->udev->dev; 5461 u16 val16; 5462 int ret = 0, channel; 5463 bool ht40; 5464 5465 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL) 5466 dev_info(dev, 5467 "%s: channel: %i (changed %08x chandef.width %02x)\n", 5468 __func__, hw->conf.chandef.chan->hw_value, 5469 changed, hw->conf.chandef.width); 5470 5471 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) { 5472 val16 = ((hw->conf.long_frame_max_tx_count << 5473 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) | 5474 ((hw->conf.short_frame_max_tx_count << 5475 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK); 5476 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16); 5477 } 5478 5479 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { 5480 switch (hw->conf.chandef.width) { 5481 case NL80211_CHAN_WIDTH_20_NOHT: 5482 case NL80211_CHAN_WIDTH_20: 5483 ht40 = false; 5484 break; 5485 case NL80211_CHAN_WIDTH_40: 5486 ht40 = true; 5487 break; 5488 default: 5489 ret = -ENOTSUPP; 5490 goto exit; 5491 } 5492 5493 channel = hw->conf.chandef.chan->hw_value; 5494 5495 priv->fops->set_tx_power(priv, channel, ht40); 5496 5497 priv->fops->config_channel(hw); 5498 } 5499 5500 exit: 5501 return ret; 5502 } 5503 5504 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw, 5505 struct ieee80211_vif *vif, u16 queue, 5506 const struct ieee80211_tx_queue_params *param) 5507 { 5508 struct rtl8xxxu_priv *priv = hw->priv; 5509 struct device *dev = &priv->udev->dev; 5510 u32 val32; 5511 u8 aifs, acm_ctrl, acm_bit; 5512 5513 aifs = param->aifs; 5514 5515 val32 = aifs | 5516 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT | 5517 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT | 5518 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT; 5519 5520 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL); 5521 dev_dbg(dev, 5522 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n", 5523 __func__, queue, val32, param->acm, acm_ctrl); 5524 5525 switch (queue) { 5526 case IEEE80211_AC_VO: 5527 acm_bit = ACM_HW_CTRL_VO; 5528 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32); 5529 break; 5530 case IEEE80211_AC_VI: 5531 acm_bit = ACM_HW_CTRL_VI; 5532 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32); 5533 break; 5534 case IEEE80211_AC_BE: 5535 acm_bit = ACM_HW_CTRL_BE; 5536 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32); 5537 break; 5538 case IEEE80211_AC_BK: 5539 acm_bit = ACM_HW_CTRL_BK; 5540 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32); 5541 break; 5542 default: 5543 acm_bit = 0; 5544 break; 5545 } 5546 5547 if (param->acm) 5548 acm_ctrl |= acm_bit; 5549 else 5550 acm_ctrl &= ~acm_bit; 5551 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl); 5552 5553 return 0; 5554 } 5555 5556 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw, 5557 unsigned int changed_flags, 5558 unsigned int *total_flags, u64 multicast) 5559 { 5560 struct rtl8xxxu_priv *priv = hw->priv; 5561 u32 rcr = rtl8xxxu_read32(priv, REG_RCR); 5562 5563 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n", 5564 __func__, changed_flags, *total_flags); 5565 5566 /* 5567 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR) 5568 */ 5569 5570 if (*total_flags & FIF_FCSFAIL) 5571 rcr |= RCR_ACCEPT_CRC32; 5572 else 5573 rcr &= ~RCR_ACCEPT_CRC32; 5574 5575 /* 5576 * FIF_PLCPFAIL not supported? 5577 */ 5578 5579 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) 5580 rcr &= ~RCR_CHECK_BSSID_BEACON; 5581 else 5582 rcr |= RCR_CHECK_BSSID_BEACON; 5583 5584 if (*total_flags & FIF_CONTROL) 5585 rcr |= RCR_ACCEPT_CTRL_FRAME; 5586 else 5587 rcr &= ~RCR_ACCEPT_CTRL_FRAME; 5588 5589 if (*total_flags & FIF_OTHER_BSS) { 5590 rcr |= RCR_ACCEPT_AP; 5591 rcr &= ~RCR_CHECK_BSSID_MATCH; 5592 } else { 5593 rcr &= ~RCR_ACCEPT_AP; 5594 rcr |= RCR_CHECK_BSSID_MATCH; 5595 } 5596 5597 if (*total_flags & FIF_PSPOLL) 5598 rcr |= RCR_ACCEPT_PM; 5599 else 5600 rcr &= ~RCR_ACCEPT_PM; 5601 5602 /* 5603 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted 5604 */ 5605 5606 rtl8xxxu_write32(priv, REG_RCR, rcr); 5607 5608 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC | 5609 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL | 5610 FIF_PROBE_REQ); 5611 } 5612 5613 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts) 5614 { 5615 if (rts > 2347) 5616 return -EINVAL; 5617 5618 return 0; 5619 } 5620 5621 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 5622 struct ieee80211_vif *vif, 5623 struct ieee80211_sta *sta, 5624 struct ieee80211_key_conf *key) 5625 { 5626 struct rtl8xxxu_priv *priv = hw->priv; 5627 struct device *dev = &priv->udev->dev; 5628 u8 mac_addr[ETH_ALEN]; 5629 u8 val8; 5630 u16 val16; 5631 u32 val32; 5632 int retval = -EOPNOTSUPP; 5633 5634 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n", 5635 __func__, cmd, key->cipher, key->keyidx); 5636 5637 if (vif->type != NL80211_IFTYPE_STATION) 5638 return -EOPNOTSUPP; 5639 5640 if (key->keyidx > 3) 5641 return -EOPNOTSUPP; 5642 5643 switch (key->cipher) { 5644 case WLAN_CIPHER_SUITE_WEP40: 5645 case WLAN_CIPHER_SUITE_WEP104: 5646 5647 break; 5648 case WLAN_CIPHER_SUITE_CCMP: 5649 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; 5650 break; 5651 case WLAN_CIPHER_SUITE_TKIP: 5652 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 5653 default: 5654 return -EOPNOTSUPP; 5655 } 5656 5657 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { 5658 dev_dbg(dev, "%s: pairwise key\n", __func__); 5659 ether_addr_copy(mac_addr, sta->addr); 5660 } else { 5661 dev_dbg(dev, "%s: group key\n", __func__); 5662 eth_broadcast_addr(mac_addr); 5663 } 5664 5665 val16 = rtl8xxxu_read16(priv, REG_CR); 5666 val16 |= CR_SECURITY_ENABLE; 5667 rtl8xxxu_write16(priv, REG_CR, val16); 5668 5669 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY | 5670 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY; 5671 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY; 5672 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8); 5673 5674 switch (cmd) { 5675 case SET_KEY: 5676 key->hw_key_idx = key->keyidx; 5677 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 5678 rtl8xxxu_cam_write(priv, key, mac_addr); 5679 retval = 0; 5680 break; 5681 case DISABLE_KEY: 5682 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000); 5683 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE | 5684 key->keyidx << CAM_CMD_KEY_SHIFT; 5685 rtl8xxxu_write32(priv, REG_CAM_CMD, val32); 5686 retval = 0; 5687 break; 5688 default: 5689 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd); 5690 } 5691 5692 return retval; 5693 } 5694 5695 static int 5696 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 5697 struct ieee80211_ampdu_params *params) 5698 { 5699 struct rtl8xxxu_priv *priv = hw->priv; 5700 struct device *dev = &priv->udev->dev; 5701 u8 ampdu_factor, ampdu_density; 5702 struct ieee80211_sta *sta = params->sta; 5703 enum ieee80211_ampdu_mlme_action action = params->action; 5704 5705 switch (action) { 5706 case IEEE80211_AMPDU_TX_START: 5707 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__); 5708 ampdu_factor = sta->ht_cap.ampdu_factor; 5709 ampdu_density = sta->ht_cap.ampdu_density; 5710 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor); 5711 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density); 5712 dev_dbg(dev, 5713 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n", 5714 ampdu_factor, ampdu_density); 5715 break; 5716 case IEEE80211_AMPDU_TX_STOP_FLUSH: 5717 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__); 5718 rtl8xxxu_set_ampdu_factor(priv, 0); 5719 rtl8xxxu_set_ampdu_min_space(priv, 0); 5720 break; 5721 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 5722 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n", 5723 __func__); 5724 rtl8xxxu_set_ampdu_factor(priv, 0); 5725 rtl8xxxu_set_ampdu_min_space(priv, 0); 5726 break; 5727 case IEEE80211_AMPDU_RX_START: 5728 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__); 5729 break; 5730 case IEEE80211_AMPDU_RX_STOP: 5731 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__); 5732 break; 5733 default: 5734 break; 5735 } 5736 return 0; 5737 } 5738 5739 static int rtl8xxxu_start(struct ieee80211_hw *hw) 5740 { 5741 struct rtl8xxxu_priv *priv = hw->priv; 5742 struct rtl8xxxu_rx_urb *rx_urb; 5743 struct rtl8xxxu_tx_urb *tx_urb; 5744 unsigned long flags; 5745 int ret, i; 5746 5747 ret = 0; 5748 5749 init_usb_anchor(&priv->rx_anchor); 5750 init_usb_anchor(&priv->tx_anchor); 5751 init_usb_anchor(&priv->int_anchor); 5752 5753 priv->fops->enable_rf(priv); 5754 if (priv->usb_interrupts) { 5755 ret = rtl8xxxu_submit_int_urb(hw); 5756 if (ret) 5757 goto exit; 5758 } 5759 5760 for (i = 0; i < RTL8XXXU_TX_URBS; i++) { 5761 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL); 5762 if (!tx_urb) { 5763 if (!i) 5764 ret = -ENOMEM; 5765 5766 goto error_out; 5767 } 5768 usb_init_urb(&tx_urb->urb); 5769 INIT_LIST_HEAD(&tx_urb->list); 5770 tx_urb->hw = hw; 5771 list_add(&tx_urb->list, &priv->tx_urb_free_list); 5772 priv->tx_urb_free_count++; 5773 } 5774 5775 priv->tx_stopped = false; 5776 5777 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5778 priv->shutdown = false; 5779 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5780 5781 for (i = 0; i < RTL8XXXU_RX_URBS; i++) { 5782 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL); 5783 if (!rx_urb) { 5784 if (!i) 5785 ret = -ENOMEM; 5786 5787 goto error_out; 5788 } 5789 usb_init_urb(&rx_urb->urb); 5790 INIT_LIST_HEAD(&rx_urb->list); 5791 rx_urb->hw = hw; 5792 5793 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb); 5794 } 5795 exit: 5796 /* 5797 * Accept all data and mgmt frames 5798 */ 5799 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff); 5800 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff); 5801 5802 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e); 5803 5804 return ret; 5805 5806 error_out: 5807 rtl8xxxu_free_tx_resources(priv); 5808 /* 5809 * Disable all data and mgmt frames 5810 */ 5811 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); 5812 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000); 5813 5814 return ret; 5815 } 5816 5817 static void rtl8xxxu_stop(struct ieee80211_hw *hw) 5818 { 5819 struct rtl8xxxu_priv *priv = hw->priv; 5820 unsigned long flags; 5821 5822 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 5823 5824 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000); 5825 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); 5826 5827 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5828 priv->shutdown = true; 5829 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5830 5831 usb_kill_anchored_urbs(&priv->rx_anchor); 5832 usb_kill_anchored_urbs(&priv->tx_anchor); 5833 if (priv->usb_interrupts) 5834 usb_kill_anchored_urbs(&priv->int_anchor); 5835 5836 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 5837 5838 priv->fops->disable_rf(priv); 5839 5840 /* 5841 * Disable interrupts 5842 */ 5843 if (priv->usb_interrupts) 5844 rtl8xxxu_write32(priv, REG_USB_HIMR, 0); 5845 5846 rtl8xxxu_free_rx_resources(priv); 5847 rtl8xxxu_free_tx_resources(priv); 5848 } 5849 5850 static const struct ieee80211_ops rtl8xxxu_ops = { 5851 .tx = rtl8xxxu_tx, 5852 .add_interface = rtl8xxxu_add_interface, 5853 .remove_interface = rtl8xxxu_remove_interface, 5854 .config = rtl8xxxu_config, 5855 .conf_tx = rtl8xxxu_conf_tx, 5856 .bss_info_changed = rtl8xxxu_bss_info_changed, 5857 .configure_filter = rtl8xxxu_configure_filter, 5858 .set_rts_threshold = rtl8xxxu_set_rts_threshold, 5859 .start = rtl8xxxu_start, 5860 .stop = rtl8xxxu_stop, 5861 .sw_scan_start = rtl8xxxu_sw_scan_start, 5862 .sw_scan_complete = rtl8xxxu_sw_scan_complete, 5863 .set_key = rtl8xxxu_set_key, 5864 .ampdu_action = rtl8xxxu_ampdu_action, 5865 }; 5866 5867 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv, 5868 struct usb_interface *interface) 5869 { 5870 struct usb_interface_descriptor *interface_desc; 5871 struct usb_host_interface *host_interface; 5872 struct usb_endpoint_descriptor *endpoint; 5873 struct device *dev = &priv->udev->dev; 5874 int i, j = 0, endpoints; 5875 u8 dir, xtype, num; 5876 int ret = 0; 5877 5878 host_interface = &interface->altsetting[0]; 5879 interface_desc = &host_interface->desc; 5880 endpoints = interface_desc->bNumEndpoints; 5881 5882 for (i = 0; i < endpoints; i++) { 5883 endpoint = &host_interface->endpoint[i].desc; 5884 5885 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK; 5886 num = usb_endpoint_num(endpoint); 5887 xtype = usb_endpoint_type(endpoint); 5888 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 5889 dev_dbg(dev, 5890 "%s: endpoint: dir %02x, # %02x, type %02x\n", 5891 __func__, dir, num, xtype); 5892 if (usb_endpoint_dir_in(endpoint) && 5893 usb_endpoint_xfer_bulk(endpoint)) { 5894 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 5895 dev_dbg(dev, "%s: in endpoint num %i\n", 5896 __func__, num); 5897 5898 if (priv->pipe_in) { 5899 dev_warn(dev, 5900 "%s: Too many IN pipes\n", __func__); 5901 ret = -EINVAL; 5902 goto exit; 5903 } 5904 5905 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num); 5906 } 5907 5908 if (usb_endpoint_dir_in(endpoint) && 5909 usb_endpoint_xfer_int(endpoint)) { 5910 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 5911 dev_dbg(dev, "%s: interrupt endpoint num %i\n", 5912 __func__, num); 5913 5914 if (priv->pipe_interrupt) { 5915 dev_warn(dev, "%s: Too many INTERRUPT pipes\n", 5916 __func__); 5917 ret = -EINVAL; 5918 goto exit; 5919 } 5920 5921 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num); 5922 } 5923 5924 if (usb_endpoint_dir_out(endpoint) && 5925 usb_endpoint_xfer_bulk(endpoint)) { 5926 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 5927 dev_dbg(dev, "%s: out endpoint num %i\n", 5928 __func__, num); 5929 if (j >= RTL8XXXU_OUT_ENDPOINTS) { 5930 dev_warn(dev, 5931 "%s: Too many OUT pipes\n", __func__); 5932 ret = -EINVAL; 5933 goto exit; 5934 } 5935 priv->out_ep[j++] = num; 5936 } 5937 } 5938 exit: 5939 priv->nr_out_eps = j; 5940 return ret; 5941 } 5942 5943 static int rtl8xxxu_probe(struct usb_interface *interface, 5944 const struct usb_device_id *id) 5945 { 5946 struct rtl8xxxu_priv *priv; 5947 struct ieee80211_hw *hw; 5948 struct usb_device *udev; 5949 struct ieee80211_supported_band *sband; 5950 int ret = 0; 5951 int untested = 1; 5952 5953 udev = usb_get_dev(interface_to_usbdev(interface)); 5954 5955 switch (id->idVendor) { 5956 case USB_VENDOR_ID_REALTEK: 5957 switch(id->idProduct) { 5958 case 0x1724: 5959 case 0x8176: 5960 case 0x8178: 5961 case 0x817f: 5962 untested = 0; 5963 break; 5964 } 5965 break; 5966 case 0x7392: 5967 if (id->idProduct == 0x7811) 5968 untested = 0; 5969 break; 5970 case 0x050d: 5971 if (id->idProduct == 0x1004) 5972 untested = 0; 5973 break; 5974 default: 5975 break; 5976 } 5977 5978 if (untested) { 5979 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE; 5980 dev_info(&udev->dev, 5981 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n", 5982 id->idVendor, id->idProduct); 5983 dev_info(&udev->dev, 5984 "Please report results to Jes.Sorensen@gmail.com\n"); 5985 } 5986 5987 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops); 5988 if (!hw) { 5989 ret = -ENOMEM; 5990 goto exit; 5991 } 5992 5993 priv = hw->priv; 5994 priv->hw = hw; 5995 priv->udev = udev; 5996 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info; 5997 mutex_init(&priv->usb_buf_mutex); 5998 mutex_init(&priv->h2c_mutex); 5999 INIT_LIST_HEAD(&priv->tx_urb_free_list); 6000 spin_lock_init(&priv->tx_urb_lock); 6001 INIT_LIST_HEAD(&priv->rx_urb_pending_list); 6002 spin_lock_init(&priv->rx_urb_lock); 6003 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work); 6004 6005 usb_set_intfdata(interface, hw); 6006 6007 ret = rtl8xxxu_parse_usb(priv, interface); 6008 if (ret) 6009 goto exit; 6010 6011 ret = rtl8xxxu_identify_chip(priv); 6012 if (ret) { 6013 dev_err(&udev->dev, "Fatal - failed to identify chip\n"); 6014 goto exit; 6015 } 6016 6017 ret = rtl8xxxu_read_efuse(priv); 6018 if (ret) { 6019 dev_err(&udev->dev, "Fatal - failed to read EFuse\n"); 6020 goto exit; 6021 } 6022 6023 ret = priv->fops->parse_efuse(priv); 6024 if (ret) { 6025 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n"); 6026 goto exit; 6027 } 6028 6029 rtl8xxxu_print_chipinfo(priv); 6030 6031 ret = priv->fops->load_firmware(priv); 6032 if (ret) { 6033 dev_err(&udev->dev, "Fatal - failed to load firmware\n"); 6034 goto exit; 6035 } 6036 6037 ret = rtl8xxxu_init_device(hw); 6038 6039 hw->wiphy->max_scan_ssids = 1; 6040 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; 6041 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); 6042 hw->queues = 4; 6043 6044 sband = &rtl8xxxu_supported_band; 6045 sband->ht_cap.ht_supported = true; 6046 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 6047 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16; 6048 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40; 6049 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs)); 6050 sband->ht_cap.mcs.rx_mask[0] = 0xff; 6051 sband->ht_cap.mcs.rx_mask[4] = 0x01; 6052 if (priv->rf_paths > 1) { 6053 sband->ht_cap.mcs.rx_mask[1] = 0xff; 6054 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40; 6055 } 6056 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 6057 /* 6058 * Some APs will negotiate HT20_40 in a noisy environment leading 6059 * to miserable performance. Rather than defaulting to this, only 6060 * enable it if explicitly requested at module load time. 6061 */ 6062 if (rtl8xxxu_ht40_2g) { 6063 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n"); 6064 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; 6065 } 6066 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 6067 6068 hw->wiphy->rts_threshold = 2347; 6069 6070 SET_IEEE80211_DEV(priv->hw, &interface->dev); 6071 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr); 6072 6073 hw->extra_tx_headroom = priv->fops->tx_desc_size; 6074 ieee80211_hw_set(hw, SIGNAL_DBM); 6075 /* 6076 * The firmware handles rate control 6077 */ 6078 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 6079 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 6080 6081 ret = ieee80211_register_hw(priv->hw); 6082 if (ret) { 6083 dev_err(&udev->dev, "%s: Failed to register: %i\n", 6084 __func__, ret); 6085 goto exit; 6086 } 6087 6088 exit: 6089 if (ret < 0) 6090 usb_put_dev(udev); 6091 return ret; 6092 } 6093 6094 static void rtl8xxxu_disconnect(struct usb_interface *interface) 6095 { 6096 struct rtl8xxxu_priv *priv; 6097 struct ieee80211_hw *hw; 6098 6099 hw = usb_get_intfdata(interface); 6100 priv = hw->priv; 6101 6102 ieee80211_unregister_hw(hw); 6103 6104 priv->fops->power_off(priv); 6105 6106 usb_set_intfdata(interface, NULL); 6107 6108 dev_info(&priv->udev->dev, "disconnecting\n"); 6109 6110 kfree(priv->fw_data); 6111 mutex_destroy(&priv->usb_buf_mutex); 6112 mutex_destroy(&priv->h2c_mutex); 6113 6114 usb_put_dev(priv->udev); 6115 ieee80211_free_hw(hw); 6116 } 6117 6118 static struct usb_device_id dev_table[] = { 6119 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff), 6120 .driver_info = (unsigned long)&rtl8723au_fops}, 6121 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff), 6122 .driver_info = (unsigned long)&rtl8723au_fops}, 6123 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff), 6124 .driver_info = (unsigned long)&rtl8723au_fops}, 6125 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff), 6126 .driver_info = (unsigned long)&rtl8192eu_fops}, 6127 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff), 6128 .driver_info = (unsigned long)&rtl8723bu_fops}, 6129 #ifdef CONFIG_RTL8XXXU_UNTESTED 6130 /* Still supported by rtlwifi */ 6131 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff), 6132 .driver_info = (unsigned long)&rtl8192cu_fops}, 6133 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff), 6134 .driver_info = (unsigned long)&rtl8192cu_fops}, 6135 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff), 6136 .driver_info = (unsigned long)&rtl8192cu_fops}, 6137 /* Tested by Larry Finger */ 6138 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff), 6139 .driver_info = (unsigned long)&rtl8192cu_fops}, 6140 /* Tested by Andrea Merello */ 6141 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff), 6142 .driver_info = (unsigned long)&rtl8192cu_fops}, 6143 /* Currently untested 8188 series devices */ 6144 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff), 6145 .driver_info = (unsigned long)&rtl8192cu_fops}, 6146 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff), 6147 .driver_info = (unsigned long)&rtl8192cu_fops}, 6148 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff), 6149 .driver_info = (unsigned long)&rtl8192cu_fops}, 6150 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff), 6151 .driver_info = (unsigned long)&rtl8192cu_fops}, 6152 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff), 6153 .driver_info = (unsigned long)&rtl8192cu_fops}, 6154 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff), 6155 .driver_info = (unsigned long)&rtl8192cu_fops}, 6156 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff), 6157 .driver_info = (unsigned long)&rtl8192cu_fops}, 6158 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff), 6159 .driver_info = (unsigned long)&rtl8192cu_fops}, 6160 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff), 6161 .driver_info = (unsigned long)&rtl8192cu_fops}, 6162 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff), 6163 .driver_info = (unsigned long)&rtl8192cu_fops}, 6164 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff), 6165 .driver_info = (unsigned long)&rtl8192cu_fops}, 6166 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff), 6167 .driver_info = (unsigned long)&rtl8192cu_fops}, 6168 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff), 6169 .driver_info = (unsigned long)&rtl8192cu_fops}, 6170 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff), 6171 .driver_info = (unsigned long)&rtl8192cu_fops}, 6172 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff), 6173 .driver_info = (unsigned long)&rtl8192cu_fops}, 6174 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff), 6175 .driver_info = (unsigned long)&rtl8192cu_fops}, 6176 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff), 6177 .driver_info = (unsigned long)&rtl8192cu_fops}, 6178 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff), 6179 .driver_info = (unsigned long)&rtl8192cu_fops}, 6180 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff), 6181 .driver_info = (unsigned long)&rtl8192cu_fops}, 6182 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff), 6183 .driver_info = (unsigned long)&rtl8192cu_fops}, 6184 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff), 6185 .driver_info = (unsigned long)&rtl8192cu_fops}, 6186 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff), 6187 .driver_info = (unsigned long)&rtl8192cu_fops}, 6188 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff), 6189 .driver_info = (unsigned long)&rtl8192cu_fops}, 6190 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff), 6191 .driver_info = (unsigned long)&rtl8192cu_fops}, 6192 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff), 6193 .driver_info = (unsigned long)&rtl8192cu_fops}, 6194 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff), 6195 .driver_info = (unsigned long)&rtl8192cu_fops}, 6196 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff), 6197 .driver_info = (unsigned long)&rtl8192cu_fops}, 6198 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff), 6199 .driver_info = (unsigned long)&rtl8192cu_fops}, 6200 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff), 6201 .driver_info = (unsigned long)&rtl8192cu_fops}, 6202 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff), 6203 .driver_info = (unsigned long)&rtl8192cu_fops}, 6204 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff), 6205 .driver_info = (unsigned long)&rtl8192cu_fops}, 6206 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff), 6207 .driver_info = (unsigned long)&rtl8192cu_fops}, 6208 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff), 6209 .driver_info = (unsigned long)&rtl8192cu_fops}, 6210 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff), 6211 .driver_info = (unsigned long)&rtl8192cu_fops}, 6212 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff), 6213 .driver_info = (unsigned long)&rtl8192cu_fops}, 6214 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff), 6215 .driver_info = (unsigned long)&rtl8192cu_fops}, 6216 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff), 6217 .driver_info = (unsigned long)&rtl8192cu_fops}, 6218 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff), 6219 .driver_info = (unsigned long)&rtl8192cu_fops}, 6220 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff), 6221 .driver_info = (unsigned long)&rtl8192cu_fops}, 6222 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff), 6223 .driver_info = (unsigned long)&rtl8192cu_fops}, 6224 /* Currently untested 8192 series devices */ 6225 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff), 6226 .driver_info = (unsigned long)&rtl8192cu_fops}, 6227 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff), 6228 .driver_info = (unsigned long)&rtl8192cu_fops}, 6229 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff), 6230 .driver_info = (unsigned long)&rtl8192cu_fops}, 6231 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff), 6232 .driver_info = (unsigned long)&rtl8192cu_fops}, 6233 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff), 6234 .driver_info = (unsigned long)&rtl8192cu_fops}, 6235 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff), 6236 .driver_info = (unsigned long)&rtl8192cu_fops}, 6237 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff), 6238 .driver_info = (unsigned long)&rtl8192cu_fops}, 6239 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff), 6240 .driver_info = (unsigned long)&rtl8192cu_fops}, 6241 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff), 6242 .driver_info = (unsigned long)&rtl8192cu_fops}, 6243 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff), 6244 .driver_info = (unsigned long)&rtl8192cu_fops}, 6245 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff), 6246 .driver_info = (unsigned long)&rtl8192cu_fops}, 6247 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff), 6248 .driver_info = (unsigned long)&rtl8192cu_fops}, 6249 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff), 6250 .driver_info = (unsigned long)&rtl8192cu_fops}, 6251 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff), 6252 .driver_info = (unsigned long)&rtl8192cu_fops}, 6253 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff), 6254 .driver_info = (unsigned long)&rtl8192cu_fops}, 6255 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff), 6256 .driver_info = (unsigned long)&rtl8192cu_fops}, 6257 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff), 6258 .driver_info = (unsigned long)&rtl8192cu_fops}, 6259 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff), 6260 .driver_info = (unsigned long)&rtl8192cu_fops}, 6261 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff), 6262 .driver_info = (unsigned long)&rtl8192cu_fops}, 6263 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff), 6264 .driver_info = (unsigned long)&rtl8192cu_fops}, 6265 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff), 6266 .driver_info = (unsigned long)&rtl8192cu_fops}, 6267 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff), 6268 .driver_info = (unsigned long)&rtl8192cu_fops}, 6269 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff), 6270 .driver_info = (unsigned long)&rtl8192cu_fops}, 6271 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff), 6272 .driver_info = (unsigned long)&rtl8192cu_fops}, 6273 #endif 6274 { } 6275 }; 6276 6277 static struct usb_driver rtl8xxxu_driver = { 6278 .name = DRIVER_NAME, 6279 .probe = rtl8xxxu_probe, 6280 .disconnect = rtl8xxxu_disconnect, 6281 .id_table = dev_table, 6282 .no_dynamic_id = 1, 6283 .disable_hub_initiated_lpm = 1, 6284 }; 6285 6286 static int __init rtl8xxxu_module_init(void) 6287 { 6288 int res; 6289 6290 res = usb_register(&rtl8xxxu_driver); 6291 if (res < 0) 6292 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res); 6293 6294 return res; 6295 } 6296 6297 static void __exit rtl8xxxu_module_exit(void) 6298 { 6299 usb_deregister(&rtl8xxxu_driver); 6300 } 6301 6302 6303 MODULE_DEVICE_TABLE(usb, dev_table); 6304 6305 module_init(rtl8xxxu_module_init); 6306 module_exit(rtl8xxxu_module_exit); 6307