1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * RTL8XXXU mac80211 USB driver 4 * 5 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> 6 * 7 * Portions, notably calibration code: 8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 9 * 10 * This driver was written as a replacement for the vendor provided 11 * rtl8723au driver. As the Realtek 8xxx chips are very similar in 12 * their programming interface, I have started adding support for 13 * additional 8xxx chips like the 8192cu, 8188cus, etc. 14 */ 15 16 #include <linux/init.h> 17 #include <linux/kernel.h> 18 #include <linux/sched.h> 19 #include <linux/errno.h> 20 #include <linux/slab.h> 21 #include <linux/module.h> 22 #include <linux/spinlock.h> 23 #include <linux/list.h> 24 #include <linux/usb.h> 25 #include <linux/netdevice.h> 26 #include <linux/etherdevice.h> 27 #include <linux/ethtool.h> 28 #include <linux/wireless.h> 29 #include <linux/firmware.h> 30 #include <linux/moduleparam.h> 31 #include <net/mac80211.h> 32 #include "rtl8xxxu.h" 33 #include "rtl8xxxu_regs.h" 34 35 #define DRIVER_NAME "rtl8xxxu" 36 37 int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE; 38 static bool rtl8xxxu_ht40_2g; 39 static bool rtl8xxxu_dma_aggregation; 40 static int rtl8xxxu_dma_agg_timeout = -1; 41 static int rtl8xxxu_dma_agg_pages = -1; 42 43 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@gmail.com>"); 44 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver"); 45 MODULE_LICENSE("GPL"); 46 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin"); 47 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin"); 48 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin"); 49 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin"); 50 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin"); 51 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin"); 52 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin"); 53 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin"); 54 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin"); 55 MODULE_FIRMWARE("rtlwifi/rtl8188fufw.bin"); 56 57 module_param_named(debug, rtl8xxxu_debug, int, 0600); 58 MODULE_PARM_DESC(debug, "Set debug mask"); 59 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600); 60 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band"); 61 module_param_named(dma_aggregation, rtl8xxxu_dma_aggregation, bool, 0600); 62 MODULE_PARM_DESC(dma_aggregation, "Enable DMA packet aggregation"); 63 module_param_named(dma_agg_timeout, rtl8xxxu_dma_agg_timeout, int, 0600); 64 MODULE_PARM_DESC(dma_agg_timeout, "Set DMA aggregation timeout (range 1-127)"); 65 module_param_named(dma_agg_pages, rtl8xxxu_dma_agg_pages, int, 0600); 66 MODULE_PARM_DESC(dma_agg_pages, "Set DMA aggregation pages (range 1-127, 0 to disable)"); 67 68 #define USB_VENDOR_ID_REALTEK 0x0bda 69 #define RTL8XXXU_RX_URBS 32 70 #define RTL8XXXU_RX_URB_PENDING_WATER 8 71 #define RTL8XXXU_TX_URBS 64 72 #define RTL8XXXU_TX_URB_LOW_WATER 25 73 #define RTL8XXXU_TX_URB_HIGH_WATER 32 74 75 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv, 76 struct rtl8xxxu_rx_urb *rx_urb); 77 78 static struct ieee80211_rate rtl8xxxu_rates[] = { 79 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 }, 80 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 }, 81 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 }, 82 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 }, 83 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 }, 84 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 }, 85 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 }, 86 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 }, 87 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 }, 88 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 }, 89 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 }, 90 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 }, 91 }; 92 93 static struct ieee80211_channel rtl8xxxu_channels_2g[] = { 94 { .band = NL80211_BAND_2GHZ, .center_freq = 2412, 95 .hw_value = 1, .max_power = 30 }, 96 { .band = NL80211_BAND_2GHZ, .center_freq = 2417, 97 .hw_value = 2, .max_power = 30 }, 98 { .band = NL80211_BAND_2GHZ, .center_freq = 2422, 99 .hw_value = 3, .max_power = 30 }, 100 { .band = NL80211_BAND_2GHZ, .center_freq = 2427, 101 .hw_value = 4, .max_power = 30 }, 102 { .band = NL80211_BAND_2GHZ, .center_freq = 2432, 103 .hw_value = 5, .max_power = 30 }, 104 { .band = NL80211_BAND_2GHZ, .center_freq = 2437, 105 .hw_value = 6, .max_power = 30 }, 106 { .band = NL80211_BAND_2GHZ, .center_freq = 2442, 107 .hw_value = 7, .max_power = 30 }, 108 { .band = NL80211_BAND_2GHZ, .center_freq = 2447, 109 .hw_value = 8, .max_power = 30 }, 110 { .band = NL80211_BAND_2GHZ, .center_freq = 2452, 111 .hw_value = 9, .max_power = 30 }, 112 { .band = NL80211_BAND_2GHZ, .center_freq = 2457, 113 .hw_value = 10, .max_power = 30 }, 114 { .band = NL80211_BAND_2GHZ, .center_freq = 2462, 115 .hw_value = 11, .max_power = 30 }, 116 { .band = NL80211_BAND_2GHZ, .center_freq = 2467, 117 .hw_value = 12, .max_power = 30 }, 118 { .band = NL80211_BAND_2GHZ, .center_freq = 2472, 119 .hw_value = 13, .max_power = 30 }, 120 { .band = NL80211_BAND_2GHZ, .center_freq = 2484, 121 .hw_value = 14, .max_power = 30 } 122 }; 123 124 static struct ieee80211_supported_band rtl8xxxu_supported_band = { 125 .channels = rtl8xxxu_channels_2g, 126 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g), 127 .bitrates = rtl8xxxu_rates, 128 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates), 129 }; 130 131 const struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[] = { 132 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00}, 133 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, 134 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00}, 135 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05}, 136 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01}, 137 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f}, 138 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72}, 139 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08}, 140 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, 141 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, 142 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, 143 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, 144 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, 145 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, 146 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16}, 147 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00}, 148 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02}, 149 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, 150 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, 151 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, 152 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, 153 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff}, 154 }; 155 156 static const struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = { 157 {0x800, 0x80040000}, {0x804, 0x00000003}, 158 {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, 159 {0x810, 0x10001331}, {0x814, 0x020c3d10}, 160 {0x818, 0x02200385}, {0x81c, 0x00000000}, 161 {0x820, 0x01000100}, {0x824, 0x00390004}, 162 {0x828, 0x00000000}, {0x82c, 0x00000000}, 163 {0x830, 0x00000000}, {0x834, 0x00000000}, 164 {0x838, 0x00000000}, {0x83c, 0x00000000}, 165 {0x840, 0x00010000}, {0x844, 0x00000000}, 166 {0x848, 0x00000000}, {0x84c, 0x00000000}, 167 {0x850, 0x00000000}, {0x854, 0x00000000}, 168 {0x858, 0x569a569a}, {0x85c, 0x001b25a4}, 169 {0x860, 0x66f60110}, {0x864, 0x061f0130}, 170 {0x868, 0x00000000}, {0x86c, 0x32323200}, 171 {0x870, 0x07000760}, {0x874, 0x22004000}, 172 {0x878, 0x00000808}, {0x87c, 0x00000000}, 173 {0x880, 0xc0083070}, {0x884, 0x000004d5}, 174 {0x888, 0x00000000}, {0x88c, 0xccc000c0}, 175 {0x890, 0x00000800}, {0x894, 0xfffffffe}, 176 {0x898, 0x40302010}, {0x89c, 0x00706050}, 177 {0x900, 0x00000000}, {0x904, 0x00000023}, 178 {0x908, 0x00000000}, {0x90c, 0x81121111}, 179 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c}, 180 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f}, 181 {0xa10, 0x9500bb78}, {0xa14, 0x11144028}, 182 {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, 183 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, 184 {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, 185 {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, 186 {0xa78, 0x00000900}, 187 {0xc00, 0x48071d40}, {0xc04, 0x03a05611}, 188 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, 189 {0xc10, 0x08800000}, {0xc14, 0x40000100}, 190 {0xc18, 0x08800000}, {0xc1c, 0x40000100}, 191 {0xc20, 0x00000000}, {0xc24, 0x00000000}, 192 {0xc28, 0x00000000}, {0xc2c, 0x00000000}, 193 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af}, 194 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, 195 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, 196 {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, 197 {0xc50, 0x69543420}, {0xc54, 0x43bc0094}, 198 {0xc58, 0x69543420}, {0xc5c, 0x433c0094}, 199 {0xc60, 0x00000000}, {0xc64, 0x7112848b}, 200 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, 201 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db}, 202 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612}, 203 {0xc80, 0x40000100}, {0xc84, 0x20f60000}, 204 {0xc88, 0x40000100}, {0xc8c, 0x20200000}, 205 {0xc90, 0x00121820}, {0xc94, 0x00000000}, 206 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, 207 {0xca0, 0x00000000}, {0xca4, 0x00000080}, 208 {0xca8, 0x00000000}, {0xcac, 0x00000000}, 209 {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, 210 {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, 211 {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, 212 {0xcc8, 0x00000000}, {0xccc, 0x00000000}, 213 {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, 214 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, 215 {0xce0, 0x00222222}, {0xce4, 0x00000000}, 216 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, 217 {0xd00, 0x00080740}, {0xd04, 0x00020401}, 218 {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, 219 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, 220 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975}, 221 {0xd30, 0x00000000}, {0xd34, 0x80608000}, 222 {0xd38, 0x00000000}, {0xd3c, 0x00027293}, 223 {0xd40, 0x00000000}, {0xd44, 0x00000000}, 224 {0xd48, 0x00000000}, {0xd4c, 0x00000000}, 225 {0xd50, 0x6437140a}, {0xd54, 0x00000000}, 226 {0xd58, 0x00000000}, {0xd5c, 0x30032064}, 227 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, 228 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, 229 {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, 230 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a}, 231 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a}, 232 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a}, 233 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a}, 234 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, 235 {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, 236 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, 237 {0xe44, 0x01004800}, {0xe48, 0xfb000000}, 238 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, 239 {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, 240 {0xe5c, 0x28160d05}, {0xe60, 0x00000008}, 241 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0}, 242 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0}, 243 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0}, 244 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0}, 245 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0}, 246 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0}, 247 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0}, 248 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0}, 249 {0xf14, 0x00000003}, {0xf4c, 0x00000000}, 250 {0xf00, 0x00000300}, 251 {0xffff, 0xffffffff}, 252 }; 253 254 static const struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = { 255 {0x024, 0x0011800f}, {0x028, 0x00ffdb83}, 256 {0x800, 0x80040002}, {0x804, 0x00000003}, 257 {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, 258 {0x810, 0x10000330}, {0x814, 0x020c3d10}, 259 {0x818, 0x02200385}, {0x81c, 0x00000000}, 260 {0x820, 0x01000100}, {0x824, 0x00390004}, 261 {0x828, 0x01000100}, {0x82c, 0x00390004}, 262 {0x830, 0x27272727}, {0x834, 0x27272727}, 263 {0x838, 0x27272727}, {0x83c, 0x27272727}, 264 {0x840, 0x00010000}, {0x844, 0x00010000}, 265 {0x848, 0x27272727}, {0x84c, 0x27272727}, 266 {0x850, 0x00000000}, {0x854, 0x00000000}, 267 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4}, 268 {0x860, 0x66e60230}, {0x864, 0x061f0130}, 269 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27}, 270 {0x870, 0x07000700}, {0x874, 0x22184000}, 271 {0x878, 0x08080808}, {0x87c, 0x00000000}, 272 {0x880, 0xc0083070}, {0x884, 0x000004d5}, 273 {0x888, 0x00000000}, {0x88c, 0xcc0000c0}, 274 {0x890, 0x00000800}, {0x894, 0xfffffffe}, 275 {0x898, 0x40302010}, {0x89c, 0x00706050}, 276 {0x900, 0x00000000}, {0x904, 0x00000023}, 277 {0x908, 0x00000000}, {0x90c, 0x81121313}, 278 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c}, 279 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f}, 280 {0xa10, 0x9500bb78}, {0xa14, 0x11144028}, 281 {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, 282 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, 283 {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, 284 {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, 285 {0xc00, 0x48071d40}, {0xc04, 0x03a05633}, 286 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, 287 {0xc10, 0x08800000}, {0xc14, 0x40000100}, 288 {0xc18, 0x08800000}, {0xc1c, 0x40000100}, 289 {0xc20, 0x00000000}, {0xc24, 0x00000000}, 290 {0xc28, 0x00000000}, {0xc2c, 0x00000000}, 291 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf}, 292 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, 293 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, 294 {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, 295 {0xc50, 0x69543420}, {0xc54, 0x43bc0094}, 296 {0xc58, 0x69543420}, {0xc5c, 0x433c0094}, 297 {0xc60, 0x00000000}, {0xc64, 0x5116848b}, 298 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, 299 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b}, 300 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612}, 301 {0xc80, 0x40000100}, {0xc84, 0x20f60000}, 302 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000}, 303 {0xc90, 0x00121820}, {0xc94, 0x00000000}, 304 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, 305 {0xca0, 0x00000000}, {0xca4, 0x00000080}, 306 {0xca8, 0x00000000}, {0xcac, 0x00000000}, 307 {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, 308 {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, 309 {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, 310 {0xcc8, 0x00000000}, {0xccc, 0x00000000}, 311 {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, 312 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, 313 {0xce0, 0x00222222}, {0xce4, 0x00000000}, 314 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, 315 {0xd00, 0x00080740}, {0xd04, 0x00020403}, 316 {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, 317 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, 318 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975}, 319 {0xd30, 0x00000000}, {0xd34, 0x80608000}, 320 {0xd38, 0x00000000}, {0xd3c, 0x00027293}, 321 {0xd40, 0x00000000}, {0xd44, 0x00000000}, 322 {0xd48, 0x00000000}, {0xd4c, 0x00000000}, 323 {0xd50, 0x6437140a}, {0xd54, 0x00000000}, 324 {0xd58, 0x00000000}, {0xd5c, 0x30032064}, 325 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, 326 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, 327 {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, 328 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a}, 329 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a}, 330 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a}, 331 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a}, 332 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, 333 {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, 334 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, 335 {0xe44, 0x01004800}, {0xe48, 0xfb000000}, 336 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, 337 {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, 338 {0xe5c, 0x28160d05}, {0xe60, 0x00000010}, 339 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4}, 340 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4}, 341 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4}, 342 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4}, 343 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4}, 344 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4}, 345 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4}, 346 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4}, 347 {0xf14, 0x00000003}, {0xf4c, 0x00000000}, 348 {0xf00, 0x00000300}, 349 {0xffff, 0xffffffff}, 350 }; 351 352 static const struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = { 353 {0x024, 0x0011800f}, {0x028, 0x00ffdb83}, 354 {0x040, 0x000c0004}, {0x800, 0x80040000}, 355 {0x804, 0x00000001}, {0x808, 0x0000fc00}, 356 {0x80c, 0x0000000a}, {0x810, 0x10005388}, 357 {0x814, 0x020c3d10}, {0x818, 0x02200385}, 358 {0x81c, 0x00000000}, {0x820, 0x01000100}, 359 {0x824, 0x00390204}, {0x828, 0x00000000}, 360 {0x82c, 0x00000000}, {0x830, 0x00000000}, 361 {0x834, 0x00000000}, {0x838, 0x00000000}, 362 {0x83c, 0x00000000}, {0x840, 0x00010000}, 363 {0x844, 0x00000000}, {0x848, 0x00000000}, 364 {0x84c, 0x00000000}, {0x850, 0x00000000}, 365 {0x854, 0x00000000}, {0x858, 0x569a569a}, 366 {0x85c, 0x001b25a4}, {0x860, 0x66e60230}, 367 {0x864, 0x061f0130}, {0x868, 0x00000000}, 368 {0x86c, 0x20202000}, {0x870, 0x03000300}, 369 {0x874, 0x22004000}, {0x878, 0x00000808}, 370 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070}, 371 {0x884, 0x000004d5}, {0x888, 0x00000000}, 372 {0x88c, 0xccc000c0}, {0x890, 0x00000800}, 373 {0x894, 0xfffffffe}, {0x898, 0x40302010}, 374 {0x89c, 0x00706050}, {0x900, 0x00000000}, 375 {0x904, 0x00000023}, {0x908, 0x00000000}, 376 {0x90c, 0x81121111}, {0xa00, 0x00d047c8}, 377 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300}, 378 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78}, 379 {0xa14, 0x11144028}, {0xa18, 0x00881117}, 380 {0xa1c, 0x89140f00}, {0xa20, 0x15160000}, 381 {0xa24, 0x070b0f12}, {0xa28, 0x00000104}, 382 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00}, 383 {0xa74, 0x00000007}, {0xc00, 0x48071d40}, 384 {0xc04, 0x03a05611}, {0xc08, 0x000000e4}, 385 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000}, 386 {0xc14, 0x40000100}, {0xc18, 0x08800000}, 387 {0xc1c, 0x40000100}, {0xc20, 0x00000000}, 388 {0xc24, 0x00000000}, {0xc28, 0x00000000}, 389 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44}, 390 {0xc34, 0x469652cf}, {0xc38, 0x49795994}, 391 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f}, 392 {0xc44, 0x000100b7}, {0xc48, 0xec020107}, 393 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e}, 394 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f}, 395 {0xc5c, 0x433c0094}, {0xc60, 0x00000000}, 396 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff}, 397 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d}, 398 {0xc74, 0x018610db}, {0xc78, 0x0000001f}, 399 {0xc7c, 0x00b91612}, {0xc80, 0x24000090}, 400 {0xc84, 0x20f60000}, {0xc88, 0x24000090}, 401 {0xc8c, 0x20200000}, {0xc90, 0x00121820}, 402 {0xc94, 0x00000000}, {0xc98, 0x00121820}, 403 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000}, 404 {0xca4, 0x00000080}, {0xca8, 0x00000000}, 405 {0xcac, 0x00000000}, {0xcb0, 0x00000000}, 406 {0xcb4, 0x00000000}, {0xcb8, 0x00000000}, 407 {0xcbc, 0x28000000}, {0xcc0, 0x00000000}, 408 {0xcc4, 0x00000000}, {0xcc8, 0x00000000}, 409 {0xccc, 0x00000000}, {0xcd0, 0x00000000}, 410 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427}, 411 {0xcdc, 0x00766932}, {0xce0, 0x00222222}, 412 {0xce4, 0x00000000}, {0xce8, 0x37644302}, 413 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740}, 414 {0xd04, 0x00020401}, {0xd08, 0x0000907f}, 415 {0xd0c, 0x20010201}, {0xd10, 0xa0633333}, 416 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b}, 417 {0xd2c, 0xcc979975}, {0xd30, 0x00000000}, 418 {0xd34, 0x80608000}, {0xd38, 0x00000000}, 419 {0xd3c, 0x00027293}, {0xd40, 0x00000000}, 420 {0xd44, 0x00000000}, {0xd48, 0x00000000}, 421 {0xd4c, 0x00000000}, {0xd50, 0x6437140a}, 422 {0xd54, 0x00000000}, {0xd58, 0x00000000}, 423 {0xd5c, 0x30032064}, {0xd60, 0x4653de68}, 424 {0xd64, 0x04518a3c}, {0xd68, 0x00002101}, 425 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e}, 426 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24}, 427 {0xe00, 0x24242424}, {0xe04, 0x24242424}, 428 {0xe08, 0x03902024}, {0xe10, 0x24242424}, 429 {0xe14, 0x24242424}, {0xe18, 0x24242424}, 430 {0xe1c, 0x24242424}, {0xe28, 0x00000000}, 431 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f}, 432 {0xe38, 0x02140102}, {0xe3c, 0x681604c2}, 433 {0xe40, 0x01007c00}, {0xe44, 0x01004800}, 434 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1}, 435 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f}, 436 {0xe58, 0x02140102}, {0xe5c, 0x28160d05}, 437 {0xe60, 0x00000008}, {0xe68, 0x001b25a4}, 438 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0}, 439 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0}, 440 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0}, 441 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0}, 442 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0}, 443 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0}, 444 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0}, 445 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448}, 446 {0xf14, 0x00000003}, {0xf4c, 0x00000000}, 447 {0xf00, 0x00000300}, 448 {0xffff, 0xffffffff}, 449 }; 450 451 static const struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = { 452 {0xc78, 0x7b000001}, {0xc78, 0x7b010001}, 453 {0xc78, 0x7b020001}, {0xc78, 0x7b030001}, 454 {0xc78, 0x7b040001}, {0xc78, 0x7b050001}, 455 {0xc78, 0x7a060001}, {0xc78, 0x79070001}, 456 {0xc78, 0x78080001}, {0xc78, 0x77090001}, 457 {0xc78, 0x760a0001}, {0xc78, 0x750b0001}, 458 {0xc78, 0x740c0001}, {0xc78, 0x730d0001}, 459 {0xc78, 0x720e0001}, {0xc78, 0x710f0001}, 460 {0xc78, 0x70100001}, {0xc78, 0x6f110001}, 461 {0xc78, 0x6e120001}, {0xc78, 0x6d130001}, 462 {0xc78, 0x6c140001}, {0xc78, 0x6b150001}, 463 {0xc78, 0x6a160001}, {0xc78, 0x69170001}, 464 {0xc78, 0x68180001}, {0xc78, 0x67190001}, 465 {0xc78, 0x661a0001}, {0xc78, 0x651b0001}, 466 {0xc78, 0x641c0001}, {0xc78, 0x631d0001}, 467 {0xc78, 0x621e0001}, {0xc78, 0x611f0001}, 468 {0xc78, 0x60200001}, {0xc78, 0x49210001}, 469 {0xc78, 0x48220001}, {0xc78, 0x47230001}, 470 {0xc78, 0x46240001}, {0xc78, 0x45250001}, 471 {0xc78, 0x44260001}, {0xc78, 0x43270001}, 472 {0xc78, 0x42280001}, {0xc78, 0x41290001}, 473 {0xc78, 0x402a0001}, {0xc78, 0x262b0001}, 474 {0xc78, 0x252c0001}, {0xc78, 0x242d0001}, 475 {0xc78, 0x232e0001}, {0xc78, 0x222f0001}, 476 {0xc78, 0x21300001}, {0xc78, 0x20310001}, 477 {0xc78, 0x06320001}, {0xc78, 0x05330001}, 478 {0xc78, 0x04340001}, {0xc78, 0x03350001}, 479 {0xc78, 0x02360001}, {0xc78, 0x01370001}, 480 {0xc78, 0x00380001}, {0xc78, 0x00390001}, 481 {0xc78, 0x003a0001}, {0xc78, 0x003b0001}, 482 {0xc78, 0x003c0001}, {0xc78, 0x003d0001}, 483 {0xc78, 0x003e0001}, {0xc78, 0x003f0001}, 484 {0xc78, 0x7b400001}, {0xc78, 0x7b410001}, 485 {0xc78, 0x7b420001}, {0xc78, 0x7b430001}, 486 {0xc78, 0x7b440001}, {0xc78, 0x7b450001}, 487 {0xc78, 0x7a460001}, {0xc78, 0x79470001}, 488 {0xc78, 0x78480001}, {0xc78, 0x77490001}, 489 {0xc78, 0x764a0001}, {0xc78, 0x754b0001}, 490 {0xc78, 0x744c0001}, {0xc78, 0x734d0001}, 491 {0xc78, 0x724e0001}, {0xc78, 0x714f0001}, 492 {0xc78, 0x70500001}, {0xc78, 0x6f510001}, 493 {0xc78, 0x6e520001}, {0xc78, 0x6d530001}, 494 {0xc78, 0x6c540001}, {0xc78, 0x6b550001}, 495 {0xc78, 0x6a560001}, {0xc78, 0x69570001}, 496 {0xc78, 0x68580001}, {0xc78, 0x67590001}, 497 {0xc78, 0x665a0001}, {0xc78, 0x655b0001}, 498 {0xc78, 0x645c0001}, {0xc78, 0x635d0001}, 499 {0xc78, 0x625e0001}, {0xc78, 0x615f0001}, 500 {0xc78, 0x60600001}, {0xc78, 0x49610001}, 501 {0xc78, 0x48620001}, {0xc78, 0x47630001}, 502 {0xc78, 0x46640001}, {0xc78, 0x45650001}, 503 {0xc78, 0x44660001}, {0xc78, 0x43670001}, 504 {0xc78, 0x42680001}, {0xc78, 0x41690001}, 505 {0xc78, 0x406a0001}, {0xc78, 0x266b0001}, 506 {0xc78, 0x256c0001}, {0xc78, 0x246d0001}, 507 {0xc78, 0x236e0001}, {0xc78, 0x226f0001}, 508 {0xc78, 0x21700001}, {0xc78, 0x20710001}, 509 {0xc78, 0x06720001}, {0xc78, 0x05730001}, 510 {0xc78, 0x04740001}, {0xc78, 0x03750001}, 511 {0xc78, 0x02760001}, {0xc78, 0x01770001}, 512 {0xc78, 0x00780001}, {0xc78, 0x00790001}, 513 {0xc78, 0x007a0001}, {0xc78, 0x007b0001}, 514 {0xc78, 0x007c0001}, {0xc78, 0x007d0001}, 515 {0xc78, 0x007e0001}, {0xc78, 0x007f0001}, 516 {0xc78, 0x3800001e}, {0xc78, 0x3801001e}, 517 {0xc78, 0x3802001e}, {0xc78, 0x3803001e}, 518 {0xc78, 0x3804001e}, {0xc78, 0x3805001e}, 519 {0xc78, 0x3806001e}, {0xc78, 0x3807001e}, 520 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e}, 521 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e}, 522 {0xc78, 0x440c001e}, {0xc78, 0x480d001e}, 523 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e}, 524 {0xc78, 0x5210001e}, {0xc78, 0x5611001e}, 525 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e}, 526 {0xc78, 0x6014001e}, {0xc78, 0x6015001e}, 527 {0xc78, 0x6016001e}, {0xc78, 0x6217001e}, 528 {0xc78, 0x6218001e}, {0xc78, 0x6219001e}, 529 {0xc78, 0x621a001e}, {0xc78, 0x621b001e}, 530 {0xc78, 0x621c001e}, {0xc78, 0x621d001e}, 531 {0xc78, 0x621e001e}, {0xc78, 0x621f001e}, 532 {0xffff, 0xffffffff} 533 }; 534 535 static const struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = { 536 {0xc78, 0x7b000001}, {0xc78, 0x7b010001}, 537 {0xc78, 0x7b020001}, {0xc78, 0x7b030001}, 538 {0xc78, 0x7b040001}, {0xc78, 0x7b050001}, 539 {0xc78, 0x7b060001}, {0xc78, 0x7b070001}, 540 {0xc78, 0x7b080001}, {0xc78, 0x7a090001}, 541 {0xc78, 0x790a0001}, {0xc78, 0x780b0001}, 542 {0xc78, 0x770c0001}, {0xc78, 0x760d0001}, 543 {0xc78, 0x750e0001}, {0xc78, 0x740f0001}, 544 {0xc78, 0x73100001}, {0xc78, 0x72110001}, 545 {0xc78, 0x71120001}, {0xc78, 0x70130001}, 546 {0xc78, 0x6f140001}, {0xc78, 0x6e150001}, 547 {0xc78, 0x6d160001}, {0xc78, 0x6c170001}, 548 {0xc78, 0x6b180001}, {0xc78, 0x6a190001}, 549 {0xc78, 0x691a0001}, {0xc78, 0x681b0001}, 550 {0xc78, 0x671c0001}, {0xc78, 0x661d0001}, 551 {0xc78, 0x651e0001}, {0xc78, 0x641f0001}, 552 {0xc78, 0x63200001}, {0xc78, 0x62210001}, 553 {0xc78, 0x61220001}, {0xc78, 0x60230001}, 554 {0xc78, 0x46240001}, {0xc78, 0x45250001}, 555 {0xc78, 0x44260001}, {0xc78, 0x43270001}, 556 {0xc78, 0x42280001}, {0xc78, 0x41290001}, 557 {0xc78, 0x402a0001}, {0xc78, 0x262b0001}, 558 {0xc78, 0x252c0001}, {0xc78, 0x242d0001}, 559 {0xc78, 0x232e0001}, {0xc78, 0x222f0001}, 560 {0xc78, 0x21300001}, {0xc78, 0x20310001}, 561 {0xc78, 0x06320001}, {0xc78, 0x05330001}, 562 {0xc78, 0x04340001}, {0xc78, 0x03350001}, 563 {0xc78, 0x02360001}, {0xc78, 0x01370001}, 564 {0xc78, 0x00380001}, {0xc78, 0x00390001}, 565 {0xc78, 0x003a0001}, {0xc78, 0x003b0001}, 566 {0xc78, 0x003c0001}, {0xc78, 0x003d0001}, 567 {0xc78, 0x003e0001}, {0xc78, 0x003f0001}, 568 {0xc78, 0x7b400001}, {0xc78, 0x7b410001}, 569 {0xc78, 0x7b420001}, {0xc78, 0x7b430001}, 570 {0xc78, 0x7b440001}, {0xc78, 0x7b450001}, 571 {0xc78, 0x7b460001}, {0xc78, 0x7b470001}, 572 {0xc78, 0x7b480001}, {0xc78, 0x7a490001}, 573 {0xc78, 0x794a0001}, {0xc78, 0x784b0001}, 574 {0xc78, 0x774c0001}, {0xc78, 0x764d0001}, 575 {0xc78, 0x754e0001}, {0xc78, 0x744f0001}, 576 {0xc78, 0x73500001}, {0xc78, 0x72510001}, 577 {0xc78, 0x71520001}, {0xc78, 0x70530001}, 578 {0xc78, 0x6f540001}, {0xc78, 0x6e550001}, 579 {0xc78, 0x6d560001}, {0xc78, 0x6c570001}, 580 {0xc78, 0x6b580001}, {0xc78, 0x6a590001}, 581 {0xc78, 0x695a0001}, {0xc78, 0x685b0001}, 582 {0xc78, 0x675c0001}, {0xc78, 0x665d0001}, 583 {0xc78, 0x655e0001}, {0xc78, 0x645f0001}, 584 {0xc78, 0x63600001}, {0xc78, 0x62610001}, 585 {0xc78, 0x61620001}, {0xc78, 0x60630001}, 586 {0xc78, 0x46640001}, {0xc78, 0x45650001}, 587 {0xc78, 0x44660001}, {0xc78, 0x43670001}, 588 {0xc78, 0x42680001}, {0xc78, 0x41690001}, 589 {0xc78, 0x406a0001}, {0xc78, 0x266b0001}, 590 {0xc78, 0x256c0001}, {0xc78, 0x246d0001}, 591 {0xc78, 0x236e0001}, {0xc78, 0x226f0001}, 592 {0xc78, 0x21700001}, {0xc78, 0x20710001}, 593 {0xc78, 0x06720001}, {0xc78, 0x05730001}, 594 {0xc78, 0x04740001}, {0xc78, 0x03750001}, 595 {0xc78, 0x02760001}, {0xc78, 0x01770001}, 596 {0xc78, 0x00780001}, {0xc78, 0x00790001}, 597 {0xc78, 0x007a0001}, {0xc78, 0x007b0001}, 598 {0xc78, 0x007c0001}, {0xc78, 0x007d0001}, 599 {0xc78, 0x007e0001}, {0xc78, 0x007f0001}, 600 {0xc78, 0x3800001e}, {0xc78, 0x3801001e}, 601 {0xc78, 0x3802001e}, {0xc78, 0x3803001e}, 602 {0xc78, 0x3804001e}, {0xc78, 0x3805001e}, 603 {0xc78, 0x3806001e}, {0xc78, 0x3807001e}, 604 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e}, 605 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e}, 606 {0xc78, 0x440c001e}, {0xc78, 0x480d001e}, 607 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e}, 608 {0xc78, 0x5210001e}, {0xc78, 0x5611001e}, 609 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e}, 610 {0xc78, 0x6014001e}, {0xc78, 0x6015001e}, 611 {0xc78, 0x6016001e}, {0xc78, 0x6217001e}, 612 {0xc78, 0x6218001e}, {0xc78, 0x6219001e}, 613 {0xc78, 0x621a001e}, {0xc78, 0x621b001e}, 614 {0xc78, 0x621c001e}, {0xc78, 0x621d001e}, 615 {0xc78, 0x621e001e}, {0xc78, 0x621f001e}, 616 {0xffff, 0xffffffff} 617 }; 618 619 static const struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = { 620 { /* RF_A */ 621 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1, 622 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2, 623 .lssiparm = REG_FPGA0_XA_LSSI_PARM, 624 .hspiread = REG_HSPI_XA_READBACK, 625 .lssiread = REG_FPGA0_XA_LSSI_READBACK, 626 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL, 627 }, 628 { /* RF_B */ 629 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1, 630 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2, 631 .lssiparm = REG_FPGA0_XB_LSSI_PARM, 632 .hspiread = REG_HSPI_XB_READBACK, 633 .lssiread = REG_FPGA0_XB_LSSI_READBACK, 634 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL, 635 }, 636 }; 637 638 const u32 rtl8xxxu_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = { 639 REG_OFDM0_XA_RX_IQ_IMBALANCE, 640 REG_OFDM0_XB_RX_IQ_IMBALANCE, 641 REG_OFDM0_ENERGY_CCA_THRES, 642 REG_OFDM0_AGCR_SSI_TABLE, 643 REG_OFDM0_XA_TX_IQ_IMBALANCE, 644 REG_OFDM0_XB_TX_IQ_IMBALANCE, 645 REG_OFDM0_XC_TX_AFE, 646 REG_OFDM0_XD_TX_AFE, 647 REG_OFDM0_RX_IQ_EXT_ANTA 648 }; 649 650 u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr) 651 { 652 struct usb_device *udev = priv->udev; 653 int len; 654 u8 data; 655 656 mutex_lock(&priv->usb_buf_mutex); 657 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 658 REALTEK_USB_CMD_REQ, REALTEK_USB_READ, 659 addr, 0, &priv->usb_buf.val8, sizeof(u8), 660 RTW_USB_CONTROL_MSG_TIMEOUT); 661 data = priv->usb_buf.val8; 662 mutex_unlock(&priv->usb_buf_mutex); 663 664 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) 665 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n", 666 __func__, addr, data, len); 667 return data; 668 } 669 670 u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr) 671 { 672 struct usb_device *udev = priv->udev; 673 int len; 674 u16 data; 675 676 mutex_lock(&priv->usb_buf_mutex); 677 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 678 REALTEK_USB_CMD_REQ, REALTEK_USB_READ, 679 addr, 0, &priv->usb_buf.val16, sizeof(u16), 680 RTW_USB_CONTROL_MSG_TIMEOUT); 681 data = le16_to_cpu(priv->usb_buf.val16); 682 mutex_unlock(&priv->usb_buf_mutex); 683 684 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) 685 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n", 686 __func__, addr, data, len); 687 return data; 688 } 689 690 u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr) 691 { 692 struct usb_device *udev = priv->udev; 693 int len; 694 u32 data; 695 696 mutex_lock(&priv->usb_buf_mutex); 697 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 698 REALTEK_USB_CMD_REQ, REALTEK_USB_READ, 699 addr, 0, &priv->usb_buf.val32, sizeof(u32), 700 RTW_USB_CONTROL_MSG_TIMEOUT); 701 data = le32_to_cpu(priv->usb_buf.val32); 702 mutex_unlock(&priv->usb_buf_mutex); 703 704 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) 705 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n", 706 __func__, addr, data, len); 707 return data; 708 } 709 710 int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val) 711 { 712 struct usb_device *udev = priv->udev; 713 int ret; 714 715 mutex_lock(&priv->usb_buf_mutex); 716 priv->usb_buf.val8 = val; 717 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 718 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 719 addr, 0, &priv->usb_buf.val8, sizeof(u8), 720 RTW_USB_CONTROL_MSG_TIMEOUT); 721 722 mutex_unlock(&priv->usb_buf_mutex); 723 724 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) 725 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n", 726 __func__, addr, val); 727 return ret; 728 } 729 730 int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val) 731 { 732 struct usb_device *udev = priv->udev; 733 int ret; 734 735 mutex_lock(&priv->usb_buf_mutex); 736 priv->usb_buf.val16 = cpu_to_le16(val); 737 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 738 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 739 addr, 0, &priv->usb_buf.val16, sizeof(u16), 740 RTW_USB_CONTROL_MSG_TIMEOUT); 741 mutex_unlock(&priv->usb_buf_mutex); 742 743 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) 744 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n", 745 __func__, addr, val); 746 return ret; 747 } 748 749 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val) 750 { 751 struct usb_device *udev = priv->udev; 752 int ret; 753 754 mutex_lock(&priv->usb_buf_mutex); 755 priv->usb_buf.val32 = cpu_to_le32(val); 756 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 757 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 758 addr, 0, &priv->usb_buf.val32, sizeof(u32), 759 RTW_USB_CONTROL_MSG_TIMEOUT); 760 mutex_unlock(&priv->usb_buf_mutex); 761 762 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) 763 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n", 764 __func__, addr, val); 765 return ret; 766 } 767 768 static int 769 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len) 770 { 771 struct usb_device *udev = priv->udev; 772 int blocksize = priv->fops->writeN_block_size; 773 int ret, i, count, remainder; 774 775 count = len / blocksize; 776 remainder = len % blocksize; 777 778 for (i = 0; i < count; i++) { 779 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 780 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 781 addr, 0, buf, blocksize, 782 RTW_USB_CONTROL_MSG_TIMEOUT); 783 if (ret != blocksize) 784 goto write_error; 785 786 addr += blocksize; 787 buf += blocksize; 788 } 789 790 if (remainder) { 791 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 792 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 793 addr, 0, buf, remainder, 794 RTW_USB_CONTROL_MSG_TIMEOUT); 795 if (ret != remainder) 796 goto write_error; 797 } 798 799 return len; 800 801 write_error: 802 dev_info(&udev->dev, 803 "%s: Failed to write block at addr: %04x size: %04x\n", 804 __func__, addr, blocksize); 805 return -EAGAIN; 806 } 807 808 u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv, 809 enum rtl8xxxu_rfpath path, u8 reg) 810 { 811 u32 hssia, val32, retval; 812 813 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2); 814 if (path != RF_A) 815 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2); 816 else 817 val32 = hssia; 818 819 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK; 820 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT); 821 val32 |= FPGA0_HSSI_PARM2_EDGE_READ; 822 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ; 823 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); 824 825 udelay(10); 826 827 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32); 828 udelay(100); 829 830 hssia |= FPGA0_HSSI_PARM2_EDGE_READ; 831 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); 832 udelay(10); 833 834 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1); 835 if (val32 & FPGA0_HSSI_PARM1_PI) 836 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread); 837 else 838 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread); 839 840 retval &= 0xfffff; 841 842 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ) 843 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n", 844 __func__, reg, retval); 845 return retval; 846 } 847 848 /* 849 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can 850 * have write issues in high temperature conditions. We may have to 851 * retry writing them. 852 */ 853 int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv, 854 enum rtl8xxxu_rfpath path, u8 reg, u32 data) 855 { 856 int ret, retval; 857 u32 dataaddr, val32; 858 859 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE) 860 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n", 861 __func__, reg, data); 862 863 data &= FPGA0_LSSI_PARM_DATA_MASK; 864 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data; 865 866 if (priv->rtl_chip == RTL8192E) { 867 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 868 val32 &= ~0x20000; 869 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 870 } 871 872 /* Use XB for path B */ 873 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr); 874 if (ret != sizeof(dataaddr)) 875 retval = -EIO; 876 else 877 retval = 0; 878 879 udelay(1); 880 881 if (priv->rtl_chip == RTL8192E) { 882 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 883 val32 |= 0x20000; 884 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 885 } 886 887 return retval; 888 } 889 890 static int 891 rtl8xxxu_gen1_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len) 892 { 893 struct device *dev = &priv->udev->dev; 894 int mbox_nr, retry, retval = 0; 895 int mbox_reg, mbox_ext_reg; 896 u8 val8; 897 898 mutex_lock(&priv->h2c_mutex); 899 900 mbox_nr = priv->next_mbox; 901 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4); 902 mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2); 903 904 /* 905 * MBOX ready? 906 */ 907 retry = 100; 908 do { 909 val8 = rtl8xxxu_read8(priv, REG_HMTFR); 910 if (!(val8 & BIT(mbox_nr))) 911 break; 912 } while (retry--); 913 914 if (!retry) { 915 dev_info(dev, "%s: Mailbox busy\n", __func__); 916 retval = -EBUSY; 917 goto error; 918 } 919 920 /* 921 * Need to swap as it's being swapped again by rtl8xxxu_write16/32() 922 */ 923 if (len > sizeof(u32)) { 924 rtl8xxxu_write16(priv, mbox_ext_reg, le16_to_cpu(h2c->raw.ext)); 925 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 926 dev_info(dev, "H2C_EXT %04x\n", 927 le16_to_cpu(h2c->raw.ext)); 928 } 929 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data)); 930 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 931 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data)); 932 933 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX; 934 935 error: 936 mutex_unlock(&priv->h2c_mutex); 937 return retval; 938 } 939 940 int 941 rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len) 942 { 943 struct device *dev = &priv->udev->dev; 944 int mbox_nr, retry, retval = 0; 945 int mbox_reg, mbox_ext_reg; 946 u8 val8; 947 948 mutex_lock(&priv->h2c_mutex); 949 950 mbox_nr = priv->next_mbox; 951 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4); 952 mbox_ext_reg = REG_HMBOX_EXT0_8723B + (mbox_nr * 4); 953 954 /* 955 * MBOX ready? 956 */ 957 retry = 100; 958 do { 959 val8 = rtl8xxxu_read8(priv, REG_HMTFR); 960 if (!(val8 & BIT(mbox_nr))) 961 break; 962 } while (retry--); 963 964 if (!retry) { 965 dev_info(dev, "%s: Mailbox busy\n", __func__); 966 retval = -EBUSY; 967 goto error; 968 } 969 970 /* 971 * Need to swap as it's being swapped again by rtl8xxxu_write16/32() 972 */ 973 if (len > sizeof(u32)) { 974 rtl8xxxu_write32(priv, mbox_ext_reg, 975 le32_to_cpu(h2c->raw_wide.ext)); 976 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 977 dev_info(dev, "H2C_EXT %08x\n", 978 le32_to_cpu(h2c->raw_wide.ext)); 979 } 980 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data)); 981 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 982 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data)); 983 984 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX; 985 986 error: 987 mutex_unlock(&priv->h2c_mutex); 988 return retval; 989 } 990 991 void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv) 992 { 993 u8 val8; 994 u32 val32; 995 996 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL); 997 val8 |= BIT(0) | BIT(3); 998 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8); 999 1000 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); 1001 val32 &= ~(BIT(4) | BIT(5)); 1002 val32 |= BIT(3); 1003 if (priv->rf_paths == 2) { 1004 val32 &= ~(BIT(20) | BIT(21)); 1005 val32 |= BIT(19); 1006 } 1007 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); 1008 1009 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1010 val32 &= ~OFDM_RF_PATH_TX_MASK; 1011 if (priv->tx_paths == 2) 1012 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B; 1013 else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C) 1014 val32 |= OFDM_RF_PATH_TX_B; 1015 else 1016 val32 |= OFDM_RF_PATH_TX_A; 1017 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1018 1019 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1020 val32 &= ~FPGA_RF_MODE_JAPAN; 1021 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1022 1023 if (priv->rf_paths == 2) 1024 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0); 1025 else 1026 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0); 1027 1028 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95); 1029 if (priv->rf_paths == 2) 1030 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95); 1031 1032 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); 1033 } 1034 1035 void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv) 1036 { 1037 u8 sps0; 1038 u32 val32; 1039 1040 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL); 1041 1042 /* RF RX code for preamble power saving */ 1043 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); 1044 val32 &= ~(BIT(3) | BIT(4) | BIT(5)); 1045 if (priv->rf_paths == 2) 1046 val32 &= ~(BIT(19) | BIT(20) | BIT(21)); 1047 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); 1048 1049 /* Disable TX for four paths */ 1050 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1051 val32 &= ~OFDM_RF_PATH_TX_MASK; 1052 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1053 1054 /* Enable power saving */ 1055 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1056 val32 |= FPGA_RF_MODE_JAPAN; 1057 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1058 1059 /* AFE control register to power down bits [30:22] */ 1060 if (priv->rf_paths == 2) 1061 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0); 1062 else 1063 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0); 1064 1065 /* Power down RF module */ 1066 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); 1067 if (priv->rf_paths == 2) 1068 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0); 1069 1070 sps0 &= ~(BIT(0) | BIT(3)); 1071 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0); 1072 } 1073 1074 static void rtl8xxxu_stop_tx_beacon(struct rtl8xxxu_priv *priv) 1075 { 1076 u8 val8; 1077 1078 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2); 1079 val8 &= ~BIT(6); 1080 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8); 1081 1082 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64); 1083 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2); 1084 val8 &= ~BIT(0); 1085 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8); 1086 } 1087 1088 1089 /* 1090 * The rtl8723a has 3 channel groups for it's efuse settings. It only 1091 * supports the 2.4GHz band, so channels 1 - 14: 1092 * group 0: channels 1 - 3 1093 * group 1: channels 4 - 9 1094 * group 2: channels 10 - 14 1095 * 1096 * Note: We index from 0 in the code 1097 */ 1098 static int rtl8xxxu_gen1_channel_to_group(int channel) 1099 { 1100 int group; 1101 1102 if (channel < 4) 1103 group = 0; 1104 else if (channel < 10) 1105 group = 1; 1106 else 1107 group = 2; 1108 1109 return group; 1110 } 1111 1112 /* 1113 * Valid for rtl8723bu and rtl8192eu 1114 */ 1115 int rtl8xxxu_gen2_channel_to_group(int channel) 1116 { 1117 int group; 1118 1119 if (channel < 3) 1120 group = 0; 1121 else if (channel < 6) 1122 group = 1; 1123 else if (channel < 9) 1124 group = 2; 1125 else if (channel < 12) 1126 group = 3; 1127 else 1128 group = 4; 1129 1130 return group; 1131 } 1132 1133 void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw) 1134 { 1135 struct rtl8xxxu_priv *priv = hw->priv; 1136 u32 val32, rsr; 1137 u8 val8, opmode; 1138 bool ht = true; 1139 int sec_ch_above, channel; 1140 int i; 1141 1142 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE); 1143 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 1144 channel = hw->conf.chandef.chan->hw_value; 1145 1146 switch (hw->conf.chandef.width) { 1147 case NL80211_CHAN_WIDTH_20_NOHT: 1148 ht = false; 1149 fallthrough; 1150 case NL80211_CHAN_WIDTH_20: 1151 opmode |= BW_OPMODE_20MHZ; 1152 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); 1153 1154 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1155 val32 &= ~FPGA_RF_MODE; 1156 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1157 1158 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1159 val32 &= ~FPGA_RF_MODE; 1160 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1161 1162 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); 1163 val32 |= FPGA0_ANALOG2_20MHZ; 1164 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); 1165 break; 1166 case NL80211_CHAN_WIDTH_40: 1167 if (hw->conf.chandef.center_freq1 > 1168 hw->conf.chandef.chan->center_freq) { 1169 sec_ch_above = 1; 1170 channel += 2; 1171 } else { 1172 sec_ch_above = 0; 1173 channel -= 2; 1174 } 1175 1176 opmode &= ~BW_OPMODE_20MHZ; 1177 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); 1178 rsr &= ~RSR_RSC_BANDWIDTH_40M; 1179 if (sec_ch_above) 1180 rsr |= RSR_RSC_UPPER_SUB_CHANNEL; 1181 else 1182 rsr |= RSR_RSC_LOWER_SUB_CHANNEL; 1183 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr); 1184 1185 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1186 val32 |= FPGA_RF_MODE; 1187 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1188 1189 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1190 val32 |= FPGA_RF_MODE; 1191 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1192 1193 /* 1194 * Set Control channel to upper or lower. These settings 1195 * are required only for 40MHz 1196 */ 1197 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); 1198 val32 &= ~CCK0_SIDEBAND; 1199 if (!sec_ch_above) 1200 val32 |= CCK0_SIDEBAND; 1201 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); 1202 1203 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 1204 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ 1205 if (sec_ch_above) 1206 val32 |= OFDM_LSTF_PRIME_CH_LOW; 1207 else 1208 val32 |= OFDM_LSTF_PRIME_CH_HIGH; 1209 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 1210 1211 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); 1212 val32 &= ~FPGA0_ANALOG2_20MHZ; 1213 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); 1214 1215 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 1216 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); 1217 if (sec_ch_above) 1218 val32 |= FPGA0_PS_UPPER_CHANNEL; 1219 else 1220 val32 |= FPGA0_PS_LOWER_CHANNEL; 1221 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 1222 break; 1223 1224 default: 1225 break; 1226 } 1227 1228 for (i = RF_A; i < priv->rf_paths; i++) { 1229 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1230 val32 &= ~MODE_AG_CHANNEL_MASK; 1231 val32 |= channel; 1232 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1233 } 1234 1235 if (ht) 1236 val8 = 0x0e; 1237 else 1238 val8 = 0x0a; 1239 1240 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8); 1241 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8); 1242 1243 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808); 1244 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a); 1245 1246 for (i = RF_A; i < priv->rf_paths; i++) { 1247 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1248 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) 1249 val32 &= ~MODE_AG_CHANNEL_20MHZ; 1250 else 1251 val32 |= MODE_AG_CHANNEL_20MHZ; 1252 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1253 } 1254 } 1255 1256 void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw) 1257 { 1258 struct rtl8xxxu_priv *priv = hw->priv; 1259 u32 val32; 1260 u8 val8, subchannel; 1261 u16 rf_mode_bw; 1262 bool ht = true; 1263 int sec_ch_above, channel; 1264 int i; 1265 1266 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL); 1267 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK; 1268 channel = hw->conf.chandef.chan->hw_value; 1269 1270 /* Hack */ 1271 subchannel = 0; 1272 1273 switch (hw->conf.chandef.width) { 1274 case NL80211_CHAN_WIDTH_20_NOHT: 1275 ht = false; 1276 fallthrough; 1277 case NL80211_CHAN_WIDTH_20: 1278 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20; 1279 subchannel = 0; 1280 1281 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1282 val32 &= ~FPGA_RF_MODE; 1283 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1284 1285 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1286 val32 &= ~FPGA_RF_MODE; 1287 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1288 1289 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); 1290 val32 &= ~(BIT(30) | BIT(31)); 1291 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); 1292 1293 break; 1294 case NL80211_CHAN_WIDTH_40: 1295 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40; 1296 1297 if (hw->conf.chandef.center_freq1 > 1298 hw->conf.chandef.chan->center_freq) { 1299 sec_ch_above = 1; 1300 channel += 2; 1301 } else { 1302 sec_ch_above = 0; 1303 channel -= 2; 1304 } 1305 1306 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1307 val32 |= FPGA_RF_MODE; 1308 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1309 1310 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1311 val32 |= FPGA_RF_MODE; 1312 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1313 1314 /* 1315 * Set Control channel to upper or lower. These settings 1316 * are required only for 40MHz 1317 */ 1318 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); 1319 val32 &= ~CCK0_SIDEBAND; 1320 if (!sec_ch_above) 1321 val32 |= CCK0_SIDEBAND; 1322 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); 1323 1324 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 1325 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ 1326 if (sec_ch_above) 1327 val32 |= OFDM_LSTF_PRIME_CH_LOW; 1328 else 1329 val32 |= OFDM_LSTF_PRIME_CH_HIGH; 1330 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 1331 1332 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 1333 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); 1334 if (sec_ch_above) 1335 val32 |= FPGA0_PS_UPPER_CHANNEL; 1336 else 1337 val32 |= FPGA0_PS_LOWER_CHANNEL; 1338 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 1339 break; 1340 case NL80211_CHAN_WIDTH_80: 1341 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80; 1342 break; 1343 default: 1344 break; 1345 } 1346 1347 for (i = RF_A; i < priv->rf_paths; i++) { 1348 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1349 val32 &= ~MODE_AG_CHANNEL_MASK; 1350 val32 |= channel; 1351 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1352 } 1353 1354 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw); 1355 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel); 1356 1357 if (ht) 1358 val8 = 0x0e; 1359 else 1360 val8 = 0x0a; 1361 1362 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8); 1363 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8); 1364 1365 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808); 1366 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a); 1367 1368 for (i = RF_A; i < priv->rf_paths; i++) { 1369 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1370 val32 &= ~MODE_AG_BW_MASK; 1371 switch(hw->conf.chandef.width) { 1372 case NL80211_CHAN_WIDTH_80: 1373 val32 |= MODE_AG_BW_80MHZ_8723B; 1374 break; 1375 case NL80211_CHAN_WIDTH_40: 1376 val32 |= MODE_AG_BW_40MHZ_8723B; 1377 break; 1378 default: 1379 val32 |= MODE_AG_BW_20MHZ_8723B; 1380 break; 1381 } 1382 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1383 } 1384 } 1385 1386 void 1387 rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) 1388 { 1389 struct rtl8xxxu_power_base *power_base = priv->power_base; 1390 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS]; 1391 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS]; 1392 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b; 1393 u8 val8; 1394 int group, i; 1395 1396 group = rtl8xxxu_gen1_channel_to_group(channel); 1397 1398 cck[0] = priv->cck_tx_power_index_A[group] - 1; 1399 cck[1] = priv->cck_tx_power_index_B[group] - 1; 1400 1401 if (priv->hi_pa) { 1402 if (cck[0] > 0x20) 1403 cck[0] = 0x20; 1404 if (cck[1] > 0x20) 1405 cck[1] = 0x20; 1406 } 1407 1408 ofdm[0] = priv->ht40_1s_tx_power_index_A[group]; 1409 ofdm[1] = priv->ht40_1s_tx_power_index_B[group]; 1410 if (ofdm[0]) 1411 ofdm[0] -= 1; 1412 if (ofdm[1]) 1413 ofdm[1] -= 1; 1414 1415 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a; 1416 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b; 1417 1418 mcsbase[0] = ofdm[0]; 1419 mcsbase[1] = ofdm[1]; 1420 if (!ht40) { 1421 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a; 1422 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b; 1423 } 1424 1425 if (priv->tx_paths > 1) { 1426 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a) 1427 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a; 1428 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b) 1429 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b; 1430 } 1431 1432 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL) 1433 dev_info(&priv->udev->dev, 1434 "%s: Setting TX power CCK A: %02x, " 1435 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n", 1436 __func__, cck[0], cck[1], ofdm[0], ofdm[1]); 1437 1438 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) { 1439 if (cck[i] > RF6052_MAX_TX_PWR) 1440 cck[i] = RF6052_MAX_TX_PWR; 1441 if (ofdm[i] > RF6052_MAX_TX_PWR) 1442 ofdm[i] = RF6052_MAX_TX_PWR; 1443 } 1444 1445 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); 1446 val32 &= 0xffff00ff; 1447 val32 |= (cck[0] << 8); 1448 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); 1449 1450 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); 1451 val32 &= 0xff; 1452 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24)); 1453 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); 1454 1455 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); 1456 val32 &= 0xffffff00; 1457 val32 |= cck[1]; 1458 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); 1459 1460 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32); 1461 val32 &= 0xff; 1462 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24)); 1463 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32); 1464 1465 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 | 1466 ofdmbase[0] << 16 | ofdmbase[0] << 24; 1467 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 | 1468 ofdmbase[1] << 16 | ofdmbase[1] << 24; 1469 1470 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, 1471 ofdm_a + power_base->reg_0e00); 1472 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, 1473 ofdm_b + power_base->reg_0830); 1474 1475 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, 1476 ofdm_a + power_base->reg_0e04); 1477 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, 1478 ofdm_b + power_base->reg_0834); 1479 1480 mcs_a = mcsbase[0] | mcsbase[0] << 8 | 1481 mcsbase[0] << 16 | mcsbase[0] << 24; 1482 mcs_b = mcsbase[1] | mcsbase[1] << 8 | 1483 mcsbase[1] << 16 | mcsbase[1] << 24; 1484 1485 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, 1486 mcs_a + power_base->reg_0e10); 1487 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, 1488 mcs_b + power_base->reg_083c); 1489 1490 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, 1491 mcs_a + power_base->reg_0e14); 1492 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, 1493 mcs_b + power_base->reg_0848); 1494 1495 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, 1496 mcs_a + power_base->reg_0e18); 1497 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, 1498 mcs_b + power_base->reg_084c); 1499 1500 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, 1501 mcs_a + power_base->reg_0e1c); 1502 for (i = 0; i < 3; i++) { 1503 if (i != 2) 1504 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0; 1505 else 1506 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0; 1507 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8); 1508 } 1509 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, 1510 mcs_b + power_base->reg_0868); 1511 for (i = 0; i < 3; i++) { 1512 if (i != 2) 1513 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0; 1514 else 1515 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0; 1516 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8); 1517 } 1518 } 1519 1520 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv, 1521 enum nl80211_iftype linktype) 1522 { 1523 u8 val8; 1524 1525 val8 = rtl8xxxu_read8(priv, REG_MSR); 1526 val8 &= ~MSR_LINKTYPE_MASK; 1527 1528 switch (linktype) { 1529 case NL80211_IFTYPE_UNSPECIFIED: 1530 val8 |= MSR_LINKTYPE_NONE; 1531 break; 1532 case NL80211_IFTYPE_ADHOC: 1533 val8 |= MSR_LINKTYPE_ADHOC; 1534 break; 1535 case NL80211_IFTYPE_STATION: 1536 val8 |= MSR_LINKTYPE_STATION; 1537 break; 1538 case NL80211_IFTYPE_AP: 1539 val8 |= MSR_LINKTYPE_AP; 1540 break; 1541 default: 1542 goto out; 1543 } 1544 1545 rtl8xxxu_write8(priv, REG_MSR, val8); 1546 out: 1547 return; 1548 } 1549 1550 static void 1551 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry) 1552 { 1553 u16 val16; 1554 1555 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) & 1556 RETRY_LIMIT_SHORT_MASK) | 1557 ((long_retry << RETRY_LIMIT_LONG_SHIFT) & 1558 RETRY_LIMIT_LONG_MASK); 1559 1560 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16); 1561 } 1562 1563 static void 1564 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm) 1565 { 1566 u16 val16; 1567 1568 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) | 1569 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK); 1570 1571 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16); 1572 } 1573 1574 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv) 1575 { 1576 struct device *dev = &priv->udev->dev; 1577 char cut = '?'; 1578 1579 /* Currently always true: chip_cut is 4 bits. */ 1580 if (priv->chip_cut <= 15) 1581 cut = 'A' + priv->chip_cut; 1582 1583 dev_info(dev, 1584 "RTL%s rev %c (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n", 1585 priv->chip_name, cut, priv->chip_vendor, priv->tx_paths, 1586 priv->rx_paths, priv->ep_tx_count, priv->has_wifi, 1587 priv->has_bluetooth, priv->has_gps, priv->hi_pa); 1588 1589 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr); 1590 } 1591 1592 void rtl8xxxu_identify_vendor_1bit(struct rtl8xxxu_priv *priv, u32 vendor) 1593 { 1594 if (vendor) { 1595 strscpy(priv->chip_vendor, "UMC", sizeof(priv->chip_vendor)); 1596 priv->vendor_umc = 1; 1597 } else { 1598 strscpy(priv->chip_vendor, "TSMC", sizeof(priv->chip_vendor)); 1599 } 1600 } 1601 1602 void rtl8xxxu_identify_vendor_2bits(struct rtl8xxxu_priv *priv, u32 vendor) 1603 { 1604 switch (vendor) { 1605 case SYS_CFG_VENDOR_ID_TSMC: 1606 strscpy(priv->chip_vendor, "TSMC", sizeof(priv->chip_vendor)); 1607 break; 1608 case SYS_CFG_VENDOR_ID_SMIC: 1609 strscpy(priv->chip_vendor, "SMIC", sizeof(priv->chip_vendor)); 1610 priv->vendor_smic = 1; 1611 break; 1612 case SYS_CFG_VENDOR_ID_UMC: 1613 strscpy(priv->chip_vendor, "UMC", sizeof(priv->chip_vendor)); 1614 priv->vendor_umc = 1; 1615 break; 1616 default: 1617 strscpy(priv->chip_vendor, "unknown", sizeof(priv->chip_vendor)); 1618 } 1619 } 1620 1621 void rtl8xxxu_config_endpoints_sie(struct rtl8xxxu_priv *priv) 1622 { 1623 u16 val16; 1624 1625 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX); 1626 1627 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) { 1628 priv->ep_tx_high_queue = 1; 1629 priv->ep_tx_count++; 1630 } 1631 1632 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) { 1633 priv->ep_tx_normal_queue = 1; 1634 priv->ep_tx_count++; 1635 } 1636 1637 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) { 1638 priv->ep_tx_low_queue = 1; 1639 priv->ep_tx_count++; 1640 } 1641 } 1642 1643 int rtl8xxxu_config_endpoints_no_sie(struct rtl8xxxu_priv *priv) 1644 { 1645 struct device *dev = &priv->udev->dev; 1646 1647 switch (priv->nr_out_eps) { 1648 case 4: 1649 case 3: 1650 priv->ep_tx_low_queue = 1; 1651 priv->ep_tx_count++; 1652 fallthrough; 1653 case 2: 1654 priv->ep_tx_normal_queue = 1; 1655 priv->ep_tx_count++; 1656 fallthrough; 1657 case 1: 1658 priv->ep_tx_high_queue = 1; 1659 priv->ep_tx_count++; 1660 break; 1661 default: 1662 dev_info(dev, "Unsupported USB TX end-points\n"); 1663 return -ENOTSUPP; 1664 } 1665 1666 return 0; 1667 } 1668 1669 int 1670 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data) 1671 { 1672 int i; 1673 u8 val8; 1674 u32 val32; 1675 1676 /* Write Address */ 1677 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff); 1678 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2); 1679 val8 &= 0xfc; 1680 val8 |= (offset >> 8) & 0x03; 1681 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8); 1682 1683 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3); 1684 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f); 1685 1686 /* Poll for data read */ 1687 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); 1688 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) { 1689 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); 1690 if (val32 & BIT(31)) 1691 break; 1692 } 1693 1694 if (i == RTL8XXXU_MAX_REG_POLL) 1695 return -EIO; 1696 1697 udelay(50); 1698 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); 1699 1700 *data = val32 & 0xff; 1701 return 0; 1702 } 1703 1704 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv) 1705 { 1706 struct device *dev = &priv->udev->dev; 1707 int i, ret = 0; 1708 u8 val8, word_mask, header, extheader; 1709 u16 val16, efuse_addr, offset; 1710 u32 val32; 1711 1712 val16 = rtl8xxxu_read16(priv, REG_9346CR); 1713 if (val16 & EEPROM_ENABLE) 1714 priv->has_eeprom = 1; 1715 if (val16 & EEPROM_BOOT) 1716 priv->boot_eeprom = 1; 1717 1718 if (priv->is_multi_func) { 1719 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST); 1720 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT; 1721 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32); 1722 } 1723 1724 dev_dbg(dev, "Booting from %s\n", 1725 priv->boot_eeprom ? "EEPROM" : "EFUSE"); 1726 1727 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE); 1728 1729 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */ 1730 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL); 1731 if (!(val16 & SYS_ISO_PWC_EV12V)) { 1732 val16 |= SYS_ISO_PWC_EV12V; 1733 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16); 1734 } 1735 /* Reset: 0x0000[28], default valid */ 1736 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1737 if (!(val16 & SYS_FUNC_ELDR)) { 1738 val16 |= SYS_FUNC_ELDR; 1739 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 1740 } 1741 1742 /* 1743 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid 1744 */ 1745 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR); 1746 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) { 1747 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M); 1748 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16); 1749 } 1750 1751 /* Default value is 0xff */ 1752 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN); 1753 1754 efuse_addr = 0; 1755 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) { 1756 u16 map_addr; 1757 1758 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header); 1759 if (ret || header == 0xff) 1760 goto exit; 1761 1762 if ((header & 0x1f) == 0x0f) { /* extended header */ 1763 offset = (header & 0xe0) >> 5; 1764 1765 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, 1766 &extheader); 1767 if (ret) 1768 goto exit; 1769 /* All words disabled */ 1770 if ((extheader & 0x0f) == 0x0f) 1771 continue; 1772 1773 offset |= ((extheader & 0xf0) >> 1); 1774 word_mask = extheader & 0x0f; 1775 } else { 1776 offset = (header >> 4) & 0x0f; 1777 word_mask = header & 0x0f; 1778 } 1779 1780 /* Get word enable value from PG header */ 1781 1782 /* We have 8 bits to indicate validity */ 1783 map_addr = offset * 8; 1784 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { 1785 /* Check word enable condition in the section */ 1786 if (word_mask & BIT(i)) { 1787 map_addr += 2; 1788 continue; 1789 } 1790 1791 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8); 1792 if (ret) 1793 goto exit; 1794 if (map_addr >= EFUSE_MAP_LEN - 1) { 1795 dev_warn(dev, "%s: Illegal map_addr (%04x), " 1796 "efuse corrupt!\n", 1797 __func__, map_addr); 1798 ret = -EINVAL; 1799 goto exit; 1800 } 1801 priv->efuse_wifi.raw[map_addr++] = val8; 1802 1803 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8); 1804 if (ret) 1805 goto exit; 1806 priv->efuse_wifi.raw[map_addr++] = val8; 1807 } 1808 } 1809 1810 exit: 1811 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE); 1812 1813 return ret; 1814 } 1815 1816 void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv) 1817 { 1818 u8 val8; 1819 u16 sys_func; 1820 1821 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 1822 val8 &= ~BIT(0); 1823 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 1824 1825 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1826 sys_func &= ~SYS_FUNC_CPU_ENABLE; 1827 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); 1828 1829 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 1830 val8 |= BIT(0); 1831 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 1832 1833 sys_func |= SYS_FUNC_CPU_ENABLE; 1834 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); 1835 } 1836 1837 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv) 1838 { 1839 struct device *dev = &priv->udev->dev; 1840 int ret = 0, i; 1841 u32 val32; 1842 1843 /* Poll checksum report */ 1844 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) { 1845 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); 1846 if (val32 & MCU_FW_DL_CSUM_REPORT) 1847 break; 1848 } 1849 1850 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) { 1851 dev_warn(dev, "Firmware checksum poll timed out\n"); 1852 ret = -EAGAIN; 1853 goto exit; 1854 } 1855 1856 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); 1857 val32 |= MCU_FW_DL_READY; 1858 val32 &= ~MCU_WINT_INIT_READY; 1859 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32); 1860 1861 /* 1862 * Reset the 8051 in order for the firmware to start running, 1863 * otherwise it won't come up on the 8192eu 1864 */ 1865 priv->fops->reset_8051(priv); 1866 1867 /* Wait for firmware to become ready */ 1868 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) { 1869 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); 1870 if (val32 & MCU_WINT_INIT_READY) 1871 break; 1872 1873 udelay(100); 1874 } 1875 1876 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) { 1877 dev_warn(dev, "Firmware failed to start\n"); 1878 ret = -EAGAIN; 1879 goto exit; 1880 } 1881 1882 /* 1883 * Init H2C command 1884 */ 1885 if (priv->rtl_chip == RTL8723B || priv->rtl_chip == RTL8188F) 1886 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f); 1887 exit: 1888 return ret; 1889 } 1890 1891 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv) 1892 { 1893 int pages, remainder, i, ret; 1894 u8 val8; 1895 u16 val16; 1896 u32 val32; 1897 u8 *fwptr; 1898 1899 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1); 1900 val8 |= 4; 1901 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8); 1902 1903 /* 8051 enable */ 1904 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1905 val16 |= SYS_FUNC_CPU_ENABLE; 1906 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 1907 1908 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL); 1909 if (val8 & MCU_FW_RAM_SEL) { 1910 dev_info(&priv->udev->dev, 1911 "Firmware is already running, resetting the MCU.\n"); 1912 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); 1913 priv->fops->reset_8051(priv); 1914 } 1915 1916 /* MCU firmware download enable */ 1917 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL); 1918 val8 |= MCU_FW_DL_ENABLE; 1919 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8); 1920 1921 /* 8051 reset */ 1922 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); 1923 val32 &= ~BIT(19); 1924 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32); 1925 1926 /* Reset firmware download checksum */ 1927 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL); 1928 val8 |= MCU_FW_DL_CSUM_REPORT; 1929 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8); 1930 1931 pages = priv->fw_size / RTL_FW_PAGE_SIZE; 1932 remainder = priv->fw_size % RTL_FW_PAGE_SIZE; 1933 1934 fwptr = priv->fw_data->data; 1935 1936 for (i = 0; i < pages; i++) { 1937 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8; 1938 val8 |= i; 1939 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8); 1940 1941 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS, 1942 fwptr, RTL_FW_PAGE_SIZE); 1943 if (ret != RTL_FW_PAGE_SIZE) { 1944 ret = -EAGAIN; 1945 goto fw_abort; 1946 } 1947 1948 fwptr += RTL_FW_PAGE_SIZE; 1949 } 1950 1951 if (remainder) { 1952 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8; 1953 val8 |= i; 1954 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8); 1955 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS, 1956 fwptr, remainder); 1957 if (ret != remainder) { 1958 ret = -EAGAIN; 1959 goto fw_abort; 1960 } 1961 } 1962 1963 ret = 0; 1964 fw_abort: 1965 /* MCU firmware download disable */ 1966 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL); 1967 val16 &= ~MCU_FW_DL_ENABLE; 1968 rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16); 1969 1970 return ret; 1971 } 1972 1973 int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name) 1974 { 1975 struct device *dev = &priv->udev->dev; 1976 const struct firmware *fw; 1977 int ret = 0; 1978 u16 signature; 1979 1980 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name); 1981 if (request_firmware(&fw, fw_name, &priv->udev->dev)) { 1982 dev_warn(dev, "request_firmware(%s) failed\n", fw_name); 1983 ret = -EAGAIN; 1984 goto exit; 1985 } 1986 if (!fw) { 1987 dev_warn(dev, "Firmware data not available\n"); 1988 ret = -EINVAL; 1989 goto exit; 1990 } 1991 1992 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL); 1993 if (!priv->fw_data) { 1994 ret = -ENOMEM; 1995 goto exit; 1996 } 1997 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header); 1998 1999 signature = le16_to_cpu(priv->fw_data->signature); 2000 switch (signature & 0xfff0) { 2001 case 0x92e0: 2002 case 0x92c0: 2003 case 0x88c0: 2004 case 0x5300: 2005 case 0x2300: 2006 case 0x88f0: 2007 break; 2008 default: 2009 ret = -EINVAL; 2010 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n", 2011 __func__, signature); 2012 } 2013 2014 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n", 2015 le16_to_cpu(priv->fw_data->major_version), 2016 priv->fw_data->minor_version, signature); 2017 2018 exit: 2019 release_firmware(fw); 2020 return ret; 2021 } 2022 2023 void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv) 2024 { 2025 u16 val16; 2026 int i = 100; 2027 2028 /* Inform 8051 to perform reset */ 2029 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20); 2030 2031 for (i = 100; i > 0; i--) { 2032 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2033 2034 if (!(val16 & SYS_FUNC_CPU_ENABLE)) { 2035 dev_dbg(&priv->udev->dev, 2036 "%s: Firmware self reset success!\n", __func__); 2037 break; 2038 } 2039 udelay(50); 2040 } 2041 2042 if (!i) { 2043 /* Force firmware reset */ 2044 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2045 val16 &= ~SYS_FUNC_CPU_ENABLE; 2046 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 2047 } 2048 } 2049 2050 static int 2051 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv) 2052 { 2053 const struct rtl8xxxu_reg8val *array = priv->fops->mactable; 2054 int i, ret; 2055 u16 reg; 2056 u8 val; 2057 2058 for (i = 0; ; i++) { 2059 reg = array[i].reg; 2060 val = array[i].val; 2061 2062 if (reg == 0xffff && val == 0xff) 2063 break; 2064 2065 ret = rtl8xxxu_write8(priv, reg, val); 2066 if (ret != 1) { 2067 dev_warn(&priv->udev->dev, 2068 "Failed to initialize MAC " 2069 "(reg: %04x, val %02x)\n", reg, val); 2070 return -EAGAIN; 2071 } 2072 } 2073 2074 if (priv->rtl_chip != RTL8723B && 2075 priv->rtl_chip != RTL8192E && 2076 priv->rtl_chip != RTL8188F) 2077 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a); 2078 2079 return 0; 2080 } 2081 2082 int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv, 2083 const struct rtl8xxxu_reg32val *array) 2084 { 2085 int i, ret; 2086 u16 reg; 2087 u32 val; 2088 2089 for (i = 0; ; i++) { 2090 reg = array[i].reg; 2091 val = array[i].val; 2092 2093 if (reg == 0xffff && val == 0xffffffff) 2094 break; 2095 2096 ret = rtl8xxxu_write32(priv, reg, val); 2097 if (ret != sizeof(val)) { 2098 dev_warn(&priv->udev->dev, 2099 "Failed to initialize PHY\n"); 2100 return -EAGAIN; 2101 } 2102 udelay(1); 2103 } 2104 2105 return 0; 2106 } 2107 2108 void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv) 2109 { 2110 u8 val8, ldoa15, ldov12d, lpldo, ldohci12; 2111 u16 val16; 2112 u32 val32; 2113 2114 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); 2115 udelay(2); 2116 val8 |= AFE_PLL_320_ENABLE; 2117 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); 2118 udelay(2); 2119 2120 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff); 2121 udelay(2); 2122 2123 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2124 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB; 2125 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 2126 2127 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); 2128 val32 &= ~AFE_XTAL_RF_GATE; 2129 if (priv->has_bluetooth) 2130 val32 &= ~AFE_XTAL_BT_GATE; 2131 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); 2132 2133 /* 6. 0x1f[7:0] = 0x07 */ 2134 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; 2135 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); 2136 2137 if (priv->hi_pa) 2138 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table); 2139 else if (priv->tx_paths == 2) 2140 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table); 2141 else 2142 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table); 2143 2144 if (priv->rtl_chip == RTL8188R && priv->hi_pa && 2145 priv->vendor_umc && priv->chip_cut == 1) 2146 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50); 2147 2148 if (priv->hi_pa) 2149 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table); 2150 else 2151 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table); 2152 2153 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF; 2154 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT); 2155 ldohci12 = 0x57; 2156 lpldo = 1; 2157 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15; 2158 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32); 2159 } 2160 2161 /* 2162 * Most of this is black magic retrieved from the old rtl8723au driver 2163 */ 2164 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv) 2165 { 2166 u32 val32; 2167 2168 priv->fops->init_phy_bb(priv); 2169 2170 if (priv->tx_paths == 1 && priv->rx_paths == 2) { 2171 /* 2172 * For 1T2R boards, patch the registers. 2173 * 2174 * It looks like 8191/2 1T2R boards use path B for TX 2175 */ 2176 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO); 2177 val32 &= ~(BIT(0) | BIT(1)); 2178 val32 |= BIT(1); 2179 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32); 2180 2181 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO); 2182 val32 &= ~0x300033; 2183 val32 |= 0x200022; 2184 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32); 2185 2186 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); 2187 val32 &= ~CCK0_AFE_RX_MASK; 2188 val32 &= 0x00ffffff; 2189 val32 |= 0x40000000; 2190 val32 |= CCK0_AFE_RX_ANT_B; 2191 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); 2192 2193 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 2194 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); 2195 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B | 2196 OFDM_RF_PATH_TX_B); 2197 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 2198 2199 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1); 2200 val32 &= ~(BIT(4) | BIT(5)); 2201 val32 |= BIT(4); 2202 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32); 2203 2204 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON); 2205 val32 &= ~(BIT(27) | BIT(26)); 2206 val32 |= BIT(27); 2207 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32); 2208 2209 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON); 2210 val32 &= ~(BIT(27) | BIT(26)); 2211 val32 |= BIT(27); 2212 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32); 2213 2214 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON); 2215 val32 &= ~(BIT(27) | BIT(26)); 2216 val32 |= BIT(27); 2217 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32); 2218 2219 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON); 2220 val32 &= ~(BIT(27) | BIT(26)); 2221 val32 |= BIT(27); 2222 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32); 2223 2224 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX); 2225 val32 &= ~(BIT(27) | BIT(26)); 2226 val32 |= BIT(27); 2227 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32); 2228 } 2229 2230 if (priv->fops->set_crystal_cap) 2231 priv->fops->set_crystal_cap(priv, priv->default_crystal_cap); 2232 2233 if (priv->rtl_chip == RTL8192E) 2234 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x000f81fb); 2235 2236 return 0; 2237 } 2238 2239 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv, 2240 const struct rtl8xxxu_rfregval *array, 2241 enum rtl8xxxu_rfpath path) 2242 { 2243 int i, ret; 2244 u8 reg; 2245 u32 val; 2246 2247 for (i = 0; ; i++) { 2248 reg = array[i].reg; 2249 val = array[i].val; 2250 2251 if (reg == 0xff && val == 0xffffffff) 2252 break; 2253 2254 switch (reg) { 2255 case 0xfe: 2256 msleep(50); 2257 continue; 2258 case 0xfd: 2259 mdelay(5); 2260 continue; 2261 case 0xfc: 2262 mdelay(1); 2263 continue; 2264 case 0xfb: 2265 udelay(50); 2266 continue; 2267 case 0xfa: 2268 udelay(5); 2269 continue; 2270 case 0xf9: 2271 udelay(1); 2272 continue; 2273 } 2274 2275 ret = rtl8xxxu_write_rfreg(priv, path, reg, val); 2276 if (ret) { 2277 dev_warn(&priv->udev->dev, 2278 "Failed to initialize RF\n"); 2279 return -EAGAIN; 2280 } 2281 udelay(1); 2282 } 2283 2284 return 0; 2285 } 2286 2287 int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv, 2288 const struct rtl8xxxu_rfregval *table, 2289 enum rtl8xxxu_rfpath path) 2290 { 2291 u32 val32; 2292 u16 val16, rfsi_rfenv; 2293 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2; 2294 2295 switch (path) { 2296 case RF_A: 2297 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL; 2298 reg_int_oe = REG_FPGA0_XA_RF_INT_OE; 2299 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2; 2300 break; 2301 case RF_B: 2302 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL; 2303 reg_int_oe = REG_FPGA0_XB_RF_INT_OE; 2304 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2; 2305 break; 2306 default: 2307 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n", 2308 __func__, path + 'A'); 2309 return -EINVAL; 2310 } 2311 /* For path B, use XB */ 2312 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl); 2313 rfsi_rfenv &= FPGA0_RF_RFENV; 2314 2315 /* 2316 * These two we might be able to optimize into one 2317 */ 2318 val32 = rtl8xxxu_read32(priv, reg_int_oe); 2319 val32 |= BIT(20); /* 0x10 << 16 */ 2320 rtl8xxxu_write32(priv, reg_int_oe, val32); 2321 udelay(1); 2322 2323 val32 = rtl8xxxu_read32(priv, reg_int_oe); 2324 val32 |= BIT(4); 2325 rtl8xxxu_write32(priv, reg_int_oe, val32); 2326 udelay(1); 2327 2328 /* 2329 * These two we might be able to optimize into one 2330 */ 2331 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); 2332 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN; 2333 rtl8xxxu_write32(priv, reg_hssi_parm2, val32); 2334 udelay(1); 2335 2336 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); 2337 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN; 2338 rtl8xxxu_write32(priv, reg_hssi_parm2, val32); 2339 udelay(1); 2340 2341 rtl8xxxu_init_rf_regs(priv, table, path); 2342 2343 /* For path B, use XB */ 2344 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl); 2345 val16 &= ~FPGA0_RF_RFENV; 2346 val16 |= rfsi_rfenv; 2347 rtl8xxxu_write16(priv, reg_sw_ctrl, val16); 2348 2349 return 0; 2350 } 2351 2352 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data) 2353 { 2354 int ret = -EBUSY; 2355 int count = 0; 2356 u32 value; 2357 2358 value = LLT_OP_WRITE | address << 8 | data; 2359 2360 rtl8xxxu_write32(priv, REG_LLT_INIT, value); 2361 2362 do { 2363 value = rtl8xxxu_read32(priv, REG_LLT_INIT); 2364 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) { 2365 ret = 0; 2366 break; 2367 } 2368 } while (count++ < 20); 2369 2370 return ret; 2371 } 2372 2373 int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv) 2374 { 2375 int ret; 2376 int i; 2377 u8 last_tx_page; 2378 2379 last_tx_page = priv->fops->total_page_num; 2380 2381 for (i = 0; i < last_tx_page; i++) { 2382 ret = rtl8xxxu_llt_write(priv, i, i + 1); 2383 if (ret) 2384 goto exit; 2385 } 2386 2387 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff); 2388 if (ret) 2389 goto exit; 2390 2391 /* Mark remaining pages as a ring buffer */ 2392 for (i = last_tx_page + 1; i < 0xff; i++) { 2393 ret = rtl8xxxu_llt_write(priv, i, (i + 1)); 2394 if (ret) 2395 goto exit; 2396 } 2397 2398 /* Let last entry point to the start entry of ring buffer */ 2399 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1); 2400 if (ret) 2401 goto exit; 2402 2403 exit: 2404 return ret; 2405 } 2406 2407 int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv) 2408 { 2409 u32 val32; 2410 int ret = 0; 2411 int i; 2412 2413 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT); 2414 val32 |= AUTO_LLT_INIT_LLT; 2415 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32); 2416 2417 for (i = 500; i; i--) { 2418 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT); 2419 if (!(val32 & AUTO_LLT_INIT_LLT)) 2420 break; 2421 usleep_range(2, 4); 2422 } 2423 2424 if (!i) { 2425 ret = -EBUSY; 2426 dev_warn(&priv->udev->dev, "LLT table init failed\n"); 2427 } 2428 2429 return ret; 2430 } 2431 2432 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv) 2433 { 2434 u16 val16, hi, lo; 2435 u16 hiq, mgq, bkq, beq, viq, voq; 2436 int hip, mgp, bkp, bep, vip, vop; 2437 int ret = 0; 2438 2439 switch (priv->ep_tx_count) { 2440 case 1: 2441 if (priv->ep_tx_high_queue) { 2442 hi = TRXDMA_QUEUE_HIGH; 2443 } else if (priv->ep_tx_low_queue) { 2444 hi = TRXDMA_QUEUE_LOW; 2445 } else if (priv->ep_tx_normal_queue) { 2446 hi = TRXDMA_QUEUE_NORMAL; 2447 } else { 2448 hi = 0; 2449 ret = -EINVAL; 2450 } 2451 2452 hiq = hi; 2453 mgq = hi; 2454 bkq = hi; 2455 beq = hi; 2456 viq = hi; 2457 voq = hi; 2458 2459 hip = 0; 2460 mgp = 0; 2461 bkp = 0; 2462 bep = 0; 2463 vip = 0; 2464 vop = 0; 2465 break; 2466 case 2: 2467 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) { 2468 hi = TRXDMA_QUEUE_HIGH; 2469 lo = TRXDMA_QUEUE_LOW; 2470 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) { 2471 hi = TRXDMA_QUEUE_NORMAL; 2472 lo = TRXDMA_QUEUE_LOW; 2473 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) { 2474 hi = TRXDMA_QUEUE_HIGH; 2475 lo = TRXDMA_QUEUE_NORMAL; 2476 } else { 2477 ret = -EINVAL; 2478 hi = 0; 2479 lo = 0; 2480 } 2481 2482 hiq = hi; 2483 mgq = hi; 2484 bkq = lo; 2485 beq = lo; 2486 viq = hi; 2487 voq = hi; 2488 2489 hip = 0; 2490 mgp = 0; 2491 bkp = 1; 2492 bep = 1; 2493 vip = 0; 2494 vop = 0; 2495 break; 2496 case 3: 2497 beq = TRXDMA_QUEUE_LOW; 2498 bkq = TRXDMA_QUEUE_LOW; 2499 viq = TRXDMA_QUEUE_NORMAL; 2500 voq = TRXDMA_QUEUE_HIGH; 2501 mgq = TRXDMA_QUEUE_HIGH; 2502 hiq = TRXDMA_QUEUE_HIGH; 2503 2504 hip = hiq ^ 3; 2505 mgp = mgq ^ 3; 2506 bkp = bkq ^ 3; 2507 bep = beq ^ 3; 2508 vip = viq ^ 3; 2509 vop = viq ^ 3; 2510 break; 2511 default: 2512 ret = -EINVAL; 2513 } 2514 2515 /* 2516 * None of the vendor drivers are configuring the beacon 2517 * queue here .... why? 2518 */ 2519 if (!ret) { 2520 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL); 2521 val16 &= 0x7; 2522 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) | 2523 (viq << TRXDMA_CTRL_VIQ_SHIFT) | 2524 (beq << TRXDMA_CTRL_BEQ_SHIFT) | 2525 (bkq << TRXDMA_CTRL_BKQ_SHIFT) | 2526 (mgq << TRXDMA_CTRL_MGQ_SHIFT) | 2527 (hiq << TRXDMA_CTRL_HIQ_SHIFT); 2528 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16); 2529 2530 priv->pipe_out[TXDESC_QUEUE_VO] = 2531 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]); 2532 priv->pipe_out[TXDESC_QUEUE_VI] = 2533 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]); 2534 priv->pipe_out[TXDESC_QUEUE_BE] = 2535 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]); 2536 priv->pipe_out[TXDESC_QUEUE_BK] = 2537 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]); 2538 priv->pipe_out[TXDESC_QUEUE_BEACON] = 2539 usb_sndbulkpipe(priv->udev, priv->out_ep[0]); 2540 priv->pipe_out[TXDESC_QUEUE_MGNT] = 2541 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]); 2542 priv->pipe_out[TXDESC_QUEUE_HIGH] = 2543 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]); 2544 priv->pipe_out[TXDESC_QUEUE_CMD] = 2545 usb_sndbulkpipe(priv->udev, priv->out_ep[0]); 2546 } 2547 2548 return ret; 2549 } 2550 2551 void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok, 2552 int result[][8], int candidate, bool tx_only) 2553 { 2554 u32 oldval, x, tx0_a, reg; 2555 int y, tx0_c; 2556 u32 val32; 2557 2558 if (!iqk_ok) 2559 return; 2560 2561 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); 2562 oldval = val32 >> 22; 2563 2564 x = result[candidate][0]; 2565 if ((x & 0x00000200) != 0) 2566 x = x | 0xfffffc00; 2567 tx0_a = (x * oldval) >> 8; 2568 2569 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); 2570 val32 &= ~0x3ff; 2571 val32 |= tx0_a; 2572 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); 2573 2574 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2575 val32 &= ~BIT(31); 2576 if ((x * oldval >> 7) & 0x1) 2577 val32 |= BIT(31); 2578 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2579 2580 y = result[candidate][1]; 2581 if ((y & 0x00000200) != 0) 2582 y = y | 0xfffffc00; 2583 tx0_c = (y * oldval) >> 8; 2584 2585 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE); 2586 val32 &= ~0xf0000000; 2587 val32 |= (((tx0_c & 0x3c0) >> 6) << 28); 2588 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32); 2589 2590 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); 2591 val32 &= ~0x003f0000; 2592 val32 |= ((tx0_c & 0x3f) << 16); 2593 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); 2594 2595 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2596 val32 &= ~BIT(29); 2597 if ((y * oldval >> 7) & 0x1) 2598 val32 |= BIT(29); 2599 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2600 2601 if (tx_only) { 2602 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__); 2603 return; 2604 } 2605 2606 reg = result[candidate][2]; 2607 2608 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); 2609 val32 &= ~0x3ff; 2610 val32 |= (reg & 0x3ff); 2611 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); 2612 2613 reg = result[candidate][3] & 0x3F; 2614 2615 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); 2616 val32 &= ~0xfc00; 2617 val32 |= ((reg << 10) & 0xfc00); 2618 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); 2619 2620 reg = (result[candidate][3] >> 6) & 0xF; 2621 2622 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA); 2623 val32 &= ~0xf0000000; 2624 val32 |= (reg << 28); 2625 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32); 2626 } 2627 2628 void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok, 2629 int result[][8], int candidate, bool tx_only) 2630 { 2631 u32 oldval, x, tx1_a, reg; 2632 int y, tx1_c; 2633 u32 val32; 2634 2635 if (!iqk_ok) 2636 return; 2637 2638 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); 2639 oldval = val32 >> 22; 2640 2641 x = result[candidate][4]; 2642 if ((x & 0x00000200) != 0) 2643 x = x | 0xfffffc00; 2644 tx1_a = (x * oldval) >> 8; 2645 2646 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); 2647 val32 &= ~0x3ff; 2648 val32 |= tx1_a; 2649 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); 2650 2651 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2652 val32 &= ~BIT(27); 2653 if ((x * oldval >> 7) & 0x1) 2654 val32 |= BIT(27); 2655 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2656 2657 y = result[candidate][5]; 2658 if ((y & 0x00000200) != 0) 2659 y = y | 0xfffffc00; 2660 tx1_c = (y * oldval) >> 8; 2661 2662 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE); 2663 val32 &= ~0xf0000000; 2664 val32 |= (((tx1_c & 0x3c0) >> 6) << 28); 2665 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32); 2666 2667 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); 2668 val32 &= ~0x003f0000; 2669 val32 |= ((tx1_c & 0x3f) << 16); 2670 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); 2671 2672 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2673 val32 &= ~BIT(25); 2674 if ((y * oldval >> 7) & 0x1) 2675 val32 |= BIT(25); 2676 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2677 2678 if (tx_only) { 2679 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__); 2680 return; 2681 } 2682 2683 reg = result[candidate][6]; 2684 2685 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); 2686 val32 &= ~0x3ff; 2687 val32 |= (reg & 0x3ff); 2688 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); 2689 2690 reg = result[candidate][7] & 0x3f; 2691 2692 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); 2693 val32 &= ~0xfc00; 2694 val32 |= ((reg << 10) & 0xfc00); 2695 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); 2696 2697 reg = (result[candidate][7] >> 6) & 0xf; 2698 2699 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE); 2700 val32 &= ~0x0000f000; 2701 val32 |= (reg << 12); 2702 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32); 2703 } 2704 2705 #define MAX_TOLERANCE 5 2706 2707 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv, 2708 int result[][8], int c1, int c2) 2709 { 2710 u32 i, j, diff, simubitmap, bound = 0; 2711 int candidate[2] = {-1, -1}; /* for path A and path B */ 2712 bool retval = true; 2713 2714 if (priv->tx_paths > 1) 2715 bound = 8; 2716 else 2717 bound = 4; 2718 2719 simubitmap = 0; 2720 2721 for (i = 0; i < bound; i++) { 2722 diff = (result[c1][i] > result[c2][i]) ? 2723 (result[c1][i] - result[c2][i]) : 2724 (result[c2][i] - result[c1][i]); 2725 if (diff > MAX_TOLERANCE) { 2726 if ((i == 2 || i == 6) && !simubitmap) { 2727 if (result[c1][i] + result[c1][i + 1] == 0) 2728 candidate[(i / 4)] = c2; 2729 else if (result[c2][i] + result[c2][i + 1] == 0) 2730 candidate[(i / 4)] = c1; 2731 else 2732 simubitmap = simubitmap | (1 << i); 2733 } else { 2734 simubitmap = simubitmap | (1 << i); 2735 } 2736 } 2737 } 2738 2739 if (simubitmap == 0) { 2740 for (i = 0; i < (bound / 4); i++) { 2741 if (candidate[i] >= 0) { 2742 for (j = i * 4; j < (i + 1) * 4 - 2; j++) 2743 result[3][j] = result[candidate[i]][j]; 2744 retval = false; 2745 } 2746 } 2747 return retval; 2748 } else if (!(simubitmap & 0x0f)) { 2749 /* path A OK */ 2750 for (i = 0; i < 4; i++) 2751 result[3][i] = result[c1][i]; 2752 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) { 2753 /* path B OK */ 2754 for (i = 4; i < 8; i++) 2755 result[3][i] = result[c1][i]; 2756 } 2757 2758 return false; 2759 } 2760 2761 bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv, 2762 int result[][8], int c1, int c2) 2763 { 2764 u32 i, j, diff, simubitmap, bound = 0; 2765 int candidate[2] = {-1, -1}; /* for path A and path B */ 2766 int tmp1, tmp2; 2767 bool retval = true; 2768 2769 if (priv->tx_paths > 1) 2770 bound = 8; 2771 else 2772 bound = 4; 2773 2774 simubitmap = 0; 2775 2776 for (i = 0; i < bound; i++) { 2777 if (i & 1) { 2778 if ((result[c1][i] & 0x00000200)) 2779 tmp1 = result[c1][i] | 0xfffffc00; 2780 else 2781 tmp1 = result[c1][i]; 2782 2783 if ((result[c2][i]& 0x00000200)) 2784 tmp2 = result[c2][i] | 0xfffffc00; 2785 else 2786 tmp2 = result[c2][i]; 2787 } else { 2788 tmp1 = result[c1][i]; 2789 tmp2 = result[c2][i]; 2790 } 2791 2792 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); 2793 2794 if (diff > MAX_TOLERANCE) { 2795 if ((i == 2 || i == 6) && !simubitmap) { 2796 if (result[c1][i] + result[c1][i + 1] == 0) 2797 candidate[(i / 4)] = c2; 2798 else if (result[c2][i] + result[c2][i + 1] == 0) 2799 candidate[(i / 4)] = c1; 2800 else 2801 simubitmap = simubitmap | (1 << i); 2802 } else { 2803 simubitmap = simubitmap | (1 << i); 2804 } 2805 } 2806 } 2807 2808 if (simubitmap == 0) { 2809 for (i = 0; i < (bound / 4); i++) { 2810 if (candidate[i] >= 0) { 2811 for (j = i * 4; j < (i + 1) * 4 - 2; j++) 2812 result[3][j] = result[candidate[i]][j]; 2813 retval = false; 2814 } 2815 } 2816 return retval; 2817 } else { 2818 if (!(simubitmap & 0x03)) { 2819 /* path A TX OK */ 2820 for (i = 0; i < 2; i++) 2821 result[3][i] = result[c1][i]; 2822 } 2823 2824 if (!(simubitmap & 0x0c)) { 2825 /* path A RX OK */ 2826 for (i = 2; i < 4; i++) 2827 result[3][i] = result[c1][i]; 2828 } 2829 2830 if (!(simubitmap & 0x30) && priv->tx_paths > 1) { 2831 /* path B TX OK */ 2832 for (i = 4; i < 6; i++) 2833 result[3][i] = result[c1][i]; 2834 } 2835 2836 if (!(simubitmap & 0xc0) && priv->tx_paths > 1) { 2837 /* path B RX OK */ 2838 for (i = 6; i < 8; i++) 2839 result[3][i] = result[c1][i]; 2840 } 2841 } 2842 2843 return false; 2844 } 2845 2846 void 2847 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup) 2848 { 2849 int i; 2850 2851 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++) 2852 backup[i] = rtl8xxxu_read8(priv, reg[i]); 2853 2854 backup[i] = rtl8xxxu_read32(priv, reg[i]); 2855 } 2856 2857 void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv, 2858 const u32 *reg, u32 *backup) 2859 { 2860 int i; 2861 2862 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++) 2863 rtl8xxxu_write8(priv, reg[i], backup[i]); 2864 2865 rtl8xxxu_write32(priv, reg[i], backup[i]); 2866 } 2867 2868 void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 2869 u32 *backup, int count) 2870 { 2871 int i; 2872 2873 for (i = 0; i < count; i++) 2874 backup[i] = rtl8xxxu_read32(priv, regs[i]); 2875 } 2876 2877 void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 2878 u32 *backup, int count) 2879 { 2880 int i; 2881 2882 for (i = 0; i < count; i++) 2883 rtl8xxxu_write32(priv, regs[i], backup[i]); 2884 } 2885 2886 2887 void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs, 2888 bool path_a_on) 2889 { 2890 u32 path_on; 2891 int i; 2892 2893 if (priv->tx_paths == 1) { 2894 path_on = priv->fops->adda_1t_path_on; 2895 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init); 2896 } else { 2897 path_on = path_a_on ? priv->fops->adda_2t_path_on_a : 2898 priv->fops->adda_2t_path_on_b; 2899 2900 rtl8xxxu_write32(priv, regs[0], path_on); 2901 } 2902 2903 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++) 2904 rtl8xxxu_write32(priv, regs[i], path_on); 2905 } 2906 2907 void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv, 2908 const u32 *regs, u32 *backup) 2909 { 2910 int i = 0; 2911 2912 rtl8xxxu_write8(priv, regs[i], 0x3f); 2913 2914 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++) 2915 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3))); 2916 2917 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5))); 2918 } 2919 2920 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv) 2921 { 2922 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32; 2923 int result = 0; 2924 2925 /* path-A IQK setting */ 2926 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f); 2927 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f); 2928 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102); 2929 2930 val32 = (priv->rf_paths > 1) ? 0x28160202 : 2931 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */ 2932 0x28160502; 2933 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32); 2934 2935 /* path-B IQK setting */ 2936 if (priv->rf_paths > 1) { 2937 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22); 2938 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22); 2939 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102); 2940 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202); 2941 } 2942 2943 /* LO calibration setting */ 2944 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1); 2945 2946 /* One shot, path A LOK & IQK */ 2947 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 2948 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 2949 2950 mdelay(1); 2951 2952 /* Check failed */ 2953 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 2954 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 2955 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 2956 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); 2957 2958 if (!(reg_eac & BIT(28)) && 2959 ((reg_e94 & 0x03ff0000) != 0x01420000) && 2960 ((reg_e9c & 0x03ff0000) != 0x00420000)) 2961 result |= 0x01; 2962 else /* If TX not OK, ignore RX */ 2963 goto out; 2964 2965 /* If TX is OK, check whether RX is OK */ 2966 if (!(reg_eac & BIT(27)) && 2967 ((reg_ea4 & 0x03ff0000) != 0x01320000) && 2968 ((reg_eac & 0x03ff0000) != 0x00360000)) 2969 result |= 0x02; 2970 else 2971 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n", 2972 __func__); 2973 out: 2974 return result; 2975 } 2976 2977 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv) 2978 { 2979 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc; 2980 int result = 0; 2981 2982 /* One shot, path B LOK & IQK */ 2983 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002); 2984 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000); 2985 2986 mdelay(1); 2987 2988 /* Check failed */ 2989 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 2990 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 2991 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 2992 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); 2993 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); 2994 2995 if (!(reg_eac & BIT(31)) && 2996 ((reg_eb4 & 0x03ff0000) != 0x01420000) && 2997 ((reg_ebc & 0x03ff0000) != 0x00420000)) 2998 result |= 0x01; 2999 else 3000 goto out; 3001 3002 if (!(reg_eac & BIT(30)) && 3003 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) && 3004 (((reg_ecc & 0x03ff0000) >> 16) != 0x36)) 3005 result |= 0x02; 3006 else 3007 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", 3008 __func__); 3009 out: 3010 return result; 3011 } 3012 3013 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, 3014 int result[][8], int t) 3015 { 3016 struct device *dev = &priv->udev->dev; 3017 u32 i, val32; 3018 int path_a_ok, path_b_ok; 3019 int retry = 2; 3020 static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { 3021 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, 3022 REG_RX_WAIT_CCA, REG_TX_CCK_RFON, 3023 REG_TX_CCK_BBON, REG_TX_OFDM_RFON, 3024 REG_TX_OFDM_BBON, REG_TX_TO_RX, 3025 REG_TX_TO_TX, REG_RX_CCK, 3026 REG_RX_OFDM, REG_RX_WAIT_RIFS, 3027 REG_RX_TO_RX, REG_STANDBY, 3028 REG_SLEEP, REG_PMPD_ANAEN 3029 }; 3030 static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { 3031 REG_TXPAUSE, REG_BEACON_CTRL, 3032 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG 3033 }; 3034 static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { 3035 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, 3036 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, 3037 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, 3038 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE 3039 }; 3040 3041 /* 3042 * Note: IQ calibration must be performed after loading 3043 * PHY_REG.txt , and radio_a, radio_b.txt 3044 */ 3045 3046 if (t == 0) { 3047 /* Save ADDA parameters, turn Path A ADDA on */ 3048 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, 3049 RTL8XXXU_ADDA_REGS); 3050 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 3051 rtl8xxxu_save_regs(priv, iqk_bb_regs, 3052 priv->bb_backup, RTL8XXXU_BB_REGS); 3053 } 3054 3055 rtl8xxxu_path_adda_on(priv, adda_regs, true); 3056 3057 if (t == 0) { 3058 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); 3059 if (val32 & FPGA0_HSSI_PARM1_PI) 3060 priv->pi_enabled = 1; 3061 } 3062 3063 if (!priv->pi_enabled) { 3064 /* Switch BB to PI mode to do IQ Calibration. */ 3065 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); 3066 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100); 3067 } 3068 3069 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 3070 val32 &= ~FPGA_RF_MODE_CCK; 3071 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 3072 3073 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); 3074 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); 3075 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); 3076 3077 if (!priv->no_pape) { 3078 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); 3079 val32 |= (FPGA0_RF_PAPE | 3080 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); 3081 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); 3082 } 3083 3084 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); 3085 val32 &= ~BIT(10); 3086 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); 3087 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); 3088 val32 &= ~BIT(10); 3089 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); 3090 3091 if (priv->tx_paths > 1) { 3092 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); 3093 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000); 3094 } 3095 3096 /* MAC settings */ 3097 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); 3098 3099 /* Page B init */ 3100 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000); 3101 3102 if (priv->tx_paths > 1) 3103 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000); 3104 3105 /* IQ calibration setting */ 3106 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); 3107 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 3108 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 3109 3110 for (i = 0; i < retry; i++) { 3111 path_a_ok = rtl8xxxu_iqk_path_a(priv); 3112 if (path_a_ok == 0x03) { 3113 val32 = rtl8xxxu_read32(priv, 3114 REG_TX_POWER_BEFORE_IQK_A); 3115 result[t][0] = (val32 >> 16) & 0x3ff; 3116 val32 = rtl8xxxu_read32(priv, 3117 REG_TX_POWER_AFTER_IQK_A); 3118 result[t][1] = (val32 >> 16) & 0x3ff; 3119 val32 = rtl8xxxu_read32(priv, 3120 REG_RX_POWER_BEFORE_IQK_A_2); 3121 result[t][2] = (val32 >> 16) & 0x3ff; 3122 val32 = rtl8xxxu_read32(priv, 3123 REG_RX_POWER_AFTER_IQK_A_2); 3124 result[t][3] = (val32 >> 16) & 0x3ff; 3125 break; 3126 } else if (i == (retry - 1) && path_a_ok == 0x01) { 3127 /* TX IQK OK */ 3128 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n", 3129 __func__); 3130 3131 val32 = rtl8xxxu_read32(priv, 3132 REG_TX_POWER_BEFORE_IQK_A); 3133 result[t][0] = (val32 >> 16) & 0x3ff; 3134 val32 = rtl8xxxu_read32(priv, 3135 REG_TX_POWER_AFTER_IQK_A); 3136 result[t][1] = (val32 >> 16) & 0x3ff; 3137 } 3138 } 3139 3140 if (!path_a_ok) 3141 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__); 3142 3143 if (priv->tx_paths > 1) { 3144 /* 3145 * Path A into standby 3146 */ 3147 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0); 3148 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); 3149 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); 3150 3151 /* Turn Path B ADDA on */ 3152 rtl8xxxu_path_adda_on(priv, adda_regs, false); 3153 3154 for (i = 0; i < retry; i++) { 3155 path_b_ok = rtl8xxxu_iqk_path_b(priv); 3156 if (path_b_ok == 0x03) { 3157 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 3158 result[t][4] = (val32 >> 16) & 0x3ff; 3159 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 3160 result[t][5] = (val32 >> 16) & 0x3ff; 3161 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); 3162 result[t][6] = (val32 >> 16) & 0x3ff; 3163 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); 3164 result[t][7] = (val32 >> 16) & 0x3ff; 3165 break; 3166 } else if (i == (retry - 1) && path_b_ok == 0x01) { 3167 /* TX IQK OK */ 3168 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 3169 result[t][4] = (val32 >> 16) & 0x3ff; 3170 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 3171 result[t][5] = (val32 >> 16) & 0x3ff; 3172 } 3173 } 3174 3175 if (!path_b_ok) 3176 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__); 3177 } 3178 3179 /* Back to BB mode, load original value */ 3180 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0); 3181 3182 if (t) { 3183 if (!priv->pi_enabled) { 3184 /* 3185 * Switch back BB to SI mode after finishing 3186 * IQ Calibration 3187 */ 3188 val32 = 0x01000000; 3189 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32); 3190 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32); 3191 } 3192 3193 /* Reload ADDA power saving parameters */ 3194 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, 3195 RTL8XXXU_ADDA_REGS); 3196 3197 /* Reload MAC parameters */ 3198 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 3199 3200 /* Reload BB parameters */ 3201 rtl8xxxu_restore_regs(priv, iqk_bb_regs, 3202 priv->bb_backup, RTL8XXXU_BB_REGS); 3203 3204 /* Restore RX initial gain */ 3205 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3); 3206 3207 if (priv->tx_paths > 1) { 3208 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 3209 0x00032ed3); 3210 } 3211 3212 /* Load 0xe30 IQC default value */ 3213 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); 3214 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); 3215 } 3216 } 3217 3218 void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start) 3219 { 3220 struct h2c_cmd h2c; 3221 3222 memset(&h2c, 0, sizeof(struct h2c_cmd)); 3223 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION; 3224 h2c.bt_wlan_calibration.data = start; 3225 3226 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration)); 3227 } 3228 3229 void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv) 3230 { 3231 struct device *dev = &priv->udev->dev; 3232 int result[4][8]; /* last is final result */ 3233 int i, candidate; 3234 bool path_a_ok, path_b_ok; 3235 u32 reg_e94, reg_e9c, reg_ea4, reg_eac; 3236 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; 3237 s32 reg_tmp = 0; 3238 bool simu; 3239 3240 memset(result, 0, sizeof(result)); 3241 candidate = -1; 3242 3243 path_a_ok = false; 3244 path_b_ok = false; 3245 3246 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 3247 3248 for (i = 0; i < 3; i++) { 3249 rtl8xxxu_phy_iqcalibrate(priv, result, i); 3250 3251 if (i == 1) { 3252 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1); 3253 if (simu) { 3254 candidate = 0; 3255 break; 3256 } 3257 } 3258 3259 if (i == 2) { 3260 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2); 3261 if (simu) { 3262 candidate = 0; 3263 break; 3264 } 3265 3266 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2); 3267 if (simu) { 3268 candidate = 1; 3269 } else { 3270 for (i = 0; i < 8; i++) 3271 reg_tmp += result[3][i]; 3272 3273 if (reg_tmp) 3274 candidate = 3; 3275 else 3276 candidate = -1; 3277 } 3278 } 3279 } 3280 3281 for (i = 0; i < 4; i++) { 3282 reg_e94 = result[i][0]; 3283 reg_e9c = result[i][1]; 3284 reg_ea4 = result[i][2]; 3285 reg_eac = result[i][3]; 3286 reg_eb4 = result[i][4]; 3287 reg_ebc = result[i][5]; 3288 reg_ec4 = result[i][6]; 3289 reg_ecc = result[i][7]; 3290 } 3291 3292 if (candidate >= 0) { 3293 reg_e94 = result[candidate][0]; 3294 priv->rege94 = reg_e94; 3295 reg_e9c = result[candidate][1]; 3296 priv->rege9c = reg_e9c; 3297 reg_ea4 = result[candidate][2]; 3298 reg_eac = result[candidate][3]; 3299 reg_eb4 = result[candidate][4]; 3300 priv->regeb4 = reg_eb4; 3301 reg_ebc = result[candidate][5]; 3302 priv->regebc = reg_ebc; 3303 reg_ec4 = result[candidate][6]; 3304 reg_ecc = result[candidate][7]; 3305 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); 3306 dev_dbg(dev, 3307 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n", 3308 __func__, reg_e94, reg_e9c, 3309 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); 3310 path_a_ok = true; 3311 path_b_ok = true; 3312 } else { 3313 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; 3314 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; 3315 } 3316 3317 if (reg_e94 && candidate >= 0) 3318 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, 3319 candidate, (reg_ea4 == 0)); 3320 3321 if (priv->tx_paths > 1 && reg_eb4) 3322 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, 3323 candidate, (reg_ec4 == 0)); 3324 3325 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, 3326 priv->bb_recovery_backup, RTL8XXXU_BB_REGS); 3327 } 3328 3329 void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv) 3330 { 3331 u32 val32; 3332 u32 rf_amode, rf_bmode = 0, lstf; 3333 3334 /* Check continuous TX and Packet TX */ 3335 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 3336 3337 if (lstf & OFDM_LSTF_MASK) { 3338 /* Disable all continuous TX */ 3339 val32 = lstf & ~OFDM_LSTF_MASK; 3340 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 3341 3342 /* Read original RF mode Path A */ 3343 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC); 3344 3345 /* Set RF mode to standby Path A */ 3346 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 3347 (rf_amode & 0x8ffff) | 0x10000); 3348 3349 /* Path-B */ 3350 if (priv->tx_paths > 1) { 3351 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B, 3352 RF6052_REG_AC); 3353 3354 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 3355 (rf_bmode & 0x8ffff) | 0x10000); 3356 } 3357 } else { 3358 /* Deal with Packet TX case */ 3359 /* block all queues */ 3360 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 3361 } 3362 3363 /* Start LC calibration */ 3364 if (priv->fops->has_s0s1) 3365 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0); 3366 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); 3367 val32 |= 0x08000; 3368 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); 3369 3370 msleep(100); 3371 3372 if (priv->fops->has_s0s1) 3373 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0); 3374 3375 /* Restore original parameters */ 3376 if (lstf & OFDM_LSTF_MASK) { 3377 /* Path-A */ 3378 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf); 3379 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode); 3380 3381 /* Path-B */ 3382 if (priv->tx_paths > 1) 3383 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 3384 rf_bmode); 3385 } else /* Deal with Packet TX case */ 3386 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); 3387 } 3388 3389 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv) 3390 { 3391 int i; 3392 u16 reg; 3393 3394 reg = REG_MACID; 3395 3396 for (i = 0; i < ETH_ALEN; i++) 3397 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]); 3398 3399 return 0; 3400 } 3401 3402 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid) 3403 { 3404 int i; 3405 u16 reg; 3406 3407 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid); 3408 3409 reg = REG_BSSID; 3410 3411 for (i = 0; i < ETH_ALEN; i++) 3412 rtl8xxxu_write8(priv, reg + i, bssid[i]); 3413 3414 return 0; 3415 } 3416 3417 static void 3418 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor) 3419 { 3420 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 }; 3421 u8 max_agg = 0xf; 3422 int i; 3423 3424 ampdu_factor = 1 << (ampdu_factor + 2); 3425 if (ampdu_factor > max_agg) 3426 ampdu_factor = max_agg; 3427 3428 for (i = 0; i < 4; i++) { 3429 if ((vals[i] & 0xf0) > (ampdu_factor << 4)) 3430 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4); 3431 3432 if ((vals[i] & 0x0f) > ampdu_factor) 3433 vals[i] = (vals[i] & 0xf0) | ampdu_factor; 3434 3435 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]); 3436 } 3437 } 3438 3439 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density) 3440 { 3441 u8 val8; 3442 3443 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE); 3444 val8 &= 0xf8; 3445 val8 |= density; 3446 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8); 3447 } 3448 3449 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv) 3450 { 3451 u8 val8; 3452 int count, ret = 0; 3453 3454 /* Start of rtl8723AU_card_enable_flow */ 3455 /* Act to Cardemu sequence*/ 3456 /* Turn off RF */ 3457 rtl8xxxu_write8(priv, REG_RF_CTRL, 0); 3458 3459 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */ 3460 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); 3461 val8 &= ~LEDCFG2_DPDT_SELECT; 3462 rtl8xxxu_write8(priv, REG_LEDCFG2, val8); 3463 3464 /* 0x0005[1] = 1 turn off MAC by HW state machine*/ 3465 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3466 val8 |= BIT(1); 3467 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3468 3469 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 3470 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3471 if ((val8 & BIT(1)) == 0) 3472 break; 3473 udelay(10); 3474 } 3475 3476 if (!count) { 3477 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", 3478 __func__); 3479 ret = -EBUSY; 3480 goto exit; 3481 } 3482 3483 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */ 3484 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); 3485 val8 |= SYS_ISO_ANALOG_IPS; 3486 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); 3487 3488 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/ 3489 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); 3490 val8 &= ~LDOA15_ENABLE; 3491 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); 3492 3493 exit: 3494 return ret; 3495 } 3496 3497 int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv) 3498 { 3499 u8 val8; 3500 u8 val32; 3501 int count, ret = 0; 3502 3503 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 3504 3505 /* 3506 * Poll - wait for RX packet to complete 3507 */ 3508 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 3509 val32 = rtl8xxxu_read32(priv, 0x5f8); 3510 if (!val32) 3511 break; 3512 udelay(10); 3513 } 3514 3515 if (!count) { 3516 dev_warn(&priv->udev->dev, 3517 "%s: RX poll timed out (0x05f8)\n", __func__); 3518 ret = -EBUSY; 3519 goto exit; 3520 } 3521 3522 /* Disable CCK and OFDM, clock gated */ 3523 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 3524 val8 &= ~SYS_FUNC_BBRSTB; 3525 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 3526 3527 udelay(2); 3528 3529 /* Reset baseband */ 3530 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 3531 val8 &= ~SYS_FUNC_BB_GLB_RSTN; 3532 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 3533 3534 /* Reset MAC TRX */ 3535 val8 = rtl8xxxu_read8(priv, REG_CR); 3536 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE; 3537 rtl8xxxu_write8(priv, REG_CR, val8); 3538 3539 /* Reset MAC TRX */ 3540 val8 = rtl8xxxu_read8(priv, REG_CR + 1); 3541 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */ 3542 rtl8xxxu_write8(priv, REG_CR + 1, val8); 3543 3544 /* Respond TX OK to scheduler */ 3545 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); 3546 val8 |= DUAL_TSF_TX_OK; 3547 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); 3548 3549 exit: 3550 return ret; 3551 } 3552 3553 void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv) 3554 { 3555 u8 val8; 3556 3557 /* Clear suspend enable and power down enable*/ 3558 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3559 val8 &= ~(BIT(3) | BIT(7)); 3560 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3561 3562 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ 3563 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); 3564 val8 &= ~BIT(0); 3565 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); 3566 3567 /* 0x04[12:11] = 11 enable WL suspend*/ 3568 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3569 val8 &= ~(BIT(3) | BIT(4)); 3570 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3571 } 3572 3573 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv) 3574 { 3575 u8 val8; 3576 3577 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */ 3578 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20); 3579 3580 /* 0x04[12:11] = 01 enable WL suspend */ 3581 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3582 val8 &= ~BIT(4); 3583 val8 |= BIT(3); 3584 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3585 3586 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3587 val8 |= BIT(7); 3588 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3589 3590 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */ 3591 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); 3592 val8 |= BIT(0); 3593 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); 3594 3595 return 0; 3596 } 3597 3598 int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv) 3599 { 3600 struct device *dev = &priv->udev->dev; 3601 u32 val32; 3602 int retry, retval; 3603 3604 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 3605 3606 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM); 3607 val32 |= RXPKT_NUM_RW_RELEASE_EN; 3608 rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32); 3609 3610 retry = 100; 3611 retval = -EBUSY; 3612 3613 do { 3614 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM); 3615 if (val32 & RXPKT_NUM_RXDMA_IDLE) { 3616 retval = 0; 3617 break; 3618 } 3619 } while (retry--); 3620 3621 rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0); 3622 rtl8xxxu_write32(priv, REG_RQPN, 0x80000000); 3623 mdelay(2); 3624 3625 if (!retry) 3626 dev_warn(dev, "Failed to flush FIFO\n"); 3627 3628 return retval; 3629 } 3630 3631 void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv) 3632 { 3633 /* Fix USB interface interference issue */ 3634 rtl8xxxu_write8(priv, 0xfe40, 0xe0); 3635 rtl8xxxu_write8(priv, 0xfe41, 0x8d); 3636 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3637 /* 3638 * This sets TXDMA_OFFSET_DROP_DATA_EN (bit 9) as well as bits 3639 * 8 and 5, for which I have found no documentation. 3640 */ 3641 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320); 3642 3643 /* 3644 * Solve too many protocol error on USB bus. 3645 * Can't do this for 8188/8192 UMC A cut parts 3646 */ 3647 if (!(!priv->chip_cut && priv->vendor_umc)) { 3648 rtl8xxxu_write8(priv, 0xfe40, 0xe6); 3649 rtl8xxxu_write8(priv, 0xfe41, 0x94); 3650 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3651 3652 rtl8xxxu_write8(priv, 0xfe40, 0xe0); 3653 rtl8xxxu_write8(priv, 0xfe41, 0x19); 3654 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3655 3656 rtl8xxxu_write8(priv, 0xfe40, 0xe5); 3657 rtl8xxxu_write8(priv, 0xfe41, 0x91); 3658 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3659 3660 rtl8xxxu_write8(priv, 0xfe40, 0xe2); 3661 rtl8xxxu_write8(priv, 0xfe41, 0x81); 3662 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3663 } 3664 } 3665 3666 void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv) 3667 { 3668 u32 val32; 3669 3670 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK); 3671 val32 |= TXDMA_OFFSET_DROP_DATA_EN; 3672 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32); 3673 } 3674 3675 void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv) 3676 { 3677 u8 val8; 3678 u16 val16; 3679 u32 val32; 3680 3681 /* 3682 * Workaround for 8188RU LNA power leakage problem. 3683 */ 3684 if (priv->rtl_chip == RTL8188R) { 3685 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM); 3686 val32 |= BIT(1); 3687 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32); 3688 } 3689 3690 rtl8xxxu_flush_fifo(priv); 3691 3692 rtl8xxxu_active_to_lps(priv); 3693 3694 /* Turn off RF */ 3695 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); 3696 3697 /* Reset Firmware if running in RAM */ 3698 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) 3699 rtl8xxxu_firmware_self_reset(priv); 3700 3701 /* Reset MCU */ 3702 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 3703 val16 &= ~SYS_FUNC_CPU_ENABLE; 3704 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 3705 3706 /* Reset MCU ready status */ 3707 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); 3708 3709 rtl8xxxu_active_to_emu(priv); 3710 rtl8xxxu_emu_to_disabled(priv); 3711 3712 /* Reset MCU IO Wrapper */ 3713 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 3714 val8 &= ~BIT(0); 3715 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 3716 3717 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 3718 val8 |= BIT(0); 3719 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 3720 3721 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */ 3722 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e); 3723 } 3724 3725 void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv, 3726 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5) 3727 { 3728 struct h2c_cmd h2c; 3729 3730 memset(&h2c, 0, sizeof(struct h2c_cmd)); 3731 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA; 3732 h2c.b_type_dma.data1 = arg1; 3733 h2c.b_type_dma.data2 = arg2; 3734 h2c.b_type_dma.data3 = arg3; 3735 h2c.b_type_dma.data4 = arg4; 3736 h2c.b_type_dma.data5 = arg5; 3737 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma)); 3738 } 3739 3740 void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv) 3741 { 3742 u32 val32; 3743 3744 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); 3745 val32 &= ~(BIT(22) | BIT(23)); 3746 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); 3747 } 3748 3749 static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv *priv) 3750 { 3751 struct rtl8xxxu_fileops *fops = priv->fops; 3752 u32 hq, lq, nq, eq, pubq; 3753 u32 val32; 3754 3755 hq = 0; 3756 lq = 0; 3757 nq = 0; 3758 eq = 0; 3759 pubq = 0; 3760 3761 if (priv->ep_tx_high_queue) 3762 hq = fops->page_num_hi; 3763 if (priv->ep_tx_low_queue) 3764 lq = fops->page_num_lo; 3765 if (priv->ep_tx_normal_queue) 3766 nq = fops->page_num_norm; 3767 3768 val32 = (nq << RQPN_NPQ_SHIFT) | (eq << RQPN_EPQ_SHIFT); 3769 rtl8xxxu_write32(priv, REG_RQPN_NPQ, val32); 3770 3771 pubq = fops->total_page_num - hq - lq - nq - 1; 3772 3773 val32 = RQPN_LOAD; 3774 val32 |= (hq << RQPN_HI_PQ_SHIFT); 3775 val32 |= (lq << RQPN_LO_PQ_SHIFT); 3776 val32 |= (pubq << RQPN_PUB_PQ_SHIFT); 3777 3778 rtl8xxxu_write32(priv, REG_RQPN, val32); 3779 } 3780 3781 void rtl8xxxu_init_burst(struct rtl8xxxu_priv *priv) 3782 { 3783 u8 val8; 3784 3785 /* 3786 * For USB high speed set 512B packets 3787 */ 3788 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B); 3789 u8p_replace_bits(&val8, 1, RXDMA_PRO_DMA_BURST_SIZE); 3790 u8p_replace_bits(&val8, 3, RXDMA_PRO_DMA_BURST_CNT); 3791 val8 |= RXDMA_PRO_DMA_MODE; 3792 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8); 3793 3794 /* 3795 * Enable single packet AMPDU 3796 */ 3797 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B); 3798 val8 |= HT_SINGLE_AMPDU_ENABLE; 3799 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8); 3800 3801 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14); 3802 if (priv->rtl_chip == RTL8723B) 3803 val8 = 0x5e; 3804 else if (priv->rtl_chip == RTL8188F) 3805 val8 = 0x70; /* 0x5e would make it very slow */ 3806 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, val8); 3807 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff); 3808 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18); 3809 rtl8xxxu_write8(priv, REG_PIFS, 0x00); 3810 if (priv->rtl_chip == RTL8188F) { 3811 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, FWHW_TXQ_CTRL_AMPDU_RETRY); 3812 rtl8xxxu_write32(priv, REG_FAST_EDCA_CTRL, 0x03086666); 3813 } 3814 if (priv->rtl_chip == RTL8723B) 3815 val8 = 0x50; 3816 else if (priv->rtl_chip == RTL8188F) 3817 val8 = 0x28; /* 0x50 would make the upload slow */ 3818 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, val8); 3819 rtl8xxxu_write8(priv, REG_USTIME_EDCA, val8); 3820 3821 /* to prevent mac is reseted by bus. */ 3822 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); 3823 val8 |= RSV_CTRL_WLOCK_1C | RSV_CTRL_DIS_PRST; 3824 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); 3825 } 3826 3827 static int rtl8xxxu_init_device(struct ieee80211_hw *hw) 3828 { 3829 struct rtl8xxxu_priv *priv = hw->priv; 3830 struct device *dev = &priv->udev->dev; 3831 struct rtl8xxxu_fileops *fops = priv->fops; 3832 bool macpower; 3833 int ret; 3834 u8 val8; 3835 u16 val16; 3836 u32 val32; 3837 3838 /* Check if MAC is already powered on */ 3839 val8 = rtl8xxxu_read8(priv, REG_CR); 3840 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR); 3841 3842 /* 3843 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not 3844 * initialized. First MAC returns 0xea, second MAC returns 0x00 3845 */ 3846 if (val8 == 0xea || !(val16 & SYS_CLK_MAC_CLK_ENABLE)) 3847 macpower = false; 3848 else 3849 macpower = true; 3850 3851 if (fops->needs_full_init) 3852 macpower = false; 3853 3854 ret = fops->power_on(priv); 3855 if (ret < 0) { 3856 dev_warn(dev, "%s: Failed power on\n", __func__); 3857 goto exit; 3858 } 3859 3860 if (!macpower) 3861 rtl8xxxu_init_queue_reserved_page(priv); 3862 3863 ret = rtl8xxxu_init_queue_priority(priv); 3864 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret); 3865 if (ret) 3866 goto exit; 3867 3868 /* 3869 * Set RX page boundary 3870 */ 3871 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, fops->trxff_boundary); 3872 3873 ret = rtl8xxxu_download_firmware(priv); 3874 dev_dbg(dev, "%s: download_firmware %i\n", __func__, ret); 3875 if (ret) 3876 goto exit; 3877 ret = rtl8xxxu_start_firmware(priv); 3878 dev_dbg(dev, "%s: start_firmware %i\n", __func__, ret); 3879 if (ret) 3880 goto exit; 3881 3882 if (fops->phy_init_antenna_selection) 3883 fops->phy_init_antenna_selection(priv); 3884 3885 ret = rtl8xxxu_init_mac(priv); 3886 3887 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret); 3888 if (ret) 3889 goto exit; 3890 3891 ret = rtl8xxxu_init_phy_bb(priv); 3892 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret); 3893 if (ret) 3894 goto exit; 3895 3896 ret = fops->init_phy_rf(priv); 3897 if (ret) 3898 goto exit; 3899 3900 /* RFSW Control - clear bit 14 ?? */ 3901 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E) 3902 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003); 3903 3904 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW | 3905 FPGA0_RF_ANTSWB | 3906 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB) << FPGA0_RF_BD_CTRL_SHIFT); 3907 if (!priv->no_pape) { 3908 val32 |= (FPGA0_RF_PAPE | 3909 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); 3910 } 3911 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); 3912 3913 /* 0x860[6:5]= 00 - why? - this sets antenna B */ 3914 if (priv->rtl_chip != RTL8192E) 3915 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210); 3916 3917 if (!macpower) { 3918 /* 3919 * Set TX buffer boundary 3920 */ 3921 val8 = fops->total_page_num + 1; 3922 3923 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8); 3924 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8); 3925 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8); 3926 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8); 3927 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8); 3928 } 3929 3930 /* 3931 * The vendor drivers set PBP for all devices, except 8192e. 3932 * There is no explanation for this in any of the sources. 3933 */ 3934 val8 = (fops->pbp_rx << PBP_PAGE_SIZE_RX_SHIFT) | 3935 (fops->pbp_tx << PBP_PAGE_SIZE_TX_SHIFT); 3936 if (priv->rtl_chip != RTL8192E) 3937 rtl8xxxu_write8(priv, REG_PBP, val8); 3938 3939 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower); 3940 if (!macpower) { 3941 ret = fops->llt_init(priv); 3942 if (ret) { 3943 dev_warn(dev, "%s: LLT table init failed\n", __func__); 3944 goto exit; 3945 } 3946 3947 /* 3948 * Chip specific quirks 3949 */ 3950 fops->usb_quirks(priv); 3951 3952 /* 3953 * Enable TX report and TX report timer for 8723bu/8188eu/... 3954 */ 3955 if (fops->has_tx_report) { 3956 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); 3957 val8 |= TX_REPORT_CTRL_TIMER_ENABLE; 3958 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); 3959 /* Set MAX RPT MACID */ 3960 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02); 3961 /* TX report Timer. Unit: 32us */ 3962 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0); 3963 3964 /* tmp ps ? */ 3965 val8 = rtl8xxxu_read8(priv, 0xa3); 3966 val8 &= 0xf8; 3967 rtl8xxxu_write8(priv, 0xa3, val8); 3968 } 3969 } 3970 3971 /* 3972 * Unit in 8 bytes, not obvious what it is used for 3973 */ 3974 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4); 3975 3976 if (priv->rtl_chip == RTL8192E) { 3977 rtl8xxxu_write32(priv, REG_HIMR0, 0x00); 3978 rtl8xxxu_write32(priv, REG_HIMR1, 0x00); 3979 } else if (priv->rtl_chip == RTL8188F) { 3980 rtl8xxxu_write32(priv, REG_HISR0, 0xffffffff); 3981 rtl8xxxu_write32(priv, REG_HISR1, 0xffffffff); 3982 } else { 3983 /* 3984 * Enable all interrupts - not obvious USB needs to do this 3985 */ 3986 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff); 3987 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff); 3988 } 3989 3990 rtl8xxxu_set_mac(priv); 3991 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION); 3992 3993 /* 3994 * Configure initial WMAC settings 3995 */ 3996 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST | 3997 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL | 3998 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC; 3999 rtl8xxxu_write32(priv, REG_RCR, val32); 4000 4001 if (priv->rtl_chip == RTL8188F) { 4002 /* Accept all data frames */ 4003 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff); 4004 4005 /* 4006 * Since ADF is removed from RCR, ps-poll will not be indicate to driver, 4007 * RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. 4008 */ 4009 rtl8xxxu_write16(priv, REG_RXFLTMAP1, 0x400); 4010 4011 /* Accept all management frames */ 4012 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff); 4013 } else { 4014 /* 4015 * Accept all multicast 4016 */ 4017 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff); 4018 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff); 4019 } 4020 4021 /* 4022 * Init adaptive controls 4023 */ 4024 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 4025 val32 &= ~RESPONSE_RATE_BITMAP_ALL; 4026 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M; 4027 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 4028 4029 /* CCK = 0x0a, OFDM = 0x10 */ 4030 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10); 4031 rtl8xxxu_set_retry(priv, 0x30, 0x30); 4032 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10); 4033 4034 /* 4035 * Init EDCA 4036 */ 4037 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a); 4038 4039 /* Set CCK SIFS */ 4040 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a); 4041 4042 /* Set OFDM SIFS */ 4043 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a); 4044 4045 /* TXOP */ 4046 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b); 4047 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f); 4048 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324); 4049 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226); 4050 4051 /* Set data auto rate fallback retry count */ 4052 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000); 4053 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404); 4054 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201); 4055 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605); 4056 4057 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL); 4058 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY; 4059 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8); 4060 4061 /* Set ACK timeout */ 4062 rtl8xxxu_write8(priv, REG_ACKTO, 0x40); 4063 4064 /* 4065 * Initialize beacon parameters 4066 */ 4067 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8); 4068 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16); 4069 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404); 4070 if (priv->rtl_chip != RTL8188F) 4071 /* Firmware will control REG_DRVERLYINT when power saving is enable, */ 4072 /* so don't set this register on STA mode. */ 4073 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME); 4074 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME); 4075 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F); 4076 4077 /* 4078 * Initialize burst parameters 4079 */ 4080 4081 if (priv->fops->init_burst) 4082 priv->fops->init_burst(priv); 4083 4084 if (fops->init_aggregation) 4085 fops->init_aggregation(priv); 4086 4087 if (priv->rtl_chip == RTL8188F) { 4088 rtl8xxxu_write16(priv, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ 4089 rtl8xxxu_write16(priv, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ 4090 } 4091 4092 /* 4093 * Enable CCK and OFDM block 4094 */ 4095 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 4096 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM); 4097 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 4098 4099 /* 4100 * Invalidate all CAM entries - bit 30 is undocumented 4101 */ 4102 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30)); 4103 4104 /* 4105 * Start out with default power levels for channel 6, 20MHz 4106 */ 4107 fops->set_tx_power(priv, 1, false); 4108 4109 /* Let the 8051 take control of antenna setting */ 4110 if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188F) { 4111 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); 4112 val8 |= LEDCFG2_DPDT_SELECT; 4113 rtl8xxxu_write8(priv, REG_LEDCFG2, val8); 4114 } 4115 4116 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff); 4117 4118 /* Disable BAR - not sure if this has any effect on USB */ 4119 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff); 4120 4121 if (priv->rtl_chip != RTL8188F) 4122 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0); 4123 4124 if (fops->init_statistics) 4125 fops->init_statistics(priv); 4126 4127 if (priv->rtl_chip == RTL8192E) { 4128 /* 4129 * 0x4c6[3] 1: RTS BW = Data BW 4130 * 0: RTS BW depends on CCA / secondary CCA result. 4131 */ 4132 val8 = rtl8xxxu_read8(priv, REG_QUEUE_CTRL); 4133 val8 &= ~BIT(3); 4134 rtl8xxxu_write8(priv, REG_QUEUE_CTRL, val8); 4135 /* 4136 * Reset USB mode switch setting 4137 */ 4138 rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00); 4139 } else if (priv->rtl_chip == RTL8188F) { 4140 /* 4141 * Init GPIO settings for 8188f 4142 */ 4143 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG); 4144 val8 &= ~GPIO_MUXCFG_IO_SEL_ENBT; 4145 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8); 4146 } 4147 4148 if (priv->rtl_chip == RTL8188F) 4149 /* CCK PD */ 4150 rtl8xxxu_write8(priv, REG_CCK_PD_THRESH, CCK_PD_TYPE1_LV1_TH); 4151 4152 fops->phy_lc_calibrate(priv); 4153 4154 fops->phy_iq_calibrate(priv); 4155 4156 /* 4157 * This should enable thermal meter 4158 */ 4159 if (fops->gen2_thermal_meter) { 4160 if (priv->rtl_chip == RTL8188F) { 4161 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B); 4162 val32 |= 0x30000; 4163 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B, val32); 4164 } else { 4165 rtl8xxxu_write_rfreg(priv, 4166 RF_A, RF6052_REG_T_METER_8723B, 0x37cf8); 4167 } 4168 } else { 4169 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60); 4170 } 4171 4172 /* Set NAV_UPPER to 30000us */ 4173 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT); 4174 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8); 4175 4176 if (priv->rtl_chip == RTL8723A) { 4177 /* 4178 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test, 4179 * but we need to find root cause. 4180 * This is 8723au only. 4181 */ 4182 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 4183 if ((val32 & 0xff000000) != 0x83000000) { 4184 val32 |= FPGA_RF_MODE_CCK; 4185 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 4186 } 4187 } else if (priv->rtl_chip == RTL8192E) { 4188 rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00); 4189 } 4190 4191 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL); 4192 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK; 4193 /* ack for xmit mgmt frames. */ 4194 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32); 4195 4196 if (priv->rtl_chip == RTL8192E) { 4197 /* 4198 * Fix LDPC rx hang issue. 4199 */ 4200 val32 = rtl8xxxu_read32(priv, REG_AFE_MISC); 4201 rtl8xxxu_write8(priv, REG_8192E_LDOV12_CTRL, 0x75); 4202 val32 &= 0xfff00fff; 4203 val32 |= 0x0007e000; 4204 rtl8xxxu_write32(priv, REG_AFE_MISC, val32); 4205 4206 /* 4207 * 0x824[9] = 0x82C[9] = 0xA80[7] those registers setting 4208 * should be equal or CCK RSSI report may be incorrect 4209 */ 4210 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2); 4211 priv->cck_agc_report_type = val32 & FPGA0_HSSI_PARM2_CCK_HIGH_PWR; 4212 4213 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_HSSI_PARM2); 4214 if (priv->cck_agc_report_type != (bool)(val32 & FPGA0_HSSI_PARM2_CCK_HIGH_PWR)) { 4215 if (priv->cck_agc_report_type) 4216 val32 |= FPGA0_HSSI_PARM2_CCK_HIGH_PWR; 4217 else 4218 val32 &= ~FPGA0_HSSI_PARM2_CCK_HIGH_PWR; 4219 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM2, val32); 4220 } 4221 4222 val32 = rtl8xxxu_read32(priv, REG_AGC_RPT); 4223 if (priv->cck_agc_report_type) 4224 val32 |= AGC_RPT_CCK; 4225 else 4226 val32 &= ~AGC_RPT_CCK; 4227 rtl8xxxu_write32(priv, REG_AGC_RPT, val32); 4228 } 4229 4230 /* Initialise the center frequency offset tracking */ 4231 if (priv->fops->set_crystal_cap) { 4232 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); 4233 priv->cfo_tracking.atc_status = val32 & CFO_TRACKING_ATC_STATUS; 4234 priv->cfo_tracking.adjust = true; 4235 priv->cfo_tracking.crystal_cap = priv->default_crystal_cap; 4236 } 4237 4238 exit: 4239 return ret; 4240 } 4241 4242 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv, 4243 struct ieee80211_key_conf *key, const u8 *mac) 4244 { 4245 u32 cmd, val32, addr, ctrl; 4246 int j, i, tmp_debug; 4247 4248 tmp_debug = rtl8xxxu_debug; 4249 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY) 4250 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE; 4251 4252 /* 4253 * This is a bit of a hack - the lower bits of the cipher 4254 * suite selector happens to match the cipher index in the CAM 4255 */ 4256 addr = key->keyidx << CAM_CMD_KEY_SHIFT; 4257 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID; 4258 4259 for (j = 5; j >= 0; j--) { 4260 switch (j) { 4261 case 0: 4262 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24); 4263 break; 4264 case 1: 4265 val32 = mac[2] | (mac[3] << 8) | 4266 (mac[4] << 16) | (mac[5] << 24); 4267 break; 4268 default: 4269 i = (j - 2) << 2; 4270 val32 = key->key[i] | (key->key[i + 1] << 8) | 4271 key->key[i + 2] << 16 | key->key[i + 3] << 24; 4272 break; 4273 } 4274 4275 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32); 4276 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j); 4277 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd); 4278 udelay(100); 4279 } 4280 4281 rtl8xxxu_debug = tmp_debug; 4282 } 4283 4284 static 4285 int rtl8xxxu_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) 4286 { 4287 struct rtl8xxxu_priv *priv = hw->priv; 4288 4289 *tx_ant = BIT(priv->tx_paths) - 1; 4290 *rx_ant = BIT(priv->rx_paths) - 1; 4291 4292 return 0; 4293 } 4294 4295 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw, 4296 struct ieee80211_vif *vif, const u8 *mac) 4297 { 4298 struct rtl8xxxu_priv *priv = hw->priv; 4299 u8 val8; 4300 4301 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 4302 val8 |= BEACON_DISABLE_TSF_UPDATE; 4303 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 4304 } 4305 4306 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw, 4307 struct ieee80211_vif *vif) 4308 { 4309 struct rtl8xxxu_priv *priv = hw->priv; 4310 u8 val8; 4311 4312 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 4313 val8 &= ~BEACON_DISABLE_TSF_UPDATE; 4314 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 4315 } 4316 4317 void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv, 4318 u32 ramask, u8 rateid, int sgi, int txbw_40mhz) 4319 { 4320 struct h2c_cmd h2c; 4321 4322 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4323 4324 h2c.ramask.cmd = H2C_SET_RATE_MASK; 4325 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff); 4326 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16); 4327 4328 h2c.ramask.arg = 0x80; 4329 if (sgi) 4330 h2c.ramask.arg |= 0x20; 4331 4332 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n", 4333 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask)); 4334 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.ramask)); 4335 } 4336 4337 void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv, 4338 u32 ramask, u8 rateid, int sgi, int txbw_40mhz) 4339 { 4340 struct h2c_cmd h2c; 4341 u8 bw; 4342 4343 if (txbw_40mhz) 4344 bw = RTL8XXXU_CHANNEL_WIDTH_40; 4345 else 4346 bw = RTL8XXXU_CHANNEL_WIDTH_20; 4347 4348 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4349 4350 h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID; 4351 h2c.b_macid_cfg.ramask0 = ramask & 0xff; 4352 h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff; 4353 h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff; 4354 h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff; 4355 4356 h2c.b_macid_cfg.data1 = rateid; 4357 if (sgi) 4358 h2c.b_macid_cfg.data1 |= BIT(7); 4359 4360 h2c.b_macid_cfg.data2 = bw; 4361 4362 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, rateid %02x, sgi %d, size %zi\n", 4363 __func__, ramask, rateid, sgi, sizeof(h2c.b_macid_cfg)); 4364 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg)); 4365 } 4366 4367 void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv, 4368 u8 macid, bool connect) 4369 { 4370 struct h2c_cmd h2c; 4371 4372 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4373 4374 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT; 4375 4376 if (connect) 4377 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT; 4378 else 4379 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT; 4380 4381 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss)); 4382 } 4383 4384 void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv, 4385 u8 macid, bool connect) 4386 { 4387 /* 4388 * The firmware turns on the rate control when it knows it's 4389 * connected to a network. 4390 */ 4391 struct h2c_cmd h2c; 4392 4393 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4394 4395 h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT; 4396 if (connect) 4397 h2c.media_status_rpt.parm |= BIT(0); 4398 else 4399 h2c.media_status_rpt.parm &= ~BIT(0); 4400 4401 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt)); 4402 } 4403 4404 void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv) 4405 { 4406 u8 agg_ctrl, usb_spec, page_thresh, timeout; 4407 4408 usb_spec = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION); 4409 usb_spec &= ~USB_SPEC_USB_AGG_ENABLE; 4410 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, usb_spec); 4411 4412 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); 4413 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; 4414 4415 if (!rtl8xxxu_dma_aggregation) { 4416 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); 4417 return; 4418 } 4419 4420 agg_ctrl |= TRXDMA_CTRL_RXDMA_AGG_EN; 4421 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); 4422 4423 /* 4424 * The number of packets we can take looks to be buffer size / 512 4425 * which matches the 512 byte rounding we have to do when de-muxing 4426 * the packets. 4427 * 4428 * Sample numbers from the vendor driver: 4429 * USB High-Speed mode values: 4430 * RxAggBlockCount = 8 : 512 byte unit 4431 * RxAggBlockTimeout = 6 4432 * RxAggPageCount = 48 : 128 byte unit 4433 * RxAggPageTimeout = 4 or 6 (absolute time 34ms/(2^6)) 4434 */ 4435 4436 page_thresh = (priv->fops->rx_agg_buf_size / 512); 4437 if (rtl8xxxu_dma_agg_pages >= 0) { 4438 if (rtl8xxxu_dma_agg_pages <= page_thresh) 4439 timeout = page_thresh; 4440 else if (rtl8xxxu_dma_agg_pages <= 6) 4441 dev_err(&priv->udev->dev, 4442 "%s: dma_agg_pages=%i too small, minimum is 6\n", 4443 __func__, rtl8xxxu_dma_agg_pages); 4444 else 4445 dev_err(&priv->udev->dev, 4446 "%s: dma_agg_pages=%i larger than limit %i\n", 4447 __func__, rtl8xxxu_dma_agg_pages, page_thresh); 4448 } 4449 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH, page_thresh); 4450 /* 4451 * REG_RXDMA_AGG_PG_TH + 1 seems to be the timeout register on 4452 * gen2 chips and rtl8188eu. The rtl8723au seems unhappy if we 4453 * don't set it, so better set both. 4454 */ 4455 timeout = 4; 4456 4457 if (rtl8xxxu_dma_agg_timeout >= 0) { 4458 if (rtl8xxxu_dma_agg_timeout <= 127) 4459 timeout = rtl8xxxu_dma_agg_timeout; 4460 else 4461 dev_err(&priv->udev->dev, 4462 "%s: Invalid dma_agg_timeout: %i\n", 4463 __func__, rtl8xxxu_dma_agg_timeout); 4464 } 4465 4466 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH + 1, timeout); 4467 rtl8xxxu_write8(priv, REG_USB_DMA_AGG_TO, timeout); 4468 priv->rx_buf_aggregation = 1; 4469 } 4470 4471 static const struct ieee80211_rate rtl8xxxu_legacy_ratetable[] = { 4472 {.bitrate = 10, .hw_value = 0x00,}, 4473 {.bitrate = 20, .hw_value = 0x01,}, 4474 {.bitrate = 55, .hw_value = 0x02,}, 4475 {.bitrate = 110, .hw_value = 0x03,}, 4476 {.bitrate = 60, .hw_value = 0x04,}, 4477 {.bitrate = 90, .hw_value = 0x05,}, 4478 {.bitrate = 120, .hw_value = 0x06,}, 4479 {.bitrate = 180, .hw_value = 0x07,}, 4480 {.bitrate = 240, .hw_value = 0x08,}, 4481 {.bitrate = 360, .hw_value = 0x09,}, 4482 {.bitrate = 480, .hw_value = 0x0a,}, 4483 {.bitrate = 540, .hw_value = 0x0b,}, 4484 }; 4485 4486 static void rtl8xxxu_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss) 4487 { 4488 if (rate <= DESC_RATE_54M) 4489 return; 4490 4491 if (rate >= DESC_RATE_MCS0 && rate <= DESC_RATE_MCS15) { 4492 if (rate < DESC_RATE_MCS8) 4493 *nss = 1; 4494 else 4495 *nss = 2; 4496 *mcs = rate - DESC_RATE_MCS0; 4497 } 4498 } 4499 4500 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg) 4501 { 4502 struct ieee80211_hw *hw = priv->hw; 4503 u32 val32; 4504 u8 rate_idx = 0; 4505 4506 rate_cfg &= RESPONSE_RATE_BITMAP_ALL; 4507 4508 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 4509 if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ) 4510 val32 &= RESPONSE_RATE_RRSR_INIT_5G; 4511 else 4512 val32 &= RESPONSE_RATE_RRSR_INIT_2G; 4513 val32 |= rate_cfg; 4514 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 4515 4516 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg); 4517 4518 while (rate_cfg) { 4519 rate_cfg = (rate_cfg >> 1); 4520 rate_idx++; 4521 } 4522 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx); 4523 } 4524 4525 static u16 4526 rtl8xxxu_wireless_mode(struct ieee80211_hw *hw, struct ieee80211_sta *sta) 4527 { 4528 u16 network_type = WIRELESS_MODE_UNKNOWN; 4529 4530 if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ) { 4531 if (sta->deflink.vht_cap.vht_supported) 4532 network_type = WIRELESS_MODE_AC; 4533 else if (sta->deflink.ht_cap.ht_supported) 4534 network_type = WIRELESS_MODE_N_5G; 4535 4536 network_type |= WIRELESS_MODE_A; 4537 } else { 4538 if (sta->deflink.vht_cap.vht_supported) 4539 network_type = WIRELESS_MODE_AC; 4540 else if (sta->deflink.ht_cap.ht_supported) 4541 network_type = WIRELESS_MODE_N_24G; 4542 4543 if (sta->deflink.supp_rates[0] <= 0xf) 4544 network_type |= WIRELESS_MODE_B; 4545 else if (sta->deflink.supp_rates[0] & 0xf) 4546 network_type |= (WIRELESS_MODE_B | WIRELESS_MODE_G); 4547 else 4548 network_type |= WIRELESS_MODE_G; 4549 } 4550 4551 return network_type; 4552 } 4553 4554 static void rtl8xxxu_set_aifs(struct rtl8xxxu_priv *priv, u8 slot_time) 4555 { 4556 u32 reg_edca_param[IEEE80211_NUM_ACS] = { 4557 [IEEE80211_AC_VO] = REG_EDCA_VO_PARAM, 4558 [IEEE80211_AC_VI] = REG_EDCA_VI_PARAM, 4559 [IEEE80211_AC_BE] = REG_EDCA_BE_PARAM, 4560 [IEEE80211_AC_BK] = REG_EDCA_BK_PARAM, 4561 }; 4562 u32 val32; 4563 u16 wireless_mode = 0; 4564 u8 aifs, aifsn, sifs; 4565 int i; 4566 4567 if (priv->vif) { 4568 struct ieee80211_sta *sta; 4569 4570 rcu_read_lock(); 4571 sta = ieee80211_find_sta(priv->vif, priv->vif->bss_conf.bssid); 4572 if (sta) 4573 wireless_mode = rtl8xxxu_wireless_mode(priv->hw, sta); 4574 rcu_read_unlock(); 4575 } 4576 4577 if (priv->hw->conf.chandef.chan->band == NL80211_BAND_5GHZ || 4578 (wireless_mode & WIRELESS_MODE_N_24G)) 4579 sifs = 16; 4580 else 4581 sifs = 10; 4582 4583 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 4584 val32 = rtl8xxxu_read32(priv, reg_edca_param[i]); 4585 4586 /* It was set in conf_tx. */ 4587 aifsn = val32 & 0xff; 4588 4589 /* aifsn not set yet or already fixed */ 4590 if (aifsn < 2 || aifsn > 15) 4591 continue; 4592 4593 aifs = aifsn * slot_time + sifs; 4594 4595 val32 &= ~0xff; 4596 val32 |= aifs; 4597 rtl8xxxu_write32(priv, reg_edca_param[i], val32); 4598 } 4599 } 4600 4601 static void rtl8xxxu_update_ra_report(struct rtl8xxxu_ra_report *rarpt, 4602 u8 rate, u8 sgi, u8 bw) 4603 { 4604 u8 mcs, nss; 4605 4606 rarpt->txrate.flags = 0; 4607 4608 if (rate <= DESC_RATE_54M) { 4609 rarpt->txrate.legacy = rtl8xxxu_legacy_ratetable[rate].bitrate; 4610 } else { 4611 rtl8xxxu_desc_to_mcsrate(rate, &mcs, &nss); 4612 rarpt->txrate.flags |= RATE_INFO_FLAGS_MCS; 4613 4614 rarpt->txrate.mcs = mcs; 4615 rarpt->txrate.nss = nss; 4616 4617 if (sgi) 4618 rarpt->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 4619 4620 rarpt->txrate.bw = bw; 4621 } 4622 4623 rarpt->bit_rate = cfg80211_calculate_bitrate(&rarpt->txrate); 4624 rarpt->desc_rate = rate; 4625 } 4626 4627 static void 4628 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 4629 struct ieee80211_bss_conf *bss_conf, u64 changed) 4630 { 4631 struct rtl8xxxu_priv *priv = hw->priv; 4632 struct device *dev = &priv->udev->dev; 4633 struct ieee80211_sta *sta; 4634 struct rtl8xxxu_ra_report *rarpt; 4635 u32 val32; 4636 u8 val8; 4637 4638 rarpt = &priv->ra_report; 4639 4640 if (changed & BSS_CHANGED_ASSOC) { 4641 dev_dbg(dev, "Changed ASSOC: %i!\n", vif->cfg.assoc); 4642 4643 rtl8xxxu_set_linktype(priv, vif->type); 4644 4645 if (vif->cfg.assoc) { 4646 u32 ramask; 4647 int sgi = 0; 4648 u8 highest_rate; 4649 u8 bw; 4650 4651 rcu_read_lock(); 4652 sta = ieee80211_find_sta(vif, bss_conf->bssid); 4653 if (!sta) { 4654 dev_info(dev, "%s: ASSOC no sta found\n", 4655 __func__); 4656 rcu_read_unlock(); 4657 goto error; 4658 } 4659 4660 if (sta->deflink.ht_cap.ht_supported) 4661 dev_info(dev, "%s: HT supported\n", __func__); 4662 if (sta->deflink.vht_cap.vht_supported) 4663 dev_info(dev, "%s: VHT supported\n", __func__); 4664 4665 /* TODO: Set bits 28-31 for rate adaptive id */ 4666 ramask = (sta->deflink.supp_rates[0] & 0xfff) | 4667 sta->deflink.ht_cap.mcs.rx_mask[0] << 12 | 4668 sta->deflink.ht_cap.mcs.rx_mask[1] << 20; 4669 if (sta->deflink.ht_cap.cap & 4670 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)) 4671 sgi = 1; 4672 4673 highest_rate = fls(ramask) - 1; 4674 if (rtl8xxxu_ht40_2g && 4675 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)) 4676 bw = RATE_INFO_BW_40; 4677 else 4678 bw = RATE_INFO_BW_20; 4679 rcu_read_unlock(); 4680 4681 rtl8xxxu_update_ra_report(rarpt, highest_rate, sgi, bw); 4682 4683 priv->vif = vif; 4684 priv->rssi_level = RTL8XXXU_RATR_STA_INIT; 4685 4686 priv->fops->update_rate_mask(priv, ramask, 0, sgi, bw == RATE_INFO_BW_40); 4687 4688 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff); 4689 4690 rtl8xxxu_stop_tx_beacon(priv); 4691 4692 /* joinbss sequence */ 4693 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT, 4694 0xc000 | vif->cfg.aid); 4695 4696 priv->fops->report_connect(priv, 0, true); 4697 } else { 4698 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 4699 val8 |= BEACON_DISABLE_TSF_UPDATE; 4700 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 4701 4702 priv->fops->report_connect(priv, 0, false); 4703 } 4704 } 4705 4706 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 4707 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n", 4708 bss_conf->use_short_preamble); 4709 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 4710 if (bss_conf->use_short_preamble) 4711 val32 |= RSR_ACK_SHORT_PREAMBLE; 4712 else 4713 val32 &= ~RSR_ACK_SHORT_PREAMBLE; 4714 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 4715 } 4716 4717 if (changed & BSS_CHANGED_ERP_SLOT) { 4718 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n", 4719 bss_conf->use_short_slot); 4720 4721 if (bss_conf->use_short_slot) 4722 val8 = 9; 4723 else 4724 val8 = 20; 4725 rtl8xxxu_write8(priv, REG_SLOT, val8); 4726 4727 rtl8xxxu_set_aifs(priv, val8); 4728 } 4729 4730 if (changed & BSS_CHANGED_BSSID) { 4731 dev_dbg(dev, "Changed BSSID!\n"); 4732 rtl8xxxu_set_bssid(priv, bss_conf->bssid); 4733 } 4734 4735 if (changed & BSS_CHANGED_BASIC_RATES) { 4736 dev_dbg(dev, "Changed BASIC_RATES!\n"); 4737 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates); 4738 } 4739 error: 4740 return; 4741 } 4742 4743 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue) 4744 { 4745 u32 rtlqueue; 4746 4747 switch (queue) { 4748 case IEEE80211_AC_VO: 4749 rtlqueue = TXDESC_QUEUE_VO; 4750 break; 4751 case IEEE80211_AC_VI: 4752 rtlqueue = TXDESC_QUEUE_VI; 4753 break; 4754 case IEEE80211_AC_BE: 4755 rtlqueue = TXDESC_QUEUE_BE; 4756 break; 4757 case IEEE80211_AC_BK: 4758 rtlqueue = TXDESC_QUEUE_BK; 4759 break; 4760 default: 4761 rtlqueue = TXDESC_QUEUE_BE; 4762 } 4763 4764 return rtlqueue; 4765 } 4766 4767 static u32 rtl8xxxu_queue_select(struct ieee80211_hdr *hdr, struct sk_buff *skb) 4768 { 4769 u32 queue; 4770 4771 if (ieee80211_is_mgmt(hdr->frame_control)) 4772 queue = TXDESC_QUEUE_MGNT; 4773 else 4774 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb)); 4775 4776 return queue; 4777 } 4778 4779 /* 4780 * Despite newer chips 8723b/8812/8821 having a larger TX descriptor 4781 * format. The descriptor checksum is still only calculated over the 4782 * initial 32 bytes of the descriptor! 4783 */ 4784 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc) 4785 { 4786 __le16 *ptr = (__le16 *)tx_desc; 4787 u16 csum = 0; 4788 int i; 4789 4790 /* 4791 * Clear csum field before calculation, as the csum field is 4792 * in the middle of the struct. 4793 */ 4794 tx_desc->csum = cpu_to_le16(0); 4795 4796 for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++) 4797 csum = csum ^ le16_to_cpu(ptr[i]); 4798 4799 tx_desc->csum |= cpu_to_le16(csum); 4800 } 4801 4802 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv) 4803 { 4804 struct rtl8xxxu_tx_urb *tx_urb, *tmp; 4805 unsigned long flags; 4806 4807 spin_lock_irqsave(&priv->tx_urb_lock, flags); 4808 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) { 4809 list_del(&tx_urb->list); 4810 priv->tx_urb_free_count--; 4811 usb_free_urb(&tx_urb->urb); 4812 } 4813 spin_unlock_irqrestore(&priv->tx_urb_lock, flags); 4814 } 4815 4816 static struct rtl8xxxu_tx_urb * 4817 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv) 4818 { 4819 struct rtl8xxxu_tx_urb *tx_urb; 4820 unsigned long flags; 4821 4822 spin_lock_irqsave(&priv->tx_urb_lock, flags); 4823 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list, 4824 struct rtl8xxxu_tx_urb, list); 4825 if (tx_urb) { 4826 list_del(&tx_urb->list); 4827 priv->tx_urb_free_count--; 4828 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER && 4829 !priv->tx_stopped) { 4830 priv->tx_stopped = true; 4831 ieee80211_stop_queues(priv->hw); 4832 } 4833 } 4834 4835 spin_unlock_irqrestore(&priv->tx_urb_lock, flags); 4836 4837 return tx_urb; 4838 } 4839 4840 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv, 4841 struct rtl8xxxu_tx_urb *tx_urb) 4842 { 4843 unsigned long flags; 4844 4845 INIT_LIST_HEAD(&tx_urb->list); 4846 4847 spin_lock_irqsave(&priv->tx_urb_lock, flags); 4848 4849 list_add(&tx_urb->list, &priv->tx_urb_free_list); 4850 priv->tx_urb_free_count++; 4851 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER && 4852 priv->tx_stopped) { 4853 priv->tx_stopped = false; 4854 ieee80211_wake_queues(priv->hw); 4855 } 4856 4857 spin_unlock_irqrestore(&priv->tx_urb_lock, flags); 4858 } 4859 4860 static void rtl8xxxu_tx_complete(struct urb *urb) 4861 { 4862 struct sk_buff *skb = (struct sk_buff *)urb->context; 4863 struct ieee80211_tx_info *tx_info; 4864 struct ieee80211_hw *hw; 4865 struct rtl8xxxu_priv *priv; 4866 struct rtl8xxxu_tx_urb *tx_urb = 4867 container_of(urb, struct rtl8xxxu_tx_urb, urb); 4868 4869 tx_info = IEEE80211_SKB_CB(skb); 4870 hw = tx_info->rate_driver_data[0]; 4871 priv = hw->priv; 4872 4873 skb_pull(skb, priv->fops->tx_desc_size); 4874 4875 ieee80211_tx_info_clear_status(tx_info); 4876 tx_info->status.rates[0].idx = -1; 4877 tx_info->status.rates[0].count = 0; 4878 4879 if (!urb->status) 4880 tx_info->flags |= IEEE80211_TX_STAT_ACK; 4881 4882 ieee80211_tx_status_irqsafe(hw, skb); 4883 4884 rtl8xxxu_free_tx_urb(priv, tx_urb); 4885 } 4886 4887 static void rtl8xxxu_dump_action(struct device *dev, 4888 struct ieee80211_hdr *hdr) 4889 { 4890 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr; 4891 u16 cap, timeout; 4892 4893 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION)) 4894 return; 4895 4896 switch (mgmt->u.action.u.addba_resp.action_code) { 4897 case WLAN_ACTION_ADDBA_RESP: 4898 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab); 4899 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout); 4900 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: " 4901 "timeout %i, tid %02x, buf_size %02x, policy %02x, " 4902 "status %02x\n", 4903 timeout, 4904 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2, 4905 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6, 4906 (cap >> 1) & 0x1, 4907 le16_to_cpu(mgmt->u.action.u.addba_resp.status)); 4908 break; 4909 case WLAN_ACTION_ADDBA_REQ: 4910 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab); 4911 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout); 4912 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: " 4913 "timeout %i, tid %02x, buf_size %02x, policy %02x\n", 4914 timeout, 4915 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2, 4916 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6, 4917 (cap >> 1) & 0x1); 4918 break; 4919 default: 4920 dev_info(dev, "action frame %02x\n", 4921 mgmt->u.action.u.addba_resp.action_code); 4922 break; 4923 } 4924 } 4925 4926 /* 4927 * Fill in v1 (gen1) specific TX descriptor bits. 4928 * This format is used on 8188cu/8192cu/8723au 4929 */ 4930 void 4931 rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 4932 struct ieee80211_tx_info *tx_info, 4933 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 4934 bool short_preamble, bool ampdu_enable, u32 rts_rate) 4935 { 4936 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info); 4937 struct rtl8xxxu_priv *priv = hw->priv; 4938 struct device *dev = &priv->udev->dev; 4939 u8 *qc = ieee80211_get_qos_ctl(hdr); 4940 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; 4941 u32 rate; 4942 u16 rate_flags = tx_info->control.rates[0].flags; 4943 u16 seq_number; 4944 4945 if (rate_flags & IEEE80211_TX_RC_MCS && 4946 !ieee80211_is_mgmt(hdr->frame_control)) 4947 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0; 4948 else 4949 rate = tx_rate->hw_value; 4950 4951 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) 4952 dev_info(dev, "%s: TX rate: %d, pkt size %u\n", 4953 __func__, rate, le16_to_cpu(tx_desc->pkt_size)); 4954 4955 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 4956 4957 tx_desc->txdw5 = cpu_to_le32(rate); 4958 4959 if (ieee80211_is_data(hdr->frame_control)) 4960 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00); 4961 4962 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT); 4963 4964 if (ampdu_enable && test_bit(tid, priv->tid_tx_operational)) 4965 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE); 4966 else 4967 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK); 4968 4969 if (ieee80211_is_mgmt(hdr->frame_control)) { 4970 tx_desc->txdw5 = cpu_to_le32(rate); 4971 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE); 4972 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT); 4973 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE); 4974 } 4975 4976 if (ieee80211_is_data_qos(hdr->frame_control)) 4977 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS); 4978 4979 if (short_preamble) 4980 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE); 4981 4982 if (sgi) 4983 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI); 4984 4985 /* 4986 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled 4987 */ 4988 tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT); 4989 if (ampdu_enable || (rate_flags & IEEE80211_TX_RC_USE_RTS_CTS)) { 4990 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE); 4991 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); 4992 } else if (rate_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 4993 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE); 4994 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); 4995 } 4996 } 4997 4998 /* 4999 * Fill in v2 (gen2) specific TX descriptor bits. 5000 * This format is used on 8192eu/8723bu 5001 */ 5002 void 5003 rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 5004 struct ieee80211_tx_info *tx_info, 5005 struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi, 5006 bool short_preamble, bool ampdu_enable, u32 rts_rate) 5007 { 5008 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info); 5009 struct rtl8xxxu_priv *priv = hw->priv; 5010 struct device *dev = &priv->udev->dev; 5011 struct rtl8xxxu_txdesc40 *tx_desc40; 5012 u8 *qc = ieee80211_get_qos_ctl(hdr); 5013 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; 5014 u32 rate; 5015 u16 rate_flags = tx_info->control.rates[0].flags; 5016 u16 seq_number; 5017 5018 tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc32; 5019 5020 if (rate_flags & IEEE80211_TX_RC_MCS && 5021 !ieee80211_is_mgmt(hdr->frame_control)) 5022 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0; 5023 else 5024 rate = tx_rate->hw_value; 5025 5026 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) 5027 dev_info(dev, "%s: TX rate: %d, pkt size %u\n", 5028 __func__, rate, le16_to_cpu(tx_desc40->pkt_size)); 5029 5030 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 5031 5032 tx_desc40->txdw4 = cpu_to_le32(rate); 5033 if (ieee80211_is_data(hdr->frame_control)) { 5034 tx_desc40->txdw4 |= cpu_to_le32(0x1f << 5035 TXDESC40_DATA_RATE_FB_SHIFT); 5036 } 5037 5038 tx_desc40->txdw9 = cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT); 5039 5040 if (ampdu_enable && test_bit(tid, priv->tid_tx_operational)) 5041 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE); 5042 else 5043 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK); 5044 5045 if (ieee80211_is_mgmt(hdr->frame_control)) { 5046 tx_desc40->txdw4 = cpu_to_le32(rate); 5047 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_USE_DRIVER_RATE); 5048 tx_desc40->txdw4 |= 5049 cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT); 5050 tx_desc40->txdw4 |= cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE); 5051 } 5052 5053 if (short_preamble) 5054 tx_desc40->txdw5 |= cpu_to_le32(TXDESC40_SHORT_PREAMBLE); 5055 5056 tx_desc40->txdw4 |= cpu_to_le32(rts_rate << TXDESC40_RTS_RATE_SHIFT); 5057 /* 5058 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled 5059 */ 5060 if (ampdu_enable || (rate_flags & IEEE80211_TX_RC_USE_RTS_CTS)) { 5061 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE); 5062 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE); 5063 } else if (rate_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 5064 /* 5065 * For some reason the vendor driver doesn't set 5066 * TXDESC40_HW_RTS_ENABLE for CTS to SELF 5067 */ 5068 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_CTS_SELF_ENABLE); 5069 } 5070 } 5071 5072 static void rtl8xxxu_tx(struct ieee80211_hw *hw, 5073 struct ieee80211_tx_control *control, 5074 struct sk_buff *skb) 5075 { 5076 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 5077 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 5078 struct rtl8xxxu_priv *priv = hw->priv; 5079 struct rtl8xxxu_txdesc32 *tx_desc; 5080 struct rtl8xxxu_tx_urb *tx_urb; 5081 struct ieee80211_sta *sta = NULL; 5082 struct ieee80211_vif *vif = tx_info->control.vif; 5083 struct device *dev = &priv->udev->dev; 5084 u32 queue, rts_rate; 5085 u16 pktlen = skb->len; 5086 u16 rate_flag = tx_info->control.rates[0].flags; 5087 int tx_desc_size = priv->fops->tx_desc_size; 5088 int ret; 5089 bool ampdu_enable, sgi = false, short_preamble = false; 5090 5091 if (skb_headroom(skb) < tx_desc_size) { 5092 dev_warn(dev, 5093 "%s: Not enough headroom (%i) for tx descriptor\n", 5094 __func__, skb_headroom(skb)); 5095 goto error; 5096 } 5097 5098 if (unlikely(skb->len > (65535 - tx_desc_size))) { 5099 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n", 5100 __func__, skb->len); 5101 goto error; 5102 } 5103 5104 tx_urb = rtl8xxxu_alloc_tx_urb(priv); 5105 if (!tx_urb) { 5106 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__); 5107 goto error; 5108 } 5109 5110 if (ieee80211_is_action(hdr->frame_control)) 5111 rtl8xxxu_dump_action(dev, hdr); 5112 5113 tx_info->rate_driver_data[0] = hw; 5114 5115 if (control && control->sta) 5116 sta = control->sta; 5117 5118 queue = rtl8xxxu_queue_select(hdr, skb); 5119 5120 tx_desc = skb_push(skb, tx_desc_size); 5121 5122 memset(tx_desc, 0, tx_desc_size); 5123 tx_desc->pkt_size = cpu_to_le16(pktlen); 5124 tx_desc->pkt_offset = tx_desc_size; 5125 5126 tx_desc->txdw0 = 5127 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT; 5128 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) || 5129 is_broadcast_ether_addr(ieee80211_get_DA(hdr))) 5130 tx_desc->txdw0 |= TXDESC_BROADMULTICAST; 5131 5132 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT); 5133 5134 if (tx_info->control.hw_key) { 5135 switch (tx_info->control.hw_key->cipher) { 5136 case WLAN_CIPHER_SUITE_WEP40: 5137 case WLAN_CIPHER_SUITE_WEP104: 5138 case WLAN_CIPHER_SUITE_TKIP: 5139 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4); 5140 break; 5141 case WLAN_CIPHER_SUITE_CCMP: 5142 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES); 5143 break; 5144 default: 5145 break; 5146 } 5147 } 5148 5149 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */ 5150 ampdu_enable = false; 5151 if (ieee80211_is_data_qos(hdr->frame_control) && sta) { 5152 if (sta->deflink.ht_cap.ht_supported) { 5153 u32 ampdu, val32; 5154 u8 *qc = ieee80211_get_qos_ctl(hdr); 5155 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; 5156 5157 ampdu = (u32)sta->deflink.ht_cap.ampdu_density; 5158 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT; 5159 tx_desc->txdw2 |= cpu_to_le32(val32); 5160 5161 ampdu_enable = true; 5162 5163 if (!test_bit(tid, priv->tx_aggr_started) && 5164 !(skb->protocol == cpu_to_be16(ETH_P_PAE))) 5165 if (!ieee80211_start_tx_ba_session(sta, tid, 0)) 5166 set_bit(tid, priv->tx_aggr_started); 5167 } 5168 } 5169 5170 if (rate_flag & IEEE80211_TX_RC_SHORT_GI || 5171 (ieee80211_is_data_qos(hdr->frame_control) && 5172 sta && sta->deflink.ht_cap.cap & 5173 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) 5174 sgi = true; 5175 5176 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE || 5177 (sta && vif && vif->bss_conf.use_short_preamble)) 5178 short_preamble = true; 5179 5180 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) 5181 rts_rate = ieee80211_get_rts_cts_rate(hw, tx_info)->hw_value; 5182 else if (rate_flag & IEEE80211_TX_RC_USE_CTS_PROTECT) 5183 rts_rate = ieee80211_get_rts_cts_rate(hw, tx_info)->hw_value; 5184 else 5185 rts_rate = 0; 5186 5187 5188 priv->fops->fill_txdesc(hw, hdr, tx_info, tx_desc, sgi, short_preamble, 5189 ampdu_enable, rts_rate); 5190 5191 rtl8xxxu_calc_tx_desc_csum(tx_desc); 5192 5193 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue], 5194 skb->data, skb->len, rtl8xxxu_tx_complete, skb); 5195 5196 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor); 5197 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC); 5198 if (ret) { 5199 usb_unanchor_urb(&tx_urb->urb); 5200 rtl8xxxu_free_tx_urb(priv, tx_urb); 5201 goto error; 5202 } 5203 return; 5204 error: 5205 dev_kfree_skb(skb); 5206 } 5207 5208 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv, 5209 struct ieee80211_rx_status *rx_status, 5210 struct rtl8723au_phy_stats *phy_stats, 5211 u32 rxmcs, struct ieee80211_hdr *hdr, 5212 bool crc_icv_err) 5213 { 5214 if (phy_stats->sgi_en) 5215 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 5216 5217 if (rxmcs < DESC_RATE_6M) { 5218 /* 5219 * Handle PHY stats for CCK rates 5220 */ 5221 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a; 5222 5223 rx_status->signal = priv->fops->cck_rssi(priv, cck_agc_rpt); 5224 } else { 5225 bool parse_cfo = priv->fops->set_crystal_cap && 5226 priv->vif && 5227 priv->vif->type == NL80211_IFTYPE_STATION && 5228 priv->vif->cfg.assoc && 5229 !crc_icv_err && 5230 !ieee80211_is_ctl(hdr->frame_control) && 5231 ether_addr_equal(priv->vif->bss_conf.bssid, hdr->addr2); 5232 5233 if (parse_cfo) { 5234 priv->cfo_tracking.cfo_tail[0] = phy_stats->path_cfotail[0]; 5235 priv->cfo_tracking.cfo_tail[1] = phy_stats->path_cfotail[1]; 5236 5237 priv->cfo_tracking.packet_count++; 5238 } 5239 5240 rx_status->signal = 5241 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110; 5242 } 5243 } 5244 5245 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv) 5246 { 5247 struct rtl8xxxu_rx_urb *rx_urb, *tmp; 5248 unsigned long flags; 5249 5250 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5251 5252 list_for_each_entry_safe(rx_urb, tmp, 5253 &priv->rx_urb_pending_list, list) { 5254 list_del(&rx_urb->list); 5255 priv->rx_urb_pending_count--; 5256 usb_free_urb(&rx_urb->urb); 5257 } 5258 5259 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5260 } 5261 5262 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv, 5263 struct rtl8xxxu_rx_urb *rx_urb) 5264 { 5265 struct sk_buff *skb; 5266 unsigned long flags; 5267 int pending = 0; 5268 5269 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5270 5271 if (!priv->shutdown) { 5272 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list); 5273 priv->rx_urb_pending_count++; 5274 pending = priv->rx_urb_pending_count; 5275 } else { 5276 skb = (struct sk_buff *)rx_urb->urb.context; 5277 dev_kfree_skb(skb); 5278 usb_free_urb(&rx_urb->urb); 5279 } 5280 5281 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5282 5283 if (pending > RTL8XXXU_RX_URB_PENDING_WATER) 5284 schedule_work(&priv->rx_urb_wq); 5285 } 5286 5287 static void rtl8xxxu_rx_urb_work(struct work_struct *work) 5288 { 5289 struct rtl8xxxu_priv *priv; 5290 struct rtl8xxxu_rx_urb *rx_urb, *tmp; 5291 struct list_head local; 5292 struct sk_buff *skb; 5293 unsigned long flags; 5294 int ret; 5295 5296 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq); 5297 INIT_LIST_HEAD(&local); 5298 5299 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5300 5301 list_splice_init(&priv->rx_urb_pending_list, &local); 5302 priv->rx_urb_pending_count = 0; 5303 5304 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5305 5306 list_for_each_entry_safe(rx_urb, tmp, &local, list) { 5307 list_del_init(&rx_urb->list); 5308 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb); 5309 /* 5310 * If out of memory or temporary error, put it back on the 5311 * queue and try again. Otherwise the device is dead/gone 5312 * and we should drop it. 5313 */ 5314 switch (ret) { 5315 case 0: 5316 break; 5317 case -ENOMEM: 5318 case -EAGAIN: 5319 rtl8xxxu_queue_rx_urb(priv, rx_urb); 5320 break; 5321 default: 5322 dev_warn(&priv->udev->dev, 5323 "failed to requeue urb with error %i\n", ret); 5324 skb = (struct sk_buff *)rx_urb->urb.context; 5325 dev_kfree_skb(skb); 5326 usb_free_urb(&rx_urb->urb); 5327 } 5328 } 5329 } 5330 5331 /* 5332 * The RTL8723BU/RTL8192EU vendor driver use coexistence table type 5333 * 0-7 to represent writing different combinations of register values 5334 * to REG_BT_COEX_TABLEs. It's for different kinds of coexistence use 5335 * cases which Realtek doesn't provide detail for these settings. Keep 5336 * this aligned with vendor driver for easier maintenance. 5337 */ 5338 static 5339 void rtl8723bu_set_coex_with_type(struct rtl8xxxu_priv *priv, u8 type) 5340 { 5341 switch (type) { 5342 case 0: 5343 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); 5344 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555); 5345 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5346 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5347 break; 5348 case 1: 5349 case 3: 5350 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); 5351 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a); 5352 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5353 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5354 break; 5355 case 2: 5356 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a); 5357 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a); 5358 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5359 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5360 break; 5361 case 4: 5362 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a); 5363 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaa5a5a); 5364 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5365 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5366 break; 5367 case 5: 5368 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a); 5369 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaa5a5a5a); 5370 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5371 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5372 break; 5373 case 6: 5374 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); 5375 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa); 5376 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5377 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5378 break; 5379 case 7: 5380 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0xaaaaaaaa); 5381 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa); 5382 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5383 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5384 break; 5385 default: 5386 break; 5387 } 5388 } 5389 5390 static 5391 void rtl8723bu_update_bt_link_info(struct rtl8xxxu_priv *priv, u8 bt_info) 5392 { 5393 struct rtl8xxxu_btcoex *btcoex = &priv->bt_coex; 5394 5395 if (bt_info & BT_INFO_8723B_1ANT_B_INQ_PAGE) 5396 btcoex->c2h_bt_inquiry = true; 5397 else 5398 btcoex->c2h_bt_inquiry = false; 5399 5400 if (!(bt_info & BT_INFO_8723B_1ANT_B_CONNECTION)) { 5401 btcoex->bt_status = BT_8723B_1ANT_STATUS_NON_CONNECTED_IDLE; 5402 btcoex->has_sco = false; 5403 btcoex->has_hid = false; 5404 btcoex->has_pan = false; 5405 btcoex->has_a2dp = false; 5406 } else { 5407 if ((bt_info & 0x1f) == BT_INFO_8723B_1ANT_B_CONNECTION) 5408 btcoex->bt_status = BT_8723B_1ANT_STATUS_CONNECTED_IDLE; 5409 else if ((bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) || 5410 (bt_info & BT_INFO_8723B_1ANT_B_SCO_BUSY)) 5411 btcoex->bt_status = BT_8723B_1ANT_STATUS_SCO_BUSY; 5412 else if (bt_info & BT_INFO_8723B_1ANT_B_ACL_BUSY) 5413 btcoex->bt_status = BT_8723B_1ANT_STATUS_ACL_BUSY; 5414 else 5415 btcoex->bt_status = BT_8723B_1ANT_STATUS_MAX; 5416 5417 if (bt_info & BT_INFO_8723B_1ANT_B_FTP) 5418 btcoex->has_pan = true; 5419 else 5420 btcoex->has_pan = false; 5421 5422 if (bt_info & BT_INFO_8723B_1ANT_B_A2DP) 5423 btcoex->has_a2dp = true; 5424 else 5425 btcoex->has_a2dp = false; 5426 5427 if (bt_info & BT_INFO_8723B_1ANT_B_HID) 5428 btcoex->has_hid = true; 5429 else 5430 btcoex->has_hid = false; 5431 5432 if (bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) 5433 btcoex->has_sco = true; 5434 else 5435 btcoex->has_sco = false; 5436 } 5437 5438 if (!btcoex->has_a2dp && !btcoex->has_sco && 5439 !btcoex->has_pan && btcoex->has_hid) 5440 btcoex->hid_only = true; 5441 else 5442 btcoex->hid_only = false; 5443 5444 if (!btcoex->has_sco && !btcoex->has_pan && 5445 !btcoex->has_hid && btcoex->has_a2dp) 5446 btcoex->has_a2dp = true; 5447 else 5448 btcoex->has_a2dp = false; 5449 5450 if (btcoex->bt_status == BT_8723B_1ANT_STATUS_SCO_BUSY || 5451 btcoex->bt_status == BT_8723B_1ANT_STATUS_ACL_BUSY) 5452 btcoex->bt_busy = true; 5453 else 5454 btcoex->bt_busy = false; 5455 } 5456 5457 static 5458 void rtl8723bu_handle_bt_inquiry(struct rtl8xxxu_priv *priv) 5459 { 5460 struct ieee80211_vif *vif; 5461 struct rtl8xxxu_btcoex *btcoex; 5462 bool wifi_connected; 5463 5464 vif = priv->vif; 5465 btcoex = &priv->bt_coex; 5466 wifi_connected = (vif && vif->cfg.assoc); 5467 5468 if (!wifi_connected) { 5469 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); 5470 rtl8723bu_set_coex_with_type(priv, 0); 5471 } else if (btcoex->has_sco || btcoex->has_hid || btcoex->has_a2dp) { 5472 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, 0x3, 0x11, 0x11); 5473 rtl8723bu_set_coex_with_type(priv, 4); 5474 } else if (btcoex->has_pan) { 5475 rtl8723bu_set_ps_tdma(priv, 0x61, 0x3f, 0x3, 0x11, 0x11); 5476 rtl8723bu_set_coex_with_type(priv, 4); 5477 } else { 5478 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); 5479 rtl8723bu_set_coex_with_type(priv, 7); 5480 } 5481 } 5482 5483 static 5484 void rtl8723bu_handle_bt_info(struct rtl8xxxu_priv *priv) 5485 { 5486 struct ieee80211_vif *vif; 5487 struct rtl8xxxu_btcoex *btcoex; 5488 bool wifi_connected; 5489 5490 vif = priv->vif; 5491 btcoex = &priv->bt_coex; 5492 wifi_connected = (vif && vif->cfg.assoc); 5493 5494 if (wifi_connected) { 5495 u32 val32 = 0; 5496 u32 high_prio_tx = 0, high_prio_rx = 0; 5497 5498 val32 = rtl8xxxu_read32(priv, 0x770); 5499 high_prio_tx = val32 & 0x0000ffff; 5500 high_prio_rx = (val32 & 0xffff0000) >> 16; 5501 5502 if (btcoex->bt_busy) { 5503 if (btcoex->hid_only) { 5504 rtl8723bu_set_ps_tdma(priv, 0x61, 0x20, 5505 0x3, 0x11, 0x11); 5506 rtl8723bu_set_coex_with_type(priv, 5); 5507 } else if (btcoex->a2dp_only) { 5508 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, 5509 0x3, 0x11, 0x11); 5510 rtl8723bu_set_coex_with_type(priv, 4); 5511 } else if ((btcoex->has_a2dp && btcoex->has_pan) || 5512 (btcoex->has_hid && btcoex->has_a2dp && 5513 btcoex->has_pan)) { 5514 rtl8723bu_set_ps_tdma(priv, 0x51, 0x21, 5515 0x3, 0x10, 0x10); 5516 rtl8723bu_set_coex_with_type(priv, 4); 5517 } else if (btcoex->has_hid && btcoex->has_a2dp) { 5518 rtl8723bu_set_ps_tdma(priv, 0x51, 0x21, 5519 0x3, 0x10, 0x10); 5520 rtl8723bu_set_coex_with_type(priv, 3); 5521 } else { 5522 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, 5523 0x3, 0x11, 0x11); 5524 rtl8723bu_set_coex_with_type(priv, 4); 5525 } 5526 } else { 5527 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); 5528 if (high_prio_tx + high_prio_rx <= 60) 5529 rtl8723bu_set_coex_with_type(priv, 2); 5530 else 5531 rtl8723bu_set_coex_with_type(priv, 7); 5532 } 5533 } else { 5534 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); 5535 rtl8723bu_set_coex_with_type(priv, 0); 5536 } 5537 } 5538 5539 static void rtl8xxxu_c2hcmd_callback(struct work_struct *work) 5540 { 5541 struct rtl8xxxu_priv *priv; 5542 struct rtl8723bu_c2h *c2h; 5543 struct sk_buff *skb = NULL; 5544 u8 bt_info = 0; 5545 struct rtl8xxxu_btcoex *btcoex; 5546 struct rtl8xxxu_ra_report *rarpt; 5547 u8 bw; 5548 5549 priv = container_of(work, struct rtl8xxxu_priv, c2hcmd_work); 5550 btcoex = &priv->bt_coex; 5551 rarpt = &priv->ra_report; 5552 5553 if (priv->rf_paths > 1) 5554 goto out; 5555 5556 while (!skb_queue_empty(&priv->c2hcmd_queue)) { 5557 skb = skb_dequeue(&priv->c2hcmd_queue); 5558 5559 c2h = (struct rtl8723bu_c2h *)skb->data; 5560 5561 switch (c2h->id) { 5562 case C2H_8723B_BT_INFO: 5563 bt_info = c2h->bt_info.bt_info; 5564 5565 rtl8723bu_update_bt_link_info(priv, bt_info); 5566 if (btcoex->c2h_bt_inquiry) { 5567 rtl8723bu_handle_bt_inquiry(priv); 5568 break; 5569 } 5570 rtl8723bu_handle_bt_info(priv); 5571 break; 5572 case C2H_8723B_RA_REPORT: 5573 bw = rarpt->txrate.bw; 5574 5575 if (skb->len >= offsetofend(typeof(*c2h), ra_report.bw)) { 5576 if (c2h->ra_report.bw == RTL8XXXU_CHANNEL_WIDTH_40) 5577 bw = RATE_INFO_BW_40; 5578 else 5579 bw = RATE_INFO_BW_20; 5580 } 5581 5582 rtl8xxxu_update_ra_report(rarpt, c2h->ra_report.rate, 5583 c2h->ra_report.sgi, bw); 5584 break; 5585 default: 5586 break; 5587 } 5588 } 5589 5590 out: 5591 dev_kfree_skb(skb); 5592 } 5593 5594 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv, 5595 struct sk_buff *skb) 5596 { 5597 struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data; 5598 struct device *dev = &priv->udev->dev; 5599 int len; 5600 5601 len = skb->len - 2; 5602 5603 dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n", 5604 c2h->id, c2h->seq, len, c2h->bt_info.response_source); 5605 5606 switch(c2h->id) { 5607 case C2H_8723B_BT_INFO: 5608 if (c2h->bt_info.response_source > 5609 BT_INFO_SRC_8723B_BT_ACTIVE_SEND) 5610 dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n"); 5611 else 5612 dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n"); 5613 5614 if (c2h->bt_info.bt_has_reset) 5615 dev_dbg(dev, "BT has been reset\n"); 5616 if (c2h->bt_info.tx_rx_mask) 5617 dev_dbg(dev, "BT TRx mask\n"); 5618 5619 break; 5620 case C2H_8723B_BT_MP_INFO: 5621 dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n", 5622 c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status); 5623 break; 5624 case C2H_8723B_RA_REPORT: 5625 dev_dbg(dev, 5626 "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n", 5627 c2h->ra_report.rate, c2h->ra_report.sgi, 5628 c2h->ra_report.macid, c2h->ra_report.noisy_state); 5629 break; 5630 default: 5631 dev_info(dev, "Unhandled C2H event %02x seq %02x\n", 5632 c2h->id, c2h->seq); 5633 print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE, 5634 16, 1, c2h->raw.payload, len, false); 5635 break; 5636 } 5637 5638 skb_queue_tail(&priv->c2hcmd_queue, skb); 5639 5640 schedule_work(&priv->c2hcmd_work); 5641 } 5642 5643 int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb) 5644 { 5645 struct ieee80211_hw *hw = priv->hw; 5646 struct ieee80211_rx_status *rx_status; 5647 struct rtl8xxxu_rxdesc16 *rx_desc; 5648 struct rtl8723au_phy_stats *phy_stats; 5649 struct sk_buff *next_skb = NULL; 5650 __le32 *_rx_desc_le; 5651 u32 *_rx_desc; 5652 int drvinfo_sz, desc_shift; 5653 int i, pkt_cnt, pkt_len, urb_len, pkt_offset; 5654 5655 urb_len = skb->len; 5656 pkt_cnt = 0; 5657 5658 if (urb_len < sizeof(struct rtl8xxxu_rxdesc16)) { 5659 kfree_skb(skb); 5660 return RX_TYPE_ERROR; 5661 } 5662 5663 do { 5664 rx_desc = (struct rtl8xxxu_rxdesc16 *)skb->data; 5665 _rx_desc_le = (__le32 *)skb->data; 5666 _rx_desc = (u32 *)skb->data; 5667 5668 for (i = 0; 5669 i < (sizeof(struct rtl8xxxu_rxdesc16) / sizeof(u32)); i++) 5670 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]); 5671 5672 /* 5673 * Only read pkt_cnt from the header if we're parsing the 5674 * first packet 5675 */ 5676 if (!pkt_cnt) 5677 pkt_cnt = rx_desc->pkt_cnt; 5678 pkt_len = rx_desc->pktlen; 5679 5680 drvinfo_sz = rx_desc->drvinfo_sz * 8; 5681 desc_shift = rx_desc->shift; 5682 pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift + 5683 sizeof(struct rtl8xxxu_rxdesc16), 128); 5684 5685 /* 5686 * Only clone the skb if there's enough data at the end to 5687 * at least cover the rx descriptor 5688 */ 5689 if (pkt_cnt > 1 && 5690 urb_len >= (pkt_offset + sizeof(struct rtl8xxxu_rxdesc16))) 5691 next_skb = skb_clone(skb, GFP_ATOMIC); 5692 5693 rx_status = IEEE80211_SKB_RXCB(skb); 5694 memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); 5695 5696 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc16)); 5697 5698 phy_stats = (struct rtl8723au_phy_stats *)skb->data; 5699 5700 skb_pull(skb, drvinfo_sz + desc_shift); 5701 5702 skb_trim(skb, pkt_len); 5703 5704 if (rx_desc->phy_stats) 5705 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats, 5706 rx_desc->rxmcs, (struct ieee80211_hdr *)skb->data, 5707 rx_desc->crc32 || rx_desc->icverr); 5708 5709 rx_status->mactime = rx_desc->tsfl; 5710 rx_status->flag |= RX_FLAG_MACTIME_START; 5711 5712 if (!rx_desc->swdec) 5713 rx_status->flag |= RX_FLAG_DECRYPTED; 5714 if (rx_desc->crc32) 5715 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 5716 if (rx_desc->bw) 5717 rx_status->bw = RATE_INFO_BW_40; 5718 5719 if (rx_desc->rxht) { 5720 rx_status->encoding = RX_ENC_HT; 5721 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0; 5722 } else { 5723 rx_status->rate_idx = rx_desc->rxmcs; 5724 } 5725 5726 rx_status->freq = hw->conf.chandef.chan->center_freq; 5727 rx_status->band = hw->conf.chandef.chan->band; 5728 5729 ieee80211_rx_irqsafe(hw, skb); 5730 5731 skb = next_skb; 5732 if (skb) 5733 skb_pull(next_skb, pkt_offset); 5734 5735 pkt_cnt--; 5736 urb_len -= pkt_offset; 5737 next_skb = NULL; 5738 } while (skb && pkt_cnt > 0 && 5739 urb_len >= sizeof(struct rtl8xxxu_rxdesc16)); 5740 5741 return RX_TYPE_DATA_PKT; 5742 } 5743 5744 int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb) 5745 { 5746 struct ieee80211_hw *hw = priv->hw; 5747 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 5748 struct rtl8xxxu_rxdesc24 *rx_desc = 5749 (struct rtl8xxxu_rxdesc24 *)skb->data; 5750 struct rtl8723au_phy_stats *phy_stats; 5751 __le32 *_rx_desc_le = (__le32 *)skb->data; 5752 u32 *_rx_desc = (u32 *)skb->data; 5753 int drvinfo_sz, desc_shift; 5754 int i; 5755 5756 for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++) 5757 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]); 5758 5759 memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); 5760 5761 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24)); 5762 5763 phy_stats = (struct rtl8723au_phy_stats *)skb->data; 5764 5765 drvinfo_sz = rx_desc->drvinfo_sz * 8; 5766 desc_shift = rx_desc->shift; 5767 skb_pull(skb, drvinfo_sz + desc_shift); 5768 5769 if (rx_desc->rpt_sel) { 5770 struct device *dev = &priv->udev->dev; 5771 dev_dbg(dev, "%s: C2H packet\n", __func__); 5772 rtl8723bu_handle_c2h(priv, skb); 5773 return RX_TYPE_C2H; 5774 } 5775 5776 if (rx_desc->phy_stats) 5777 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats, 5778 rx_desc->rxmcs, (struct ieee80211_hdr *)skb->data, 5779 rx_desc->crc32 || rx_desc->icverr); 5780 5781 rx_status->mactime = rx_desc->tsfl; 5782 rx_status->flag |= RX_FLAG_MACTIME_START; 5783 5784 if (!rx_desc->swdec) 5785 rx_status->flag |= RX_FLAG_DECRYPTED; 5786 if (rx_desc->crc32) 5787 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 5788 if (rx_desc->bw) 5789 rx_status->bw = RATE_INFO_BW_40; 5790 5791 if (rx_desc->rxmcs >= DESC_RATE_MCS0) { 5792 rx_status->encoding = RX_ENC_HT; 5793 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0; 5794 } else { 5795 rx_status->rate_idx = rx_desc->rxmcs; 5796 } 5797 5798 rx_status->freq = hw->conf.chandef.chan->center_freq; 5799 rx_status->band = hw->conf.chandef.chan->band; 5800 5801 ieee80211_rx_irqsafe(hw, skb); 5802 return RX_TYPE_DATA_PKT; 5803 } 5804 5805 static void rtl8xxxu_rx_complete(struct urb *urb) 5806 { 5807 struct rtl8xxxu_rx_urb *rx_urb = 5808 container_of(urb, struct rtl8xxxu_rx_urb, urb); 5809 struct ieee80211_hw *hw = rx_urb->hw; 5810 struct rtl8xxxu_priv *priv = hw->priv; 5811 struct sk_buff *skb = (struct sk_buff *)urb->context; 5812 struct device *dev = &priv->udev->dev; 5813 5814 skb_put(skb, urb->actual_length); 5815 5816 if (urb->status == 0) { 5817 priv->fops->parse_rx_desc(priv, skb); 5818 5819 skb = NULL; 5820 rx_urb->urb.context = NULL; 5821 rtl8xxxu_queue_rx_urb(priv, rx_urb); 5822 } else { 5823 dev_dbg(dev, "%s: status %i\n", __func__, urb->status); 5824 goto cleanup; 5825 } 5826 return; 5827 5828 cleanup: 5829 usb_free_urb(urb); 5830 dev_kfree_skb(skb); 5831 return; 5832 } 5833 5834 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv, 5835 struct rtl8xxxu_rx_urb *rx_urb) 5836 { 5837 struct rtl8xxxu_fileops *fops = priv->fops; 5838 struct sk_buff *skb; 5839 int skb_size; 5840 int ret, rx_desc_sz; 5841 5842 rx_desc_sz = fops->rx_desc_size; 5843 5844 if (priv->rx_buf_aggregation && fops->rx_agg_buf_size) { 5845 skb_size = fops->rx_agg_buf_size; 5846 skb_size += (rx_desc_sz + sizeof(struct rtl8723au_phy_stats)); 5847 } else { 5848 skb_size = IEEE80211_MAX_FRAME_LEN; 5849 } 5850 5851 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL); 5852 if (!skb) 5853 return -ENOMEM; 5854 5855 memset(skb->data, 0, rx_desc_sz); 5856 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data, 5857 skb_size, rtl8xxxu_rx_complete, skb); 5858 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor); 5859 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC); 5860 if (ret) 5861 usb_unanchor_urb(&rx_urb->urb); 5862 return ret; 5863 } 5864 5865 static void rtl8xxxu_int_complete(struct urb *urb) 5866 { 5867 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context; 5868 struct device *dev = &priv->udev->dev; 5869 int ret; 5870 5871 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_INTERRUPT) 5872 dev_dbg(dev, "%s: status %i\n", __func__, urb->status); 5873 if (urb->status == 0) { 5874 usb_anchor_urb(urb, &priv->int_anchor); 5875 ret = usb_submit_urb(urb, GFP_ATOMIC); 5876 if (ret) 5877 usb_unanchor_urb(urb); 5878 } else { 5879 dev_dbg(dev, "%s: Error %i\n", __func__, urb->status); 5880 } 5881 } 5882 5883 5884 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw) 5885 { 5886 struct rtl8xxxu_priv *priv = hw->priv; 5887 struct urb *urb; 5888 u32 val32; 5889 int ret; 5890 5891 urb = usb_alloc_urb(0, GFP_KERNEL); 5892 if (!urb) 5893 return -ENOMEM; 5894 5895 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt, 5896 priv->int_buf, USB_INTR_CONTENT_LENGTH, 5897 rtl8xxxu_int_complete, priv, 1); 5898 usb_anchor_urb(urb, &priv->int_anchor); 5899 ret = usb_submit_urb(urb, GFP_KERNEL); 5900 if (ret) { 5901 usb_unanchor_urb(urb); 5902 goto error; 5903 } 5904 5905 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR); 5906 val32 |= USB_HIMR_CPWM; 5907 rtl8xxxu_write32(priv, REG_USB_HIMR, val32); 5908 5909 error: 5910 usb_free_urb(urb); 5911 return ret; 5912 } 5913 5914 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw, 5915 struct ieee80211_vif *vif) 5916 { 5917 struct rtl8xxxu_priv *priv = hw->priv; 5918 int ret; 5919 u8 val8; 5920 5921 switch (vif->type) { 5922 case NL80211_IFTYPE_STATION: 5923 if (!priv->vif) 5924 priv->vif = vif; 5925 else 5926 return -EOPNOTSUPP; 5927 rtl8xxxu_stop_tx_beacon(priv); 5928 5929 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 5930 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE | 5931 BEACON_DISABLE_TSF_UPDATE; 5932 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 5933 ret = 0; 5934 break; 5935 default: 5936 ret = -EOPNOTSUPP; 5937 } 5938 5939 rtl8xxxu_set_linktype(priv, vif->type); 5940 5941 return ret; 5942 } 5943 5944 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw, 5945 struct ieee80211_vif *vif) 5946 { 5947 struct rtl8xxxu_priv *priv = hw->priv; 5948 5949 dev_dbg(&priv->udev->dev, "%s\n", __func__); 5950 5951 if (priv->vif) 5952 priv->vif = NULL; 5953 } 5954 5955 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed) 5956 { 5957 struct rtl8xxxu_priv *priv = hw->priv; 5958 struct device *dev = &priv->udev->dev; 5959 u16 val16; 5960 int ret = 0, channel; 5961 bool ht40; 5962 5963 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL) 5964 dev_info(dev, 5965 "%s: channel: %i (changed %08x chandef.width %02x)\n", 5966 __func__, hw->conf.chandef.chan->hw_value, 5967 changed, hw->conf.chandef.width); 5968 5969 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) { 5970 val16 = ((hw->conf.long_frame_max_tx_count << 5971 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) | 5972 ((hw->conf.short_frame_max_tx_count << 5973 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK); 5974 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16); 5975 } 5976 5977 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { 5978 switch (hw->conf.chandef.width) { 5979 case NL80211_CHAN_WIDTH_20_NOHT: 5980 case NL80211_CHAN_WIDTH_20: 5981 ht40 = false; 5982 break; 5983 case NL80211_CHAN_WIDTH_40: 5984 ht40 = true; 5985 break; 5986 default: 5987 ret = -ENOTSUPP; 5988 goto exit; 5989 } 5990 5991 channel = hw->conf.chandef.chan->hw_value; 5992 5993 priv->fops->set_tx_power(priv, channel, ht40); 5994 5995 priv->fops->config_channel(hw); 5996 } 5997 5998 exit: 5999 return ret; 6000 } 6001 6002 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw, 6003 struct ieee80211_vif *vif, 6004 unsigned int link_id, u16 queue, 6005 const struct ieee80211_tx_queue_params *param) 6006 { 6007 struct rtl8xxxu_priv *priv = hw->priv; 6008 struct device *dev = &priv->udev->dev; 6009 u32 val32; 6010 u8 aifs, acm_ctrl, acm_bit; 6011 6012 aifs = param->aifs; 6013 6014 val32 = aifs | 6015 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT | 6016 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT | 6017 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT; 6018 6019 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL); 6020 dev_dbg(dev, 6021 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n", 6022 __func__, queue, val32, param->acm, acm_ctrl); 6023 6024 switch (queue) { 6025 case IEEE80211_AC_VO: 6026 acm_bit = ACM_HW_CTRL_VO; 6027 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32); 6028 break; 6029 case IEEE80211_AC_VI: 6030 acm_bit = ACM_HW_CTRL_VI; 6031 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32); 6032 break; 6033 case IEEE80211_AC_BE: 6034 acm_bit = ACM_HW_CTRL_BE; 6035 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32); 6036 break; 6037 case IEEE80211_AC_BK: 6038 acm_bit = ACM_HW_CTRL_BK; 6039 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32); 6040 break; 6041 default: 6042 acm_bit = 0; 6043 break; 6044 } 6045 6046 if (param->acm) 6047 acm_ctrl |= acm_bit; 6048 else 6049 acm_ctrl &= ~acm_bit; 6050 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl); 6051 6052 return 0; 6053 } 6054 6055 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw, 6056 unsigned int changed_flags, 6057 unsigned int *total_flags, u64 multicast) 6058 { 6059 struct rtl8xxxu_priv *priv = hw->priv; 6060 u32 rcr = rtl8xxxu_read32(priv, REG_RCR); 6061 6062 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n", 6063 __func__, changed_flags, *total_flags); 6064 6065 /* 6066 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR) 6067 */ 6068 6069 if (*total_flags & FIF_FCSFAIL) 6070 rcr |= RCR_ACCEPT_CRC32; 6071 else 6072 rcr &= ~RCR_ACCEPT_CRC32; 6073 6074 /* 6075 * FIF_PLCPFAIL not supported? 6076 */ 6077 6078 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) 6079 rcr &= ~RCR_CHECK_BSSID_BEACON; 6080 else 6081 rcr |= RCR_CHECK_BSSID_BEACON; 6082 6083 if (*total_flags & FIF_CONTROL) 6084 rcr |= RCR_ACCEPT_CTRL_FRAME; 6085 else 6086 rcr &= ~RCR_ACCEPT_CTRL_FRAME; 6087 6088 if (*total_flags & FIF_OTHER_BSS) { 6089 rcr |= RCR_ACCEPT_AP; 6090 rcr &= ~RCR_CHECK_BSSID_MATCH; 6091 } else { 6092 rcr &= ~RCR_ACCEPT_AP; 6093 rcr |= RCR_CHECK_BSSID_MATCH; 6094 } 6095 6096 if (*total_flags & FIF_PSPOLL) 6097 rcr |= RCR_ACCEPT_PM; 6098 else 6099 rcr &= ~RCR_ACCEPT_PM; 6100 6101 /* 6102 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted 6103 */ 6104 6105 rtl8xxxu_write32(priv, REG_RCR, rcr); 6106 6107 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC | 6108 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL | 6109 FIF_PROBE_REQ); 6110 } 6111 6112 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts) 6113 { 6114 if (rts > 2347) 6115 return -EINVAL; 6116 6117 return 0; 6118 } 6119 6120 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 6121 struct ieee80211_vif *vif, 6122 struct ieee80211_sta *sta, 6123 struct ieee80211_key_conf *key) 6124 { 6125 struct rtl8xxxu_priv *priv = hw->priv; 6126 struct device *dev = &priv->udev->dev; 6127 u8 mac_addr[ETH_ALEN]; 6128 u8 val8; 6129 u16 val16; 6130 u32 val32; 6131 int retval = -EOPNOTSUPP; 6132 6133 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n", 6134 __func__, cmd, key->cipher, key->keyidx); 6135 6136 if (vif->type != NL80211_IFTYPE_STATION) 6137 return -EOPNOTSUPP; 6138 6139 if (key->keyidx > 3) 6140 return -EOPNOTSUPP; 6141 6142 switch (key->cipher) { 6143 case WLAN_CIPHER_SUITE_WEP40: 6144 case WLAN_CIPHER_SUITE_WEP104: 6145 6146 break; 6147 case WLAN_CIPHER_SUITE_CCMP: 6148 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; 6149 break; 6150 case WLAN_CIPHER_SUITE_TKIP: 6151 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 6152 break; 6153 default: 6154 return -EOPNOTSUPP; 6155 } 6156 6157 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { 6158 dev_dbg(dev, "%s: pairwise key\n", __func__); 6159 ether_addr_copy(mac_addr, sta->addr); 6160 } else { 6161 dev_dbg(dev, "%s: group key\n", __func__); 6162 eth_broadcast_addr(mac_addr); 6163 } 6164 6165 val16 = rtl8xxxu_read16(priv, REG_CR); 6166 val16 |= CR_SECURITY_ENABLE; 6167 rtl8xxxu_write16(priv, REG_CR, val16); 6168 6169 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY | 6170 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY; 6171 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY; 6172 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8); 6173 6174 switch (cmd) { 6175 case SET_KEY: 6176 key->hw_key_idx = key->keyidx; 6177 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 6178 rtl8xxxu_cam_write(priv, key, mac_addr); 6179 retval = 0; 6180 break; 6181 case DISABLE_KEY: 6182 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000); 6183 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE | 6184 key->keyidx << CAM_CMD_KEY_SHIFT; 6185 rtl8xxxu_write32(priv, REG_CAM_CMD, val32); 6186 retval = 0; 6187 break; 6188 default: 6189 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd); 6190 } 6191 6192 return retval; 6193 } 6194 6195 static int 6196 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 6197 struct ieee80211_ampdu_params *params) 6198 { 6199 struct rtl8xxxu_priv *priv = hw->priv; 6200 struct device *dev = &priv->udev->dev; 6201 u8 ampdu_factor, ampdu_density; 6202 struct ieee80211_sta *sta = params->sta; 6203 u16 tid = params->tid; 6204 enum ieee80211_ampdu_mlme_action action = params->action; 6205 6206 switch (action) { 6207 case IEEE80211_AMPDU_TX_START: 6208 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__); 6209 ampdu_factor = sta->deflink.ht_cap.ampdu_factor; 6210 ampdu_density = sta->deflink.ht_cap.ampdu_density; 6211 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor); 6212 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density); 6213 dev_dbg(dev, 6214 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n", 6215 ampdu_factor, ampdu_density); 6216 return IEEE80211_AMPDU_TX_START_IMMEDIATE; 6217 case IEEE80211_AMPDU_TX_STOP_CONT: 6218 case IEEE80211_AMPDU_TX_STOP_FLUSH: 6219 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 6220 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP\n", __func__); 6221 rtl8xxxu_set_ampdu_factor(priv, 0); 6222 rtl8xxxu_set_ampdu_min_space(priv, 0); 6223 clear_bit(tid, priv->tx_aggr_started); 6224 clear_bit(tid, priv->tid_tx_operational); 6225 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 6226 break; 6227 case IEEE80211_AMPDU_TX_OPERATIONAL: 6228 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_OPERATIONAL\n", __func__); 6229 set_bit(tid, priv->tid_tx_operational); 6230 break; 6231 case IEEE80211_AMPDU_RX_START: 6232 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__); 6233 break; 6234 case IEEE80211_AMPDU_RX_STOP: 6235 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__); 6236 break; 6237 default: 6238 break; 6239 } 6240 return 0; 6241 } 6242 6243 static void 6244 rtl8xxxu_sta_statistics(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 6245 struct ieee80211_sta *sta, struct station_info *sinfo) 6246 { 6247 struct rtl8xxxu_priv *priv = hw->priv; 6248 6249 sinfo->txrate = priv->ra_report.txrate; 6250 sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE); 6251 } 6252 6253 static u8 rtl8xxxu_signal_to_snr(int signal) 6254 { 6255 if (signal < RTL8XXXU_NOISE_FLOOR_MIN) 6256 signal = RTL8XXXU_NOISE_FLOOR_MIN; 6257 else if (signal > 0) 6258 signal = 0; 6259 return (u8)(signal - RTL8XXXU_NOISE_FLOOR_MIN); 6260 } 6261 6262 static void rtl8xxxu_refresh_rate_mask(struct rtl8xxxu_priv *priv, 6263 int signal, struct ieee80211_sta *sta) 6264 { 6265 struct ieee80211_hw *hw = priv->hw; 6266 u16 wireless_mode; 6267 u8 rssi_level, ratr_idx; 6268 u8 txbw_40mhz; 6269 u8 snr, snr_thresh_high, snr_thresh_low; 6270 u8 go_up_gap = 5; 6271 6272 rssi_level = priv->rssi_level; 6273 snr = rtl8xxxu_signal_to_snr(signal); 6274 snr_thresh_high = RTL8XXXU_SNR_THRESH_HIGH; 6275 snr_thresh_low = RTL8XXXU_SNR_THRESH_LOW; 6276 txbw_40mhz = (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) ? 1 : 0; 6277 6278 switch (rssi_level) { 6279 case RTL8XXXU_RATR_STA_MID: 6280 snr_thresh_high += go_up_gap; 6281 break; 6282 case RTL8XXXU_RATR_STA_LOW: 6283 snr_thresh_high += go_up_gap; 6284 snr_thresh_low += go_up_gap; 6285 break; 6286 default: 6287 break; 6288 } 6289 6290 if (snr > snr_thresh_high) 6291 rssi_level = RTL8XXXU_RATR_STA_HIGH; 6292 else if (snr > snr_thresh_low) 6293 rssi_level = RTL8XXXU_RATR_STA_MID; 6294 else 6295 rssi_level = RTL8XXXU_RATR_STA_LOW; 6296 6297 if (rssi_level != priv->rssi_level) { 6298 int sgi = 0; 6299 u32 rate_bitmap = 0; 6300 6301 rcu_read_lock(); 6302 rate_bitmap = (sta->deflink.supp_rates[0] & 0xfff) | 6303 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12) | 6304 (sta->deflink.ht_cap.mcs.rx_mask[1] << 20); 6305 if (sta->deflink.ht_cap.cap & 6306 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)) 6307 sgi = 1; 6308 rcu_read_unlock(); 6309 6310 wireless_mode = rtl8xxxu_wireless_mode(hw, sta); 6311 switch (wireless_mode) { 6312 case WIRELESS_MODE_B: 6313 ratr_idx = RATEID_IDX_B; 6314 if (rate_bitmap & 0x0000000c) 6315 rate_bitmap &= 0x0000000d; 6316 else 6317 rate_bitmap &= 0x0000000f; 6318 break; 6319 case WIRELESS_MODE_A: 6320 case WIRELESS_MODE_G: 6321 ratr_idx = RATEID_IDX_G; 6322 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) 6323 rate_bitmap &= 0x00000f00; 6324 else 6325 rate_bitmap &= 0x00000ff0; 6326 break; 6327 case (WIRELESS_MODE_B | WIRELESS_MODE_G): 6328 ratr_idx = RATEID_IDX_BG; 6329 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) 6330 rate_bitmap &= 0x00000f00; 6331 else if (rssi_level == RTL8XXXU_RATR_STA_MID) 6332 rate_bitmap &= 0x00000ff0; 6333 else 6334 rate_bitmap &= 0x00000ff5; 6335 break; 6336 case WIRELESS_MODE_N_24G: 6337 case WIRELESS_MODE_N_5G: 6338 case (WIRELESS_MODE_G | WIRELESS_MODE_N_24G): 6339 case (WIRELESS_MODE_A | WIRELESS_MODE_N_5G): 6340 if (priv->tx_paths == 2 && priv->rx_paths == 2) 6341 ratr_idx = RATEID_IDX_GN_N2SS; 6342 else 6343 ratr_idx = RATEID_IDX_GN_N1SS; 6344 break; 6345 case (WIRELESS_MODE_B | WIRELESS_MODE_G | WIRELESS_MODE_N_24G): 6346 case (WIRELESS_MODE_B | WIRELESS_MODE_N_24G): 6347 if (txbw_40mhz) { 6348 if (priv->tx_paths == 2 && priv->rx_paths == 2) 6349 ratr_idx = RATEID_IDX_BGN_40M_2SS; 6350 else 6351 ratr_idx = RATEID_IDX_BGN_40M_1SS; 6352 } else { 6353 if (priv->tx_paths == 2 && priv->rx_paths == 2) 6354 ratr_idx = RATEID_IDX_BGN_20M_2SS_BN; 6355 else 6356 ratr_idx = RATEID_IDX_BGN_20M_1SS_BN; 6357 } 6358 6359 if (priv->tx_paths == 2 && priv->rx_paths == 2) { 6360 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) { 6361 rate_bitmap &= 0x0f8f0000; 6362 } else if (rssi_level == RTL8XXXU_RATR_STA_MID) { 6363 rate_bitmap &= 0x0f8ff000; 6364 } else { 6365 if (txbw_40mhz) 6366 rate_bitmap &= 0x0f8ff015; 6367 else 6368 rate_bitmap &= 0x0f8ff005; 6369 } 6370 } else { 6371 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) { 6372 rate_bitmap &= 0x000f0000; 6373 } else if (rssi_level == RTL8XXXU_RATR_STA_MID) { 6374 rate_bitmap &= 0x000ff000; 6375 } else { 6376 if (txbw_40mhz) 6377 rate_bitmap &= 0x000ff015; 6378 else 6379 rate_bitmap &= 0x000ff005; 6380 } 6381 } 6382 break; 6383 default: 6384 ratr_idx = RATEID_IDX_BGN_40M_2SS; 6385 rate_bitmap &= 0x0fffffff; 6386 break; 6387 } 6388 6389 priv->rssi_level = rssi_level; 6390 priv->fops->update_rate_mask(priv, rate_bitmap, ratr_idx, sgi, txbw_40mhz); 6391 } 6392 } 6393 6394 static void rtl8xxxu_set_atc_status(struct rtl8xxxu_priv *priv, bool atc_status) 6395 { 6396 struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; 6397 u32 val32; 6398 6399 if (atc_status == cfo->atc_status) 6400 return; 6401 6402 cfo->atc_status = atc_status; 6403 6404 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); 6405 if (atc_status) 6406 val32 |= CFO_TRACKING_ATC_STATUS; 6407 else 6408 val32 &= ~CFO_TRACKING_ATC_STATUS; 6409 rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); 6410 } 6411 6412 /* Central frequency offset correction */ 6413 static void rtl8xxxu_track_cfo(struct rtl8xxxu_priv *priv) 6414 { 6415 struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; 6416 int cfo_khz_a, cfo_khz_b, cfo_average; 6417 int crystal_cap; 6418 6419 if (!priv->vif || !priv->vif->cfg.assoc) { 6420 /* Reset */ 6421 cfo->adjust = true; 6422 6423 if (cfo->crystal_cap > priv->default_crystal_cap) 6424 priv->fops->set_crystal_cap(priv, cfo->crystal_cap - 1); 6425 else if (cfo->crystal_cap < priv->default_crystal_cap) 6426 priv->fops->set_crystal_cap(priv, cfo->crystal_cap + 1); 6427 6428 rtl8xxxu_set_atc_status(priv, true); 6429 6430 return; 6431 } 6432 6433 if (cfo->packet_count == cfo->packet_count_pre) 6434 /* No new information. */ 6435 return; 6436 6437 cfo->packet_count_pre = cfo->packet_count; 6438 6439 /* CFO_tail[1:0] is S(8,7), (num_subcarrier>>7) x 312.5K = CFO value(K Hz) */ 6440 cfo_khz_a = (int)((cfo->cfo_tail[0] * 3125) / 10) >> 7; 6441 cfo_khz_b = (int)((cfo->cfo_tail[1] * 3125) / 10) >> 7; 6442 6443 if (priv->tx_paths == 1) 6444 cfo_average = cfo_khz_a; 6445 else 6446 cfo_average = (cfo_khz_a + cfo_khz_b) / 2; 6447 6448 dev_dbg(&priv->udev->dev, "cfo_average: %d\n", cfo_average); 6449 6450 if (cfo->adjust) { 6451 if (abs(cfo_average) < CFO_TH_XTAL_LOW) 6452 cfo->adjust = false; 6453 } else { 6454 if (abs(cfo_average) > CFO_TH_XTAL_HIGH) 6455 cfo->adjust = true; 6456 } 6457 6458 /* 6459 * TODO: We should return here only if bluetooth is enabled. 6460 * See the vendor drivers for how to determine that. 6461 */ 6462 if (priv->has_bluetooth) 6463 return; 6464 6465 if (!cfo->adjust) 6466 return; 6467 6468 crystal_cap = cfo->crystal_cap; 6469 6470 if (cfo_average > CFO_TH_XTAL_LOW) 6471 crystal_cap++; 6472 else if (cfo_average < -CFO_TH_XTAL_LOW) 6473 crystal_cap--; 6474 6475 crystal_cap = clamp(crystal_cap, 0, 0x3f); 6476 6477 priv->fops->set_crystal_cap(priv, crystal_cap); 6478 6479 rtl8xxxu_set_atc_status(priv, abs(cfo_average) >= CFO_TH_ATC); 6480 } 6481 6482 static void rtl8xxxu_watchdog_callback(struct work_struct *work) 6483 { 6484 struct ieee80211_vif *vif; 6485 struct rtl8xxxu_priv *priv; 6486 6487 priv = container_of(work, struct rtl8xxxu_priv, ra_watchdog.work); 6488 vif = priv->vif; 6489 6490 if (vif && vif->type == NL80211_IFTYPE_STATION) { 6491 int signal; 6492 struct ieee80211_sta *sta; 6493 6494 rcu_read_lock(); 6495 sta = ieee80211_find_sta(vif, vif->bss_conf.bssid); 6496 if (!sta) { 6497 struct device *dev = &priv->udev->dev; 6498 6499 dev_dbg(dev, "%s: no sta found\n", __func__); 6500 rcu_read_unlock(); 6501 goto out; 6502 } 6503 rcu_read_unlock(); 6504 6505 signal = ieee80211_ave_rssi(vif); 6506 6507 if (priv->fops->set_crystal_cap) 6508 rtl8xxxu_track_cfo(priv); 6509 6510 rtl8xxxu_refresh_rate_mask(priv, signal, sta); 6511 } 6512 6513 out: 6514 schedule_delayed_work(&priv->ra_watchdog, 2 * HZ); 6515 } 6516 6517 static int rtl8xxxu_start(struct ieee80211_hw *hw) 6518 { 6519 struct rtl8xxxu_priv *priv = hw->priv; 6520 struct rtl8xxxu_rx_urb *rx_urb; 6521 struct rtl8xxxu_tx_urb *tx_urb; 6522 struct sk_buff *skb; 6523 unsigned long flags; 6524 int ret, i; 6525 6526 ret = 0; 6527 6528 init_usb_anchor(&priv->rx_anchor); 6529 init_usb_anchor(&priv->tx_anchor); 6530 init_usb_anchor(&priv->int_anchor); 6531 6532 priv->fops->enable_rf(priv); 6533 if (priv->usb_interrupts) { 6534 ret = rtl8xxxu_submit_int_urb(hw); 6535 if (ret) 6536 goto exit; 6537 } 6538 6539 for (i = 0; i < RTL8XXXU_TX_URBS; i++) { 6540 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL); 6541 if (!tx_urb) { 6542 if (!i) 6543 ret = -ENOMEM; 6544 6545 goto error_out; 6546 } 6547 usb_init_urb(&tx_urb->urb); 6548 INIT_LIST_HEAD(&tx_urb->list); 6549 tx_urb->hw = hw; 6550 list_add(&tx_urb->list, &priv->tx_urb_free_list); 6551 priv->tx_urb_free_count++; 6552 } 6553 6554 priv->tx_stopped = false; 6555 6556 spin_lock_irqsave(&priv->rx_urb_lock, flags); 6557 priv->shutdown = false; 6558 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 6559 6560 for (i = 0; i < RTL8XXXU_RX_URBS; i++) { 6561 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL); 6562 if (!rx_urb) { 6563 if (!i) 6564 ret = -ENOMEM; 6565 6566 goto error_out; 6567 } 6568 usb_init_urb(&rx_urb->urb); 6569 INIT_LIST_HEAD(&rx_urb->list); 6570 rx_urb->hw = hw; 6571 6572 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb); 6573 if (ret) { 6574 if (ret != -ENOMEM) { 6575 skb = (struct sk_buff *)rx_urb->urb.context; 6576 dev_kfree_skb(skb); 6577 } 6578 rtl8xxxu_queue_rx_urb(priv, rx_urb); 6579 } 6580 } 6581 6582 schedule_delayed_work(&priv->ra_watchdog, 2 * HZ); 6583 exit: 6584 /* 6585 * Accept all data and mgmt frames 6586 */ 6587 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff); 6588 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff); 6589 6590 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e); 6591 6592 return ret; 6593 6594 error_out: 6595 rtl8xxxu_free_tx_resources(priv); 6596 /* 6597 * Disable all data and mgmt frames 6598 */ 6599 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); 6600 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000); 6601 6602 return ret; 6603 } 6604 6605 static void rtl8xxxu_stop(struct ieee80211_hw *hw) 6606 { 6607 struct rtl8xxxu_priv *priv = hw->priv; 6608 unsigned long flags; 6609 6610 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 6611 6612 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000); 6613 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); 6614 6615 spin_lock_irqsave(&priv->rx_urb_lock, flags); 6616 priv->shutdown = true; 6617 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 6618 6619 usb_kill_anchored_urbs(&priv->rx_anchor); 6620 usb_kill_anchored_urbs(&priv->tx_anchor); 6621 if (priv->usb_interrupts) 6622 usb_kill_anchored_urbs(&priv->int_anchor); 6623 6624 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 6625 6626 priv->fops->disable_rf(priv); 6627 6628 /* 6629 * Disable interrupts 6630 */ 6631 if (priv->usb_interrupts) 6632 rtl8xxxu_write32(priv, REG_USB_HIMR, 0); 6633 6634 cancel_delayed_work_sync(&priv->ra_watchdog); 6635 6636 rtl8xxxu_free_rx_resources(priv); 6637 rtl8xxxu_free_tx_resources(priv); 6638 } 6639 6640 static const struct ieee80211_ops rtl8xxxu_ops = { 6641 .tx = rtl8xxxu_tx, 6642 .wake_tx_queue = ieee80211_handle_wake_tx_queue, 6643 .add_interface = rtl8xxxu_add_interface, 6644 .remove_interface = rtl8xxxu_remove_interface, 6645 .config = rtl8xxxu_config, 6646 .conf_tx = rtl8xxxu_conf_tx, 6647 .bss_info_changed = rtl8xxxu_bss_info_changed, 6648 .configure_filter = rtl8xxxu_configure_filter, 6649 .set_rts_threshold = rtl8xxxu_set_rts_threshold, 6650 .start = rtl8xxxu_start, 6651 .stop = rtl8xxxu_stop, 6652 .sw_scan_start = rtl8xxxu_sw_scan_start, 6653 .sw_scan_complete = rtl8xxxu_sw_scan_complete, 6654 .set_key = rtl8xxxu_set_key, 6655 .ampdu_action = rtl8xxxu_ampdu_action, 6656 .sta_statistics = rtl8xxxu_sta_statistics, 6657 .get_antenna = rtl8xxxu_get_antenna, 6658 }; 6659 6660 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv, 6661 struct usb_interface *interface) 6662 { 6663 struct usb_interface_descriptor *interface_desc; 6664 struct usb_host_interface *host_interface; 6665 struct usb_endpoint_descriptor *endpoint; 6666 struct device *dev = &priv->udev->dev; 6667 int i, j = 0, endpoints; 6668 u8 dir, xtype, num; 6669 int ret = 0; 6670 6671 host_interface = interface->cur_altsetting; 6672 interface_desc = &host_interface->desc; 6673 endpoints = interface_desc->bNumEndpoints; 6674 6675 for (i = 0; i < endpoints; i++) { 6676 endpoint = &host_interface->endpoint[i].desc; 6677 6678 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK; 6679 num = usb_endpoint_num(endpoint); 6680 xtype = usb_endpoint_type(endpoint); 6681 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 6682 dev_dbg(dev, 6683 "%s: endpoint: dir %02x, # %02x, type %02x\n", 6684 __func__, dir, num, xtype); 6685 if (usb_endpoint_dir_in(endpoint) && 6686 usb_endpoint_xfer_bulk(endpoint)) { 6687 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 6688 dev_dbg(dev, "%s: in endpoint num %i\n", 6689 __func__, num); 6690 6691 if (priv->pipe_in) { 6692 dev_warn(dev, 6693 "%s: Too many IN pipes\n", __func__); 6694 ret = -EINVAL; 6695 goto exit; 6696 } 6697 6698 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num); 6699 } 6700 6701 if (usb_endpoint_dir_in(endpoint) && 6702 usb_endpoint_xfer_int(endpoint)) { 6703 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 6704 dev_dbg(dev, "%s: interrupt endpoint num %i\n", 6705 __func__, num); 6706 6707 if (priv->pipe_interrupt) { 6708 dev_warn(dev, "%s: Too many INTERRUPT pipes\n", 6709 __func__); 6710 ret = -EINVAL; 6711 goto exit; 6712 } 6713 6714 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num); 6715 } 6716 6717 if (usb_endpoint_dir_out(endpoint) && 6718 usb_endpoint_xfer_bulk(endpoint)) { 6719 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 6720 dev_dbg(dev, "%s: out endpoint num %i\n", 6721 __func__, num); 6722 if (j >= RTL8XXXU_OUT_ENDPOINTS) { 6723 dev_warn(dev, 6724 "%s: Too many OUT pipes\n", __func__); 6725 ret = -EINVAL; 6726 goto exit; 6727 } 6728 priv->out_ep[j++] = num; 6729 } 6730 } 6731 exit: 6732 priv->nr_out_eps = j; 6733 return ret; 6734 } 6735 6736 static int rtl8xxxu_probe(struct usb_interface *interface, 6737 const struct usb_device_id *id) 6738 { 6739 struct rtl8xxxu_priv *priv; 6740 struct ieee80211_hw *hw; 6741 struct usb_device *udev; 6742 struct ieee80211_supported_band *sband; 6743 int ret; 6744 int untested = 1; 6745 6746 udev = usb_get_dev(interface_to_usbdev(interface)); 6747 6748 switch (id->idVendor) { 6749 case USB_VENDOR_ID_REALTEK: 6750 switch(id->idProduct) { 6751 case 0x1724: 6752 case 0x8176: 6753 case 0x8178: 6754 case 0x817f: 6755 case 0x818b: 6756 case 0xf179: 6757 untested = 0; 6758 break; 6759 } 6760 break; 6761 case 0x7392: 6762 if (id->idProduct == 0x7811 || id->idProduct == 0xa611) 6763 untested = 0; 6764 break; 6765 case 0x050d: 6766 if (id->idProduct == 0x1004) 6767 untested = 0; 6768 break; 6769 case 0x20f4: 6770 if (id->idProduct == 0x648b) 6771 untested = 0; 6772 break; 6773 case 0x2001: 6774 if (id->idProduct == 0x3308) 6775 untested = 0; 6776 break; 6777 case 0x2357: 6778 if (id->idProduct == 0x0109) 6779 untested = 0; 6780 break; 6781 default: 6782 break; 6783 } 6784 6785 if (untested) { 6786 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE; 6787 dev_info(&udev->dev, 6788 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n", 6789 id->idVendor, id->idProduct); 6790 dev_info(&udev->dev, 6791 "Please report results to Jes.Sorensen@gmail.com\n"); 6792 } 6793 6794 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops); 6795 if (!hw) { 6796 ret = -ENOMEM; 6797 goto err_put_dev; 6798 } 6799 6800 priv = hw->priv; 6801 priv->hw = hw; 6802 priv->udev = udev; 6803 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info; 6804 mutex_init(&priv->usb_buf_mutex); 6805 mutex_init(&priv->h2c_mutex); 6806 INIT_LIST_HEAD(&priv->tx_urb_free_list); 6807 spin_lock_init(&priv->tx_urb_lock); 6808 INIT_LIST_HEAD(&priv->rx_urb_pending_list); 6809 spin_lock_init(&priv->rx_urb_lock); 6810 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work); 6811 INIT_DELAYED_WORK(&priv->ra_watchdog, rtl8xxxu_watchdog_callback); 6812 INIT_WORK(&priv->c2hcmd_work, rtl8xxxu_c2hcmd_callback); 6813 skb_queue_head_init(&priv->c2hcmd_queue); 6814 6815 usb_set_intfdata(interface, hw); 6816 6817 ret = rtl8xxxu_parse_usb(priv, interface); 6818 if (ret) 6819 goto err_set_intfdata; 6820 6821 ret = priv->fops->identify_chip(priv); 6822 if (ret) { 6823 dev_err(&udev->dev, "Fatal - failed to identify chip\n"); 6824 goto err_set_intfdata; 6825 } 6826 6827 hw->wiphy->available_antennas_tx = BIT(priv->tx_paths) - 1; 6828 hw->wiphy->available_antennas_rx = BIT(priv->rx_paths) - 1; 6829 6830 ret = rtl8xxxu_read_efuse(priv); 6831 if (ret) { 6832 dev_err(&udev->dev, "Fatal - failed to read EFuse\n"); 6833 goto err_set_intfdata; 6834 } 6835 6836 ret = priv->fops->parse_efuse(priv); 6837 if (ret) { 6838 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n"); 6839 goto err_set_intfdata; 6840 } 6841 6842 rtl8xxxu_print_chipinfo(priv); 6843 6844 ret = priv->fops->load_firmware(priv); 6845 if (ret) { 6846 dev_err(&udev->dev, "Fatal - failed to load firmware\n"); 6847 goto err_set_intfdata; 6848 } 6849 6850 ret = rtl8xxxu_init_device(hw); 6851 if (ret) 6852 goto err_set_intfdata; 6853 6854 hw->wiphy->max_scan_ssids = 1; 6855 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; 6856 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); 6857 hw->queues = 4; 6858 6859 sband = &rtl8xxxu_supported_band; 6860 sband->ht_cap.ht_supported = true; 6861 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 6862 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16; 6863 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40; 6864 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs)); 6865 sband->ht_cap.mcs.rx_mask[0] = 0xff; 6866 sband->ht_cap.mcs.rx_mask[4] = 0x01; 6867 if (priv->rf_paths > 1) { 6868 sband->ht_cap.mcs.rx_mask[1] = 0xff; 6869 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40; 6870 } 6871 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 6872 /* 6873 * Some APs will negotiate HT20_40 in a noisy environment leading 6874 * to miserable performance. Rather than defaulting to this, only 6875 * enable it if explicitly requested at module load time. 6876 */ 6877 if (rtl8xxxu_ht40_2g) { 6878 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n"); 6879 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; 6880 } 6881 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 6882 6883 hw->wiphy->rts_threshold = 2347; 6884 6885 SET_IEEE80211_DEV(priv->hw, &interface->dev); 6886 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr); 6887 6888 hw->extra_tx_headroom = priv->fops->tx_desc_size; 6889 ieee80211_hw_set(hw, SIGNAL_DBM); 6890 /* 6891 * The firmware handles rate control 6892 */ 6893 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 6894 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 6895 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 6896 6897 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); 6898 6899 ret = ieee80211_register_hw(priv->hw); 6900 if (ret) { 6901 dev_err(&udev->dev, "%s: Failed to register: %i\n", 6902 __func__, ret); 6903 goto err_set_intfdata; 6904 } 6905 6906 return 0; 6907 6908 err_set_intfdata: 6909 usb_set_intfdata(interface, NULL); 6910 6911 kfree(priv->fw_data); 6912 mutex_destroy(&priv->usb_buf_mutex); 6913 mutex_destroy(&priv->h2c_mutex); 6914 6915 ieee80211_free_hw(hw); 6916 err_put_dev: 6917 usb_put_dev(udev); 6918 6919 return ret; 6920 } 6921 6922 static void rtl8xxxu_disconnect(struct usb_interface *interface) 6923 { 6924 struct rtl8xxxu_priv *priv; 6925 struct ieee80211_hw *hw; 6926 6927 hw = usb_get_intfdata(interface); 6928 priv = hw->priv; 6929 6930 ieee80211_unregister_hw(hw); 6931 6932 priv->fops->power_off(priv); 6933 6934 usb_set_intfdata(interface, NULL); 6935 6936 dev_info(&priv->udev->dev, "disconnecting\n"); 6937 6938 kfree(priv->fw_data); 6939 mutex_destroy(&priv->usb_buf_mutex); 6940 mutex_destroy(&priv->h2c_mutex); 6941 6942 if (priv->udev->state != USB_STATE_NOTATTACHED) { 6943 dev_info(&priv->udev->dev, 6944 "Device still attached, trying to reset\n"); 6945 usb_reset_device(priv->udev); 6946 } 6947 usb_put_dev(priv->udev); 6948 ieee80211_free_hw(hw); 6949 } 6950 6951 static const struct usb_device_id dev_table[] = { 6952 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff), 6953 .driver_info = (unsigned long)&rtl8723au_fops}, 6954 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff), 6955 .driver_info = (unsigned long)&rtl8723au_fops}, 6956 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff), 6957 .driver_info = (unsigned long)&rtl8723au_fops}, 6958 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff), 6959 .driver_info = (unsigned long)&rtl8192eu_fops}, 6960 /* TP-Link TL-WN822N v4 */ 6961 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0108, 0xff, 0xff, 0xff), 6962 .driver_info = (unsigned long)&rtl8192eu_fops}, 6963 /* D-Link DWA-131 rev E1, tested by David Patiño */ 6964 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3319, 0xff, 0xff, 0xff), 6965 .driver_info = (unsigned long)&rtl8192eu_fops}, 6966 /* Tested by Myckel Habets */ 6967 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0109, 0xff, 0xff, 0xff), 6968 .driver_info = (unsigned long)&rtl8192eu_fops}, 6969 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff), 6970 .driver_info = (unsigned long)&rtl8723bu_fops}, 6971 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xa611, 0xff, 0xff, 0xff), 6972 .driver_info = (unsigned long)&rtl8723bu_fops}, 6973 /* RTL8188FU */ 6974 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xf179, 0xff, 0xff, 0xff), 6975 .driver_info = (unsigned long)&rtl8188fu_fops}, 6976 #ifdef CONFIG_RTL8XXXU_UNTESTED 6977 /* Still supported by rtlwifi */ 6978 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff), 6979 .driver_info = (unsigned long)&rtl8192cu_fops}, 6980 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff), 6981 .driver_info = (unsigned long)&rtl8192cu_fops}, 6982 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff), 6983 .driver_info = (unsigned long)&rtl8192cu_fops}, 6984 /* Tested by Larry Finger */ 6985 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff), 6986 .driver_info = (unsigned long)&rtl8192cu_fops}, 6987 /* Tested by Andrea Merello */ 6988 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff), 6989 .driver_info = (unsigned long)&rtl8192cu_fops}, 6990 /* Tested by Jocelyn Mayer */ 6991 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff), 6992 .driver_info = (unsigned long)&rtl8192cu_fops}, 6993 /* Tested by Stefano Bravi */ 6994 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff), 6995 .driver_info = (unsigned long)&rtl8192cu_fops}, 6996 /* Currently untested 8188 series devices */ 6997 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x018a, 0xff, 0xff, 0xff), 6998 .driver_info = (unsigned long)&rtl8192cu_fops}, 6999 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff), 7000 .driver_info = (unsigned long)&rtl8192cu_fops}, 7001 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff), 7002 .driver_info = (unsigned long)&rtl8192cu_fops}, 7003 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff), 7004 .driver_info = (unsigned long)&rtl8192cu_fops}, 7005 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff), 7006 .driver_info = (unsigned long)&rtl8192cu_fops}, 7007 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff), 7008 .driver_info = (unsigned long)&rtl8192cu_fops}, 7009 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff), 7010 .driver_info = (unsigned long)&rtl8192cu_fops}, 7011 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff), 7012 .driver_info = (unsigned long)&rtl8192cu_fops}, 7013 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff), 7014 .driver_info = (unsigned long)&rtl8192cu_fops}, 7015 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff), 7016 .driver_info = (unsigned long)&rtl8192cu_fops}, 7017 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff), 7018 .driver_info = (unsigned long)&rtl8192cu_fops}, 7019 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff), 7020 .driver_info = (unsigned long)&rtl8192cu_fops}, 7021 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff), 7022 .driver_info = (unsigned long)&rtl8192cu_fops}, 7023 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff), 7024 .driver_info = (unsigned long)&rtl8192cu_fops}, 7025 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff), 7026 .driver_info = (unsigned long)&rtl8192cu_fops}, 7027 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff), 7028 .driver_info = (unsigned long)&rtl8192cu_fops}, 7029 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff), 7030 .driver_info = (unsigned long)&rtl8192cu_fops}, 7031 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff), 7032 .driver_info = (unsigned long)&rtl8192cu_fops}, 7033 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff), 7034 .driver_info = (unsigned long)&rtl8192cu_fops}, 7035 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff), 7036 .driver_info = (unsigned long)&rtl8192cu_fops}, 7037 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff), 7038 .driver_info = (unsigned long)&rtl8192cu_fops}, 7039 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff), 7040 .driver_info = (unsigned long)&rtl8192cu_fops}, 7041 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff), 7042 .driver_info = (unsigned long)&rtl8192cu_fops}, 7043 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff), 7044 .driver_info = (unsigned long)&rtl8192cu_fops}, 7045 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff), 7046 .driver_info = (unsigned long)&rtl8192cu_fops}, 7047 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff), 7048 .driver_info = (unsigned long)&rtl8192cu_fops}, 7049 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff), 7050 .driver_info = (unsigned long)&rtl8192cu_fops}, 7051 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff), 7052 .driver_info = (unsigned long)&rtl8192cu_fops}, 7053 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff), 7054 .driver_info = (unsigned long)&rtl8192cu_fops}, 7055 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff), 7056 .driver_info = (unsigned long)&rtl8192cu_fops}, 7057 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff), 7058 .driver_info = (unsigned long)&rtl8192cu_fops}, 7059 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff), 7060 .driver_info = (unsigned long)&rtl8192cu_fops}, 7061 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff), 7062 .driver_info = (unsigned long)&rtl8192cu_fops}, 7063 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff), 7064 .driver_info = (unsigned long)&rtl8192cu_fops}, 7065 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff), 7066 .driver_info = (unsigned long)&rtl8192cu_fops}, 7067 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff), 7068 .driver_info = (unsigned long)&rtl8192cu_fops}, 7069 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff), 7070 .driver_info = (unsigned long)&rtl8192cu_fops}, 7071 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff), 7072 .driver_info = (unsigned long)&rtl8192cu_fops}, 7073 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff), 7074 .driver_info = (unsigned long)&rtl8192cu_fops}, 7075 /* Currently untested 8192 series devices */ 7076 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff), 7077 .driver_info = (unsigned long)&rtl8192cu_fops}, 7078 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff), 7079 .driver_info = (unsigned long)&rtl8192cu_fops}, 7080 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff), 7081 .driver_info = (unsigned long)&rtl8192cu_fops}, 7082 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff), 7083 .driver_info = (unsigned long)&rtl8192cu_fops}, 7084 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff), 7085 .driver_info = (unsigned long)&rtl8192cu_fops}, 7086 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff), 7087 .driver_info = (unsigned long)&rtl8192cu_fops}, 7088 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff), 7089 .driver_info = (unsigned long)&rtl8192cu_fops}, 7090 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff), 7091 .driver_info = (unsigned long)&rtl8192cu_fops}, 7092 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff), 7093 .driver_info = (unsigned long)&rtl8192cu_fops}, 7094 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff), 7095 .driver_info = (unsigned long)&rtl8192cu_fops}, 7096 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff), 7097 .driver_info = (unsigned long)&rtl8192cu_fops}, 7098 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff), 7099 .driver_info = (unsigned long)&rtl8192cu_fops}, 7100 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff), 7101 .driver_info = (unsigned long)&rtl8192cu_fops}, 7102 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff), 7103 .driver_info = (unsigned long)&rtl8192cu_fops}, 7104 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff), 7105 .driver_info = (unsigned long)&rtl8192cu_fops}, 7106 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff), 7107 .driver_info = (unsigned long)&rtl8192cu_fops}, 7108 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff), 7109 .driver_info = (unsigned long)&rtl8192cu_fops}, 7110 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff), 7111 .driver_info = (unsigned long)&rtl8192cu_fops}, 7112 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff), 7113 .driver_info = (unsigned long)&rtl8192cu_fops}, 7114 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff), 7115 .driver_info = (unsigned long)&rtl8192cu_fops}, 7116 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff), 7117 .driver_info = (unsigned long)&rtl8192cu_fops}, 7118 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff), 7119 .driver_info = (unsigned long)&rtl8192cu_fops}, 7120 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff), 7121 .driver_info = (unsigned long)&rtl8192cu_fops}, 7122 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff), 7123 .driver_info = (unsigned long)&rtl8192cu_fops}, 7124 /* found in rtl8192eu vendor driver */ 7125 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0107, 0xff, 0xff, 0xff), 7126 .driver_info = (unsigned long)&rtl8192eu_fops}, 7127 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab33, 0xff, 0xff, 0xff), 7128 .driver_info = (unsigned long)&rtl8192eu_fops}, 7129 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818c, 0xff, 0xff, 0xff), 7130 .driver_info = (unsigned long)&rtl8192eu_fops}, 7131 #endif 7132 { } 7133 }; 7134 7135 static struct usb_driver rtl8xxxu_driver = { 7136 .name = DRIVER_NAME, 7137 .probe = rtl8xxxu_probe, 7138 .disconnect = rtl8xxxu_disconnect, 7139 .id_table = dev_table, 7140 .no_dynamic_id = 1, 7141 .disable_hub_initiated_lpm = 1, 7142 }; 7143 7144 static int __init rtl8xxxu_module_init(void) 7145 { 7146 int res; 7147 7148 res = usb_register(&rtl8xxxu_driver); 7149 if (res < 0) 7150 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res); 7151 7152 return res; 7153 } 7154 7155 static void __exit rtl8xxxu_module_exit(void) 7156 { 7157 usb_deregister(&rtl8xxxu_driver); 7158 } 7159 7160 7161 MODULE_DEVICE_TABLE(usb, dev_table); 7162 7163 module_init(rtl8xxxu_module_init); 7164 module_exit(rtl8xxxu_module_exit); 7165