1 /* 2 * RTL8XXXU mac80211 USB driver 3 * 4 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> 5 * 6 * Portions, notably calibration code: 7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 8 * 9 * This driver was written as a replacement for the vendor provided 10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in 11 * their programming interface, I have started adding support for 12 * additional 8xxx chips like the 8192cu, 8188cus, etc. 13 * 14 * This program is free software; you can redistribute it and/or modify it 15 * under the terms of version 2 of the GNU General Public License as 16 * published by the Free Software Foundation. 17 * 18 * This program is distributed in the hope that it will be useful, but WITHOUT 19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 21 * more details. 22 */ 23 24 #include <linux/init.h> 25 #include <linux/kernel.h> 26 #include <linux/sched.h> 27 #include <linux/errno.h> 28 #include <linux/slab.h> 29 #include <linux/module.h> 30 #include <linux/spinlock.h> 31 #include <linux/list.h> 32 #include <linux/usb.h> 33 #include <linux/netdevice.h> 34 #include <linux/etherdevice.h> 35 #include <linux/ethtool.h> 36 #include <linux/wireless.h> 37 #include <linux/firmware.h> 38 #include <linux/moduleparam.h> 39 #include <net/mac80211.h> 40 #include "rtl8xxxu.h" 41 #include "rtl8xxxu_regs.h" 42 43 #define DRIVER_NAME "rtl8xxxu" 44 45 int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE; 46 static bool rtl8xxxu_ht40_2g; 47 static bool rtl8xxxu_dma_aggregation; 48 static int rtl8xxxu_dma_agg_timeout = -1; 49 static int rtl8xxxu_dma_agg_pages = -1; 50 51 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@gmail.com>"); 52 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver"); 53 MODULE_LICENSE("GPL"); 54 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin"); 55 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin"); 56 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin"); 57 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin"); 58 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin"); 59 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin"); 60 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin"); 61 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin"); 62 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin"); 63 64 module_param_named(debug, rtl8xxxu_debug, int, 0600); 65 MODULE_PARM_DESC(debug, "Set debug mask"); 66 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600); 67 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band"); 68 module_param_named(dma_aggregation, rtl8xxxu_dma_aggregation, bool, 0600); 69 MODULE_PARM_DESC(dma_aggregation, "Enable DMA packet aggregation"); 70 module_param_named(dma_agg_timeout, rtl8xxxu_dma_agg_timeout, int, 0600); 71 MODULE_PARM_DESC(dma_agg_timeout, "Set DMA aggregation timeout (range 1-127)"); 72 module_param_named(dma_agg_pages, rtl8xxxu_dma_agg_pages, int, 0600); 73 MODULE_PARM_DESC(dma_agg_pages, "Set DMA aggregation pages (range 1-127, 0 to disable)"); 74 75 #define USB_VENDOR_ID_REALTEK 0x0bda 76 #define RTL8XXXU_RX_URBS 32 77 #define RTL8XXXU_RX_URB_PENDING_WATER 8 78 #define RTL8XXXU_TX_URBS 64 79 #define RTL8XXXU_TX_URB_LOW_WATER 25 80 #define RTL8XXXU_TX_URB_HIGH_WATER 32 81 82 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv, 83 struct rtl8xxxu_rx_urb *rx_urb); 84 85 static struct ieee80211_rate rtl8xxxu_rates[] = { 86 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 }, 87 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 }, 88 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 }, 89 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 }, 90 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 }, 91 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 }, 92 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 }, 93 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 }, 94 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 }, 95 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 }, 96 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 }, 97 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 }, 98 }; 99 100 static struct ieee80211_channel rtl8xxxu_channels_2g[] = { 101 { .band = NL80211_BAND_2GHZ, .center_freq = 2412, 102 .hw_value = 1, .max_power = 30 }, 103 { .band = NL80211_BAND_2GHZ, .center_freq = 2417, 104 .hw_value = 2, .max_power = 30 }, 105 { .band = NL80211_BAND_2GHZ, .center_freq = 2422, 106 .hw_value = 3, .max_power = 30 }, 107 { .band = NL80211_BAND_2GHZ, .center_freq = 2427, 108 .hw_value = 4, .max_power = 30 }, 109 { .band = NL80211_BAND_2GHZ, .center_freq = 2432, 110 .hw_value = 5, .max_power = 30 }, 111 { .band = NL80211_BAND_2GHZ, .center_freq = 2437, 112 .hw_value = 6, .max_power = 30 }, 113 { .band = NL80211_BAND_2GHZ, .center_freq = 2442, 114 .hw_value = 7, .max_power = 30 }, 115 { .band = NL80211_BAND_2GHZ, .center_freq = 2447, 116 .hw_value = 8, .max_power = 30 }, 117 { .band = NL80211_BAND_2GHZ, .center_freq = 2452, 118 .hw_value = 9, .max_power = 30 }, 119 { .band = NL80211_BAND_2GHZ, .center_freq = 2457, 120 .hw_value = 10, .max_power = 30 }, 121 { .band = NL80211_BAND_2GHZ, .center_freq = 2462, 122 .hw_value = 11, .max_power = 30 }, 123 { .band = NL80211_BAND_2GHZ, .center_freq = 2467, 124 .hw_value = 12, .max_power = 30 }, 125 { .band = NL80211_BAND_2GHZ, .center_freq = 2472, 126 .hw_value = 13, .max_power = 30 }, 127 { .band = NL80211_BAND_2GHZ, .center_freq = 2484, 128 .hw_value = 14, .max_power = 30 } 129 }; 130 131 static struct ieee80211_supported_band rtl8xxxu_supported_band = { 132 .channels = rtl8xxxu_channels_2g, 133 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g), 134 .bitrates = rtl8xxxu_rates, 135 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates), 136 }; 137 138 struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[] = { 139 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00}, 140 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, 141 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00}, 142 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05}, 143 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01}, 144 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f}, 145 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72}, 146 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08}, 147 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, 148 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, 149 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, 150 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, 151 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, 152 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, 153 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16}, 154 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00}, 155 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02}, 156 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, 157 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, 158 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, 159 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, 160 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff}, 161 }; 162 163 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = { 164 {0x800, 0x80040000}, {0x804, 0x00000003}, 165 {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, 166 {0x810, 0x10001331}, {0x814, 0x020c3d10}, 167 {0x818, 0x02200385}, {0x81c, 0x00000000}, 168 {0x820, 0x01000100}, {0x824, 0x00390004}, 169 {0x828, 0x00000000}, {0x82c, 0x00000000}, 170 {0x830, 0x00000000}, {0x834, 0x00000000}, 171 {0x838, 0x00000000}, {0x83c, 0x00000000}, 172 {0x840, 0x00010000}, {0x844, 0x00000000}, 173 {0x848, 0x00000000}, {0x84c, 0x00000000}, 174 {0x850, 0x00000000}, {0x854, 0x00000000}, 175 {0x858, 0x569a569a}, {0x85c, 0x001b25a4}, 176 {0x860, 0x66f60110}, {0x864, 0x061f0130}, 177 {0x868, 0x00000000}, {0x86c, 0x32323200}, 178 {0x870, 0x07000760}, {0x874, 0x22004000}, 179 {0x878, 0x00000808}, {0x87c, 0x00000000}, 180 {0x880, 0xc0083070}, {0x884, 0x000004d5}, 181 {0x888, 0x00000000}, {0x88c, 0xccc000c0}, 182 {0x890, 0x00000800}, {0x894, 0xfffffffe}, 183 {0x898, 0x40302010}, {0x89c, 0x00706050}, 184 {0x900, 0x00000000}, {0x904, 0x00000023}, 185 {0x908, 0x00000000}, {0x90c, 0x81121111}, 186 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c}, 187 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f}, 188 {0xa10, 0x9500bb78}, {0xa14, 0x11144028}, 189 {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, 190 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, 191 {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, 192 {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, 193 {0xa78, 0x00000900}, 194 {0xc00, 0x48071d40}, {0xc04, 0x03a05611}, 195 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, 196 {0xc10, 0x08800000}, {0xc14, 0x40000100}, 197 {0xc18, 0x08800000}, {0xc1c, 0x40000100}, 198 {0xc20, 0x00000000}, {0xc24, 0x00000000}, 199 {0xc28, 0x00000000}, {0xc2c, 0x00000000}, 200 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af}, 201 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, 202 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, 203 {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, 204 {0xc50, 0x69543420}, {0xc54, 0x43bc0094}, 205 {0xc58, 0x69543420}, {0xc5c, 0x433c0094}, 206 {0xc60, 0x00000000}, {0xc64, 0x7112848b}, 207 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, 208 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db}, 209 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612}, 210 {0xc80, 0x40000100}, {0xc84, 0x20f60000}, 211 {0xc88, 0x40000100}, {0xc8c, 0x20200000}, 212 {0xc90, 0x00121820}, {0xc94, 0x00000000}, 213 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, 214 {0xca0, 0x00000000}, {0xca4, 0x00000080}, 215 {0xca8, 0x00000000}, {0xcac, 0x00000000}, 216 {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, 217 {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, 218 {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, 219 {0xcc8, 0x00000000}, {0xccc, 0x00000000}, 220 {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, 221 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, 222 {0xce0, 0x00222222}, {0xce4, 0x00000000}, 223 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, 224 {0xd00, 0x00080740}, {0xd04, 0x00020401}, 225 {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, 226 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, 227 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975}, 228 {0xd30, 0x00000000}, {0xd34, 0x80608000}, 229 {0xd38, 0x00000000}, {0xd3c, 0x00027293}, 230 {0xd40, 0x00000000}, {0xd44, 0x00000000}, 231 {0xd48, 0x00000000}, {0xd4c, 0x00000000}, 232 {0xd50, 0x6437140a}, {0xd54, 0x00000000}, 233 {0xd58, 0x00000000}, {0xd5c, 0x30032064}, 234 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, 235 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, 236 {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, 237 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a}, 238 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a}, 239 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a}, 240 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a}, 241 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, 242 {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, 243 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, 244 {0xe44, 0x01004800}, {0xe48, 0xfb000000}, 245 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, 246 {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, 247 {0xe5c, 0x28160d05}, {0xe60, 0x00000008}, 248 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0}, 249 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0}, 250 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0}, 251 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0}, 252 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0}, 253 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0}, 254 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0}, 255 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0}, 256 {0xf14, 0x00000003}, {0xf4c, 0x00000000}, 257 {0xf00, 0x00000300}, 258 {0xffff, 0xffffffff}, 259 }; 260 261 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = { 262 {0x024, 0x0011800f}, {0x028, 0x00ffdb83}, 263 {0x800, 0x80040002}, {0x804, 0x00000003}, 264 {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, 265 {0x810, 0x10000330}, {0x814, 0x020c3d10}, 266 {0x818, 0x02200385}, {0x81c, 0x00000000}, 267 {0x820, 0x01000100}, {0x824, 0x00390004}, 268 {0x828, 0x01000100}, {0x82c, 0x00390004}, 269 {0x830, 0x27272727}, {0x834, 0x27272727}, 270 {0x838, 0x27272727}, {0x83c, 0x27272727}, 271 {0x840, 0x00010000}, {0x844, 0x00010000}, 272 {0x848, 0x27272727}, {0x84c, 0x27272727}, 273 {0x850, 0x00000000}, {0x854, 0x00000000}, 274 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4}, 275 {0x860, 0x66e60230}, {0x864, 0x061f0130}, 276 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27}, 277 {0x870, 0x07000700}, {0x874, 0x22184000}, 278 {0x878, 0x08080808}, {0x87c, 0x00000000}, 279 {0x880, 0xc0083070}, {0x884, 0x000004d5}, 280 {0x888, 0x00000000}, {0x88c, 0xcc0000c0}, 281 {0x890, 0x00000800}, {0x894, 0xfffffffe}, 282 {0x898, 0x40302010}, {0x89c, 0x00706050}, 283 {0x900, 0x00000000}, {0x904, 0x00000023}, 284 {0x908, 0x00000000}, {0x90c, 0x81121313}, 285 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c}, 286 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f}, 287 {0xa10, 0x9500bb78}, {0xa14, 0x11144028}, 288 {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, 289 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, 290 {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, 291 {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, 292 {0xc00, 0x48071d40}, {0xc04, 0x03a05633}, 293 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, 294 {0xc10, 0x08800000}, {0xc14, 0x40000100}, 295 {0xc18, 0x08800000}, {0xc1c, 0x40000100}, 296 {0xc20, 0x00000000}, {0xc24, 0x00000000}, 297 {0xc28, 0x00000000}, {0xc2c, 0x00000000}, 298 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf}, 299 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, 300 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, 301 {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, 302 {0xc50, 0x69543420}, {0xc54, 0x43bc0094}, 303 {0xc58, 0x69543420}, {0xc5c, 0x433c0094}, 304 {0xc60, 0x00000000}, {0xc64, 0x5116848b}, 305 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, 306 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b}, 307 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612}, 308 {0xc80, 0x40000100}, {0xc84, 0x20f60000}, 309 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000}, 310 {0xc90, 0x00121820}, {0xc94, 0x00000000}, 311 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, 312 {0xca0, 0x00000000}, {0xca4, 0x00000080}, 313 {0xca8, 0x00000000}, {0xcac, 0x00000000}, 314 {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, 315 {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, 316 {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, 317 {0xcc8, 0x00000000}, {0xccc, 0x00000000}, 318 {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, 319 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, 320 {0xce0, 0x00222222}, {0xce4, 0x00000000}, 321 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, 322 {0xd00, 0x00080740}, {0xd04, 0x00020403}, 323 {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, 324 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, 325 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975}, 326 {0xd30, 0x00000000}, {0xd34, 0x80608000}, 327 {0xd38, 0x00000000}, {0xd3c, 0x00027293}, 328 {0xd40, 0x00000000}, {0xd44, 0x00000000}, 329 {0xd48, 0x00000000}, {0xd4c, 0x00000000}, 330 {0xd50, 0x6437140a}, {0xd54, 0x00000000}, 331 {0xd58, 0x00000000}, {0xd5c, 0x30032064}, 332 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, 333 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, 334 {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, 335 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a}, 336 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a}, 337 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a}, 338 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a}, 339 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, 340 {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, 341 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, 342 {0xe44, 0x01004800}, {0xe48, 0xfb000000}, 343 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, 344 {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, 345 {0xe5c, 0x28160d05}, {0xe60, 0x00000010}, 346 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4}, 347 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4}, 348 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4}, 349 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4}, 350 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4}, 351 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4}, 352 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4}, 353 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4}, 354 {0xf14, 0x00000003}, {0xf4c, 0x00000000}, 355 {0xf00, 0x00000300}, 356 {0xffff, 0xffffffff}, 357 }; 358 359 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = { 360 {0x024, 0x0011800f}, {0x028, 0x00ffdb83}, 361 {0x040, 0x000c0004}, {0x800, 0x80040000}, 362 {0x804, 0x00000001}, {0x808, 0x0000fc00}, 363 {0x80c, 0x0000000a}, {0x810, 0x10005388}, 364 {0x814, 0x020c3d10}, {0x818, 0x02200385}, 365 {0x81c, 0x00000000}, {0x820, 0x01000100}, 366 {0x824, 0x00390204}, {0x828, 0x00000000}, 367 {0x82c, 0x00000000}, {0x830, 0x00000000}, 368 {0x834, 0x00000000}, {0x838, 0x00000000}, 369 {0x83c, 0x00000000}, {0x840, 0x00010000}, 370 {0x844, 0x00000000}, {0x848, 0x00000000}, 371 {0x84c, 0x00000000}, {0x850, 0x00000000}, 372 {0x854, 0x00000000}, {0x858, 0x569a569a}, 373 {0x85c, 0x001b25a4}, {0x860, 0x66e60230}, 374 {0x864, 0x061f0130}, {0x868, 0x00000000}, 375 {0x86c, 0x20202000}, {0x870, 0x03000300}, 376 {0x874, 0x22004000}, {0x878, 0x00000808}, 377 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070}, 378 {0x884, 0x000004d5}, {0x888, 0x00000000}, 379 {0x88c, 0xccc000c0}, {0x890, 0x00000800}, 380 {0x894, 0xfffffffe}, {0x898, 0x40302010}, 381 {0x89c, 0x00706050}, {0x900, 0x00000000}, 382 {0x904, 0x00000023}, {0x908, 0x00000000}, 383 {0x90c, 0x81121111}, {0xa00, 0x00d047c8}, 384 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300}, 385 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78}, 386 {0xa14, 0x11144028}, {0xa18, 0x00881117}, 387 {0xa1c, 0x89140f00}, {0xa20, 0x15160000}, 388 {0xa24, 0x070b0f12}, {0xa28, 0x00000104}, 389 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00}, 390 {0xa74, 0x00000007}, {0xc00, 0x48071d40}, 391 {0xc04, 0x03a05611}, {0xc08, 0x000000e4}, 392 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000}, 393 {0xc14, 0x40000100}, {0xc18, 0x08800000}, 394 {0xc1c, 0x40000100}, {0xc20, 0x00000000}, 395 {0xc24, 0x00000000}, {0xc28, 0x00000000}, 396 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44}, 397 {0xc34, 0x469652cf}, {0xc38, 0x49795994}, 398 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f}, 399 {0xc44, 0x000100b7}, {0xc48, 0xec020107}, 400 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e}, 401 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f}, 402 {0xc5c, 0x433c0094}, {0xc60, 0x00000000}, 403 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff}, 404 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d}, 405 {0xc74, 0x018610db}, {0xc78, 0x0000001f}, 406 {0xc7c, 0x00b91612}, {0xc80, 0x24000090}, 407 {0xc84, 0x20f60000}, {0xc88, 0x24000090}, 408 {0xc8c, 0x20200000}, {0xc90, 0x00121820}, 409 {0xc94, 0x00000000}, {0xc98, 0x00121820}, 410 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000}, 411 {0xca4, 0x00000080}, {0xca8, 0x00000000}, 412 {0xcac, 0x00000000}, {0xcb0, 0x00000000}, 413 {0xcb4, 0x00000000}, {0xcb8, 0x00000000}, 414 {0xcbc, 0x28000000}, {0xcc0, 0x00000000}, 415 {0xcc4, 0x00000000}, {0xcc8, 0x00000000}, 416 {0xccc, 0x00000000}, {0xcd0, 0x00000000}, 417 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427}, 418 {0xcdc, 0x00766932}, {0xce0, 0x00222222}, 419 {0xce4, 0x00000000}, {0xce8, 0x37644302}, 420 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740}, 421 {0xd04, 0x00020401}, {0xd08, 0x0000907f}, 422 {0xd0c, 0x20010201}, {0xd10, 0xa0633333}, 423 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b}, 424 {0xd2c, 0xcc979975}, {0xd30, 0x00000000}, 425 {0xd34, 0x80608000}, {0xd38, 0x00000000}, 426 {0xd3c, 0x00027293}, {0xd40, 0x00000000}, 427 {0xd44, 0x00000000}, {0xd48, 0x00000000}, 428 {0xd4c, 0x00000000}, {0xd50, 0x6437140a}, 429 {0xd54, 0x00000000}, {0xd58, 0x00000000}, 430 {0xd5c, 0x30032064}, {0xd60, 0x4653de68}, 431 {0xd64, 0x04518a3c}, {0xd68, 0x00002101}, 432 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e}, 433 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24}, 434 {0xe00, 0x24242424}, {0xe04, 0x24242424}, 435 {0xe08, 0x03902024}, {0xe10, 0x24242424}, 436 {0xe14, 0x24242424}, {0xe18, 0x24242424}, 437 {0xe1c, 0x24242424}, {0xe28, 0x00000000}, 438 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f}, 439 {0xe38, 0x02140102}, {0xe3c, 0x681604c2}, 440 {0xe40, 0x01007c00}, {0xe44, 0x01004800}, 441 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1}, 442 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f}, 443 {0xe58, 0x02140102}, {0xe5c, 0x28160d05}, 444 {0xe60, 0x00000008}, {0xe68, 0x001b25a4}, 445 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0}, 446 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0}, 447 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0}, 448 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0}, 449 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0}, 450 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0}, 451 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0}, 452 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448}, 453 {0xf14, 0x00000003}, {0xf4c, 0x00000000}, 454 {0xf00, 0x00000300}, 455 {0xffff, 0xffffffff}, 456 }; 457 458 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = { 459 {0xc78, 0x7b000001}, {0xc78, 0x7b010001}, 460 {0xc78, 0x7b020001}, {0xc78, 0x7b030001}, 461 {0xc78, 0x7b040001}, {0xc78, 0x7b050001}, 462 {0xc78, 0x7a060001}, {0xc78, 0x79070001}, 463 {0xc78, 0x78080001}, {0xc78, 0x77090001}, 464 {0xc78, 0x760a0001}, {0xc78, 0x750b0001}, 465 {0xc78, 0x740c0001}, {0xc78, 0x730d0001}, 466 {0xc78, 0x720e0001}, {0xc78, 0x710f0001}, 467 {0xc78, 0x70100001}, {0xc78, 0x6f110001}, 468 {0xc78, 0x6e120001}, {0xc78, 0x6d130001}, 469 {0xc78, 0x6c140001}, {0xc78, 0x6b150001}, 470 {0xc78, 0x6a160001}, {0xc78, 0x69170001}, 471 {0xc78, 0x68180001}, {0xc78, 0x67190001}, 472 {0xc78, 0x661a0001}, {0xc78, 0x651b0001}, 473 {0xc78, 0x641c0001}, {0xc78, 0x631d0001}, 474 {0xc78, 0x621e0001}, {0xc78, 0x611f0001}, 475 {0xc78, 0x60200001}, {0xc78, 0x49210001}, 476 {0xc78, 0x48220001}, {0xc78, 0x47230001}, 477 {0xc78, 0x46240001}, {0xc78, 0x45250001}, 478 {0xc78, 0x44260001}, {0xc78, 0x43270001}, 479 {0xc78, 0x42280001}, {0xc78, 0x41290001}, 480 {0xc78, 0x402a0001}, {0xc78, 0x262b0001}, 481 {0xc78, 0x252c0001}, {0xc78, 0x242d0001}, 482 {0xc78, 0x232e0001}, {0xc78, 0x222f0001}, 483 {0xc78, 0x21300001}, {0xc78, 0x20310001}, 484 {0xc78, 0x06320001}, {0xc78, 0x05330001}, 485 {0xc78, 0x04340001}, {0xc78, 0x03350001}, 486 {0xc78, 0x02360001}, {0xc78, 0x01370001}, 487 {0xc78, 0x00380001}, {0xc78, 0x00390001}, 488 {0xc78, 0x003a0001}, {0xc78, 0x003b0001}, 489 {0xc78, 0x003c0001}, {0xc78, 0x003d0001}, 490 {0xc78, 0x003e0001}, {0xc78, 0x003f0001}, 491 {0xc78, 0x7b400001}, {0xc78, 0x7b410001}, 492 {0xc78, 0x7b420001}, {0xc78, 0x7b430001}, 493 {0xc78, 0x7b440001}, {0xc78, 0x7b450001}, 494 {0xc78, 0x7a460001}, {0xc78, 0x79470001}, 495 {0xc78, 0x78480001}, {0xc78, 0x77490001}, 496 {0xc78, 0x764a0001}, {0xc78, 0x754b0001}, 497 {0xc78, 0x744c0001}, {0xc78, 0x734d0001}, 498 {0xc78, 0x724e0001}, {0xc78, 0x714f0001}, 499 {0xc78, 0x70500001}, {0xc78, 0x6f510001}, 500 {0xc78, 0x6e520001}, {0xc78, 0x6d530001}, 501 {0xc78, 0x6c540001}, {0xc78, 0x6b550001}, 502 {0xc78, 0x6a560001}, {0xc78, 0x69570001}, 503 {0xc78, 0x68580001}, {0xc78, 0x67590001}, 504 {0xc78, 0x665a0001}, {0xc78, 0x655b0001}, 505 {0xc78, 0x645c0001}, {0xc78, 0x635d0001}, 506 {0xc78, 0x625e0001}, {0xc78, 0x615f0001}, 507 {0xc78, 0x60600001}, {0xc78, 0x49610001}, 508 {0xc78, 0x48620001}, {0xc78, 0x47630001}, 509 {0xc78, 0x46640001}, {0xc78, 0x45650001}, 510 {0xc78, 0x44660001}, {0xc78, 0x43670001}, 511 {0xc78, 0x42680001}, {0xc78, 0x41690001}, 512 {0xc78, 0x406a0001}, {0xc78, 0x266b0001}, 513 {0xc78, 0x256c0001}, {0xc78, 0x246d0001}, 514 {0xc78, 0x236e0001}, {0xc78, 0x226f0001}, 515 {0xc78, 0x21700001}, {0xc78, 0x20710001}, 516 {0xc78, 0x06720001}, {0xc78, 0x05730001}, 517 {0xc78, 0x04740001}, {0xc78, 0x03750001}, 518 {0xc78, 0x02760001}, {0xc78, 0x01770001}, 519 {0xc78, 0x00780001}, {0xc78, 0x00790001}, 520 {0xc78, 0x007a0001}, {0xc78, 0x007b0001}, 521 {0xc78, 0x007c0001}, {0xc78, 0x007d0001}, 522 {0xc78, 0x007e0001}, {0xc78, 0x007f0001}, 523 {0xc78, 0x3800001e}, {0xc78, 0x3801001e}, 524 {0xc78, 0x3802001e}, {0xc78, 0x3803001e}, 525 {0xc78, 0x3804001e}, {0xc78, 0x3805001e}, 526 {0xc78, 0x3806001e}, {0xc78, 0x3807001e}, 527 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e}, 528 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e}, 529 {0xc78, 0x440c001e}, {0xc78, 0x480d001e}, 530 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e}, 531 {0xc78, 0x5210001e}, {0xc78, 0x5611001e}, 532 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e}, 533 {0xc78, 0x6014001e}, {0xc78, 0x6015001e}, 534 {0xc78, 0x6016001e}, {0xc78, 0x6217001e}, 535 {0xc78, 0x6218001e}, {0xc78, 0x6219001e}, 536 {0xc78, 0x621a001e}, {0xc78, 0x621b001e}, 537 {0xc78, 0x621c001e}, {0xc78, 0x621d001e}, 538 {0xc78, 0x621e001e}, {0xc78, 0x621f001e}, 539 {0xffff, 0xffffffff} 540 }; 541 542 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = { 543 {0xc78, 0x7b000001}, {0xc78, 0x7b010001}, 544 {0xc78, 0x7b020001}, {0xc78, 0x7b030001}, 545 {0xc78, 0x7b040001}, {0xc78, 0x7b050001}, 546 {0xc78, 0x7b060001}, {0xc78, 0x7b070001}, 547 {0xc78, 0x7b080001}, {0xc78, 0x7a090001}, 548 {0xc78, 0x790a0001}, {0xc78, 0x780b0001}, 549 {0xc78, 0x770c0001}, {0xc78, 0x760d0001}, 550 {0xc78, 0x750e0001}, {0xc78, 0x740f0001}, 551 {0xc78, 0x73100001}, {0xc78, 0x72110001}, 552 {0xc78, 0x71120001}, {0xc78, 0x70130001}, 553 {0xc78, 0x6f140001}, {0xc78, 0x6e150001}, 554 {0xc78, 0x6d160001}, {0xc78, 0x6c170001}, 555 {0xc78, 0x6b180001}, {0xc78, 0x6a190001}, 556 {0xc78, 0x691a0001}, {0xc78, 0x681b0001}, 557 {0xc78, 0x671c0001}, {0xc78, 0x661d0001}, 558 {0xc78, 0x651e0001}, {0xc78, 0x641f0001}, 559 {0xc78, 0x63200001}, {0xc78, 0x62210001}, 560 {0xc78, 0x61220001}, {0xc78, 0x60230001}, 561 {0xc78, 0x46240001}, {0xc78, 0x45250001}, 562 {0xc78, 0x44260001}, {0xc78, 0x43270001}, 563 {0xc78, 0x42280001}, {0xc78, 0x41290001}, 564 {0xc78, 0x402a0001}, {0xc78, 0x262b0001}, 565 {0xc78, 0x252c0001}, {0xc78, 0x242d0001}, 566 {0xc78, 0x232e0001}, {0xc78, 0x222f0001}, 567 {0xc78, 0x21300001}, {0xc78, 0x20310001}, 568 {0xc78, 0x06320001}, {0xc78, 0x05330001}, 569 {0xc78, 0x04340001}, {0xc78, 0x03350001}, 570 {0xc78, 0x02360001}, {0xc78, 0x01370001}, 571 {0xc78, 0x00380001}, {0xc78, 0x00390001}, 572 {0xc78, 0x003a0001}, {0xc78, 0x003b0001}, 573 {0xc78, 0x003c0001}, {0xc78, 0x003d0001}, 574 {0xc78, 0x003e0001}, {0xc78, 0x003f0001}, 575 {0xc78, 0x7b400001}, {0xc78, 0x7b410001}, 576 {0xc78, 0x7b420001}, {0xc78, 0x7b430001}, 577 {0xc78, 0x7b440001}, {0xc78, 0x7b450001}, 578 {0xc78, 0x7b460001}, {0xc78, 0x7b470001}, 579 {0xc78, 0x7b480001}, {0xc78, 0x7a490001}, 580 {0xc78, 0x794a0001}, {0xc78, 0x784b0001}, 581 {0xc78, 0x774c0001}, {0xc78, 0x764d0001}, 582 {0xc78, 0x754e0001}, {0xc78, 0x744f0001}, 583 {0xc78, 0x73500001}, {0xc78, 0x72510001}, 584 {0xc78, 0x71520001}, {0xc78, 0x70530001}, 585 {0xc78, 0x6f540001}, {0xc78, 0x6e550001}, 586 {0xc78, 0x6d560001}, {0xc78, 0x6c570001}, 587 {0xc78, 0x6b580001}, {0xc78, 0x6a590001}, 588 {0xc78, 0x695a0001}, {0xc78, 0x685b0001}, 589 {0xc78, 0x675c0001}, {0xc78, 0x665d0001}, 590 {0xc78, 0x655e0001}, {0xc78, 0x645f0001}, 591 {0xc78, 0x63600001}, {0xc78, 0x62610001}, 592 {0xc78, 0x61620001}, {0xc78, 0x60630001}, 593 {0xc78, 0x46640001}, {0xc78, 0x45650001}, 594 {0xc78, 0x44660001}, {0xc78, 0x43670001}, 595 {0xc78, 0x42680001}, {0xc78, 0x41690001}, 596 {0xc78, 0x406a0001}, {0xc78, 0x266b0001}, 597 {0xc78, 0x256c0001}, {0xc78, 0x246d0001}, 598 {0xc78, 0x236e0001}, {0xc78, 0x226f0001}, 599 {0xc78, 0x21700001}, {0xc78, 0x20710001}, 600 {0xc78, 0x06720001}, {0xc78, 0x05730001}, 601 {0xc78, 0x04740001}, {0xc78, 0x03750001}, 602 {0xc78, 0x02760001}, {0xc78, 0x01770001}, 603 {0xc78, 0x00780001}, {0xc78, 0x00790001}, 604 {0xc78, 0x007a0001}, {0xc78, 0x007b0001}, 605 {0xc78, 0x007c0001}, {0xc78, 0x007d0001}, 606 {0xc78, 0x007e0001}, {0xc78, 0x007f0001}, 607 {0xc78, 0x3800001e}, {0xc78, 0x3801001e}, 608 {0xc78, 0x3802001e}, {0xc78, 0x3803001e}, 609 {0xc78, 0x3804001e}, {0xc78, 0x3805001e}, 610 {0xc78, 0x3806001e}, {0xc78, 0x3807001e}, 611 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e}, 612 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e}, 613 {0xc78, 0x440c001e}, {0xc78, 0x480d001e}, 614 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e}, 615 {0xc78, 0x5210001e}, {0xc78, 0x5611001e}, 616 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e}, 617 {0xc78, 0x6014001e}, {0xc78, 0x6015001e}, 618 {0xc78, 0x6016001e}, {0xc78, 0x6217001e}, 619 {0xc78, 0x6218001e}, {0xc78, 0x6219001e}, 620 {0xc78, 0x621a001e}, {0xc78, 0x621b001e}, 621 {0xc78, 0x621c001e}, {0xc78, 0x621d001e}, 622 {0xc78, 0x621e001e}, {0xc78, 0x621f001e}, 623 {0xffff, 0xffffffff} 624 }; 625 626 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = { 627 { /* RF_A */ 628 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1, 629 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2, 630 .lssiparm = REG_FPGA0_XA_LSSI_PARM, 631 .hspiread = REG_HSPI_XA_READBACK, 632 .lssiread = REG_FPGA0_XA_LSSI_READBACK, 633 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL, 634 }, 635 { /* RF_B */ 636 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1, 637 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2, 638 .lssiparm = REG_FPGA0_XB_LSSI_PARM, 639 .hspiread = REG_HSPI_XB_READBACK, 640 .lssiread = REG_FPGA0_XB_LSSI_READBACK, 641 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL, 642 }, 643 }; 644 645 const u32 rtl8xxxu_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = { 646 REG_OFDM0_XA_RX_IQ_IMBALANCE, 647 REG_OFDM0_XB_RX_IQ_IMBALANCE, 648 REG_OFDM0_ENERGY_CCA_THRES, 649 REG_OFDM0_AGCR_SSI_TABLE, 650 REG_OFDM0_XA_TX_IQ_IMBALANCE, 651 REG_OFDM0_XB_TX_IQ_IMBALANCE, 652 REG_OFDM0_XC_TX_AFE, 653 REG_OFDM0_XD_TX_AFE, 654 REG_OFDM0_RX_IQ_EXT_ANTA 655 }; 656 657 u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr) 658 { 659 struct usb_device *udev = priv->udev; 660 int len; 661 u8 data; 662 663 mutex_lock(&priv->usb_buf_mutex); 664 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 665 REALTEK_USB_CMD_REQ, REALTEK_USB_READ, 666 addr, 0, &priv->usb_buf.val8, sizeof(u8), 667 RTW_USB_CONTROL_MSG_TIMEOUT); 668 data = priv->usb_buf.val8; 669 mutex_unlock(&priv->usb_buf_mutex); 670 671 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) 672 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n", 673 __func__, addr, data, len); 674 return data; 675 } 676 677 u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr) 678 { 679 struct usb_device *udev = priv->udev; 680 int len; 681 u16 data; 682 683 mutex_lock(&priv->usb_buf_mutex); 684 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 685 REALTEK_USB_CMD_REQ, REALTEK_USB_READ, 686 addr, 0, &priv->usb_buf.val16, sizeof(u16), 687 RTW_USB_CONTROL_MSG_TIMEOUT); 688 data = le16_to_cpu(priv->usb_buf.val16); 689 mutex_unlock(&priv->usb_buf_mutex); 690 691 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) 692 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n", 693 __func__, addr, data, len); 694 return data; 695 } 696 697 u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr) 698 { 699 struct usb_device *udev = priv->udev; 700 int len; 701 u32 data; 702 703 mutex_lock(&priv->usb_buf_mutex); 704 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 705 REALTEK_USB_CMD_REQ, REALTEK_USB_READ, 706 addr, 0, &priv->usb_buf.val32, sizeof(u32), 707 RTW_USB_CONTROL_MSG_TIMEOUT); 708 data = le32_to_cpu(priv->usb_buf.val32); 709 mutex_unlock(&priv->usb_buf_mutex); 710 711 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) 712 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n", 713 __func__, addr, data, len); 714 return data; 715 } 716 717 int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val) 718 { 719 struct usb_device *udev = priv->udev; 720 int ret; 721 722 mutex_lock(&priv->usb_buf_mutex); 723 priv->usb_buf.val8 = val; 724 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 725 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 726 addr, 0, &priv->usb_buf.val8, sizeof(u8), 727 RTW_USB_CONTROL_MSG_TIMEOUT); 728 729 mutex_unlock(&priv->usb_buf_mutex); 730 731 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) 732 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n", 733 __func__, addr, val); 734 return ret; 735 } 736 737 int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val) 738 { 739 struct usb_device *udev = priv->udev; 740 int ret; 741 742 mutex_lock(&priv->usb_buf_mutex); 743 priv->usb_buf.val16 = cpu_to_le16(val); 744 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 745 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 746 addr, 0, &priv->usb_buf.val16, sizeof(u16), 747 RTW_USB_CONTROL_MSG_TIMEOUT); 748 mutex_unlock(&priv->usb_buf_mutex); 749 750 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) 751 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n", 752 __func__, addr, val); 753 return ret; 754 } 755 756 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val) 757 { 758 struct usb_device *udev = priv->udev; 759 int ret; 760 761 mutex_lock(&priv->usb_buf_mutex); 762 priv->usb_buf.val32 = cpu_to_le32(val); 763 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 764 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 765 addr, 0, &priv->usb_buf.val32, sizeof(u32), 766 RTW_USB_CONTROL_MSG_TIMEOUT); 767 mutex_unlock(&priv->usb_buf_mutex); 768 769 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) 770 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n", 771 __func__, addr, val); 772 return ret; 773 } 774 775 static int 776 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len) 777 { 778 struct usb_device *udev = priv->udev; 779 int blocksize = priv->fops->writeN_block_size; 780 int ret, i, count, remainder; 781 782 count = len / blocksize; 783 remainder = len % blocksize; 784 785 for (i = 0; i < count; i++) { 786 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 787 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 788 addr, 0, buf, blocksize, 789 RTW_USB_CONTROL_MSG_TIMEOUT); 790 if (ret != blocksize) 791 goto write_error; 792 793 addr += blocksize; 794 buf += blocksize; 795 } 796 797 if (remainder) { 798 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 799 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 800 addr, 0, buf, remainder, 801 RTW_USB_CONTROL_MSG_TIMEOUT); 802 if (ret != remainder) 803 goto write_error; 804 } 805 806 return len; 807 808 write_error: 809 dev_info(&udev->dev, 810 "%s: Failed to write block at addr: %04x size: %04x\n", 811 __func__, addr, blocksize); 812 return -EAGAIN; 813 } 814 815 u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv, 816 enum rtl8xxxu_rfpath path, u8 reg) 817 { 818 u32 hssia, val32, retval; 819 820 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2); 821 if (path != RF_A) 822 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2); 823 else 824 val32 = hssia; 825 826 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK; 827 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT); 828 val32 |= FPGA0_HSSI_PARM2_EDGE_READ; 829 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ; 830 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); 831 832 udelay(10); 833 834 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32); 835 udelay(100); 836 837 hssia |= FPGA0_HSSI_PARM2_EDGE_READ; 838 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); 839 udelay(10); 840 841 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1); 842 if (val32 & FPGA0_HSSI_PARM1_PI) 843 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread); 844 else 845 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread); 846 847 retval &= 0xfffff; 848 849 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ) 850 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n", 851 __func__, reg, retval); 852 return retval; 853 } 854 855 /* 856 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can 857 * have write issues in high temperature conditions. We may have to 858 * retry writing them. 859 */ 860 int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv, 861 enum rtl8xxxu_rfpath path, u8 reg, u32 data) 862 { 863 int ret, retval; 864 u32 dataaddr, val32; 865 866 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE) 867 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n", 868 __func__, reg, data); 869 870 data &= FPGA0_LSSI_PARM_DATA_MASK; 871 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data; 872 873 if (priv->rtl_chip == RTL8192E) { 874 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 875 val32 &= ~0x20000; 876 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 877 } 878 879 /* Use XB for path B */ 880 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr); 881 if (ret != sizeof(dataaddr)) 882 retval = -EIO; 883 else 884 retval = 0; 885 886 udelay(1); 887 888 if (priv->rtl_chip == RTL8192E) { 889 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 890 val32 |= 0x20000; 891 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 892 } 893 894 return retval; 895 } 896 897 static int 898 rtl8xxxu_gen1_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len) 899 { 900 struct device *dev = &priv->udev->dev; 901 int mbox_nr, retry, retval = 0; 902 int mbox_reg, mbox_ext_reg; 903 u8 val8; 904 905 mutex_lock(&priv->h2c_mutex); 906 907 mbox_nr = priv->next_mbox; 908 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4); 909 mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2); 910 911 /* 912 * MBOX ready? 913 */ 914 retry = 100; 915 do { 916 val8 = rtl8xxxu_read8(priv, REG_HMTFR); 917 if (!(val8 & BIT(mbox_nr))) 918 break; 919 } while (retry--); 920 921 if (!retry) { 922 dev_info(dev, "%s: Mailbox busy\n", __func__); 923 retval = -EBUSY; 924 goto error; 925 } 926 927 /* 928 * Need to swap as it's being swapped again by rtl8xxxu_write16/32() 929 */ 930 if (len > sizeof(u32)) { 931 rtl8xxxu_write16(priv, mbox_ext_reg, le16_to_cpu(h2c->raw.ext)); 932 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 933 dev_info(dev, "H2C_EXT %04x\n", 934 le16_to_cpu(h2c->raw.ext)); 935 } 936 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data)); 937 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 938 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data)); 939 940 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX; 941 942 error: 943 mutex_unlock(&priv->h2c_mutex); 944 return retval; 945 } 946 947 int 948 rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len) 949 { 950 struct device *dev = &priv->udev->dev; 951 int mbox_nr, retry, retval = 0; 952 int mbox_reg, mbox_ext_reg; 953 u8 val8; 954 955 mutex_lock(&priv->h2c_mutex); 956 957 mbox_nr = priv->next_mbox; 958 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4); 959 mbox_ext_reg = REG_HMBOX_EXT0_8723B + (mbox_nr * 4); 960 961 /* 962 * MBOX ready? 963 */ 964 retry = 100; 965 do { 966 val8 = rtl8xxxu_read8(priv, REG_HMTFR); 967 if (!(val8 & BIT(mbox_nr))) 968 break; 969 } while (retry--); 970 971 if (!retry) { 972 dev_info(dev, "%s: Mailbox busy\n", __func__); 973 retval = -EBUSY; 974 goto error; 975 } 976 977 /* 978 * Need to swap as it's being swapped again by rtl8xxxu_write16/32() 979 */ 980 if (len > sizeof(u32)) { 981 rtl8xxxu_write32(priv, mbox_ext_reg, 982 le32_to_cpu(h2c->raw_wide.ext)); 983 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 984 dev_info(dev, "H2C_EXT %08x\n", 985 le32_to_cpu(h2c->raw_wide.ext)); 986 } 987 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data)); 988 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 989 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data)); 990 991 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX; 992 993 error: 994 mutex_unlock(&priv->h2c_mutex); 995 return retval; 996 } 997 998 void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv) 999 { 1000 u8 val8; 1001 u32 val32; 1002 1003 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL); 1004 val8 |= BIT(0) | BIT(3); 1005 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8); 1006 1007 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); 1008 val32 &= ~(BIT(4) | BIT(5)); 1009 val32 |= BIT(3); 1010 if (priv->rf_paths == 2) { 1011 val32 &= ~(BIT(20) | BIT(21)); 1012 val32 |= BIT(19); 1013 } 1014 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); 1015 1016 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1017 val32 &= ~OFDM_RF_PATH_TX_MASK; 1018 if (priv->tx_paths == 2) 1019 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B; 1020 else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C) 1021 val32 |= OFDM_RF_PATH_TX_B; 1022 else 1023 val32 |= OFDM_RF_PATH_TX_A; 1024 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1025 1026 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1027 val32 &= ~FPGA_RF_MODE_JAPAN; 1028 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1029 1030 if (priv->rf_paths == 2) 1031 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0); 1032 else 1033 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0); 1034 1035 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95); 1036 if (priv->rf_paths == 2) 1037 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95); 1038 1039 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); 1040 } 1041 1042 void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv) 1043 { 1044 u8 sps0; 1045 u32 val32; 1046 1047 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL); 1048 1049 /* RF RX code for preamble power saving */ 1050 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); 1051 val32 &= ~(BIT(3) | BIT(4) | BIT(5)); 1052 if (priv->rf_paths == 2) 1053 val32 &= ~(BIT(19) | BIT(20) | BIT(21)); 1054 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); 1055 1056 /* Disable TX for four paths */ 1057 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1058 val32 &= ~OFDM_RF_PATH_TX_MASK; 1059 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1060 1061 /* Enable power saving */ 1062 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1063 val32 |= FPGA_RF_MODE_JAPAN; 1064 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1065 1066 /* AFE control register to power down bits [30:22] */ 1067 if (priv->rf_paths == 2) 1068 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0); 1069 else 1070 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0); 1071 1072 /* Power down RF module */ 1073 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); 1074 if (priv->rf_paths == 2) 1075 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0); 1076 1077 sps0 &= ~(BIT(0) | BIT(3)); 1078 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0); 1079 } 1080 1081 static void rtl8xxxu_stop_tx_beacon(struct rtl8xxxu_priv *priv) 1082 { 1083 u8 val8; 1084 1085 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2); 1086 val8 &= ~BIT(6); 1087 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8); 1088 1089 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64); 1090 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2); 1091 val8 &= ~BIT(0); 1092 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8); 1093 } 1094 1095 1096 /* 1097 * The rtl8723a has 3 channel groups for it's efuse settings. It only 1098 * supports the 2.4GHz band, so channels 1 - 14: 1099 * group 0: channels 1 - 3 1100 * group 1: channels 4 - 9 1101 * group 2: channels 10 - 14 1102 * 1103 * Note: We index from 0 in the code 1104 */ 1105 static int rtl8xxxu_gen1_channel_to_group(int channel) 1106 { 1107 int group; 1108 1109 if (channel < 4) 1110 group = 0; 1111 else if (channel < 10) 1112 group = 1; 1113 else 1114 group = 2; 1115 1116 return group; 1117 } 1118 1119 /* 1120 * Valid for rtl8723bu and rtl8192eu 1121 */ 1122 int rtl8xxxu_gen2_channel_to_group(int channel) 1123 { 1124 int group; 1125 1126 if (channel < 3) 1127 group = 0; 1128 else if (channel < 6) 1129 group = 1; 1130 else if (channel < 9) 1131 group = 2; 1132 else if (channel < 12) 1133 group = 3; 1134 else 1135 group = 4; 1136 1137 return group; 1138 } 1139 1140 void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw) 1141 { 1142 struct rtl8xxxu_priv *priv = hw->priv; 1143 u32 val32, rsr; 1144 u8 val8, opmode; 1145 bool ht = true; 1146 int sec_ch_above, channel; 1147 int i; 1148 1149 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE); 1150 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 1151 channel = hw->conf.chandef.chan->hw_value; 1152 1153 switch (hw->conf.chandef.width) { 1154 case NL80211_CHAN_WIDTH_20_NOHT: 1155 ht = false; 1156 /* fall through */ 1157 case NL80211_CHAN_WIDTH_20: 1158 opmode |= BW_OPMODE_20MHZ; 1159 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); 1160 1161 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1162 val32 &= ~FPGA_RF_MODE; 1163 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1164 1165 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1166 val32 &= ~FPGA_RF_MODE; 1167 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1168 1169 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); 1170 val32 |= FPGA0_ANALOG2_20MHZ; 1171 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); 1172 break; 1173 case NL80211_CHAN_WIDTH_40: 1174 if (hw->conf.chandef.center_freq1 > 1175 hw->conf.chandef.chan->center_freq) { 1176 sec_ch_above = 1; 1177 channel += 2; 1178 } else { 1179 sec_ch_above = 0; 1180 channel -= 2; 1181 } 1182 1183 opmode &= ~BW_OPMODE_20MHZ; 1184 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); 1185 rsr &= ~RSR_RSC_BANDWIDTH_40M; 1186 if (sec_ch_above) 1187 rsr |= RSR_RSC_UPPER_SUB_CHANNEL; 1188 else 1189 rsr |= RSR_RSC_LOWER_SUB_CHANNEL; 1190 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr); 1191 1192 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1193 val32 |= FPGA_RF_MODE; 1194 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1195 1196 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1197 val32 |= FPGA_RF_MODE; 1198 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1199 1200 /* 1201 * Set Control channel to upper or lower. These settings 1202 * are required only for 40MHz 1203 */ 1204 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); 1205 val32 &= ~CCK0_SIDEBAND; 1206 if (!sec_ch_above) 1207 val32 |= CCK0_SIDEBAND; 1208 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); 1209 1210 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 1211 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ 1212 if (sec_ch_above) 1213 val32 |= OFDM_LSTF_PRIME_CH_LOW; 1214 else 1215 val32 |= OFDM_LSTF_PRIME_CH_HIGH; 1216 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 1217 1218 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); 1219 val32 &= ~FPGA0_ANALOG2_20MHZ; 1220 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); 1221 1222 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 1223 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); 1224 if (sec_ch_above) 1225 val32 |= FPGA0_PS_UPPER_CHANNEL; 1226 else 1227 val32 |= FPGA0_PS_LOWER_CHANNEL; 1228 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 1229 break; 1230 1231 default: 1232 break; 1233 } 1234 1235 for (i = RF_A; i < priv->rf_paths; i++) { 1236 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1237 val32 &= ~MODE_AG_CHANNEL_MASK; 1238 val32 |= channel; 1239 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1240 } 1241 1242 if (ht) 1243 val8 = 0x0e; 1244 else 1245 val8 = 0x0a; 1246 1247 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8); 1248 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8); 1249 1250 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808); 1251 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a); 1252 1253 for (i = RF_A; i < priv->rf_paths; i++) { 1254 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1255 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) 1256 val32 &= ~MODE_AG_CHANNEL_20MHZ; 1257 else 1258 val32 |= MODE_AG_CHANNEL_20MHZ; 1259 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1260 } 1261 } 1262 1263 void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw) 1264 { 1265 struct rtl8xxxu_priv *priv = hw->priv; 1266 u32 val32, rsr; 1267 u8 val8, subchannel; 1268 u16 rf_mode_bw; 1269 bool ht = true; 1270 int sec_ch_above, channel; 1271 int i; 1272 1273 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL); 1274 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK; 1275 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 1276 channel = hw->conf.chandef.chan->hw_value; 1277 1278 /* Hack */ 1279 subchannel = 0; 1280 1281 switch (hw->conf.chandef.width) { 1282 case NL80211_CHAN_WIDTH_20_NOHT: 1283 ht = false; 1284 /* fall through */ 1285 case NL80211_CHAN_WIDTH_20: 1286 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20; 1287 subchannel = 0; 1288 1289 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1290 val32 &= ~FPGA_RF_MODE; 1291 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1292 1293 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1294 val32 &= ~FPGA_RF_MODE; 1295 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1296 1297 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); 1298 val32 &= ~(BIT(30) | BIT(31)); 1299 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); 1300 1301 break; 1302 case NL80211_CHAN_WIDTH_40: 1303 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40; 1304 1305 if (hw->conf.chandef.center_freq1 > 1306 hw->conf.chandef.chan->center_freq) { 1307 sec_ch_above = 1; 1308 channel += 2; 1309 } else { 1310 sec_ch_above = 0; 1311 channel -= 2; 1312 } 1313 1314 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1315 val32 |= FPGA_RF_MODE; 1316 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1317 1318 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1319 val32 |= FPGA_RF_MODE; 1320 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1321 1322 /* 1323 * Set Control channel to upper or lower. These settings 1324 * are required only for 40MHz 1325 */ 1326 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); 1327 val32 &= ~CCK0_SIDEBAND; 1328 if (!sec_ch_above) 1329 val32 |= CCK0_SIDEBAND; 1330 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); 1331 1332 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 1333 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ 1334 if (sec_ch_above) 1335 val32 |= OFDM_LSTF_PRIME_CH_LOW; 1336 else 1337 val32 |= OFDM_LSTF_PRIME_CH_HIGH; 1338 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 1339 1340 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 1341 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); 1342 if (sec_ch_above) 1343 val32 |= FPGA0_PS_UPPER_CHANNEL; 1344 else 1345 val32 |= FPGA0_PS_LOWER_CHANNEL; 1346 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 1347 break; 1348 case NL80211_CHAN_WIDTH_80: 1349 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80; 1350 break; 1351 default: 1352 break; 1353 } 1354 1355 for (i = RF_A; i < priv->rf_paths; i++) { 1356 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1357 val32 &= ~MODE_AG_CHANNEL_MASK; 1358 val32 |= channel; 1359 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1360 } 1361 1362 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw); 1363 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel); 1364 1365 if (ht) 1366 val8 = 0x0e; 1367 else 1368 val8 = 0x0a; 1369 1370 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8); 1371 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8); 1372 1373 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808); 1374 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a); 1375 1376 for (i = RF_A; i < priv->rf_paths; i++) { 1377 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1378 val32 &= ~MODE_AG_BW_MASK; 1379 switch(hw->conf.chandef.width) { 1380 case NL80211_CHAN_WIDTH_80: 1381 val32 |= MODE_AG_BW_80MHZ_8723B; 1382 break; 1383 case NL80211_CHAN_WIDTH_40: 1384 val32 |= MODE_AG_BW_40MHZ_8723B; 1385 break; 1386 default: 1387 val32 |= MODE_AG_BW_20MHZ_8723B; 1388 break; 1389 } 1390 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1391 } 1392 } 1393 1394 void 1395 rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) 1396 { 1397 struct rtl8xxxu_power_base *power_base = priv->power_base; 1398 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS]; 1399 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS]; 1400 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b; 1401 u8 val8; 1402 int group, i; 1403 1404 group = rtl8xxxu_gen1_channel_to_group(channel); 1405 1406 cck[0] = priv->cck_tx_power_index_A[group] - 1; 1407 cck[1] = priv->cck_tx_power_index_B[group] - 1; 1408 1409 if (priv->hi_pa) { 1410 if (cck[0] > 0x20) 1411 cck[0] = 0x20; 1412 if (cck[1] > 0x20) 1413 cck[1] = 0x20; 1414 } 1415 1416 ofdm[0] = priv->ht40_1s_tx_power_index_A[group]; 1417 ofdm[1] = priv->ht40_1s_tx_power_index_B[group]; 1418 if (ofdm[0]) 1419 ofdm[0] -= 1; 1420 if (ofdm[1]) 1421 ofdm[1] -= 1; 1422 1423 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a; 1424 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b; 1425 1426 mcsbase[0] = ofdm[0]; 1427 mcsbase[1] = ofdm[1]; 1428 if (!ht40) { 1429 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a; 1430 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b; 1431 } 1432 1433 if (priv->tx_paths > 1) { 1434 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a) 1435 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a; 1436 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b) 1437 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b; 1438 } 1439 1440 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL) 1441 dev_info(&priv->udev->dev, 1442 "%s: Setting TX power CCK A: %02x, " 1443 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n", 1444 __func__, cck[0], cck[1], ofdm[0], ofdm[1]); 1445 1446 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) { 1447 if (cck[i] > RF6052_MAX_TX_PWR) 1448 cck[i] = RF6052_MAX_TX_PWR; 1449 if (ofdm[i] > RF6052_MAX_TX_PWR) 1450 ofdm[i] = RF6052_MAX_TX_PWR; 1451 } 1452 1453 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); 1454 val32 &= 0xffff00ff; 1455 val32 |= (cck[0] << 8); 1456 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); 1457 1458 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); 1459 val32 &= 0xff; 1460 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24)); 1461 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); 1462 1463 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); 1464 val32 &= 0xffffff00; 1465 val32 |= cck[1]; 1466 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); 1467 1468 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32); 1469 val32 &= 0xff; 1470 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24)); 1471 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32); 1472 1473 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 | 1474 ofdmbase[0] << 16 | ofdmbase[0] << 24; 1475 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 | 1476 ofdmbase[1] << 16 | ofdmbase[1] << 24; 1477 1478 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, 1479 ofdm_a + power_base->reg_0e00); 1480 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, 1481 ofdm_b + power_base->reg_0830); 1482 1483 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, 1484 ofdm_a + power_base->reg_0e04); 1485 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, 1486 ofdm_b + power_base->reg_0834); 1487 1488 mcs_a = mcsbase[0] | mcsbase[0] << 8 | 1489 mcsbase[0] << 16 | mcsbase[0] << 24; 1490 mcs_b = mcsbase[1] | mcsbase[1] << 8 | 1491 mcsbase[1] << 16 | mcsbase[1] << 24; 1492 1493 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, 1494 mcs_a + power_base->reg_0e10); 1495 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, 1496 mcs_b + power_base->reg_083c); 1497 1498 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, 1499 mcs_a + power_base->reg_0e14); 1500 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, 1501 mcs_b + power_base->reg_0848); 1502 1503 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, 1504 mcs_a + power_base->reg_0e18); 1505 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, 1506 mcs_b + power_base->reg_084c); 1507 1508 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, 1509 mcs_a + power_base->reg_0e1c); 1510 for (i = 0; i < 3; i++) { 1511 if (i != 2) 1512 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0; 1513 else 1514 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0; 1515 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8); 1516 } 1517 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, 1518 mcs_b + power_base->reg_0868); 1519 for (i = 0; i < 3; i++) { 1520 if (i != 2) 1521 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0; 1522 else 1523 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0; 1524 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8); 1525 } 1526 } 1527 1528 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv, 1529 enum nl80211_iftype linktype) 1530 { 1531 u8 val8; 1532 1533 val8 = rtl8xxxu_read8(priv, REG_MSR); 1534 val8 &= ~MSR_LINKTYPE_MASK; 1535 1536 switch (linktype) { 1537 case NL80211_IFTYPE_UNSPECIFIED: 1538 val8 |= MSR_LINKTYPE_NONE; 1539 break; 1540 case NL80211_IFTYPE_ADHOC: 1541 val8 |= MSR_LINKTYPE_ADHOC; 1542 break; 1543 case NL80211_IFTYPE_STATION: 1544 val8 |= MSR_LINKTYPE_STATION; 1545 break; 1546 case NL80211_IFTYPE_AP: 1547 val8 |= MSR_LINKTYPE_AP; 1548 break; 1549 default: 1550 goto out; 1551 } 1552 1553 rtl8xxxu_write8(priv, REG_MSR, val8); 1554 out: 1555 return; 1556 } 1557 1558 static void 1559 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry) 1560 { 1561 u16 val16; 1562 1563 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) & 1564 RETRY_LIMIT_SHORT_MASK) | 1565 ((long_retry << RETRY_LIMIT_LONG_SHIFT) & 1566 RETRY_LIMIT_LONG_MASK); 1567 1568 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16); 1569 } 1570 1571 static void 1572 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm) 1573 { 1574 u16 val16; 1575 1576 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) | 1577 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK); 1578 1579 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16); 1580 } 1581 1582 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv) 1583 { 1584 struct device *dev = &priv->udev->dev; 1585 char *cut; 1586 1587 switch (priv->chip_cut) { 1588 case 0: 1589 cut = "A"; 1590 break; 1591 case 1: 1592 cut = "B"; 1593 break; 1594 case 2: 1595 cut = "C"; 1596 break; 1597 case 3: 1598 cut = "D"; 1599 break; 1600 case 4: 1601 cut = "E"; 1602 break; 1603 default: 1604 cut = "unknown"; 1605 } 1606 1607 dev_info(dev, 1608 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n", 1609 priv->chip_name, cut, priv->chip_vendor, priv->tx_paths, 1610 priv->rx_paths, priv->ep_tx_count, priv->has_wifi, 1611 priv->has_bluetooth, priv->has_gps, priv->hi_pa); 1612 1613 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr); 1614 } 1615 1616 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv) 1617 { 1618 struct device *dev = &priv->udev->dev; 1619 u32 val32, bonding; 1620 u16 val16; 1621 1622 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG); 1623 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >> 1624 SYS_CFG_CHIP_VERSION_SHIFT; 1625 if (val32 & SYS_CFG_TRP_VAUX_EN) { 1626 dev_info(dev, "Unsupported test chip\n"); 1627 return -ENOTSUPP; 1628 } 1629 1630 if (val32 & SYS_CFG_BT_FUNC) { 1631 if (priv->chip_cut >= 3) { 1632 sprintf(priv->chip_name, "8723BU"); 1633 priv->rtl_chip = RTL8723B; 1634 } else { 1635 sprintf(priv->chip_name, "8723AU"); 1636 priv->usb_interrupts = 1; 1637 priv->rtl_chip = RTL8723A; 1638 } 1639 1640 priv->rf_paths = 1; 1641 priv->rx_paths = 1; 1642 priv->tx_paths = 1; 1643 1644 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); 1645 if (val32 & MULTI_WIFI_FUNC_EN) 1646 priv->has_wifi = 1; 1647 if (val32 & MULTI_BT_FUNC_EN) 1648 priv->has_bluetooth = 1; 1649 if (val32 & MULTI_GPS_FUNC_EN) 1650 priv->has_gps = 1; 1651 priv->is_multi_func = 1; 1652 } else if (val32 & SYS_CFG_TYPE_ID) { 1653 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM); 1654 bonding &= HPON_FSM_BONDING_MASK; 1655 if (priv->fops->tx_desc_size == 1656 sizeof(struct rtl8xxxu_txdesc40)) { 1657 if (bonding == HPON_FSM_BONDING_1T2R) { 1658 sprintf(priv->chip_name, "8191EU"); 1659 priv->rf_paths = 2; 1660 priv->rx_paths = 2; 1661 priv->tx_paths = 1; 1662 priv->rtl_chip = RTL8191E; 1663 } else { 1664 sprintf(priv->chip_name, "8192EU"); 1665 priv->rf_paths = 2; 1666 priv->rx_paths = 2; 1667 priv->tx_paths = 2; 1668 priv->rtl_chip = RTL8192E; 1669 } 1670 } else if (bonding == HPON_FSM_BONDING_1T2R) { 1671 sprintf(priv->chip_name, "8191CU"); 1672 priv->rf_paths = 2; 1673 priv->rx_paths = 2; 1674 priv->tx_paths = 1; 1675 priv->usb_interrupts = 1; 1676 priv->rtl_chip = RTL8191C; 1677 } else { 1678 sprintf(priv->chip_name, "8192CU"); 1679 priv->rf_paths = 2; 1680 priv->rx_paths = 2; 1681 priv->tx_paths = 2; 1682 priv->usb_interrupts = 1; 1683 priv->rtl_chip = RTL8192C; 1684 } 1685 priv->has_wifi = 1; 1686 } else { 1687 sprintf(priv->chip_name, "8188CU"); 1688 priv->rf_paths = 1; 1689 priv->rx_paths = 1; 1690 priv->tx_paths = 1; 1691 priv->rtl_chip = RTL8188C; 1692 priv->usb_interrupts = 1; 1693 priv->has_wifi = 1; 1694 } 1695 1696 switch (priv->rtl_chip) { 1697 case RTL8188E: 1698 case RTL8192E: 1699 case RTL8723B: 1700 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) { 1701 case SYS_CFG_VENDOR_ID_TSMC: 1702 sprintf(priv->chip_vendor, "TSMC"); 1703 break; 1704 case SYS_CFG_VENDOR_ID_SMIC: 1705 sprintf(priv->chip_vendor, "SMIC"); 1706 priv->vendor_smic = 1; 1707 break; 1708 case SYS_CFG_VENDOR_ID_UMC: 1709 sprintf(priv->chip_vendor, "UMC"); 1710 priv->vendor_umc = 1; 1711 break; 1712 default: 1713 sprintf(priv->chip_vendor, "unknown"); 1714 } 1715 break; 1716 default: 1717 if (val32 & SYS_CFG_VENDOR_ID) { 1718 sprintf(priv->chip_vendor, "UMC"); 1719 priv->vendor_umc = 1; 1720 } else { 1721 sprintf(priv->chip_vendor, "TSMC"); 1722 } 1723 } 1724 1725 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); 1726 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28; 1727 1728 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX); 1729 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) { 1730 priv->ep_tx_high_queue = 1; 1731 priv->ep_tx_count++; 1732 } 1733 1734 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) { 1735 priv->ep_tx_normal_queue = 1; 1736 priv->ep_tx_count++; 1737 } 1738 1739 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) { 1740 priv->ep_tx_low_queue = 1; 1741 priv->ep_tx_count++; 1742 } 1743 1744 /* 1745 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX 1746 */ 1747 if (!priv->ep_tx_count) { 1748 switch (priv->nr_out_eps) { 1749 case 4: 1750 case 3: 1751 priv->ep_tx_low_queue = 1; 1752 priv->ep_tx_count++; 1753 /* fall through */ 1754 case 2: 1755 priv->ep_tx_normal_queue = 1; 1756 priv->ep_tx_count++; 1757 /* fall through */ 1758 case 1: 1759 priv->ep_tx_high_queue = 1; 1760 priv->ep_tx_count++; 1761 break; 1762 default: 1763 dev_info(dev, "Unsupported USB TX end-points\n"); 1764 return -ENOTSUPP; 1765 } 1766 } 1767 1768 return 0; 1769 } 1770 1771 static int 1772 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data) 1773 { 1774 int i; 1775 u8 val8; 1776 u32 val32; 1777 1778 /* Write Address */ 1779 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff); 1780 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2); 1781 val8 &= 0xfc; 1782 val8 |= (offset >> 8) & 0x03; 1783 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8); 1784 1785 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3); 1786 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f); 1787 1788 /* Poll for data read */ 1789 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); 1790 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) { 1791 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); 1792 if (val32 & BIT(31)) 1793 break; 1794 } 1795 1796 if (i == RTL8XXXU_MAX_REG_POLL) 1797 return -EIO; 1798 1799 udelay(50); 1800 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); 1801 1802 *data = val32 & 0xff; 1803 return 0; 1804 } 1805 1806 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv) 1807 { 1808 struct device *dev = &priv->udev->dev; 1809 int i, ret = 0; 1810 u8 val8, word_mask, header, extheader; 1811 u16 val16, efuse_addr, offset; 1812 u32 val32; 1813 1814 val16 = rtl8xxxu_read16(priv, REG_9346CR); 1815 if (val16 & EEPROM_ENABLE) 1816 priv->has_eeprom = 1; 1817 if (val16 & EEPROM_BOOT) 1818 priv->boot_eeprom = 1; 1819 1820 if (priv->is_multi_func) { 1821 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST); 1822 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT; 1823 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32); 1824 } 1825 1826 dev_dbg(dev, "Booting from %s\n", 1827 priv->boot_eeprom ? "EEPROM" : "EFUSE"); 1828 1829 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE); 1830 1831 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */ 1832 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL); 1833 if (!(val16 & SYS_ISO_PWC_EV12V)) { 1834 val16 |= SYS_ISO_PWC_EV12V; 1835 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16); 1836 } 1837 /* Reset: 0x0000[28], default valid */ 1838 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1839 if (!(val16 & SYS_FUNC_ELDR)) { 1840 val16 |= SYS_FUNC_ELDR; 1841 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 1842 } 1843 1844 /* 1845 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid 1846 */ 1847 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR); 1848 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) { 1849 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M); 1850 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16); 1851 } 1852 1853 /* Default value is 0xff */ 1854 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN); 1855 1856 efuse_addr = 0; 1857 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) { 1858 u16 map_addr; 1859 1860 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header); 1861 if (ret || header == 0xff) 1862 goto exit; 1863 1864 if ((header & 0x1f) == 0x0f) { /* extended header */ 1865 offset = (header & 0xe0) >> 5; 1866 1867 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, 1868 &extheader); 1869 if (ret) 1870 goto exit; 1871 /* All words disabled */ 1872 if ((extheader & 0x0f) == 0x0f) 1873 continue; 1874 1875 offset |= ((extheader & 0xf0) >> 1); 1876 word_mask = extheader & 0x0f; 1877 } else { 1878 offset = (header >> 4) & 0x0f; 1879 word_mask = header & 0x0f; 1880 } 1881 1882 /* Get word enable value from PG header */ 1883 1884 /* We have 8 bits to indicate validity */ 1885 map_addr = offset * 8; 1886 if (map_addr >= EFUSE_MAP_LEN) { 1887 dev_warn(dev, "%s: Illegal map_addr (%04x), " 1888 "efuse corrupt!\n", 1889 __func__, map_addr); 1890 ret = -EINVAL; 1891 goto exit; 1892 } 1893 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { 1894 /* Check word enable condition in the section */ 1895 if (word_mask & BIT(i)) { 1896 map_addr += 2; 1897 continue; 1898 } 1899 1900 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8); 1901 if (ret) 1902 goto exit; 1903 priv->efuse_wifi.raw[map_addr++] = val8; 1904 1905 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8); 1906 if (ret) 1907 goto exit; 1908 priv->efuse_wifi.raw[map_addr++] = val8; 1909 } 1910 } 1911 1912 exit: 1913 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE); 1914 1915 return ret; 1916 } 1917 1918 void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv) 1919 { 1920 u8 val8; 1921 u16 sys_func; 1922 1923 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 1924 val8 &= ~BIT(0); 1925 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 1926 1927 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1928 sys_func &= ~SYS_FUNC_CPU_ENABLE; 1929 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); 1930 1931 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 1932 val8 |= BIT(0); 1933 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 1934 1935 sys_func |= SYS_FUNC_CPU_ENABLE; 1936 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); 1937 } 1938 1939 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv) 1940 { 1941 struct device *dev = &priv->udev->dev; 1942 int ret = 0, i; 1943 u32 val32; 1944 1945 /* Poll checksum report */ 1946 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) { 1947 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); 1948 if (val32 & MCU_FW_DL_CSUM_REPORT) 1949 break; 1950 } 1951 1952 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) { 1953 dev_warn(dev, "Firmware checksum poll timed out\n"); 1954 ret = -EAGAIN; 1955 goto exit; 1956 } 1957 1958 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); 1959 val32 |= MCU_FW_DL_READY; 1960 val32 &= ~MCU_WINT_INIT_READY; 1961 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32); 1962 1963 /* 1964 * Reset the 8051 in order for the firmware to start running, 1965 * otherwise it won't come up on the 8192eu 1966 */ 1967 priv->fops->reset_8051(priv); 1968 1969 /* Wait for firmware to become ready */ 1970 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) { 1971 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); 1972 if (val32 & MCU_WINT_INIT_READY) 1973 break; 1974 1975 udelay(100); 1976 } 1977 1978 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) { 1979 dev_warn(dev, "Firmware failed to start\n"); 1980 ret = -EAGAIN; 1981 goto exit; 1982 } 1983 1984 /* 1985 * Init H2C command 1986 */ 1987 if (priv->rtl_chip == RTL8723B) 1988 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f); 1989 exit: 1990 return ret; 1991 } 1992 1993 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv) 1994 { 1995 int pages, remainder, i, ret; 1996 u8 val8; 1997 u16 val16; 1998 u32 val32; 1999 u8 *fwptr; 2000 2001 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1); 2002 val8 |= 4; 2003 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8); 2004 2005 /* 8051 enable */ 2006 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2007 val16 |= SYS_FUNC_CPU_ENABLE; 2008 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 2009 2010 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL); 2011 if (val8 & MCU_FW_RAM_SEL) { 2012 pr_info("do the RAM reset\n"); 2013 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); 2014 priv->fops->reset_8051(priv); 2015 } 2016 2017 /* MCU firmware download enable */ 2018 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL); 2019 val8 |= MCU_FW_DL_ENABLE; 2020 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8); 2021 2022 /* 8051 reset */ 2023 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); 2024 val32 &= ~BIT(19); 2025 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32); 2026 2027 /* Reset firmware download checksum */ 2028 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL); 2029 val8 |= MCU_FW_DL_CSUM_REPORT; 2030 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8); 2031 2032 pages = priv->fw_size / RTL_FW_PAGE_SIZE; 2033 remainder = priv->fw_size % RTL_FW_PAGE_SIZE; 2034 2035 fwptr = priv->fw_data->data; 2036 2037 for (i = 0; i < pages; i++) { 2038 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8; 2039 val8 |= i; 2040 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8); 2041 2042 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS, 2043 fwptr, RTL_FW_PAGE_SIZE); 2044 if (ret != RTL_FW_PAGE_SIZE) { 2045 ret = -EAGAIN; 2046 goto fw_abort; 2047 } 2048 2049 fwptr += RTL_FW_PAGE_SIZE; 2050 } 2051 2052 if (remainder) { 2053 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8; 2054 val8 |= i; 2055 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8); 2056 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS, 2057 fwptr, remainder); 2058 if (ret != remainder) { 2059 ret = -EAGAIN; 2060 goto fw_abort; 2061 } 2062 } 2063 2064 ret = 0; 2065 fw_abort: 2066 /* MCU firmware download disable */ 2067 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL); 2068 val16 &= ~MCU_FW_DL_ENABLE; 2069 rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16); 2070 2071 return ret; 2072 } 2073 2074 int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name) 2075 { 2076 struct device *dev = &priv->udev->dev; 2077 const struct firmware *fw; 2078 int ret = 0; 2079 u16 signature; 2080 2081 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name); 2082 if (request_firmware(&fw, fw_name, &priv->udev->dev)) { 2083 dev_warn(dev, "request_firmware(%s) failed\n", fw_name); 2084 ret = -EAGAIN; 2085 goto exit; 2086 } 2087 if (!fw) { 2088 dev_warn(dev, "Firmware data not available\n"); 2089 ret = -EINVAL; 2090 goto exit; 2091 } 2092 2093 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL); 2094 if (!priv->fw_data) { 2095 ret = -ENOMEM; 2096 goto exit; 2097 } 2098 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header); 2099 2100 signature = le16_to_cpu(priv->fw_data->signature); 2101 switch (signature & 0xfff0) { 2102 case 0x92e0: 2103 case 0x92c0: 2104 case 0x88c0: 2105 case 0x5300: 2106 case 0x2300: 2107 break; 2108 default: 2109 ret = -EINVAL; 2110 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n", 2111 __func__, signature); 2112 } 2113 2114 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n", 2115 le16_to_cpu(priv->fw_data->major_version), 2116 priv->fw_data->minor_version, signature); 2117 2118 exit: 2119 release_firmware(fw); 2120 return ret; 2121 } 2122 2123 void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv) 2124 { 2125 u16 val16; 2126 int i = 100; 2127 2128 /* Inform 8051 to perform reset */ 2129 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20); 2130 2131 for (i = 100; i > 0; i--) { 2132 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2133 2134 if (!(val16 & SYS_FUNC_CPU_ENABLE)) { 2135 dev_dbg(&priv->udev->dev, 2136 "%s: Firmware self reset success!\n", __func__); 2137 break; 2138 } 2139 udelay(50); 2140 } 2141 2142 if (!i) { 2143 /* Force firmware reset */ 2144 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2145 val16 &= ~SYS_FUNC_CPU_ENABLE; 2146 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 2147 } 2148 } 2149 2150 static int 2151 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv) 2152 { 2153 struct rtl8xxxu_reg8val *array = priv->fops->mactable; 2154 int i, ret; 2155 u16 reg; 2156 u8 val; 2157 2158 for (i = 0; ; i++) { 2159 reg = array[i].reg; 2160 val = array[i].val; 2161 2162 if (reg == 0xffff && val == 0xff) 2163 break; 2164 2165 ret = rtl8xxxu_write8(priv, reg, val); 2166 if (ret != 1) { 2167 dev_warn(&priv->udev->dev, 2168 "Failed to initialize MAC " 2169 "(reg: %04x, val %02x)\n", reg, val); 2170 return -EAGAIN; 2171 } 2172 } 2173 2174 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E) 2175 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a); 2176 2177 return 0; 2178 } 2179 2180 int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv, 2181 struct rtl8xxxu_reg32val *array) 2182 { 2183 int i, ret; 2184 u16 reg; 2185 u32 val; 2186 2187 for (i = 0; ; i++) { 2188 reg = array[i].reg; 2189 val = array[i].val; 2190 2191 if (reg == 0xffff && val == 0xffffffff) 2192 break; 2193 2194 ret = rtl8xxxu_write32(priv, reg, val); 2195 if (ret != sizeof(val)) { 2196 dev_warn(&priv->udev->dev, 2197 "Failed to initialize PHY\n"); 2198 return -EAGAIN; 2199 } 2200 udelay(1); 2201 } 2202 2203 return 0; 2204 } 2205 2206 void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv) 2207 { 2208 u8 val8, ldoa15, ldov12d, lpldo, ldohci12; 2209 u16 val16; 2210 u32 val32; 2211 2212 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); 2213 udelay(2); 2214 val8 |= AFE_PLL_320_ENABLE; 2215 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); 2216 udelay(2); 2217 2218 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff); 2219 udelay(2); 2220 2221 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2222 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB; 2223 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 2224 2225 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); 2226 val32 &= ~AFE_XTAL_RF_GATE; 2227 if (priv->has_bluetooth) 2228 val32 &= ~AFE_XTAL_BT_GATE; 2229 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); 2230 2231 /* 6. 0x1f[7:0] = 0x07 */ 2232 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; 2233 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); 2234 2235 if (priv->hi_pa) 2236 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table); 2237 else if (priv->tx_paths == 2) 2238 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table); 2239 else 2240 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table); 2241 2242 if (priv->rtl_chip == RTL8188R && priv->hi_pa && 2243 priv->vendor_umc && priv->chip_cut == 1) 2244 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50); 2245 2246 if (priv->hi_pa) 2247 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table); 2248 else 2249 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table); 2250 2251 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF; 2252 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT); 2253 ldohci12 = 0x57; 2254 lpldo = 1; 2255 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15; 2256 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32); 2257 } 2258 2259 /* 2260 * Most of this is black magic retrieved from the old rtl8723au driver 2261 */ 2262 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv) 2263 { 2264 u8 val8; 2265 u32 val32; 2266 2267 priv->fops->init_phy_bb(priv); 2268 2269 if (priv->tx_paths == 1 && priv->rx_paths == 2) { 2270 /* 2271 * For 1T2R boards, patch the registers. 2272 * 2273 * It looks like 8191/2 1T2R boards use path B for TX 2274 */ 2275 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO); 2276 val32 &= ~(BIT(0) | BIT(1)); 2277 val32 |= BIT(1); 2278 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32); 2279 2280 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO); 2281 val32 &= ~0x300033; 2282 val32 |= 0x200022; 2283 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32); 2284 2285 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); 2286 val32 &= ~CCK0_AFE_RX_MASK; 2287 val32 &= 0x00ffffff; 2288 val32 |= 0x40000000; 2289 val32 |= CCK0_AFE_RX_ANT_B; 2290 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); 2291 2292 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 2293 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); 2294 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B | 2295 OFDM_RF_PATH_TX_B); 2296 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 2297 2298 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1); 2299 val32 &= ~(BIT(4) | BIT(5)); 2300 val32 |= BIT(4); 2301 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32); 2302 2303 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON); 2304 val32 &= ~(BIT(27) | BIT(26)); 2305 val32 |= BIT(27); 2306 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32); 2307 2308 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON); 2309 val32 &= ~(BIT(27) | BIT(26)); 2310 val32 |= BIT(27); 2311 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32); 2312 2313 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON); 2314 val32 &= ~(BIT(27) | BIT(26)); 2315 val32 |= BIT(27); 2316 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32); 2317 2318 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON); 2319 val32 &= ~(BIT(27) | BIT(26)); 2320 val32 |= BIT(27); 2321 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32); 2322 2323 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX); 2324 val32 &= ~(BIT(27) | BIT(26)); 2325 val32 |= BIT(27); 2326 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32); 2327 } 2328 2329 if (priv->has_xtalk) { 2330 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL); 2331 2332 val8 = priv->xtalk; 2333 val32 &= 0xff000fff; 2334 val32 |= ((val8 | (val8 << 6)) << 12); 2335 2336 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32); 2337 } 2338 2339 if (priv->rtl_chip == RTL8192E) 2340 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x000f81fb); 2341 2342 return 0; 2343 } 2344 2345 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv, 2346 struct rtl8xxxu_rfregval *array, 2347 enum rtl8xxxu_rfpath path) 2348 { 2349 int i, ret; 2350 u8 reg; 2351 u32 val; 2352 2353 for (i = 0; ; i++) { 2354 reg = array[i].reg; 2355 val = array[i].val; 2356 2357 if (reg == 0xff && val == 0xffffffff) 2358 break; 2359 2360 switch (reg) { 2361 case 0xfe: 2362 msleep(50); 2363 continue; 2364 case 0xfd: 2365 mdelay(5); 2366 continue; 2367 case 0xfc: 2368 mdelay(1); 2369 continue; 2370 case 0xfb: 2371 udelay(50); 2372 continue; 2373 case 0xfa: 2374 udelay(5); 2375 continue; 2376 case 0xf9: 2377 udelay(1); 2378 continue; 2379 } 2380 2381 ret = rtl8xxxu_write_rfreg(priv, path, reg, val); 2382 if (ret) { 2383 dev_warn(&priv->udev->dev, 2384 "Failed to initialize RF\n"); 2385 return -EAGAIN; 2386 } 2387 udelay(1); 2388 } 2389 2390 return 0; 2391 } 2392 2393 int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv, 2394 struct rtl8xxxu_rfregval *table, 2395 enum rtl8xxxu_rfpath path) 2396 { 2397 u32 val32; 2398 u16 val16, rfsi_rfenv; 2399 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2; 2400 2401 switch (path) { 2402 case RF_A: 2403 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL; 2404 reg_int_oe = REG_FPGA0_XA_RF_INT_OE; 2405 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2; 2406 break; 2407 case RF_B: 2408 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL; 2409 reg_int_oe = REG_FPGA0_XB_RF_INT_OE; 2410 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2; 2411 break; 2412 default: 2413 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n", 2414 __func__, path + 'A'); 2415 return -EINVAL; 2416 } 2417 /* For path B, use XB */ 2418 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl); 2419 rfsi_rfenv &= FPGA0_RF_RFENV; 2420 2421 /* 2422 * These two we might be able to optimize into one 2423 */ 2424 val32 = rtl8xxxu_read32(priv, reg_int_oe); 2425 val32 |= BIT(20); /* 0x10 << 16 */ 2426 rtl8xxxu_write32(priv, reg_int_oe, val32); 2427 udelay(1); 2428 2429 val32 = rtl8xxxu_read32(priv, reg_int_oe); 2430 val32 |= BIT(4); 2431 rtl8xxxu_write32(priv, reg_int_oe, val32); 2432 udelay(1); 2433 2434 /* 2435 * These two we might be able to optimize into one 2436 */ 2437 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); 2438 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN; 2439 rtl8xxxu_write32(priv, reg_hssi_parm2, val32); 2440 udelay(1); 2441 2442 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); 2443 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN; 2444 rtl8xxxu_write32(priv, reg_hssi_parm2, val32); 2445 udelay(1); 2446 2447 rtl8xxxu_init_rf_regs(priv, table, path); 2448 2449 /* For path B, use XB */ 2450 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl); 2451 val16 &= ~FPGA0_RF_RFENV; 2452 val16 |= rfsi_rfenv; 2453 rtl8xxxu_write16(priv, reg_sw_ctrl, val16); 2454 2455 return 0; 2456 } 2457 2458 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data) 2459 { 2460 int ret = -EBUSY; 2461 int count = 0; 2462 u32 value; 2463 2464 value = LLT_OP_WRITE | address << 8 | data; 2465 2466 rtl8xxxu_write32(priv, REG_LLT_INIT, value); 2467 2468 do { 2469 value = rtl8xxxu_read32(priv, REG_LLT_INIT); 2470 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) { 2471 ret = 0; 2472 break; 2473 } 2474 } while (count++ < 20); 2475 2476 return ret; 2477 } 2478 2479 int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv) 2480 { 2481 int ret; 2482 int i; 2483 u8 last_tx_page; 2484 2485 last_tx_page = priv->fops->total_page_num; 2486 2487 for (i = 0; i < last_tx_page; i++) { 2488 ret = rtl8xxxu_llt_write(priv, i, i + 1); 2489 if (ret) 2490 goto exit; 2491 } 2492 2493 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff); 2494 if (ret) 2495 goto exit; 2496 2497 /* Mark remaining pages as a ring buffer */ 2498 for (i = last_tx_page + 1; i < 0xff; i++) { 2499 ret = rtl8xxxu_llt_write(priv, i, (i + 1)); 2500 if (ret) 2501 goto exit; 2502 } 2503 2504 /* Let last entry point to the start entry of ring buffer */ 2505 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1); 2506 if (ret) 2507 goto exit; 2508 2509 exit: 2510 return ret; 2511 } 2512 2513 int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv) 2514 { 2515 u32 val32; 2516 int ret = 0; 2517 int i; 2518 2519 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT); 2520 val32 |= AUTO_LLT_INIT_LLT; 2521 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32); 2522 2523 for (i = 500; i; i--) { 2524 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT); 2525 if (!(val32 & AUTO_LLT_INIT_LLT)) 2526 break; 2527 usleep_range(2, 4); 2528 } 2529 2530 if (!i) { 2531 ret = -EBUSY; 2532 dev_warn(&priv->udev->dev, "LLT table init failed\n"); 2533 } 2534 2535 return ret; 2536 } 2537 2538 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv) 2539 { 2540 u16 val16, hi, lo; 2541 u16 hiq, mgq, bkq, beq, viq, voq; 2542 int hip, mgp, bkp, bep, vip, vop; 2543 int ret = 0; 2544 2545 switch (priv->ep_tx_count) { 2546 case 1: 2547 if (priv->ep_tx_high_queue) { 2548 hi = TRXDMA_QUEUE_HIGH; 2549 } else if (priv->ep_tx_low_queue) { 2550 hi = TRXDMA_QUEUE_LOW; 2551 } else if (priv->ep_tx_normal_queue) { 2552 hi = TRXDMA_QUEUE_NORMAL; 2553 } else { 2554 hi = 0; 2555 ret = -EINVAL; 2556 } 2557 2558 hiq = hi; 2559 mgq = hi; 2560 bkq = hi; 2561 beq = hi; 2562 viq = hi; 2563 voq = hi; 2564 2565 hip = 0; 2566 mgp = 0; 2567 bkp = 0; 2568 bep = 0; 2569 vip = 0; 2570 vop = 0; 2571 break; 2572 case 2: 2573 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) { 2574 hi = TRXDMA_QUEUE_HIGH; 2575 lo = TRXDMA_QUEUE_LOW; 2576 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) { 2577 hi = TRXDMA_QUEUE_NORMAL; 2578 lo = TRXDMA_QUEUE_LOW; 2579 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) { 2580 hi = TRXDMA_QUEUE_HIGH; 2581 lo = TRXDMA_QUEUE_NORMAL; 2582 } else { 2583 ret = -EINVAL; 2584 hi = 0; 2585 lo = 0; 2586 } 2587 2588 hiq = hi; 2589 mgq = hi; 2590 bkq = lo; 2591 beq = lo; 2592 viq = hi; 2593 voq = hi; 2594 2595 hip = 0; 2596 mgp = 0; 2597 bkp = 1; 2598 bep = 1; 2599 vip = 0; 2600 vop = 0; 2601 break; 2602 case 3: 2603 beq = TRXDMA_QUEUE_LOW; 2604 bkq = TRXDMA_QUEUE_LOW; 2605 viq = TRXDMA_QUEUE_NORMAL; 2606 voq = TRXDMA_QUEUE_HIGH; 2607 mgq = TRXDMA_QUEUE_HIGH; 2608 hiq = TRXDMA_QUEUE_HIGH; 2609 2610 hip = hiq ^ 3; 2611 mgp = mgq ^ 3; 2612 bkp = bkq ^ 3; 2613 bep = beq ^ 3; 2614 vip = viq ^ 3; 2615 vop = viq ^ 3; 2616 break; 2617 default: 2618 ret = -EINVAL; 2619 } 2620 2621 /* 2622 * None of the vendor drivers are configuring the beacon 2623 * queue here .... why? 2624 */ 2625 if (!ret) { 2626 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL); 2627 val16 &= 0x7; 2628 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) | 2629 (viq << TRXDMA_CTRL_VIQ_SHIFT) | 2630 (beq << TRXDMA_CTRL_BEQ_SHIFT) | 2631 (bkq << TRXDMA_CTRL_BKQ_SHIFT) | 2632 (mgq << TRXDMA_CTRL_MGQ_SHIFT) | 2633 (hiq << TRXDMA_CTRL_HIQ_SHIFT); 2634 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16); 2635 2636 priv->pipe_out[TXDESC_QUEUE_VO] = 2637 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]); 2638 priv->pipe_out[TXDESC_QUEUE_VI] = 2639 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]); 2640 priv->pipe_out[TXDESC_QUEUE_BE] = 2641 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]); 2642 priv->pipe_out[TXDESC_QUEUE_BK] = 2643 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]); 2644 priv->pipe_out[TXDESC_QUEUE_BEACON] = 2645 usb_sndbulkpipe(priv->udev, priv->out_ep[0]); 2646 priv->pipe_out[TXDESC_QUEUE_MGNT] = 2647 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]); 2648 priv->pipe_out[TXDESC_QUEUE_HIGH] = 2649 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]); 2650 priv->pipe_out[TXDESC_QUEUE_CMD] = 2651 usb_sndbulkpipe(priv->udev, priv->out_ep[0]); 2652 } 2653 2654 return ret; 2655 } 2656 2657 void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok, 2658 int result[][8], int candidate, bool tx_only) 2659 { 2660 u32 oldval, x, tx0_a, reg; 2661 int y, tx0_c; 2662 u32 val32; 2663 2664 if (!iqk_ok) 2665 return; 2666 2667 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); 2668 oldval = val32 >> 22; 2669 2670 x = result[candidate][0]; 2671 if ((x & 0x00000200) != 0) 2672 x = x | 0xfffffc00; 2673 tx0_a = (x * oldval) >> 8; 2674 2675 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); 2676 val32 &= ~0x3ff; 2677 val32 |= tx0_a; 2678 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); 2679 2680 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2681 val32 &= ~BIT(31); 2682 if ((x * oldval >> 7) & 0x1) 2683 val32 |= BIT(31); 2684 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2685 2686 y = result[candidate][1]; 2687 if ((y & 0x00000200) != 0) 2688 y = y | 0xfffffc00; 2689 tx0_c = (y * oldval) >> 8; 2690 2691 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE); 2692 val32 &= ~0xf0000000; 2693 val32 |= (((tx0_c & 0x3c0) >> 6) << 28); 2694 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32); 2695 2696 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); 2697 val32 &= ~0x003f0000; 2698 val32 |= ((tx0_c & 0x3f) << 16); 2699 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); 2700 2701 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2702 val32 &= ~BIT(29); 2703 if ((y * oldval >> 7) & 0x1) 2704 val32 |= BIT(29); 2705 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2706 2707 if (tx_only) { 2708 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__); 2709 return; 2710 } 2711 2712 reg = result[candidate][2]; 2713 2714 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); 2715 val32 &= ~0x3ff; 2716 val32 |= (reg & 0x3ff); 2717 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); 2718 2719 reg = result[candidate][3] & 0x3F; 2720 2721 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); 2722 val32 &= ~0xfc00; 2723 val32 |= ((reg << 10) & 0xfc00); 2724 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); 2725 2726 reg = (result[candidate][3] >> 6) & 0xF; 2727 2728 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA); 2729 val32 &= ~0xf0000000; 2730 val32 |= (reg << 28); 2731 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32); 2732 } 2733 2734 void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok, 2735 int result[][8], int candidate, bool tx_only) 2736 { 2737 u32 oldval, x, tx1_a, reg; 2738 int y, tx1_c; 2739 u32 val32; 2740 2741 if (!iqk_ok) 2742 return; 2743 2744 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); 2745 oldval = val32 >> 22; 2746 2747 x = result[candidate][4]; 2748 if ((x & 0x00000200) != 0) 2749 x = x | 0xfffffc00; 2750 tx1_a = (x * oldval) >> 8; 2751 2752 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); 2753 val32 &= ~0x3ff; 2754 val32 |= tx1_a; 2755 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); 2756 2757 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2758 val32 &= ~BIT(27); 2759 if ((x * oldval >> 7) & 0x1) 2760 val32 |= BIT(27); 2761 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2762 2763 y = result[candidate][5]; 2764 if ((y & 0x00000200) != 0) 2765 y = y | 0xfffffc00; 2766 tx1_c = (y * oldval) >> 8; 2767 2768 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE); 2769 val32 &= ~0xf0000000; 2770 val32 |= (((tx1_c & 0x3c0) >> 6) << 28); 2771 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32); 2772 2773 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); 2774 val32 &= ~0x003f0000; 2775 val32 |= ((tx1_c & 0x3f) << 16); 2776 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); 2777 2778 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2779 val32 &= ~BIT(25); 2780 if ((y * oldval >> 7) & 0x1) 2781 val32 |= BIT(25); 2782 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2783 2784 if (tx_only) { 2785 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__); 2786 return; 2787 } 2788 2789 reg = result[candidate][6]; 2790 2791 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); 2792 val32 &= ~0x3ff; 2793 val32 |= (reg & 0x3ff); 2794 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); 2795 2796 reg = result[candidate][7] & 0x3f; 2797 2798 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); 2799 val32 &= ~0xfc00; 2800 val32 |= ((reg << 10) & 0xfc00); 2801 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); 2802 2803 reg = (result[candidate][7] >> 6) & 0xf; 2804 2805 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE); 2806 val32 &= ~0x0000f000; 2807 val32 |= (reg << 12); 2808 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32); 2809 } 2810 2811 #define MAX_TOLERANCE 5 2812 2813 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv, 2814 int result[][8], int c1, int c2) 2815 { 2816 u32 i, j, diff, simubitmap, bound = 0; 2817 int candidate[2] = {-1, -1}; /* for path A and path B */ 2818 bool retval = true; 2819 2820 if (priv->tx_paths > 1) 2821 bound = 8; 2822 else 2823 bound = 4; 2824 2825 simubitmap = 0; 2826 2827 for (i = 0; i < bound; i++) { 2828 diff = (result[c1][i] > result[c2][i]) ? 2829 (result[c1][i] - result[c2][i]) : 2830 (result[c2][i] - result[c1][i]); 2831 if (diff > MAX_TOLERANCE) { 2832 if ((i == 2 || i == 6) && !simubitmap) { 2833 if (result[c1][i] + result[c1][i + 1] == 0) 2834 candidate[(i / 4)] = c2; 2835 else if (result[c2][i] + result[c2][i + 1] == 0) 2836 candidate[(i / 4)] = c1; 2837 else 2838 simubitmap = simubitmap | (1 << i); 2839 } else { 2840 simubitmap = simubitmap | (1 << i); 2841 } 2842 } 2843 } 2844 2845 if (simubitmap == 0) { 2846 for (i = 0; i < (bound / 4); i++) { 2847 if (candidate[i] >= 0) { 2848 for (j = i * 4; j < (i + 1) * 4 - 2; j++) 2849 result[3][j] = result[candidate[i]][j]; 2850 retval = false; 2851 } 2852 } 2853 return retval; 2854 } else if (!(simubitmap & 0x0f)) { 2855 /* path A OK */ 2856 for (i = 0; i < 4; i++) 2857 result[3][i] = result[c1][i]; 2858 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) { 2859 /* path B OK */ 2860 for (i = 4; i < 8; i++) 2861 result[3][i] = result[c1][i]; 2862 } 2863 2864 return false; 2865 } 2866 2867 bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv, 2868 int result[][8], int c1, int c2) 2869 { 2870 u32 i, j, diff, simubitmap, bound = 0; 2871 int candidate[2] = {-1, -1}; /* for path A and path B */ 2872 int tmp1, tmp2; 2873 bool retval = true; 2874 2875 if (priv->tx_paths > 1) 2876 bound = 8; 2877 else 2878 bound = 4; 2879 2880 simubitmap = 0; 2881 2882 for (i = 0; i < bound; i++) { 2883 if (i & 1) { 2884 if ((result[c1][i] & 0x00000200)) 2885 tmp1 = result[c1][i] | 0xfffffc00; 2886 else 2887 tmp1 = result[c1][i]; 2888 2889 if ((result[c2][i]& 0x00000200)) 2890 tmp2 = result[c2][i] | 0xfffffc00; 2891 else 2892 tmp2 = result[c2][i]; 2893 } else { 2894 tmp1 = result[c1][i]; 2895 tmp2 = result[c2][i]; 2896 } 2897 2898 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); 2899 2900 if (diff > MAX_TOLERANCE) { 2901 if ((i == 2 || i == 6) && !simubitmap) { 2902 if (result[c1][i] + result[c1][i + 1] == 0) 2903 candidate[(i / 4)] = c2; 2904 else if (result[c2][i] + result[c2][i + 1] == 0) 2905 candidate[(i / 4)] = c1; 2906 else 2907 simubitmap = simubitmap | (1 << i); 2908 } else { 2909 simubitmap = simubitmap | (1 << i); 2910 } 2911 } 2912 } 2913 2914 if (simubitmap == 0) { 2915 for (i = 0; i < (bound / 4); i++) { 2916 if (candidate[i] >= 0) { 2917 for (j = i * 4; j < (i + 1) * 4 - 2; j++) 2918 result[3][j] = result[candidate[i]][j]; 2919 retval = false; 2920 } 2921 } 2922 return retval; 2923 } else { 2924 if (!(simubitmap & 0x03)) { 2925 /* path A TX OK */ 2926 for (i = 0; i < 2; i++) 2927 result[3][i] = result[c1][i]; 2928 } 2929 2930 if (!(simubitmap & 0x0c)) { 2931 /* path A RX OK */ 2932 for (i = 2; i < 4; i++) 2933 result[3][i] = result[c1][i]; 2934 } 2935 2936 if (!(simubitmap & 0x30) && priv->tx_paths > 1) { 2937 /* path B RX OK */ 2938 for (i = 4; i < 6; i++) 2939 result[3][i] = result[c1][i]; 2940 } 2941 2942 if (!(simubitmap & 0x30) && priv->tx_paths > 1) { 2943 /* path B RX OK */ 2944 for (i = 6; i < 8; i++) 2945 result[3][i] = result[c1][i]; 2946 } 2947 } 2948 2949 return false; 2950 } 2951 2952 void 2953 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup) 2954 { 2955 int i; 2956 2957 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++) 2958 backup[i] = rtl8xxxu_read8(priv, reg[i]); 2959 2960 backup[i] = rtl8xxxu_read32(priv, reg[i]); 2961 } 2962 2963 void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv, 2964 const u32 *reg, u32 *backup) 2965 { 2966 int i; 2967 2968 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++) 2969 rtl8xxxu_write8(priv, reg[i], backup[i]); 2970 2971 rtl8xxxu_write32(priv, reg[i], backup[i]); 2972 } 2973 2974 void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 2975 u32 *backup, int count) 2976 { 2977 int i; 2978 2979 for (i = 0; i < count; i++) 2980 backup[i] = rtl8xxxu_read32(priv, regs[i]); 2981 } 2982 2983 void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 2984 u32 *backup, int count) 2985 { 2986 int i; 2987 2988 for (i = 0; i < count; i++) 2989 rtl8xxxu_write32(priv, regs[i], backup[i]); 2990 } 2991 2992 2993 void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs, 2994 bool path_a_on) 2995 { 2996 u32 path_on; 2997 int i; 2998 2999 if (priv->tx_paths == 1) { 3000 path_on = priv->fops->adda_1t_path_on; 3001 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init); 3002 } else { 3003 path_on = path_a_on ? priv->fops->adda_2t_path_on_a : 3004 priv->fops->adda_2t_path_on_b; 3005 3006 rtl8xxxu_write32(priv, regs[0], path_on); 3007 } 3008 3009 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++) 3010 rtl8xxxu_write32(priv, regs[i], path_on); 3011 } 3012 3013 void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv, 3014 const u32 *regs, u32 *backup) 3015 { 3016 int i = 0; 3017 3018 rtl8xxxu_write8(priv, regs[i], 0x3f); 3019 3020 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++) 3021 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3))); 3022 3023 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5))); 3024 } 3025 3026 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv) 3027 { 3028 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32; 3029 int result = 0; 3030 3031 /* path-A IQK setting */ 3032 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f); 3033 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f); 3034 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102); 3035 3036 val32 = (priv->rf_paths > 1) ? 0x28160202 : 3037 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */ 3038 0x28160502; 3039 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32); 3040 3041 /* path-B IQK setting */ 3042 if (priv->rf_paths > 1) { 3043 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22); 3044 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22); 3045 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102); 3046 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202); 3047 } 3048 3049 /* LO calibration setting */ 3050 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1); 3051 3052 /* One shot, path A LOK & IQK */ 3053 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 3054 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 3055 3056 mdelay(1); 3057 3058 /* Check failed */ 3059 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 3060 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 3061 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 3062 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); 3063 3064 if (!(reg_eac & BIT(28)) && 3065 ((reg_e94 & 0x03ff0000) != 0x01420000) && 3066 ((reg_e9c & 0x03ff0000) != 0x00420000)) 3067 result |= 0x01; 3068 else /* If TX not OK, ignore RX */ 3069 goto out; 3070 3071 /* If TX is OK, check whether RX is OK */ 3072 if (!(reg_eac & BIT(27)) && 3073 ((reg_ea4 & 0x03ff0000) != 0x01320000) && 3074 ((reg_eac & 0x03ff0000) != 0x00360000)) 3075 result |= 0x02; 3076 else 3077 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n", 3078 __func__); 3079 out: 3080 return result; 3081 } 3082 3083 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv) 3084 { 3085 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc; 3086 int result = 0; 3087 3088 /* One shot, path B LOK & IQK */ 3089 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002); 3090 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000); 3091 3092 mdelay(1); 3093 3094 /* Check failed */ 3095 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 3096 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 3097 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 3098 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); 3099 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); 3100 3101 if (!(reg_eac & BIT(31)) && 3102 ((reg_eb4 & 0x03ff0000) != 0x01420000) && 3103 ((reg_ebc & 0x03ff0000) != 0x00420000)) 3104 result |= 0x01; 3105 else 3106 goto out; 3107 3108 if (!(reg_eac & BIT(30)) && 3109 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) && 3110 (((reg_ecc & 0x03ff0000) >> 16) != 0x36)) 3111 result |= 0x02; 3112 else 3113 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", 3114 __func__); 3115 out: 3116 return result; 3117 } 3118 3119 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, 3120 int result[][8], int t) 3121 { 3122 struct device *dev = &priv->udev->dev; 3123 u32 i, val32; 3124 int path_a_ok, path_b_ok; 3125 int retry = 2; 3126 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { 3127 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, 3128 REG_RX_WAIT_CCA, REG_TX_CCK_RFON, 3129 REG_TX_CCK_BBON, REG_TX_OFDM_RFON, 3130 REG_TX_OFDM_BBON, REG_TX_TO_RX, 3131 REG_TX_TO_TX, REG_RX_CCK, 3132 REG_RX_OFDM, REG_RX_WAIT_RIFS, 3133 REG_RX_TO_RX, REG_STANDBY, 3134 REG_SLEEP, REG_PMPD_ANAEN 3135 }; 3136 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { 3137 REG_TXPAUSE, REG_BEACON_CTRL, 3138 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG 3139 }; 3140 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { 3141 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, 3142 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, 3143 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, 3144 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE 3145 }; 3146 3147 /* 3148 * Note: IQ calibration must be performed after loading 3149 * PHY_REG.txt , and radio_a, radio_b.txt 3150 */ 3151 3152 if (t == 0) { 3153 /* Save ADDA parameters, turn Path A ADDA on */ 3154 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, 3155 RTL8XXXU_ADDA_REGS); 3156 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 3157 rtl8xxxu_save_regs(priv, iqk_bb_regs, 3158 priv->bb_backup, RTL8XXXU_BB_REGS); 3159 } 3160 3161 rtl8xxxu_path_adda_on(priv, adda_regs, true); 3162 3163 if (t == 0) { 3164 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); 3165 if (val32 & FPGA0_HSSI_PARM1_PI) 3166 priv->pi_enabled = 1; 3167 } 3168 3169 if (!priv->pi_enabled) { 3170 /* Switch BB to PI mode to do IQ Calibration. */ 3171 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); 3172 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100); 3173 } 3174 3175 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 3176 val32 &= ~FPGA_RF_MODE_CCK; 3177 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 3178 3179 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); 3180 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); 3181 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); 3182 3183 if (!priv->no_pape) { 3184 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); 3185 val32 |= (FPGA0_RF_PAPE | 3186 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); 3187 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); 3188 } 3189 3190 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); 3191 val32 &= ~BIT(10); 3192 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); 3193 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); 3194 val32 &= ~BIT(10); 3195 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); 3196 3197 if (priv->tx_paths > 1) { 3198 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); 3199 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000); 3200 } 3201 3202 /* MAC settings */ 3203 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); 3204 3205 /* Page B init */ 3206 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000); 3207 3208 if (priv->tx_paths > 1) 3209 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000); 3210 3211 /* IQ calibration setting */ 3212 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); 3213 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 3214 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 3215 3216 for (i = 0; i < retry; i++) { 3217 path_a_ok = rtl8xxxu_iqk_path_a(priv); 3218 if (path_a_ok == 0x03) { 3219 val32 = rtl8xxxu_read32(priv, 3220 REG_TX_POWER_BEFORE_IQK_A); 3221 result[t][0] = (val32 >> 16) & 0x3ff; 3222 val32 = rtl8xxxu_read32(priv, 3223 REG_TX_POWER_AFTER_IQK_A); 3224 result[t][1] = (val32 >> 16) & 0x3ff; 3225 val32 = rtl8xxxu_read32(priv, 3226 REG_RX_POWER_BEFORE_IQK_A_2); 3227 result[t][2] = (val32 >> 16) & 0x3ff; 3228 val32 = rtl8xxxu_read32(priv, 3229 REG_RX_POWER_AFTER_IQK_A_2); 3230 result[t][3] = (val32 >> 16) & 0x3ff; 3231 break; 3232 } else if (i == (retry - 1) && path_a_ok == 0x01) { 3233 /* TX IQK OK */ 3234 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n", 3235 __func__); 3236 3237 val32 = rtl8xxxu_read32(priv, 3238 REG_TX_POWER_BEFORE_IQK_A); 3239 result[t][0] = (val32 >> 16) & 0x3ff; 3240 val32 = rtl8xxxu_read32(priv, 3241 REG_TX_POWER_AFTER_IQK_A); 3242 result[t][1] = (val32 >> 16) & 0x3ff; 3243 } 3244 } 3245 3246 if (!path_a_ok) 3247 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__); 3248 3249 if (priv->tx_paths > 1) { 3250 /* 3251 * Path A into standby 3252 */ 3253 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0); 3254 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); 3255 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); 3256 3257 /* Turn Path B ADDA on */ 3258 rtl8xxxu_path_adda_on(priv, adda_regs, false); 3259 3260 for (i = 0; i < retry; i++) { 3261 path_b_ok = rtl8xxxu_iqk_path_b(priv); 3262 if (path_b_ok == 0x03) { 3263 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 3264 result[t][4] = (val32 >> 16) & 0x3ff; 3265 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 3266 result[t][5] = (val32 >> 16) & 0x3ff; 3267 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); 3268 result[t][6] = (val32 >> 16) & 0x3ff; 3269 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); 3270 result[t][7] = (val32 >> 16) & 0x3ff; 3271 break; 3272 } else if (i == (retry - 1) && path_b_ok == 0x01) { 3273 /* TX IQK OK */ 3274 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 3275 result[t][4] = (val32 >> 16) & 0x3ff; 3276 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 3277 result[t][5] = (val32 >> 16) & 0x3ff; 3278 } 3279 } 3280 3281 if (!path_b_ok) 3282 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__); 3283 } 3284 3285 /* Back to BB mode, load original value */ 3286 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0); 3287 3288 if (t) { 3289 if (!priv->pi_enabled) { 3290 /* 3291 * Switch back BB to SI mode after finishing 3292 * IQ Calibration 3293 */ 3294 val32 = 0x01000000; 3295 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32); 3296 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32); 3297 } 3298 3299 /* Reload ADDA power saving parameters */ 3300 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, 3301 RTL8XXXU_ADDA_REGS); 3302 3303 /* Reload MAC parameters */ 3304 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 3305 3306 /* Reload BB parameters */ 3307 rtl8xxxu_restore_regs(priv, iqk_bb_regs, 3308 priv->bb_backup, RTL8XXXU_BB_REGS); 3309 3310 /* Restore RX initial gain */ 3311 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3); 3312 3313 if (priv->tx_paths > 1) { 3314 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 3315 0x00032ed3); 3316 } 3317 3318 /* Load 0xe30 IQC default value */ 3319 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); 3320 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); 3321 } 3322 } 3323 3324 void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start) 3325 { 3326 struct h2c_cmd h2c; 3327 3328 memset(&h2c, 0, sizeof(struct h2c_cmd)); 3329 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION; 3330 h2c.bt_wlan_calibration.data = start; 3331 3332 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration)); 3333 } 3334 3335 void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv) 3336 { 3337 struct device *dev = &priv->udev->dev; 3338 int result[4][8]; /* last is final result */ 3339 int i, candidate; 3340 bool path_a_ok, path_b_ok; 3341 u32 reg_e94, reg_e9c, reg_ea4, reg_eac; 3342 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; 3343 s32 reg_tmp = 0; 3344 bool simu; 3345 3346 memset(result, 0, sizeof(result)); 3347 candidate = -1; 3348 3349 path_a_ok = false; 3350 path_b_ok = false; 3351 3352 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 3353 3354 for (i = 0; i < 3; i++) { 3355 rtl8xxxu_phy_iqcalibrate(priv, result, i); 3356 3357 if (i == 1) { 3358 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1); 3359 if (simu) { 3360 candidate = 0; 3361 break; 3362 } 3363 } 3364 3365 if (i == 2) { 3366 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2); 3367 if (simu) { 3368 candidate = 0; 3369 break; 3370 } 3371 3372 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2); 3373 if (simu) { 3374 candidate = 1; 3375 } else { 3376 for (i = 0; i < 8; i++) 3377 reg_tmp += result[3][i]; 3378 3379 if (reg_tmp) 3380 candidate = 3; 3381 else 3382 candidate = -1; 3383 } 3384 } 3385 } 3386 3387 for (i = 0; i < 4; i++) { 3388 reg_e94 = result[i][0]; 3389 reg_e9c = result[i][1]; 3390 reg_ea4 = result[i][2]; 3391 reg_eac = result[i][3]; 3392 reg_eb4 = result[i][4]; 3393 reg_ebc = result[i][5]; 3394 reg_ec4 = result[i][6]; 3395 reg_ecc = result[i][7]; 3396 } 3397 3398 if (candidate >= 0) { 3399 reg_e94 = result[candidate][0]; 3400 priv->rege94 = reg_e94; 3401 reg_e9c = result[candidate][1]; 3402 priv->rege9c = reg_e9c; 3403 reg_ea4 = result[candidate][2]; 3404 reg_eac = result[candidate][3]; 3405 reg_eb4 = result[candidate][4]; 3406 priv->regeb4 = reg_eb4; 3407 reg_ebc = result[candidate][5]; 3408 priv->regebc = reg_ebc; 3409 reg_ec4 = result[candidate][6]; 3410 reg_ecc = result[candidate][7]; 3411 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); 3412 dev_dbg(dev, 3413 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n", 3414 __func__, reg_e94, reg_e9c, 3415 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); 3416 path_a_ok = true; 3417 path_b_ok = true; 3418 } else { 3419 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; 3420 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; 3421 } 3422 3423 if (reg_e94 && candidate >= 0) 3424 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, 3425 candidate, (reg_ea4 == 0)); 3426 3427 if (priv->tx_paths > 1 && reg_eb4) 3428 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, 3429 candidate, (reg_ec4 == 0)); 3430 3431 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, 3432 priv->bb_recovery_backup, RTL8XXXU_BB_REGS); 3433 } 3434 3435 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv) 3436 { 3437 u32 val32; 3438 u32 rf_amode, rf_bmode = 0, lstf; 3439 3440 /* Check continuous TX and Packet TX */ 3441 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 3442 3443 if (lstf & OFDM_LSTF_MASK) { 3444 /* Disable all continuous TX */ 3445 val32 = lstf & ~OFDM_LSTF_MASK; 3446 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 3447 3448 /* Read original RF mode Path A */ 3449 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC); 3450 3451 /* Set RF mode to standby Path A */ 3452 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 3453 (rf_amode & 0x8ffff) | 0x10000); 3454 3455 /* Path-B */ 3456 if (priv->tx_paths > 1) { 3457 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B, 3458 RF6052_REG_AC); 3459 3460 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 3461 (rf_bmode & 0x8ffff) | 0x10000); 3462 } 3463 } else { 3464 /* Deal with Packet TX case */ 3465 /* block all queues */ 3466 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 3467 } 3468 3469 /* Start LC calibration */ 3470 if (priv->fops->has_s0s1) 3471 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0); 3472 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); 3473 val32 |= 0x08000; 3474 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); 3475 3476 msleep(100); 3477 3478 if (priv->fops->has_s0s1) 3479 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0); 3480 3481 /* Restore original parameters */ 3482 if (lstf & OFDM_LSTF_MASK) { 3483 /* Path-A */ 3484 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf); 3485 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode); 3486 3487 /* Path-B */ 3488 if (priv->tx_paths > 1) 3489 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 3490 rf_bmode); 3491 } else /* Deal with Packet TX case */ 3492 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); 3493 } 3494 3495 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv) 3496 { 3497 int i; 3498 u16 reg; 3499 3500 reg = REG_MACID; 3501 3502 for (i = 0; i < ETH_ALEN; i++) 3503 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]); 3504 3505 return 0; 3506 } 3507 3508 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid) 3509 { 3510 int i; 3511 u16 reg; 3512 3513 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid); 3514 3515 reg = REG_BSSID; 3516 3517 for (i = 0; i < ETH_ALEN; i++) 3518 rtl8xxxu_write8(priv, reg + i, bssid[i]); 3519 3520 return 0; 3521 } 3522 3523 static void 3524 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor) 3525 { 3526 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 }; 3527 u8 max_agg = 0xf; 3528 int i; 3529 3530 ampdu_factor = 1 << (ampdu_factor + 2); 3531 if (ampdu_factor > max_agg) 3532 ampdu_factor = max_agg; 3533 3534 for (i = 0; i < 4; i++) { 3535 if ((vals[i] & 0xf0) > (ampdu_factor << 4)) 3536 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4); 3537 3538 if ((vals[i] & 0x0f) > ampdu_factor) 3539 vals[i] = (vals[i] & 0xf0) | ampdu_factor; 3540 3541 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]); 3542 } 3543 } 3544 3545 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density) 3546 { 3547 u8 val8; 3548 3549 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE); 3550 val8 &= 0xf8; 3551 val8 |= density; 3552 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8); 3553 } 3554 3555 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv) 3556 { 3557 u8 val8; 3558 int count, ret = 0; 3559 3560 /* Start of rtl8723AU_card_enable_flow */ 3561 /* Act to Cardemu sequence*/ 3562 /* Turn off RF */ 3563 rtl8xxxu_write8(priv, REG_RF_CTRL, 0); 3564 3565 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */ 3566 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); 3567 val8 &= ~LEDCFG2_DPDT_SELECT; 3568 rtl8xxxu_write8(priv, REG_LEDCFG2, val8); 3569 3570 /* 0x0005[1] = 1 turn off MAC by HW state machine*/ 3571 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3572 val8 |= BIT(1); 3573 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3574 3575 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 3576 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3577 if ((val8 & BIT(1)) == 0) 3578 break; 3579 udelay(10); 3580 } 3581 3582 if (!count) { 3583 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", 3584 __func__); 3585 ret = -EBUSY; 3586 goto exit; 3587 } 3588 3589 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */ 3590 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); 3591 val8 |= SYS_ISO_ANALOG_IPS; 3592 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); 3593 3594 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/ 3595 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); 3596 val8 &= ~LDOA15_ENABLE; 3597 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); 3598 3599 exit: 3600 return ret; 3601 } 3602 3603 int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv) 3604 { 3605 u8 val8; 3606 u8 val32; 3607 int count, ret = 0; 3608 3609 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 3610 3611 /* 3612 * Poll - wait for RX packet to complete 3613 */ 3614 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 3615 val32 = rtl8xxxu_read32(priv, 0x5f8); 3616 if (!val32) 3617 break; 3618 udelay(10); 3619 } 3620 3621 if (!count) { 3622 dev_warn(&priv->udev->dev, 3623 "%s: RX poll timed out (0x05f8)\n", __func__); 3624 ret = -EBUSY; 3625 goto exit; 3626 } 3627 3628 /* Disable CCK and OFDM, clock gated */ 3629 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 3630 val8 &= ~SYS_FUNC_BBRSTB; 3631 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 3632 3633 udelay(2); 3634 3635 /* Reset baseband */ 3636 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 3637 val8 &= ~SYS_FUNC_BB_GLB_RSTN; 3638 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 3639 3640 /* Reset MAC TRX */ 3641 val8 = rtl8xxxu_read8(priv, REG_CR); 3642 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE; 3643 rtl8xxxu_write8(priv, REG_CR, val8); 3644 3645 /* Reset MAC TRX */ 3646 val8 = rtl8xxxu_read8(priv, REG_CR + 1); 3647 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */ 3648 rtl8xxxu_write8(priv, REG_CR + 1, val8); 3649 3650 /* Respond TX OK to scheduler */ 3651 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); 3652 val8 |= DUAL_TSF_TX_OK; 3653 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); 3654 3655 exit: 3656 return ret; 3657 } 3658 3659 void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv) 3660 { 3661 u8 val8; 3662 3663 /* Clear suspend enable and power down enable*/ 3664 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3665 val8 &= ~(BIT(3) | BIT(7)); 3666 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3667 3668 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ 3669 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); 3670 val8 &= ~BIT(0); 3671 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); 3672 3673 /* 0x04[12:11] = 11 enable WL suspend*/ 3674 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3675 val8 &= ~(BIT(3) | BIT(4)); 3676 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3677 } 3678 3679 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv) 3680 { 3681 u8 val8; 3682 3683 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */ 3684 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20); 3685 3686 /* 0x04[12:11] = 01 enable WL suspend */ 3687 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3688 val8 &= ~BIT(4); 3689 val8 |= BIT(3); 3690 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3691 3692 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3693 val8 |= BIT(7); 3694 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3695 3696 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */ 3697 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); 3698 val8 |= BIT(0); 3699 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); 3700 3701 return 0; 3702 } 3703 3704 int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv) 3705 { 3706 struct device *dev = &priv->udev->dev; 3707 u32 val32; 3708 int retry, retval; 3709 3710 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 3711 3712 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM); 3713 val32 |= RXPKT_NUM_RW_RELEASE_EN; 3714 rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32); 3715 3716 retry = 100; 3717 retval = -EBUSY; 3718 3719 do { 3720 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM); 3721 if (val32 & RXPKT_NUM_RXDMA_IDLE) { 3722 retval = 0; 3723 break; 3724 } 3725 } while (retry--); 3726 3727 rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0); 3728 rtl8xxxu_write32(priv, REG_RQPN, 0x80000000); 3729 mdelay(2); 3730 3731 if (!retry) 3732 dev_warn(dev, "Failed to flush FIFO\n"); 3733 3734 return retval; 3735 } 3736 3737 void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv) 3738 { 3739 /* Fix USB interface interference issue */ 3740 rtl8xxxu_write8(priv, 0xfe40, 0xe0); 3741 rtl8xxxu_write8(priv, 0xfe41, 0x8d); 3742 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3743 /* 3744 * This sets TXDMA_OFFSET_DROP_DATA_EN (bit 9) as well as bits 3745 * 8 and 5, for which I have found no documentation. 3746 */ 3747 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320); 3748 3749 /* 3750 * Solve too many protocol error on USB bus. 3751 * Can't do this for 8188/8192 UMC A cut parts 3752 */ 3753 if (!(!priv->chip_cut && priv->vendor_umc)) { 3754 rtl8xxxu_write8(priv, 0xfe40, 0xe6); 3755 rtl8xxxu_write8(priv, 0xfe41, 0x94); 3756 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3757 3758 rtl8xxxu_write8(priv, 0xfe40, 0xe0); 3759 rtl8xxxu_write8(priv, 0xfe41, 0x19); 3760 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3761 3762 rtl8xxxu_write8(priv, 0xfe40, 0xe5); 3763 rtl8xxxu_write8(priv, 0xfe41, 0x91); 3764 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3765 3766 rtl8xxxu_write8(priv, 0xfe40, 0xe2); 3767 rtl8xxxu_write8(priv, 0xfe41, 0x81); 3768 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3769 } 3770 } 3771 3772 void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv) 3773 { 3774 u32 val32; 3775 3776 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK); 3777 val32 |= TXDMA_OFFSET_DROP_DATA_EN; 3778 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32); 3779 } 3780 3781 void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv) 3782 { 3783 u8 val8; 3784 u16 val16; 3785 u32 val32; 3786 3787 /* 3788 * Workaround for 8188RU LNA power leakage problem. 3789 */ 3790 if (priv->rtl_chip == RTL8188R) { 3791 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM); 3792 val32 |= BIT(1); 3793 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32); 3794 } 3795 3796 rtl8xxxu_flush_fifo(priv); 3797 3798 rtl8xxxu_active_to_lps(priv); 3799 3800 /* Turn off RF */ 3801 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); 3802 3803 /* Reset Firmware if running in RAM */ 3804 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) 3805 rtl8xxxu_firmware_self_reset(priv); 3806 3807 /* Reset MCU */ 3808 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 3809 val16 &= ~SYS_FUNC_CPU_ENABLE; 3810 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 3811 3812 /* Reset MCU ready status */ 3813 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); 3814 3815 rtl8xxxu_active_to_emu(priv); 3816 rtl8xxxu_emu_to_disabled(priv); 3817 3818 /* Reset MCU IO Wrapper */ 3819 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 3820 val8 &= ~BIT(0); 3821 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 3822 3823 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 3824 val8 |= BIT(0); 3825 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 3826 3827 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */ 3828 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e); 3829 } 3830 3831 #ifdef NEED_PS_TDMA 3832 static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv, 3833 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5) 3834 { 3835 struct h2c_cmd h2c; 3836 3837 memset(&h2c, 0, sizeof(struct h2c_cmd)); 3838 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA; 3839 h2c.b_type_dma.data1 = arg1; 3840 h2c.b_type_dma.data2 = arg2; 3841 h2c.b_type_dma.data3 = arg3; 3842 h2c.b_type_dma.data4 = arg4; 3843 h2c.b_type_dma.data5 = arg5; 3844 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma)); 3845 } 3846 #endif 3847 3848 void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv) 3849 { 3850 u32 val32; 3851 3852 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); 3853 val32 &= ~(BIT(22) | BIT(23)); 3854 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); 3855 } 3856 3857 static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv *priv) 3858 { 3859 struct rtl8xxxu_fileops *fops = priv->fops; 3860 u32 hq, lq, nq, eq, pubq; 3861 u32 val32; 3862 3863 hq = 0; 3864 lq = 0; 3865 nq = 0; 3866 eq = 0; 3867 pubq = 0; 3868 3869 if (priv->ep_tx_high_queue) 3870 hq = fops->page_num_hi; 3871 if (priv->ep_tx_low_queue) 3872 lq = fops->page_num_lo; 3873 if (priv->ep_tx_normal_queue) 3874 nq = fops->page_num_norm; 3875 3876 val32 = (nq << RQPN_NPQ_SHIFT) | (eq << RQPN_EPQ_SHIFT); 3877 rtl8xxxu_write32(priv, REG_RQPN_NPQ, val32); 3878 3879 pubq = fops->total_page_num - hq - lq - nq - 1; 3880 3881 val32 = RQPN_LOAD; 3882 val32 |= (hq << RQPN_HI_PQ_SHIFT); 3883 val32 |= (lq << RQPN_LO_PQ_SHIFT); 3884 val32 |= (pubq << RQPN_PUB_PQ_SHIFT); 3885 3886 rtl8xxxu_write32(priv, REG_RQPN, val32); 3887 } 3888 3889 static int rtl8xxxu_init_device(struct ieee80211_hw *hw) 3890 { 3891 struct rtl8xxxu_priv *priv = hw->priv; 3892 struct device *dev = &priv->udev->dev; 3893 struct rtl8xxxu_fileops *fops = priv->fops; 3894 bool macpower; 3895 int ret; 3896 u8 val8; 3897 u16 val16; 3898 u32 val32; 3899 3900 /* Check if MAC is already powered on */ 3901 val8 = rtl8xxxu_read8(priv, REG_CR); 3902 3903 /* 3904 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not 3905 * initialized. First MAC returns 0xea, second MAC returns 0x00 3906 */ 3907 if (val8 == 0xea) 3908 macpower = false; 3909 else 3910 macpower = true; 3911 3912 ret = fops->power_on(priv); 3913 if (ret < 0) { 3914 dev_warn(dev, "%s: Failed power on\n", __func__); 3915 goto exit; 3916 } 3917 3918 if (!macpower) 3919 rtl8xxxu_init_queue_reserved_page(priv); 3920 3921 ret = rtl8xxxu_init_queue_priority(priv); 3922 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret); 3923 if (ret) 3924 goto exit; 3925 3926 /* 3927 * Set RX page boundary 3928 */ 3929 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, fops->trxff_boundary); 3930 3931 ret = rtl8xxxu_download_firmware(priv); 3932 dev_dbg(dev, "%s: download_firmware %i\n", __func__, ret); 3933 if (ret) 3934 goto exit; 3935 ret = rtl8xxxu_start_firmware(priv); 3936 dev_dbg(dev, "%s: start_firmware %i\n", __func__, ret); 3937 if (ret) 3938 goto exit; 3939 3940 if (fops->phy_init_antenna_selection) 3941 fops->phy_init_antenna_selection(priv); 3942 3943 ret = rtl8xxxu_init_mac(priv); 3944 3945 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret); 3946 if (ret) 3947 goto exit; 3948 3949 ret = rtl8xxxu_init_phy_bb(priv); 3950 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret); 3951 if (ret) 3952 goto exit; 3953 3954 ret = fops->init_phy_rf(priv); 3955 if (ret) 3956 goto exit; 3957 3958 /* RFSW Control - clear bit 14 ?? */ 3959 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E) 3960 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003); 3961 3962 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW | 3963 FPGA0_RF_ANTSWB | 3964 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB) << FPGA0_RF_BD_CTRL_SHIFT); 3965 if (!priv->no_pape) { 3966 val32 |= (FPGA0_RF_PAPE | 3967 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); 3968 } 3969 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); 3970 3971 /* 0x860[6:5]= 00 - why? - this sets antenna B */ 3972 if (priv->rtl_chip != RTL8192E) 3973 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210); 3974 3975 if (!macpower) { 3976 /* 3977 * Set TX buffer boundary 3978 */ 3979 val8 = fops->total_page_num + 1; 3980 3981 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8); 3982 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8); 3983 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8); 3984 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8); 3985 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8); 3986 } 3987 3988 /* 3989 * The vendor drivers set PBP for all devices, except 8192e. 3990 * There is no explanation for this in any of the sources. 3991 */ 3992 val8 = (fops->pbp_rx << PBP_PAGE_SIZE_RX_SHIFT) | 3993 (fops->pbp_tx << PBP_PAGE_SIZE_TX_SHIFT); 3994 if (priv->rtl_chip != RTL8192E) 3995 rtl8xxxu_write8(priv, REG_PBP, val8); 3996 3997 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower); 3998 if (!macpower) { 3999 ret = fops->llt_init(priv); 4000 if (ret) { 4001 dev_warn(dev, "%s: LLT table init failed\n", __func__); 4002 goto exit; 4003 } 4004 4005 /* 4006 * Chip specific quirks 4007 */ 4008 fops->usb_quirks(priv); 4009 4010 /* 4011 * Enable TX report and TX report timer for 8723bu/8188eu/... 4012 */ 4013 if (fops->has_tx_report) { 4014 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); 4015 val8 |= TX_REPORT_CTRL_TIMER_ENABLE; 4016 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); 4017 /* Set MAX RPT MACID */ 4018 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02); 4019 /* TX report Timer. Unit: 32us */ 4020 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0); 4021 4022 /* tmp ps ? */ 4023 val8 = rtl8xxxu_read8(priv, 0xa3); 4024 val8 &= 0xf8; 4025 rtl8xxxu_write8(priv, 0xa3, val8); 4026 } 4027 } 4028 4029 /* 4030 * Unit in 8 bytes, not obvious what it is used for 4031 */ 4032 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4); 4033 4034 if (priv->rtl_chip == RTL8192E) { 4035 rtl8xxxu_write32(priv, REG_HIMR0, 0x00); 4036 rtl8xxxu_write32(priv, REG_HIMR1, 0x00); 4037 } else { 4038 /* 4039 * Enable all interrupts - not obvious USB needs to do this 4040 */ 4041 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff); 4042 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff); 4043 } 4044 4045 rtl8xxxu_set_mac(priv); 4046 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION); 4047 4048 /* 4049 * Configure initial WMAC settings 4050 */ 4051 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST | 4052 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL | 4053 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC; 4054 rtl8xxxu_write32(priv, REG_RCR, val32); 4055 4056 /* 4057 * Accept all multicast 4058 */ 4059 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff); 4060 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff); 4061 4062 /* 4063 * Init adaptive controls 4064 */ 4065 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 4066 val32 &= ~RESPONSE_RATE_BITMAP_ALL; 4067 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M; 4068 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 4069 4070 /* CCK = 0x0a, OFDM = 0x10 */ 4071 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10); 4072 rtl8xxxu_set_retry(priv, 0x30, 0x30); 4073 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10); 4074 4075 /* 4076 * Init EDCA 4077 */ 4078 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a); 4079 4080 /* Set CCK SIFS */ 4081 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a); 4082 4083 /* Set OFDM SIFS */ 4084 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a); 4085 4086 /* TXOP */ 4087 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b); 4088 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f); 4089 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324); 4090 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226); 4091 4092 /* Set data auto rate fallback retry count */ 4093 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000); 4094 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404); 4095 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201); 4096 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605); 4097 4098 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL); 4099 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY; 4100 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8); 4101 4102 /* Set ACK timeout */ 4103 rtl8xxxu_write8(priv, REG_ACKTO, 0x40); 4104 4105 /* 4106 * Initialize beacon parameters 4107 */ 4108 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8); 4109 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16); 4110 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404); 4111 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME); 4112 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME); 4113 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F); 4114 4115 /* 4116 * Initialize burst parameters 4117 */ 4118 if (priv->rtl_chip == RTL8723B) { 4119 /* 4120 * For USB high speed set 512B packets 4121 */ 4122 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B); 4123 val8 &= ~(BIT(4) | BIT(5)); 4124 val8 |= BIT(4); 4125 val8 |= BIT(1) | BIT(2) | BIT(3); 4126 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8); 4127 4128 /* 4129 * For USB high speed set 512B packets 4130 */ 4131 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B); 4132 val8 |= BIT(7); 4133 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8); 4134 4135 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14); 4136 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 0x5e); 4137 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff); 4138 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18); 4139 rtl8xxxu_write8(priv, REG_PIFS, 0x00); 4140 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, 0x50); 4141 rtl8xxxu_write8(priv, REG_USTIME_EDCA, 0x50); 4142 4143 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); 4144 val8 |= BIT(5) | BIT(6); 4145 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); 4146 } 4147 4148 if (fops->init_aggregation) 4149 fops->init_aggregation(priv); 4150 4151 /* 4152 * Enable CCK and OFDM block 4153 */ 4154 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 4155 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM); 4156 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 4157 4158 /* 4159 * Invalidate all CAM entries - bit 30 is undocumented 4160 */ 4161 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30)); 4162 4163 /* 4164 * Start out with default power levels for channel 6, 20MHz 4165 */ 4166 fops->set_tx_power(priv, 1, false); 4167 4168 /* Let the 8051 take control of antenna setting */ 4169 if (priv->rtl_chip != RTL8192E) { 4170 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); 4171 val8 |= LEDCFG2_DPDT_SELECT; 4172 rtl8xxxu_write8(priv, REG_LEDCFG2, val8); 4173 } 4174 4175 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff); 4176 4177 /* Disable BAR - not sure if this has any effect on USB */ 4178 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff); 4179 4180 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0); 4181 4182 if (fops->init_statistics) 4183 fops->init_statistics(priv); 4184 4185 if (priv->rtl_chip == RTL8192E) { 4186 /* 4187 * 0x4c6[3] 1: RTS BW = Data BW 4188 * 0: RTS BW depends on CCA / secondary CCA result. 4189 */ 4190 val8 = rtl8xxxu_read8(priv, REG_QUEUE_CTRL); 4191 val8 &= ~BIT(3); 4192 rtl8xxxu_write8(priv, REG_QUEUE_CTRL, val8); 4193 /* 4194 * Reset USB mode switch setting 4195 */ 4196 rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00); 4197 } 4198 4199 rtl8723a_phy_lc_calibrate(priv); 4200 4201 fops->phy_iq_calibrate(priv); 4202 4203 /* 4204 * This should enable thermal meter 4205 */ 4206 if (fops->gen2_thermal_meter) 4207 rtl8xxxu_write_rfreg(priv, 4208 RF_A, RF6052_REG_T_METER_8723B, 0x37cf8); 4209 else 4210 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60); 4211 4212 /* Set NAV_UPPER to 30000us */ 4213 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT); 4214 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8); 4215 4216 if (priv->rtl_chip == RTL8723A) { 4217 /* 4218 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test, 4219 * but we need to find root cause. 4220 * This is 8723au only. 4221 */ 4222 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 4223 if ((val32 & 0xff000000) != 0x83000000) { 4224 val32 |= FPGA_RF_MODE_CCK; 4225 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 4226 } 4227 } else if (priv->rtl_chip == RTL8192E) { 4228 rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00); 4229 } 4230 4231 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL); 4232 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK; 4233 /* ack for xmit mgmt frames. */ 4234 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32); 4235 4236 if (priv->rtl_chip == RTL8192E) { 4237 /* 4238 * Fix LDPC rx hang issue. 4239 */ 4240 val32 = rtl8xxxu_read32(priv, REG_AFE_MISC); 4241 rtl8xxxu_write8(priv, REG_8192E_LDOV12_CTRL, 0x75); 4242 val32 &= 0xfff00fff; 4243 val32 |= 0x0007e000; 4244 rtl8xxxu_write32(priv, REG_AFE_MISC, val32); 4245 } 4246 exit: 4247 return ret; 4248 } 4249 4250 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv, 4251 struct ieee80211_key_conf *key, const u8 *mac) 4252 { 4253 u32 cmd, val32, addr, ctrl; 4254 int j, i, tmp_debug; 4255 4256 tmp_debug = rtl8xxxu_debug; 4257 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY) 4258 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE; 4259 4260 /* 4261 * This is a bit of a hack - the lower bits of the cipher 4262 * suite selector happens to match the cipher index in the CAM 4263 */ 4264 addr = key->keyidx << CAM_CMD_KEY_SHIFT; 4265 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID; 4266 4267 for (j = 5; j >= 0; j--) { 4268 switch (j) { 4269 case 0: 4270 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24); 4271 break; 4272 case 1: 4273 val32 = mac[2] | (mac[3] << 8) | 4274 (mac[4] << 16) | (mac[5] << 24); 4275 break; 4276 default: 4277 i = (j - 2) << 2; 4278 val32 = key->key[i] | (key->key[i + 1] << 8) | 4279 key->key[i + 2] << 16 | key->key[i + 3] << 24; 4280 break; 4281 } 4282 4283 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32); 4284 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j); 4285 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd); 4286 udelay(100); 4287 } 4288 4289 rtl8xxxu_debug = tmp_debug; 4290 } 4291 4292 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw, 4293 struct ieee80211_vif *vif, const u8 *mac) 4294 { 4295 struct rtl8xxxu_priv *priv = hw->priv; 4296 u8 val8; 4297 4298 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 4299 val8 |= BEACON_DISABLE_TSF_UPDATE; 4300 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 4301 } 4302 4303 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw, 4304 struct ieee80211_vif *vif) 4305 { 4306 struct rtl8xxxu_priv *priv = hw->priv; 4307 u8 val8; 4308 4309 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 4310 val8 &= ~BEACON_DISABLE_TSF_UPDATE; 4311 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 4312 } 4313 4314 void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv, u32 ramask, int sgi) 4315 { 4316 struct h2c_cmd h2c; 4317 4318 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4319 4320 h2c.ramask.cmd = H2C_SET_RATE_MASK; 4321 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff); 4322 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16); 4323 4324 h2c.ramask.arg = 0x80; 4325 if (sgi) 4326 h2c.ramask.arg |= 0x20; 4327 4328 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n", 4329 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask)); 4330 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.ramask)); 4331 } 4332 4333 void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv, 4334 u32 ramask, int sgi) 4335 { 4336 struct h2c_cmd h2c; 4337 u8 bw = 0; 4338 4339 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4340 4341 h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID; 4342 h2c.b_macid_cfg.ramask0 = ramask & 0xff; 4343 h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff; 4344 h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff; 4345 h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff; 4346 4347 h2c.ramask.arg = 0x80; 4348 h2c.b_macid_cfg.data1 = 0; 4349 if (sgi) 4350 h2c.b_macid_cfg.data1 |= BIT(7); 4351 4352 h2c.b_macid_cfg.data2 = bw; 4353 4354 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n", 4355 __func__, ramask, h2c.ramask.arg, sizeof(h2c.b_macid_cfg)); 4356 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg)); 4357 } 4358 4359 void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv, 4360 u8 macid, bool connect) 4361 { 4362 struct h2c_cmd h2c; 4363 4364 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4365 4366 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT; 4367 4368 if (connect) 4369 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT; 4370 else 4371 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT; 4372 4373 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss)); 4374 } 4375 4376 void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv, 4377 u8 macid, bool connect) 4378 { 4379 #ifdef RTL8XXXU_GEN2_REPORT_CONNECT 4380 /* 4381 * Barry Day reports this causes issues with 8192eu and 8723bu 4382 * devices reconnecting. The reason for this is unclear, but 4383 * until it is better understood, leave the code in place but 4384 * disabled, so it is not lost. 4385 */ 4386 struct h2c_cmd h2c; 4387 4388 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4389 4390 h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT; 4391 if (connect) 4392 h2c.media_status_rpt.parm |= BIT(0); 4393 else 4394 h2c.media_status_rpt.parm &= ~BIT(0); 4395 4396 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt)); 4397 #endif 4398 } 4399 4400 void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv) 4401 { 4402 u8 agg_ctrl, usb_spec, page_thresh, timeout; 4403 4404 usb_spec = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION); 4405 usb_spec &= ~USB_SPEC_USB_AGG_ENABLE; 4406 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, usb_spec); 4407 4408 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); 4409 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; 4410 4411 if (!rtl8xxxu_dma_aggregation) { 4412 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); 4413 return; 4414 } 4415 4416 agg_ctrl |= TRXDMA_CTRL_RXDMA_AGG_EN; 4417 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); 4418 4419 /* 4420 * The number of packets we can take looks to be buffer size / 512 4421 * which matches the 512 byte rounding we have to do when de-muxing 4422 * the packets. 4423 * 4424 * Sample numbers from the vendor driver: 4425 * USB High-Speed mode values: 4426 * RxAggBlockCount = 8 : 512 byte unit 4427 * RxAggBlockTimeout = 6 4428 * RxAggPageCount = 48 : 128 byte unit 4429 * RxAggPageTimeout = 4 or 6 (absolute time 34ms/(2^6)) 4430 */ 4431 4432 page_thresh = (priv->fops->rx_agg_buf_size / 512); 4433 if (rtl8xxxu_dma_agg_pages >= 0) { 4434 if (rtl8xxxu_dma_agg_pages <= page_thresh) 4435 timeout = page_thresh; 4436 else if (rtl8xxxu_dma_agg_pages <= 6) 4437 dev_err(&priv->udev->dev, 4438 "%s: dma_agg_pages=%i too small, minimum is 6\n", 4439 __func__, rtl8xxxu_dma_agg_pages); 4440 else 4441 dev_err(&priv->udev->dev, 4442 "%s: dma_agg_pages=%i larger than limit %i\n", 4443 __func__, rtl8xxxu_dma_agg_pages, page_thresh); 4444 } 4445 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH, page_thresh); 4446 /* 4447 * REG_RXDMA_AGG_PG_TH + 1 seems to be the timeout register on 4448 * gen2 chips and rtl8188eu. The rtl8723au seems unhappy if we 4449 * don't set it, so better set both. 4450 */ 4451 timeout = 4; 4452 4453 if (rtl8xxxu_dma_agg_timeout >= 0) { 4454 if (rtl8xxxu_dma_agg_timeout <= 127) 4455 timeout = rtl8xxxu_dma_agg_timeout; 4456 else 4457 dev_err(&priv->udev->dev, 4458 "%s: Invalid dma_agg_timeout: %i\n", 4459 __func__, rtl8xxxu_dma_agg_timeout); 4460 } 4461 4462 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH + 1, timeout); 4463 rtl8xxxu_write8(priv, REG_USB_DMA_AGG_TO, timeout); 4464 priv->rx_buf_aggregation = 1; 4465 } 4466 4467 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg) 4468 { 4469 u32 val32; 4470 u8 rate_idx = 0; 4471 4472 rate_cfg &= RESPONSE_RATE_BITMAP_ALL; 4473 4474 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 4475 val32 &= ~RESPONSE_RATE_BITMAP_ALL; 4476 val32 |= rate_cfg; 4477 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 4478 4479 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg); 4480 4481 while (rate_cfg) { 4482 rate_cfg = (rate_cfg >> 1); 4483 rate_idx++; 4484 } 4485 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx); 4486 } 4487 4488 static void 4489 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 4490 struct ieee80211_bss_conf *bss_conf, u32 changed) 4491 { 4492 struct rtl8xxxu_priv *priv = hw->priv; 4493 struct device *dev = &priv->udev->dev; 4494 struct ieee80211_sta *sta; 4495 u32 val32; 4496 u8 val8; 4497 4498 if (changed & BSS_CHANGED_ASSOC) { 4499 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc); 4500 4501 rtl8xxxu_set_linktype(priv, vif->type); 4502 4503 if (bss_conf->assoc) { 4504 u32 ramask; 4505 int sgi = 0; 4506 4507 rcu_read_lock(); 4508 sta = ieee80211_find_sta(vif, bss_conf->bssid); 4509 if (!sta) { 4510 dev_info(dev, "%s: ASSOC no sta found\n", 4511 __func__); 4512 rcu_read_unlock(); 4513 goto error; 4514 } 4515 4516 if (sta->ht_cap.ht_supported) 4517 dev_info(dev, "%s: HT supported\n", __func__); 4518 if (sta->vht_cap.vht_supported) 4519 dev_info(dev, "%s: VHT supported\n", __func__); 4520 4521 /* TODO: Set bits 28-31 for rate adaptive id */ 4522 ramask = (sta->supp_rates[0] & 0xfff) | 4523 sta->ht_cap.mcs.rx_mask[0] << 12 | 4524 sta->ht_cap.mcs.rx_mask[1] << 20; 4525 if (sta->ht_cap.cap & 4526 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)) 4527 sgi = 1; 4528 rcu_read_unlock(); 4529 4530 priv->fops->update_rate_mask(priv, ramask, sgi); 4531 4532 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff); 4533 4534 rtl8xxxu_stop_tx_beacon(priv); 4535 4536 /* joinbss sequence */ 4537 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT, 4538 0xc000 | bss_conf->aid); 4539 4540 priv->fops->report_connect(priv, 0, true); 4541 } else { 4542 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 4543 val8 |= BEACON_DISABLE_TSF_UPDATE; 4544 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 4545 4546 priv->fops->report_connect(priv, 0, false); 4547 } 4548 } 4549 4550 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 4551 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n", 4552 bss_conf->use_short_preamble); 4553 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 4554 if (bss_conf->use_short_preamble) 4555 val32 |= RSR_ACK_SHORT_PREAMBLE; 4556 else 4557 val32 &= ~RSR_ACK_SHORT_PREAMBLE; 4558 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 4559 } 4560 4561 if (changed & BSS_CHANGED_ERP_SLOT) { 4562 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n", 4563 bss_conf->use_short_slot); 4564 4565 if (bss_conf->use_short_slot) 4566 val8 = 9; 4567 else 4568 val8 = 20; 4569 rtl8xxxu_write8(priv, REG_SLOT, val8); 4570 } 4571 4572 if (changed & BSS_CHANGED_BSSID) { 4573 dev_dbg(dev, "Changed BSSID!\n"); 4574 rtl8xxxu_set_bssid(priv, bss_conf->bssid); 4575 } 4576 4577 if (changed & BSS_CHANGED_BASIC_RATES) { 4578 dev_dbg(dev, "Changed BASIC_RATES!\n"); 4579 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates); 4580 } 4581 error: 4582 return; 4583 } 4584 4585 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue) 4586 { 4587 u32 rtlqueue; 4588 4589 switch (queue) { 4590 case IEEE80211_AC_VO: 4591 rtlqueue = TXDESC_QUEUE_VO; 4592 break; 4593 case IEEE80211_AC_VI: 4594 rtlqueue = TXDESC_QUEUE_VI; 4595 break; 4596 case IEEE80211_AC_BE: 4597 rtlqueue = TXDESC_QUEUE_BE; 4598 break; 4599 case IEEE80211_AC_BK: 4600 rtlqueue = TXDESC_QUEUE_BK; 4601 break; 4602 default: 4603 rtlqueue = TXDESC_QUEUE_BE; 4604 } 4605 4606 return rtlqueue; 4607 } 4608 4609 static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb) 4610 { 4611 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 4612 u32 queue; 4613 4614 if (ieee80211_is_mgmt(hdr->frame_control)) 4615 queue = TXDESC_QUEUE_MGNT; 4616 else 4617 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb)); 4618 4619 return queue; 4620 } 4621 4622 /* 4623 * Despite newer chips 8723b/8812/8821 having a larger TX descriptor 4624 * format. The descriptor checksum is still only calculated over the 4625 * initial 32 bytes of the descriptor! 4626 */ 4627 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc) 4628 { 4629 __le16 *ptr = (__le16 *)tx_desc; 4630 u16 csum = 0; 4631 int i; 4632 4633 /* 4634 * Clear csum field before calculation, as the csum field is 4635 * in the middle of the struct. 4636 */ 4637 tx_desc->csum = cpu_to_le16(0); 4638 4639 for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++) 4640 csum = csum ^ le16_to_cpu(ptr[i]); 4641 4642 tx_desc->csum |= cpu_to_le16(csum); 4643 } 4644 4645 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv) 4646 { 4647 struct rtl8xxxu_tx_urb *tx_urb, *tmp; 4648 unsigned long flags; 4649 4650 spin_lock_irqsave(&priv->tx_urb_lock, flags); 4651 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) { 4652 list_del(&tx_urb->list); 4653 priv->tx_urb_free_count--; 4654 usb_free_urb(&tx_urb->urb); 4655 } 4656 spin_unlock_irqrestore(&priv->tx_urb_lock, flags); 4657 } 4658 4659 static struct rtl8xxxu_tx_urb * 4660 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv) 4661 { 4662 struct rtl8xxxu_tx_urb *tx_urb; 4663 unsigned long flags; 4664 4665 spin_lock_irqsave(&priv->tx_urb_lock, flags); 4666 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list, 4667 struct rtl8xxxu_tx_urb, list); 4668 if (tx_urb) { 4669 list_del(&tx_urb->list); 4670 priv->tx_urb_free_count--; 4671 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER && 4672 !priv->tx_stopped) { 4673 priv->tx_stopped = true; 4674 ieee80211_stop_queues(priv->hw); 4675 } 4676 } 4677 4678 spin_unlock_irqrestore(&priv->tx_urb_lock, flags); 4679 4680 return tx_urb; 4681 } 4682 4683 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv, 4684 struct rtl8xxxu_tx_urb *tx_urb) 4685 { 4686 unsigned long flags; 4687 4688 INIT_LIST_HEAD(&tx_urb->list); 4689 4690 spin_lock_irqsave(&priv->tx_urb_lock, flags); 4691 4692 list_add(&tx_urb->list, &priv->tx_urb_free_list); 4693 priv->tx_urb_free_count++; 4694 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER && 4695 priv->tx_stopped) { 4696 priv->tx_stopped = false; 4697 ieee80211_wake_queues(priv->hw); 4698 } 4699 4700 spin_unlock_irqrestore(&priv->tx_urb_lock, flags); 4701 } 4702 4703 static void rtl8xxxu_tx_complete(struct urb *urb) 4704 { 4705 struct sk_buff *skb = (struct sk_buff *)urb->context; 4706 struct ieee80211_tx_info *tx_info; 4707 struct ieee80211_hw *hw; 4708 struct rtl8xxxu_priv *priv; 4709 struct rtl8xxxu_tx_urb *tx_urb = 4710 container_of(urb, struct rtl8xxxu_tx_urb, urb); 4711 4712 tx_info = IEEE80211_SKB_CB(skb); 4713 hw = tx_info->rate_driver_data[0]; 4714 priv = hw->priv; 4715 4716 skb_pull(skb, priv->fops->tx_desc_size); 4717 4718 ieee80211_tx_info_clear_status(tx_info); 4719 tx_info->status.rates[0].idx = -1; 4720 tx_info->status.rates[0].count = 0; 4721 4722 if (!urb->status) 4723 tx_info->flags |= IEEE80211_TX_STAT_ACK; 4724 4725 ieee80211_tx_status_irqsafe(hw, skb); 4726 4727 rtl8xxxu_free_tx_urb(priv, tx_urb); 4728 } 4729 4730 static void rtl8xxxu_dump_action(struct device *dev, 4731 struct ieee80211_hdr *hdr) 4732 { 4733 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr; 4734 u16 cap, timeout; 4735 4736 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION)) 4737 return; 4738 4739 switch (mgmt->u.action.u.addba_resp.action_code) { 4740 case WLAN_ACTION_ADDBA_RESP: 4741 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab); 4742 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout); 4743 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: " 4744 "timeout %i, tid %02x, buf_size %02x, policy %02x, " 4745 "status %02x\n", 4746 timeout, 4747 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2, 4748 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6, 4749 (cap >> 1) & 0x1, 4750 le16_to_cpu(mgmt->u.action.u.addba_resp.status)); 4751 break; 4752 case WLAN_ACTION_ADDBA_REQ: 4753 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab); 4754 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout); 4755 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: " 4756 "timeout %i, tid %02x, buf_size %02x, policy %02x\n", 4757 timeout, 4758 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2, 4759 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6, 4760 (cap >> 1) & 0x1); 4761 break; 4762 default: 4763 dev_info(dev, "action frame %02x\n", 4764 mgmt->u.action.u.addba_resp.action_code); 4765 break; 4766 } 4767 } 4768 4769 /* 4770 * Fill in v1 (gen1) specific TX descriptor bits. 4771 * This format is used on 8188cu/8192cu/8723au 4772 */ 4773 void 4774 rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 4775 struct ieee80211_tx_info *tx_info, 4776 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 4777 bool short_preamble, bool ampdu_enable, u32 rts_rate) 4778 { 4779 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info); 4780 struct rtl8xxxu_priv *priv = hw->priv; 4781 struct device *dev = &priv->udev->dev; 4782 u32 rate; 4783 u16 rate_flags = tx_info->control.rates[0].flags; 4784 u16 seq_number; 4785 4786 if (rate_flags & IEEE80211_TX_RC_MCS && 4787 !ieee80211_is_mgmt(hdr->frame_control)) 4788 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0; 4789 else 4790 rate = tx_rate->hw_value; 4791 4792 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) 4793 dev_info(dev, "%s: TX rate: %d, pkt size %d\n", 4794 __func__, rate, cpu_to_le16(tx_desc->pkt_size)); 4795 4796 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 4797 4798 tx_desc->txdw5 = cpu_to_le32(rate); 4799 4800 if (ieee80211_is_data(hdr->frame_control)) 4801 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00); 4802 4803 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT); 4804 4805 if (ampdu_enable) 4806 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE); 4807 else 4808 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK); 4809 4810 if (ieee80211_is_mgmt(hdr->frame_control)) { 4811 tx_desc->txdw5 = cpu_to_le32(rate); 4812 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE); 4813 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT); 4814 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE); 4815 } 4816 4817 if (ieee80211_is_data_qos(hdr->frame_control)) 4818 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS); 4819 4820 if (short_preamble) 4821 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE); 4822 4823 if (sgi) 4824 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI); 4825 4826 /* 4827 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled 4828 */ 4829 tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT); 4830 if (rate_flags & IEEE80211_TX_RC_USE_RTS_CTS) { 4831 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE); 4832 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); 4833 } else if (rate_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 4834 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE); 4835 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); 4836 } 4837 } 4838 4839 /* 4840 * Fill in v2 (gen2) specific TX descriptor bits. 4841 * This format is used on 8192eu/8723bu 4842 */ 4843 void 4844 rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 4845 struct ieee80211_tx_info *tx_info, 4846 struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi, 4847 bool short_preamble, bool ampdu_enable, u32 rts_rate) 4848 { 4849 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info); 4850 struct rtl8xxxu_priv *priv = hw->priv; 4851 struct device *dev = &priv->udev->dev; 4852 struct rtl8xxxu_txdesc40 *tx_desc40; 4853 u32 rate; 4854 u16 rate_flags = tx_info->control.rates[0].flags; 4855 u16 seq_number; 4856 4857 tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc32; 4858 4859 if (rate_flags & IEEE80211_TX_RC_MCS && 4860 !ieee80211_is_mgmt(hdr->frame_control)) 4861 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0; 4862 else 4863 rate = tx_rate->hw_value; 4864 4865 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) 4866 dev_info(dev, "%s: TX rate: %d, pkt size %d\n", 4867 __func__, rate, cpu_to_le16(tx_desc40->pkt_size)); 4868 4869 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 4870 4871 tx_desc40->txdw4 = cpu_to_le32(rate); 4872 if (ieee80211_is_data(hdr->frame_control)) { 4873 tx_desc40->txdw4 |= cpu_to_le32(0x1f << 4874 TXDESC40_DATA_RATE_FB_SHIFT); 4875 } 4876 4877 tx_desc40->txdw9 = cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT); 4878 4879 if (ampdu_enable) 4880 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE); 4881 else 4882 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK); 4883 4884 if (ieee80211_is_mgmt(hdr->frame_control)) { 4885 tx_desc40->txdw4 = cpu_to_le32(rate); 4886 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_USE_DRIVER_RATE); 4887 tx_desc40->txdw4 |= 4888 cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT); 4889 tx_desc40->txdw4 |= cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE); 4890 } 4891 4892 if (short_preamble) 4893 tx_desc40->txdw5 |= cpu_to_le32(TXDESC40_SHORT_PREAMBLE); 4894 4895 tx_desc40->txdw4 |= cpu_to_le32(rts_rate << TXDESC40_RTS_RATE_SHIFT); 4896 /* 4897 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled 4898 */ 4899 if (rate_flags & IEEE80211_TX_RC_USE_RTS_CTS) { 4900 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE); 4901 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE); 4902 } else if (rate_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 4903 /* 4904 * For some reason the vendor driver doesn't set 4905 * TXDESC40_HW_RTS_ENABLE for CTS to SELF 4906 */ 4907 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_CTS_SELF_ENABLE); 4908 } 4909 } 4910 4911 static void rtl8xxxu_tx(struct ieee80211_hw *hw, 4912 struct ieee80211_tx_control *control, 4913 struct sk_buff *skb) 4914 { 4915 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 4916 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 4917 struct rtl8xxxu_priv *priv = hw->priv; 4918 struct rtl8xxxu_txdesc32 *tx_desc; 4919 struct rtl8xxxu_tx_urb *tx_urb; 4920 struct ieee80211_sta *sta = NULL; 4921 struct ieee80211_vif *vif = tx_info->control.vif; 4922 struct device *dev = &priv->udev->dev; 4923 u32 queue, rts_rate; 4924 u16 pktlen = skb->len; 4925 u16 rate_flag = tx_info->control.rates[0].flags; 4926 int tx_desc_size = priv->fops->tx_desc_size; 4927 int ret; 4928 bool ampdu_enable, sgi = false, short_preamble = false; 4929 4930 if (skb_headroom(skb) < tx_desc_size) { 4931 dev_warn(dev, 4932 "%s: Not enough headroom (%i) for tx descriptor\n", 4933 __func__, skb_headroom(skb)); 4934 goto error; 4935 } 4936 4937 if (unlikely(skb->len > (65535 - tx_desc_size))) { 4938 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n", 4939 __func__, skb->len); 4940 goto error; 4941 } 4942 4943 tx_urb = rtl8xxxu_alloc_tx_urb(priv); 4944 if (!tx_urb) { 4945 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__); 4946 goto error; 4947 } 4948 4949 if (ieee80211_is_action(hdr->frame_control)) 4950 rtl8xxxu_dump_action(dev, hdr); 4951 4952 tx_info->rate_driver_data[0] = hw; 4953 4954 if (control && control->sta) 4955 sta = control->sta; 4956 4957 tx_desc = skb_push(skb, tx_desc_size); 4958 4959 memset(tx_desc, 0, tx_desc_size); 4960 tx_desc->pkt_size = cpu_to_le16(pktlen); 4961 tx_desc->pkt_offset = tx_desc_size; 4962 4963 tx_desc->txdw0 = 4964 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT; 4965 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) || 4966 is_broadcast_ether_addr(ieee80211_get_DA(hdr))) 4967 tx_desc->txdw0 |= TXDESC_BROADMULTICAST; 4968 4969 queue = rtl8xxxu_queue_select(hw, skb); 4970 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT); 4971 4972 if (tx_info->control.hw_key) { 4973 switch (tx_info->control.hw_key->cipher) { 4974 case WLAN_CIPHER_SUITE_WEP40: 4975 case WLAN_CIPHER_SUITE_WEP104: 4976 case WLAN_CIPHER_SUITE_TKIP: 4977 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4); 4978 break; 4979 case WLAN_CIPHER_SUITE_CCMP: 4980 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES); 4981 break; 4982 default: 4983 break; 4984 } 4985 } 4986 4987 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */ 4988 ampdu_enable = false; 4989 if (ieee80211_is_data_qos(hdr->frame_control) && sta) { 4990 if (sta->ht_cap.ht_supported) { 4991 u32 ampdu, val32; 4992 4993 ampdu = (u32)sta->ht_cap.ampdu_density; 4994 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT; 4995 tx_desc->txdw2 |= cpu_to_le32(val32); 4996 4997 ampdu_enable = true; 4998 } 4999 } 5000 5001 if (rate_flag & IEEE80211_TX_RC_SHORT_GI || 5002 (ieee80211_is_data_qos(hdr->frame_control) && 5003 sta && sta->ht_cap.cap & 5004 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) 5005 sgi = true; 5006 5007 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE || 5008 (sta && vif && vif->bss_conf.use_short_preamble)) 5009 short_preamble = true; 5010 5011 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) 5012 rts_rate = ieee80211_get_rts_cts_rate(hw, tx_info)->hw_value; 5013 else if (rate_flag & IEEE80211_TX_RC_USE_CTS_PROTECT) 5014 rts_rate = ieee80211_get_rts_cts_rate(hw, tx_info)->hw_value; 5015 else 5016 rts_rate = 0; 5017 5018 5019 priv->fops->fill_txdesc(hw, hdr, tx_info, tx_desc, sgi, short_preamble, 5020 ampdu_enable, rts_rate); 5021 5022 rtl8xxxu_calc_tx_desc_csum(tx_desc); 5023 5024 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue], 5025 skb->data, skb->len, rtl8xxxu_tx_complete, skb); 5026 5027 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor); 5028 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC); 5029 if (ret) { 5030 usb_unanchor_urb(&tx_urb->urb); 5031 rtl8xxxu_free_tx_urb(priv, tx_urb); 5032 goto error; 5033 } 5034 return; 5035 error: 5036 dev_kfree_skb(skb); 5037 } 5038 5039 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv, 5040 struct ieee80211_rx_status *rx_status, 5041 struct rtl8723au_phy_stats *phy_stats, 5042 u32 rxmcs) 5043 { 5044 if (phy_stats->sgi_en) 5045 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 5046 5047 if (rxmcs < DESC_RATE_6M) { 5048 /* 5049 * Handle PHY stats for CCK rates 5050 */ 5051 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a; 5052 5053 switch (cck_agc_rpt & 0xc0) { 5054 case 0xc0: 5055 rx_status->signal = -46 - (cck_agc_rpt & 0x3e); 5056 break; 5057 case 0x80: 5058 rx_status->signal = -26 - (cck_agc_rpt & 0x3e); 5059 break; 5060 case 0x40: 5061 rx_status->signal = -12 - (cck_agc_rpt & 0x3e); 5062 break; 5063 case 0x00: 5064 rx_status->signal = 16 - (cck_agc_rpt & 0x3e); 5065 break; 5066 } 5067 } else { 5068 rx_status->signal = 5069 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110; 5070 } 5071 } 5072 5073 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv) 5074 { 5075 struct rtl8xxxu_rx_urb *rx_urb, *tmp; 5076 unsigned long flags; 5077 5078 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5079 5080 list_for_each_entry_safe(rx_urb, tmp, 5081 &priv->rx_urb_pending_list, list) { 5082 list_del(&rx_urb->list); 5083 priv->rx_urb_pending_count--; 5084 usb_free_urb(&rx_urb->urb); 5085 } 5086 5087 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5088 } 5089 5090 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv, 5091 struct rtl8xxxu_rx_urb *rx_urb) 5092 { 5093 struct sk_buff *skb; 5094 unsigned long flags; 5095 int pending = 0; 5096 5097 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5098 5099 if (!priv->shutdown) { 5100 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list); 5101 priv->rx_urb_pending_count++; 5102 pending = priv->rx_urb_pending_count; 5103 } else { 5104 skb = (struct sk_buff *)rx_urb->urb.context; 5105 dev_kfree_skb(skb); 5106 usb_free_urb(&rx_urb->urb); 5107 } 5108 5109 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5110 5111 if (pending > RTL8XXXU_RX_URB_PENDING_WATER) 5112 schedule_work(&priv->rx_urb_wq); 5113 } 5114 5115 static void rtl8xxxu_rx_urb_work(struct work_struct *work) 5116 { 5117 struct rtl8xxxu_priv *priv; 5118 struct rtl8xxxu_rx_urb *rx_urb, *tmp; 5119 struct list_head local; 5120 struct sk_buff *skb; 5121 unsigned long flags; 5122 int ret; 5123 5124 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq); 5125 INIT_LIST_HEAD(&local); 5126 5127 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5128 5129 list_splice_init(&priv->rx_urb_pending_list, &local); 5130 priv->rx_urb_pending_count = 0; 5131 5132 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5133 5134 list_for_each_entry_safe(rx_urb, tmp, &local, list) { 5135 list_del_init(&rx_urb->list); 5136 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb); 5137 /* 5138 * If out of memory or temporary error, put it back on the 5139 * queue and try again. Otherwise the device is dead/gone 5140 * and we should drop it. 5141 */ 5142 switch (ret) { 5143 case 0: 5144 break; 5145 case -ENOMEM: 5146 case -EAGAIN: 5147 rtl8xxxu_queue_rx_urb(priv, rx_urb); 5148 break; 5149 default: 5150 pr_info("failed to requeue urb %i\n", ret); 5151 skb = (struct sk_buff *)rx_urb->urb.context; 5152 dev_kfree_skb(skb); 5153 usb_free_urb(&rx_urb->urb); 5154 } 5155 } 5156 } 5157 5158 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv, 5159 struct sk_buff *skb) 5160 { 5161 struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data; 5162 struct device *dev = &priv->udev->dev; 5163 int len; 5164 5165 len = skb->len - 2; 5166 5167 dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n", 5168 c2h->id, c2h->seq, len, c2h->bt_info.response_source); 5169 5170 switch(c2h->id) { 5171 case C2H_8723B_BT_INFO: 5172 if (c2h->bt_info.response_source > 5173 BT_INFO_SRC_8723B_BT_ACTIVE_SEND) 5174 dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n"); 5175 else 5176 dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n"); 5177 5178 if (c2h->bt_info.bt_has_reset) 5179 dev_dbg(dev, "BT has been reset\n"); 5180 if (c2h->bt_info.tx_rx_mask) 5181 dev_dbg(dev, "BT TRx mask\n"); 5182 5183 break; 5184 case C2H_8723B_BT_MP_INFO: 5185 dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n", 5186 c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status); 5187 break; 5188 case C2H_8723B_RA_REPORT: 5189 dev_dbg(dev, 5190 "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n", 5191 c2h->ra_report.rate, c2h->ra_report.dummy0_0, 5192 c2h->ra_report.macid, c2h->ra_report.noisy_state); 5193 break; 5194 default: 5195 dev_info(dev, "Unhandled C2H event %02x seq %02x\n", 5196 c2h->id, c2h->seq); 5197 print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE, 5198 16, 1, c2h->raw.payload, len, false); 5199 break; 5200 } 5201 } 5202 5203 int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb) 5204 { 5205 struct ieee80211_hw *hw = priv->hw; 5206 struct ieee80211_rx_status *rx_status; 5207 struct rtl8xxxu_rxdesc16 *rx_desc; 5208 struct rtl8723au_phy_stats *phy_stats; 5209 struct sk_buff *next_skb = NULL; 5210 __le32 *_rx_desc_le; 5211 u32 *_rx_desc; 5212 int drvinfo_sz, desc_shift; 5213 int i, pkt_cnt, pkt_len, urb_len, pkt_offset; 5214 5215 urb_len = skb->len; 5216 pkt_cnt = 0; 5217 5218 do { 5219 rx_desc = (struct rtl8xxxu_rxdesc16 *)skb->data; 5220 _rx_desc_le = (__le32 *)skb->data; 5221 _rx_desc = (u32 *)skb->data; 5222 5223 for (i = 0; 5224 i < (sizeof(struct rtl8xxxu_rxdesc16) / sizeof(u32)); i++) 5225 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]); 5226 5227 /* 5228 * Only read pkt_cnt from the header if we're parsing the 5229 * first packet 5230 */ 5231 if (!pkt_cnt) 5232 pkt_cnt = rx_desc->pkt_cnt; 5233 pkt_len = rx_desc->pktlen; 5234 5235 drvinfo_sz = rx_desc->drvinfo_sz * 8; 5236 desc_shift = rx_desc->shift; 5237 pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift + 5238 sizeof(struct rtl8xxxu_rxdesc16), 128); 5239 5240 /* 5241 * Only clone the skb if there's enough data at the end to 5242 * at least cover the rx descriptor 5243 */ 5244 if (pkt_cnt > 1 && 5245 urb_len > (pkt_offset + sizeof(struct rtl8xxxu_rxdesc16))) 5246 next_skb = skb_clone(skb, GFP_ATOMIC); 5247 5248 rx_status = IEEE80211_SKB_RXCB(skb); 5249 memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); 5250 5251 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc16)); 5252 5253 phy_stats = (struct rtl8723au_phy_stats *)skb->data; 5254 5255 skb_pull(skb, drvinfo_sz + desc_shift); 5256 5257 skb_trim(skb, pkt_len); 5258 5259 if (rx_desc->phy_stats) 5260 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats, 5261 rx_desc->rxmcs); 5262 5263 rx_status->mactime = rx_desc->tsfl; 5264 rx_status->flag |= RX_FLAG_MACTIME_START; 5265 5266 if (!rx_desc->swdec) 5267 rx_status->flag |= RX_FLAG_DECRYPTED; 5268 if (rx_desc->crc32) 5269 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 5270 if (rx_desc->bw) 5271 rx_status->bw = RATE_INFO_BW_40; 5272 5273 if (rx_desc->rxht) { 5274 rx_status->encoding = RX_ENC_HT; 5275 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0; 5276 } else { 5277 rx_status->rate_idx = rx_desc->rxmcs; 5278 } 5279 5280 rx_status->freq = hw->conf.chandef.chan->center_freq; 5281 rx_status->band = hw->conf.chandef.chan->band; 5282 5283 ieee80211_rx_irqsafe(hw, skb); 5284 5285 skb = next_skb; 5286 if (skb) 5287 skb_pull(next_skb, pkt_offset); 5288 5289 pkt_cnt--; 5290 urb_len -= pkt_offset; 5291 } while (skb && urb_len > 0 && pkt_cnt > 0); 5292 5293 return RX_TYPE_DATA_PKT; 5294 } 5295 5296 int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb) 5297 { 5298 struct ieee80211_hw *hw = priv->hw; 5299 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 5300 struct rtl8xxxu_rxdesc24 *rx_desc = 5301 (struct rtl8xxxu_rxdesc24 *)skb->data; 5302 struct rtl8723au_phy_stats *phy_stats; 5303 __le32 *_rx_desc_le = (__le32 *)skb->data; 5304 u32 *_rx_desc = (u32 *)skb->data; 5305 int drvinfo_sz, desc_shift; 5306 int i; 5307 5308 for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++) 5309 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]); 5310 5311 memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); 5312 5313 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24)); 5314 5315 phy_stats = (struct rtl8723au_phy_stats *)skb->data; 5316 5317 drvinfo_sz = rx_desc->drvinfo_sz * 8; 5318 desc_shift = rx_desc->shift; 5319 skb_pull(skb, drvinfo_sz + desc_shift); 5320 5321 if (rx_desc->rpt_sel) { 5322 struct device *dev = &priv->udev->dev; 5323 dev_dbg(dev, "%s: C2H packet\n", __func__); 5324 rtl8723bu_handle_c2h(priv, skb); 5325 dev_kfree_skb(skb); 5326 return RX_TYPE_C2H; 5327 } 5328 5329 if (rx_desc->phy_stats) 5330 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats, 5331 rx_desc->rxmcs); 5332 5333 rx_status->mactime = rx_desc->tsfl; 5334 rx_status->flag |= RX_FLAG_MACTIME_START; 5335 5336 if (!rx_desc->swdec) 5337 rx_status->flag |= RX_FLAG_DECRYPTED; 5338 if (rx_desc->crc32) 5339 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 5340 if (rx_desc->bw) 5341 rx_status->bw = RATE_INFO_BW_40; 5342 5343 if (rx_desc->rxmcs >= DESC_RATE_MCS0) { 5344 rx_status->encoding = RX_ENC_HT; 5345 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0; 5346 } else { 5347 rx_status->rate_idx = rx_desc->rxmcs; 5348 } 5349 5350 rx_status->freq = hw->conf.chandef.chan->center_freq; 5351 rx_status->band = hw->conf.chandef.chan->band; 5352 5353 ieee80211_rx_irqsafe(hw, skb); 5354 return RX_TYPE_DATA_PKT; 5355 } 5356 5357 static void rtl8xxxu_rx_complete(struct urb *urb) 5358 { 5359 struct rtl8xxxu_rx_urb *rx_urb = 5360 container_of(urb, struct rtl8xxxu_rx_urb, urb); 5361 struct ieee80211_hw *hw = rx_urb->hw; 5362 struct rtl8xxxu_priv *priv = hw->priv; 5363 struct sk_buff *skb = (struct sk_buff *)urb->context; 5364 struct device *dev = &priv->udev->dev; 5365 5366 skb_put(skb, urb->actual_length); 5367 5368 if (urb->status == 0) { 5369 priv->fops->parse_rx_desc(priv, skb); 5370 5371 skb = NULL; 5372 rx_urb->urb.context = NULL; 5373 rtl8xxxu_queue_rx_urb(priv, rx_urb); 5374 } else { 5375 dev_dbg(dev, "%s: status %i\n", __func__, urb->status); 5376 goto cleanup; 5377 } 5378 return; 5379 5380 cleanup: 5381 usb_free_urb(urb); 5382 dev_kfree_skb(skb); 5383 return; 5384 } 5385 5386 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv, 5387 struct rtl8xxxu_rx_urb *rx_urb) 5388 { 5389 struct rtl8xxxu_fileops *fops = priv->fops; 5390 struct sk_buff *skb; 5391 int skb_size; 5392 int ret, rx_desc_sz; 5393 5394 rx_desc_sz = fops->rx_desc_size; 5395 5396 if (priv->rx_buf_aggregation && fops->rx_agg_buf_size) { 5397 skb_size = fops->rx_agg_buf_size; 5398 skb_size += (rx_desc_sz + sizeof(struct rtl8723au_phy_stats)); 5399 } else { 5400 skb_size = IEEE80211_MAX_FRAME_LEN; 5401 } 5402 5403 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL); 5404 if (!skb) 5405 return -ENOMEM; 5406 5407 memset(skb->data, 0, rx_desc_sz); 5408 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data, 5409 skb_size, rtl8xxxu_rx_complete, skb); 5410 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor); 5411 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC); 5412 if (ret) 5413 usb_unanchor_urb(&rx_urb->urb); 5414 return ret; 5415 } 5416 5417 static void rtl8xxxu_int_complete(struct urb *urb) 5418 { 5419 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context; 5420 struct device *dev = &priv->udev->dev; 5421 int ret; 5422 5423 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_INTERRUPT) 5424 dev_dbg(dev, "%s: status %i\n", __func__, urb->status); 5425 if (urb->status == 0) { 5426 usb_anchor_urb(urb, &priv->int_anchor); 5427 ret = usb_submit_urb(urb, GFP_ATOMIC); 5428 if (ret) 5429 usb_unanchor_urb(urb); 5430 } else { 5431 dev_dbg(dev, "%s: Error %i\n", __func__, urb->status); 5432 } 5433 } 5434 5435 5436 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw) 5437 { 5438 struct rtl8xxxu_priv *priv = hw->priv; 5439 struct urb *urb; 5440 u32 val32; 5441 int ret; 5442 5443 urb = usb_alloc_urb(0, GFP_KERNEL); 5444 if (!urb) 5445 return -ENOMEM; 5446 5447 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt, 5448 priv->int_buf, USB_INTR_CONTENT_LENGTH, 5449 rtl8xxxu_int_complete, priv, 1); 5450 usb_anchor_urb(urb, &priv->int_anchor); 5451 ret = usb_submit_urb(urb, GFP_KERNEL); 5452 if (ret) { 5453 usb_unanchor_urb(urb); 5454 goto error; 5455 } 5456 5457 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR); 5458 val32 |= USB_HIMR_CPWM; 5459 rtl8xxxu_write32(priv, REG_USB_HIMR, val32); 5460 5461 error: 5462 return ret; 5463 } 5464 5465 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw, 5466 struct ieee80211_vif *vif) 5467 { 5468 struct rtl8xxxu_priv *priv = hw->priv; 5469 int ret; 5470 u8 val8; 5471 5472 switch (vif->type) { 5473 case NL80211_IFTYPE_STATION: 5474 rtl8xxxu_stop_tx_beacon(priv); 5475 5476 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 5477 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE | 5478 BEACON_DISABLE_TSF_UPDATE; 5479 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 5480 ret = 0; 5481 break; 5482 default: 5483 ret = -EOPNOTSUPP; 5484 } 5485 5486 rtl8xxxu_set_linktype(priv, vif->type); 5487 5488 return ret; 5489 } 5490 5491 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw, 5492 struct ieee80211_vif *vif) 5493 { 5494 struct rtl8xxxu_priv *priv = hw->priv; 5495 5496 dev_dbg(&priv->udev->dev, "%s\n", __func__); 5497 } 5498 5499 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed) 5500 { 5501 struct rtl8xxxu_priv *priv = hw->priv; 5502 struct device *dev = &priv->udev->dev; 5503 u16 val16; 5504 int ret = 0, channel; 5505 bool ht40; 5506 5507 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL) 5508 dev_info(dev, 5509 "%s: channel: %i (changed %08x chandef.width %02x)\n", 5510 __func__, hw->conf.chandef.chan->hw_value, 5511 changed, hw->conf.chandef.width); 5512 5513 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) { 5514 val16 = ((hw->conf.long_frame_max_tx_count << 5515 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) | 5516 ((hw->conf.short_frame_max_tx_count << 5517 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK); 5518 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16); 5519 } 5520 5521 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { 5522 switch (hw->conf.chandef.width) { 5523 case NL80211_CHAN_WIDTH_20_NOHT: 5524 case NL80211_CHAN_WIDTH_20: 5525 ht40 = false; 5526 break; 5527 case NL80211_CHAN_WIDTH_40: 5528 ht40 = true; 5529 break; 5530 default: 5531 ret = -ENOTSUPP; 5532 goto exit; 5533 } 5534 5535 channel = hw->conf.chandef.chan->hw_value; 5536 5537 priv->fops->set_tx_power(priv, channel, ht40); 5538 5539 priv->fops->config_channel(hw); 5540 } 5541 5542 exit: 5543 return ret; 5544 } 5545 5546 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw, 5547 struct ieee80211_vif *vif, u16 queue, 5548 const struct ieee80211_tx_queue_params *param) 5549 { 5550 struct rtl8xxxu_priv *priv = hw->priv; 5551 struct device *dev = &priv->udev->dev; 5552 u32 val32; 5553 u8 aifs, acm_ctrl, acm_bit; 5554 5555 aifs = param->aifs; 5556 5557 val32 = aifs | 5558 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT | 5559 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT | 5560 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT; 5561 5562 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL); 5563 dev_dbg(dev, 5564 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n", 5565 __func__, queue, val32, param->acm, acm_ctrl); 5566 5567 switch (queue) { 5568 case IEEE80211_AC_VO: 5569 acm_bit = ACM_HW_CTRL_VO; 5570 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32); 5571 break; 5572 case IEEE80211_AC_VI: 5573 acm_bit = ACM_HW_CTRL_VI; 5574 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32); 5575 break; 5576 case IEEE80211_AC_BE: 5577 acm_bit = ACM_HW_CTRL_BE; 5578 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32); 5579 break; 5580 case IEEE80211_AC_BK: 5581 acm_bit = ACM_HW_CTRL_BK; 5582 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32); 5583 break; 5584 default: 5585 acm_bit = 0; 5586 break; 5587 } 5588 5589 if (param->acm) 5590 acm_ctrl |= acm_bit; 5591 else 5592 acm_ctrl &= ~acm_bit; 5593 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl); 5594 5595 return 0; 5596 } 5597 5598 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw, 5599 unsigned int changed_flags, 5600 unsigned int *total_flags, u64 multicast) 5601 { 5602 struct rtl8xxxu_priv *priv = hw->priv; 5603 u32 rcr = rtl8xxxu_read32(priv, REG_RCR); 5604 5605 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n", 5606 __func__, changed_flags, *total_flags); 5607 5608 /* 5609 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR) 5610 */ 5611 5612 if (*total_flags & FIF_FCSFAIL) 5613 rcr |= RCR_ACCEPT_CRC32; 5614 else 5615 rcr &= ~RCR_ACCEPT_CRC32; 5616 5617 /* 5618 * FIF_PLCPFAIL not supported? 5619 */ 5620 5621 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) 5622 rcr &= ~RCR_CHECK_BSSID_BEACON; 5623 else 5624 rcr |= RCR_CHECK_BSSID_BEACON; 5625 5626 if (*total_flags & FIF_CONTROL) 5627 rcr |= RCR_ACCEPT_CTRL_FRAME; 5628 else 5629 rcr &= ~RCR_ACCEPT_CTRL_FRAME; 5630 5631 if (*total_flags & FIF_OTHER_BSS) { 5632 rcr |= RCR_ACCEPT_AP; 5633 rcr &= ~RCR_CHECK_BSSID_MATCH; 5634 } else { 5635 rcr &= ~RCR_ACCEPT_AP; 5636 rcr |= RCR_CHECK_BSSID_MATCH; 5637 } 5638 5639 if (*total_flags & FIF_PSPOLL) 5640 rcr |= RCR_ACCEPT_PM; 5641 else 5642 rcr &= ~RCR_ACCEPT_PM; 5643 5644 /* 5645 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted 5646 */ 5647 5648 rtl8xxxu_write32(priv, REG_RCR, rcr); 5649 5650 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC | 5651 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL | 5652 FIF_PROBE_REQ); 5653 } 5654 5655 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts) 5656 { 5657 if (rts > 2347) 5658 return -EINVAL; 5659 5660 return 0; 5661 } 5662 5663 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 5664 struct ieee80211_vif *vif, 5665 struct ieee80211_sta *sta, 5666 struct ieee80211_key_conf *key) 5667 { 5668 struct rtl8xxxu_priv *priv = hw->priv; 5669 struct device *dev = &priv->udev->dev; 5670 u8 mac_addr[ETH_ALEN]; 5671 u8 val8; 5672 u16 val16; 5673 u32 val32; 5674 int retval = -EOPNOTSUPP; 5675 5676 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n", 5677 __func__, cmd, key->cipher, key->keyidx); 5678 5679 if (vif->type != NL80211_IFTYPE_STATION) 5680 return -EOPNOTSUPP; 5681 5682 if (key->keyidx > 3) 5683 return -EOPNOTSUPP; 5684 5685 switch (key->cipher) { 5686 case WLAN_CIPHER_SUITE_WEP40: 5687 case WLAN_CIPHER_SUITE_WEP104: 5688 5689 break; 5690 case WLAN_CIPHER_SUITE_CCMP: 5691 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; 5692 break; 5693 case WLAN_CIPHER_SUITE_TKIP: 5694 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 5695 break; 5696 default: 5697 return -EOPNOTSUPP; 5698 } 5699 5700 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { 5701 dev_dbg(dev, "%s: pairwise key\n", __func__); 5702 ether_addr_copy(mac_addr, sta->addr); 5703 } else { 5704 dev_dbg(dev, "%s: group key\n", __func__); 5705 eth_broadcast_addr(mac_addr); 5706 } 5707 5708 val16 = rtl8xxxu_read16(priv, REG_CR); 5709 val16 |= CR_SECURITY_ENABLE; 5710 rtl8xxxu_write16(priv, REG_CR, val16); 5711 5712 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY | 5713 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY; 5714 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY; 5715 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8); 5716 5717 switch (cmd) { 5718 case SET_KEY: 5719 key->hw_key_idx = key->keyidx; 5720 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 5721 rtl8xxxu_cam_write(priv, key, mac_addr); 5722 retval = 0; 5723 break; 5724 case DISABLE_KEY: 5725 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000); 5726 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE | 5727 key->keyidx << CAM_CMD_KEY_SHIFT; 5728 rtl8xxxu_write32(priv, REG_CAM_CMD, val32); 5729 retval = 0; 5730 break; 5731 default: 5732 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd); 5733 } 5734 5735 return retval; 5736 } 5737 5738 static int 5739 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 5740 struct ieee80211_ampdu_params *params) 5741 { 5742 struct rtl8xxxu_priv *priv = hw->priv; 5743 struct device *dev = &priv->udev->dev; 5744 u8 ampdu_factor, ampdu_density; 5745 struct ieee80211_sta *sta = params->sta; 5746 enum ieee80211_ampdu_mlme_action action = params->action; 5747 5748 switch (action) { 5749 case IEEE80211_AMPDU_TX_START: 5750 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__); 5751 ampdu_factor = sta->ht_cap.ampdu_factor; 5752 ampdu_density = sta->ht_cap.ampdu_density; 5753 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor); 5754 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density); 5755 dev_dbg(dev, 5756 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n", 5757 ampdu_factor, ampdu_density); 5758 break; 5759 case IEEE80211_AMPDU_TX_STOP_FLUSH: 5760 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__); 5761 rtl8xxxu_set_ampdu_factor(priv, 0); 5762 rtl8xxxu_set_ampdu_min_space(priv, 0); 5763 break; 5764 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 5765 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n", 5766 __func__); 5767 rtl8xxxu_set_ampdu_factor(priv, 0); 5768 rtl8xxxu_set_ampdu_min_space(priv, 0); 5769 break; 5770 case IEEE80211_AMPDU_RX_START: 5771 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__); 5772 break; 5773 case IEEE80211_AMPDU_RX_STOP: 5774 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__); 5775 break; 5776 default: 5777 break; 5778 } 5779 return 0; 5780 } 5781 5782 static int rtl8xxxu_start(struct ieee80211_hw *hw) 5783 { 5784 struct rtl8xxxu_priv *priv = hw->priv; 5785 struct rtl8xxxu_rx_urb *rx_urb; 5786 struct rtl8xxxu_tx_urb *tx_urb; 5787 unsigned long flags; 5788 int ret, i; 5789 5790 ret = 0; 5791 5792 init_usb_anchor(&priv->rx_anchor); 5793 init_usb_anchor(&priv->tx_anchor); 5794 init_usb_anchor(&priv->int_anchor); 5795 5796 priv->fops->enable_rf(priv); 5797 if (priv->usb_interrupts) { 5798 ret = rtl8xxxu_submit_int_urb(hw); 5799 if (ret) 5800 goto exit; 5801 } 5802 5803 for (i = 0; i < RTL8XXXU_TX_URBS; i++) { 5804 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL); 5805 if (!tx_urb) { 5806 if (!i) 5807 ret = -ENOMEM; 5808 5809 goto error_out; 5810 } 5811 usb_init_urb(&tx_urb->urb); 5812 INIT_LIST_HEAD(&tx_urb->list); 5813 tx_urb->hw = hw; 5814 list_add(&tx_urb->list, &priv->tx_urb_free_list); 5815 priv->tx_urb_free_count++; 5816 } 5817 5818 priv->tx_stopped = false; 5819 5820 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5821 priv->shutdown = false; 5822 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5823 5824 for (i = 0; i < RTL8XXXU_RX_URBS; i++) { 5825 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL); 5826 if (!rx_urb) { 5827 if (!i) 5828 ret = -ENOMEM; 5829 5830 goto error_out; 5831 } 5832 usb_init_urb(&rx_urb->urb); 5833 INIT_LIST_HEAD(&rx_urb->list); 5834 rx_urb->hw = hw; 5835 5836 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb); 5837 } 5838 exit: 5839 /* 5840 * Accept all data and mgmt frames 5841 */ 5842 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff); 5843 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff); 5844 5845 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e); 5846 5847 return ret; 5848 5849 error_out: 5850 rtl8xxxu_free_tx_resources(priv); 5851 /* 5852 * Disable all data and mgmt frames 5853 */ 5854 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); 5855 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000); 5856 5857 return ret; 5858 } 5859 5860 static void rtl8xxxu_stop(struct ieee80211_hw *hw) 5861 { 5862 struct rtl8xxxu_priv *priv = hw->priv; 5863 unsigned long flags; 5864 5865 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 5866 5867 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000); 5868 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); 5869 5870 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5871 priv->shutdown = true; 5872 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5873 5874 usb_kill_anchored_urbs(&priv->rx_anchor); 5875 usb_kill_anchored_urbs(&priv->tx_anchor); 5876 if (priv->usb_interrupts) 5877 usb_kill_anchored_urbs(&priv->int_anchor); 5878 5879 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 5880 5881 priv->fops->disable_rf(priv); 5882 5883 /* 5884 * Disable interrupts 5885 */ 5886 if (priv->usb_interrupts) 5887 rtl8xxxu_write32(priv, REG_USB_HIMR, 0); 5888 5889 rtl8xxxu_free_rx_resources(priv); 5890 rtl8xxxu_free_tx_resources(priv); 5891 } 5892 5893 static const struct ieee80211_ops rtl8xxxu_ops = { 5894 .tx = rtl8xxxu_tx, 5895 .add_interface = rtl8xxxu_add_interface, 5896 .remove_interface = rtl8xxxu_remove_interface, 5897 .config = rtl8xxxu_config, 5898 .conf_tx = rtl8xxxu_conf_tx, 5899 .bss_info_changed = rtl8xxxu_bss_info_changed, 5900 .configure_filter = rtl8xxxu_configure_filter, 5901 .set_rts_threshold = rtl8xxxu_set_rts_threshold, 5902 .start = rtl8xxxu_start, 5903 .stop = rtl8xxxu_stop, 5904 .sw_scan_start = rtl8xxxu_sw_scan_start, 5905 .sw_scan_complete = rtl8xxxu_sw_scan_complete, 5906 .set_key = rtl8xxxu_set_key, 5907 .ampdu_action = rtl8xxxu_ampdu_action, 5908 }; 5909 5910 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv, 5911 struct usb_interface *interface) 5912 { 5913 struct usb_interface_descriptor *interface_desc; 5914 struct usb_host_interface *host_interface; 5915 struct usb_endpoint_descriptor *endpoint; 5916 struct device *dev = &priv->udev->dev; 5917 int i, j = 0, endpoints; 5918 u8 dir, xtype, num; 5919 int ret = 0; 5920 5921 host_interface = &interface->altsetting[0]; 5922 interface_desc = &host_interface->desc; 5923 endpoints = interface_desc->bNumEndpoints; 5924 5925 for (i = 0; i < endpoints; i++) { 5926 endpoint = &host_interface->endpoint[i].desc; 5927 5928 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK; 5929 num = usb_endpoint_num(endpoint); 5930 xtype = usb_endpoint_type(endpoint); 5931 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 5932 dev_dbg(dev, 5933 "%s: endpoint: dir %02x, # %02x, type %02x\n", 5934 __func__, dir, num, xtype); 5935 if (usb_endpoint_dir_in(endpoint) && 5936 usb_endpoint_xfer_bulk(endpoint)) { 5937 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 5938 dev_dbg(dev, "%s: in endpoint num %i\n", 5939 __func__, num); 5940 5941 if (priv->pipe_in) { 5942 dev_warn(dev, 5943 "%s: Too many IN pipes\n", __func__); 5944 ret = -EINVAL; 5945 goto exit; 5946 } 5947 5948 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num); 5949 } 5950 5951 if (usb_endpoint_dir_in(endpoint) && 5952 usb_endpoint_xfer_int(endpoint)) { 5953 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 5954 dev_dbg(dev, "%s: interrupt endpoint num %i\n", 5955 __func__, num); 5956 5957 if (priv->pipe_interrupt) { 5958 dev_warn(dev, "%s: Too many INTERRUPT pipes\n", 5959 __func__); 5960 ret = -EINVAL; 5961 goto exit; 5962 } 5963 5964 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num); 5965 } 5966 5967 if (usb_endpoint_dir_out(endpoint) && 5968 usb_endpoint_xfer_bulk(endpoint)) { 5969 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 5970 dev_dbg(dev, "%s: out endpoint num %i\n", 5971 __func__, num); 5972 if (j >= RTL8XXXU_OUT_ENDPOINTS) { 5973 dev_warn(dev, 5974 "%s: Too many OUT pipes\n", __func__); 5975 ret = -EINVAL; 5976 goto exit; 5977 } 5978 priv->out_ep[j++] = num; 5979 } 5980 } 5981 exit: 5982 priv->nr_out_eps = j; 5983 return ret; 5984 } 5985 5986 static int rtl8xxxu_probe(struct usb_interface *interface, 5987 const struct usb_device_id *id) 5988 { 5989 struct rtl8xxxu_priv *priv; 5990 struct ieee80211_hw *hw; 5991 struct usb_device *udev; 5992 struct ieee80211_supported_band *sband; 5993 int ret; 5994 int untested = 1; 5995 5996 udev = usb_get_dev(interface_to_usbdev(interface)); 5997 5998 switch (id->idVendor) { 5999 case USB_VENDOR_ID_REALTEK: 6000 switch(id->idProduct) { 6001 case 0x1724: 6002 case 0x8176: 6003 case 0x8178: 6004 case 0x817f: 6005 case 0x818b: 6006 untested = 0; 6007 break; 6008 } 6009 break; 6010 case 0x7392: 6011 if (id->idProduct == 0x7811) 6012 untested = 0; 6013 break; 6014 case 0x050d: 6015 if (id->idProduct == 0x1004) 6016 untested = 0; 6017 break; 6018 case 0x20f4: 6019 if (id->idProduct == 0x648b) 6020 untested = 0; 6021 break; 6022 case 0x2001: 6023 if (id->idProduct == 0x3308) 6024 untested = 0; 6025 break; 6026 case 0x2357: 6027 if (id->idProduct == 0x0109) 6028 untested = 0; 6029 break; 6030 default: 6031 break; 6032 } 6033 6034 if (untested) { 6035 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE; 6036 dev_info(&udev->dev, 6037 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n", 6038 id->idVendor, id->idProduct); 6039 dev_info(&udev->dev, 6040 "Please report results to Jes.Sorensen@gmail.com\n"); 6041 } 6042 6043 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops); 6044 if (!hw) { 6045 ret = -ENOMEM; 6046 priv = NULL; 6047 goto exit; 6048 } 6049 6050 priv = hw->priv; 6051 priv->hw = hw; 6052 priv->udev = udev; 6053 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info; 6054 mutex_init(&priv->usb_buf_mutex); 6055 mutex_init(&priv->h2c_mutex); 6056 INIT_LIST_HEAD(&priv->tx_urb_free_list); 6057 spin_lock_init(&priv->tx_urb_lock); 6058 INIT_LIST_HEAD(&priv->rx_urb_pending_list); 6059 spin_lock_init(&priv->rx_urb_lock); 6060 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work); 6061 6062 usb_set_intfdata(interface, hw); 6063 6064 ret = rtl8xxxu_parse_usb(priv, interface); 6065 if (ret) 6066 goto exit; 6067 6068 ret = rtl8xxxu_identify_chip(priv); 6069 if (ret) { 6070 dev_err(&udev->dev, "Fatal - failed to identify chip\n"); 6071 goto exit; 6072 } 6073 6074 ret = rtl8xxxu_read_efuse(priv); 6075 if (ret) { 6076 dev_err(&udev->dev, "Fatal - failed to read EFuse\n"); 6077 goto exit; 6078 } 6079 6080 ret = priv->fops->parse_efuse(priv); 6081 if (ret) { 6082 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n"); 6083 goto exit; 6084 } 6085 6086 rtl8xxxu_print_chipinfo(priv); 6087 6088 ret = priv->fops->load_firmware(priv); 6089 if (ret) { 6090 dev_err(&udev->dev, "Fatal - failed to load firmware\n"); 6091 goto exit; 6092 } 6093 6094 ret = rtl8xxxu_init_device(hw); 6095 if (ret) 6096 goto exit; 6097 6098 hw->wiphy->max_scan_ssids = 1; 6099 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; 6100 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); 6101 hw->queues = 4; 6102 6103 sband = &rtl8xxxu_supported_band; 6104 sband->ht_cap.ht_supported = true; 6105 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 6106 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16; 6107 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40; 6108 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs)); 6109 sband->ht_cap.mcs.rx_mask[0] = 0xff; 6110 sband->ht_cap.mcs.rx_mask[4] = 0x01; 6111 if (priv->rf_paths > 1) { 6112 sband->ht_cap.mcs.rx_mask[1] = 0xff; 6113 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40; 6114 } 6115 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 6116 /* 6117 * Some APs will negotiate HT20_40 in a noisy environment leading 6118 * to miserable performance. Rather than defaulting to this, only 6119 * enable it if explicitly requested at module load time. 6120 */ 6121 if (rtl8xxxu_ht40_2g) { 6122 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n"); 6123 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; 6124 } 6125 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 6126 6127 hw->wiphy->rts_threshold = 2347; 6128 6129 SET_IEEE80211_DEV(priv->hw, &interface->dev); 6130 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr); 6131 6132 hw->extra_tx_headroom = priv->fops->tx_desc_size; 6133 ieee80211_hw_set(hw, SIGNAL_DBM); 6134 /* 6135 * The firmware handles rate control 6136 */ 6137 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 6138 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 6139 6140 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); 6141 6142 ret = ieee80211_register_hw(priv->hw); 6143 if (ret) { 6144 dev_err(&udev->dev, "%s: Failed to register: %i\n", 6145 __func__, ret); 6146 goto exit; 6147 } 6148 6149 return 0; 6150 6151 exit: 6152 usb_set_intfdata(interface, NULL); 6153 6154 if (priv) { 6155 kfree(priv->fw_data); 6156 mutex_destroy(&priv->usb_buf_mutex); 6157 mutex_destroy(&priv->h2c_mutex); 6158 } 6159 usb_put_dev(udev); 6160 6161 ieee80211_free_hw(hw); 6162 6163 return ret; 6164 } 6165 6166 static void rtl8xxxu_disconnect(struct usb_interface *interface) 6167 { 6168 struct rtl8xxxu_priv *priv; 6169 struct ieee80211_hw *hw; 6170 6171 hw = usb_get_intfdata(interface); 6172 priv = hw->priv; 6173 6174 ieee80211_unregister_hw(hw); 6175 6176 priv->fops->power_off(priv); 6177 6178 usb_set_intfdata(interface, NULL); 6179 6180 dev_info(&priv->udev->dev, "disconnecting\n"); 6181 6182 kfree(priv->fw_data); 6183 mutex_destroy(&priv->usb_buf_mutex); 6184 mutex_destroy(&priv->h2c_mutex); 6185 6186 if (priv->udev->state != USB_STATE_NOTATTACHED) { 6187 dev_info(&priv->udev->dev, 6188 "Device still attached, trying to reset\n"); 6189 usb_reset_device(priv->udev); 6190 } 6191 usb_put_dev(priv->udev); 6192 ieee80211_free_hw(hw); 6193 } 6194 6195 static const struct usb_device_id dev_table[] = { 6196 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff), 6197 .driver_info = (unsigned long)&rtl8723au_fops}, 6198 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff), 6199 .driver_info = (unsigned long)&rtl8723au_fops}, 6200 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff), 6201 .driver_info = (unsigned long)&rtl8723au_fops}, 6202 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff), 6203 .driver_info = (unsigned long)&rtl8192eu_fops}, 6204 /* TP-Link TL-WN822N v4 */ 6205 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0108, 0xff, 0xff, 0xff), 6206 .driver_info = (unsigned long)&rtl8192eu_fops}, 6207 /* D-Link DWA-131 rev E1, tested by David Patiño */ 6208 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3319, 0xff, 0xff, 0xff), 6209 .driver_info = (unsigned long)&rtl8192eu_fops}, 6210 /* Tested by Myckel Habets */ 6211 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0109, 0xff, 0xff, 0xff), 6212 .driver_info = (unsigned long)&rtl8192eu_fops}, 6213 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff), 6214 .driver_info = (unsigned long)&rtl8723bu_fops}, 6215 #ifdef CONFIG_RTL8XXXU_UNTESTED 6216 /* Still supported by rtlwifi */ 6217 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff), 6218 .driver_info = (unsigned long)&rtl8192cu_fops}, 6219 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff), 6220 .driver_info = (unsigned long)&rtl8192cu_fops}, 6221 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff), 6222 .driver_info = (unsigned long)&rtl8192cu_fops}, 6223 /* Tested by Larry Finger */ 6224 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff), 6225 .driver_info = (unsigned long)&rtl8192cu_fops}, 6226 /* Tested by Andrea Merello */ 6227 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff), 6228 .driver_info = (unsigned long)&rtl8192cu_fops}, 6229 /* Tested by Jocelyn Mayer */ 6230 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff), 6231 .driver_info = (unsigned long)&rtl8192cu_fops}, 6232 /* Tested by Stefano Bravi */ 6233 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff), 6234 .driver_info = (unsigned long)&rtl8192cu_fops}, 6235 /* Currently untested 8188 series devices */ 6236 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x018a, 0xff, 0xff, 0xff), 6237 .driver_info = (unsigned long)&rtl8192cu_fops}, 6238 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff), 6239 .driver_info = (unsigned long)&rtl8192cu_fops}, 6240 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff), 6241 .driver_info = (unsigned long)&rtl8192cu_fops}, 6242 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff), 6243 .driver_info = (unsigned long)&rtl8192cu_fops}, 6244 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff), 6245 .driver_info = (unsigned long)&rtl8192cu_fops}, 6246 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff), 6247 .driver_info = (unsigned long)&rtl8192cu_fops}, 6248 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff), 6249 .driver_info = (unsigned long)&rtl8192cu_fops}, 6250 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff), 6251 .driver_info = (unsigned long)&rtl8192cu_fops}, 6252 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff), 6253 .driver_info = (unsigned long)&rtl8192cu_fops}, 6254 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff), 6255 .driver_info = (unsigned long)&rtl8192cu_fops}, 6256 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff), 6257 .driver_info = (unsigned long)&rtl8192cu_fops}, 6258 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff), 6259 .driver_info = (unsigned long)&rtl8192cu_fops}, 6260 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff), 6261 .driver_info = (unsigned long)&rtl8192cu_fops}, 6262 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff), 6263 .driver_info = (unsigned long)&rtl8192cu_fops}, 6264 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff), 6265 .driver_info = (unsigned long)&rtl8192cu_fops}, 6266 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff), 6267 .driver_info = (unsigned long)&rtl8192cu_fops}, 6268 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff), 6269 .driver_info = (unsigned long)&rtl8192cu_fops}, 6270 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff), 6271 .driver_info = (unsigned long)&rtl8192cu_fops}, 6272 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff), 6273 .driver_info = (unsigned long)&rtl8192cu_fops}, 6274 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff), 6275 .driver_info = (unsigned long)&rtl8192cu_fops}, 6276 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff), 6277 .driver_info = (unsigned long)&rtl8192cu_fops}, 6278 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff), 6279 .driver_info = (unsigned long)&rtl8192cu_fops}, 6280 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff), 6281 .driver_info = (unsigned long)&rtl8192cu_fops}, 6282 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff), 6283 .driver_info = (unsigned long)&rtl8192cu_fops}, 6284 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff), 6285 .driver_info = (unsigned long)&rtl8192cu_fops}, 6286 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff), 6287 .driver_info = (unsigned long)&rtl8192cu_fops}, 6288 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff), 6289 .driver_info = (unsigned long)&rtl8192cu_fops}, 6290 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff), 6291 .driver_info = (unsigned long)&rtl8192cu_fops}, 6292 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff), 6293 .driver_info = (unsigned long)&rtl8192cu_fops}, 6294 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff), 6295 .driver_info = (unsigned long)&rtl8192cu_fops}, 6296 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff), 6297 .driver_info = (unsigned long)&rtl8192cu_fops}, 6298 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff), 6299 .driver_info = (unsigned long)&rtl8192cu_fops}, 6300 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff), 6301 .driver_info = (unsigned long)&rtl8192cu_fops}, 6302 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff), 6303 .driver_info = (unsigned long)&rtl8192cu_fops}, 6304 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff), 6305 .driver_info = (unsigned long)&rtl8192cu_fops}, 6306 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff), 6307 .driver_info = (unsigned long)&rtl8192cu_fops}, 6308 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff), 6309 .driver_info = (unsigned long)&rtl8192cu_fops}, 6310 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff), 6311 .driver_info = (unsigned long)&rtl8192cu_fops}, 6312 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff), 6313 .driver_info = (unsigned long)&rtl8192cu_fops}, 6314 /* Currently untested 8192 series devices */ 6315 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff), 6316 .driver_info = (unsigned long)&rtl8192cu_fops}, 6317 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff), 6318 .driver_info = (unsigned long)&rtl8192cu_fops}, 6319 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff), 6320 .driver_info = (unsigned long)&rtl8192cu_fops}, 6321 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff), 6322 .driver_info = (unsigned long)&rtl8192cu_fops}, 6323 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff), 6324 .driver_info = (unsigned long)&rtl8192cu_fops}, 6325 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff), 6326 .driver_info = (unsigned long)&rtl8192cu_fops}, 6327 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff), 6328 .driver_info = (unsigned long)&rtl8192cu_fops}, 6329 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff), 6330 .driver_info = (unsigned long)&rtl8192cu_fops}, 6331 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff), 6332 .driver_info = (unsigned long)&rtl8192cu_fops}, 6333 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff), 6334 .driver_info = (unsigned long)&rtl8192cu_fops}, 6335 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff), 6336 .driver_info = (unsigned long)&rtl8192cu_fops}, 6337 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff), 6338 .driver_info = (unsigned long)&rtl8192cu_fops}, 6339 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff), 6340 .driver_info = (unsigned long)&rtl8192cu_fops}, 6341 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff), 6342 .driver_info = (unsigned long)&rtl8192cu_fops}, 6343 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff), 6344 .driver_info = (unsigned long)&rtl8192cu_fops}, 6345 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff), 6346 .driver_info = (unsigned long)&rtl8192cu_fops}, 6347 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff), 6348 .driver_info = (unsigned long)&rtl8192cu_fops}, 6349 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff), 6350 .driver_info = (unsigned long)&rtl8192cu_fops}, 6351 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff), 6352 .driver_info = (unsigned long)&rtl8192cu_fops}, 6353 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff), 6354 .driver_info = (unsigned long)&rtl8192cu_fops}, 6355 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff), 6356 .driver_info = (unsigned long)&rtl8192cu_fops}, 6357 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff), 6358 .driver_info = (unsigned long)&rtl8192cu_fops}, 6359 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff), 6360 .driver_info = (unsigned long)&rtl8192cu_fops}, 6361 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff), 6362 .driver_info = (unsigned long)&rtl8192cu_fops}, 6363 /* found in rtl8192eu vendor driver */ 6364 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0107, 0xff, 0xff, 0xff), 6365 .driver_info = (unsigned long)&rtl8192eu_fops}, 6366 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab33, 0xff, 0xff, 0xff), 6367 .driver_info = (unsigned long)&rtl8192eu_fops}, 6368 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818c, 0xff, 0xff, 0xff), 6369 .driver_info = (unsigned long)&rtl8192eu_fops}, 6370 #endif 6371 { } 6372 }; 6373 6374 static struct usb_driver rtl8xxxu_driver = { 6375 .name = DRIVER_NAME, 6376 .probe = rtl8xxxu_probe, 6377 .disconnect = rtl8xxxu_disconnect, 6378 .id_table = dev_table, 6379 .no_dynamic_id = 1, 6380 .disable_hub_initiated_lpm = 1, 6381 }; 6382 6383 static int __init rtl8xxxu_module_init(void) 6384 { 6385 int res; 6386 6387 res = usb_register(&rtl8xxxu_driver); 6388 if (res < 0) 6389 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res); 6390 6391 return res; 6392 } 6393 6394 static void __exit rtl8xxxu_module_exit(void) 6395 { 6396 usb_deregister(&rtl8xxxu_driver); 6397 } 6398 6399 6400 MODULE_DEVICE_TABLE(usb, dev_table); 6401 6402 module_init(rtl8xxxu_module_init); 6403 module_exit(rtl8xxxu_module_exit); 6404