1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2022 MediaTek Inc. */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/platform_device.h> 7 #include <linux/pinctrl/consumer.h> 8 #include <linux/of.h> 9 #include <linux/of_device.h> 10 #include <linux/of_reserved_mem.h> 11 #include <linux/of_gpio.h> 12 #include <linux/iopoll.h> 13 #include <linux/reset.h> 14 #include <linux/of_net.h> 15 #include <linux/clk.h> 16 17 #include "mt7915.h" 18 19 /* INFRACFG */ 20 #define MT_INFRACFG_CONN2AP_SLPPROT 0x0d0 21 #define MT_INFRACFG_AP2CONN_SLPPROT 0x0d4 22 23 #define MT_INFRACFG_RX_EN_MASK BIT(16) 24 #define MT_INFRACFG_TX_RDY_MASK BIT(4) 25 #define MT_INFRACFG_TX_EN_MASK BIT(0) 26 27 /* TOP POS */ 28 #define MT_TOP_POS_FAST_CTRL 0x114 29 #define MT_TOP_POS_FAST_EN_MASK BIT(3) 30 31 #define MT_TOP_POS_SKU 0x21c 32 #define MT_TOP_POS_SKU_MASK GENMASK(31, 28) 33 #define MT_TOP_POS_SKU_ADIE_DBDC_MASK BIT(2) 34 35 enum { 36 ADIE_SB, 37 ADIE_DBDC 38 }; 39 40 static int 41 mt76_wmac_spi_read(struct mt7915_dev *dev, u8 adie, u32 addr, u32 *val) 42 { 43 int ret; 44 u32 cur; 45 46 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT), 47 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 48 dev, MT_TOP_SPI_BUSY_CR(adie)); 49 if (ret) 50 return ret; 51 52 mt76_wr(dev, MT_TOP_SPI_ADDR_CR(adie), 53 MT_TOP_SPI_READ_ADDR_FORMAT | addr); 54 mt76_wr(dev, MT_TOP_SPI_WRITE_DATA_CR(adie), 0); 55 56 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT), 57 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 58 dev, MT_TOP_SPI_BUSY_CR(adie)); 59 if (ret) 60 return ret; 61 62 *val = mt76_rr(dev, MT_TOP_SPI_READ_DATA_CR(adie)); 63 64 return 0; 65 } 66 67 static int 68 mt76_wmac_spi_write(struct mt7915_dev *dev, u8 adie, u32 addr, u32 val) 69 { 70 int ret; 71 u32 cur; 72 73 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT), 74 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 75 dev, MT_TOP_SPI_BUSY_CR(adie)); 76 if (ret) 77 return ret; 78 79 mt76_wr(dev, MT_TOP_SPI_ADDR_CR(adie), 80 MT_TOP_SPI_WRITE_ADDR_FORMAT | addr); 81 mt76_wr(dev, MT_TOP_SPI_WRITE_DATA_CR(adie), val); 82 83 return read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT), 84 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 85 dev, MT_TOP_SPI_BUSY_CR(adie)); 86 } 87 88 static int 89 mt76_wmac_spi_rmw(struct mt7915_dev *dev, u8 adie, 90 u32 addr, u32 mask, u32 val) 91 { 92 u32 cur, ret; 93 94 ret = mt76_wmac_spi_read(dev, adie, addr, &cur); 95 if (ret) 96 return ret; 97 98 cur &= ~mask; 99 cur |= val; 100 101 return mt76_wmac_spi_write(dev, adie, addr, cur); 102 } 103 104 static int 105 mt7986_wmac_adie_efuse_read(struct mt7915_dev *dev, u8 adie, 106 u32 addr, u32 *data) 107 { 108 int ret, temp; 109 u32 val, mask; 110 111 ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_EFUSE_CFG, 112 MT_ADIE_EFUSE_CTRL_MASK); 113 if (ret) 114 return ret; 115 116 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_EFUSE2_CTRL, BIT(30), 0x0); 117 if (ret) 118 return ret; 119 120 mask = (MT_ADIE_EFUSE_MODE_MASK | MT_ADIE_EFUSE_ADDR_MASK | 121 MT_ADIE_EFUSE_KICK_MASK); 122 val = FIELD_PREP(MT_ADIE_EFUSE_MODE_MASK, 0) | 123 FIELD_PREP(MT_ADIE_EFUSE_ADDR_MASK, addr) | 124 FIELD_PREP(MT_ADIE_EFUSE_KICK_MASK, 1); 125 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_EFUSE2_CTRL, mask, val); 126 if (ret) 127 return ret; 128 129 ret = read_poll_timeout(mt76_wmac_spi_read, temp, 130 !temp && !FIELD_GET(MT_ADIE_EFUSE_KICK_MASK, val), 131 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 132 dev, adie, MT_ADIE_EFUSE2_CTRL, &val); 133 if (ret) 134 return ret; 135 136 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_EFUSE2_CTRL, &val); 137 if (ret) 138 return ret; 139 140 if (FIELD_GET(MT_ADIE_EFUSE_VALID_MASK, val) == 1) 141 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_EFUSE_RDATA0, 142 data); 143 144 return ret; 145 } 146 147 static inline void mt76_wmac_spi_lock(struct mt7915_dev *dev) 148 { 149 u32 cur; 150 151 read_poll_timeout(mt76_rr, cur, 152 FIELD_GET(MT_SEMA_RFSPI_STATUS_MASK, cur), 153 1000, 1000 * MSEC_PER_SEC, false, dev, 154 MT_SEMA_RFSPI_STATUS); 155 } 156 157 static inline void mt76_wmac_spi_unlock(struct mt7915_dev *dev) 158 { 159 mt76_wr(dev, MT_SEMA_RFSPI_RELEASE, 1); 160 } 161 162 static u32 mt76_wmac_rmw(void __iomem *base, u32 offset, u32 mask, u32 val) 163 { 164 val |= readl(base + offset) & ~mask; 165 writel(val, base + offset); 166 167 return val; 168 } 169 170 static u8 mt7986_wmac_check_adie_type(struct mt7915_dev *dev) 171 { 172 u32 val; 173 174 val = readl(dev->sku + MT_TOP_POS_SKU); 175 176 return FIELD_GET(MT_TOP_POS_SKU_ADIE_DBDC_MASK, val); 177 } 178 179 static int mt7986_wmac_consys_reset(struct mt7915_dev *dev, bool enable) 180 { 181 if (!enable) 182 return reset_control_assert(dev->rstc); 183 184 mt76_wmac_rmw(dev->sku, MT_TOP_POS_FAST_CTRL, 185 MT_TOP_POS_FAST_EN_MASK, 186 FIELD_PREP(MT_TOP_POS_FAST_EN_MASK, 0x1)); 187 188 return reset_control_deassert(dev->rstc); 189 } 190 191 static int mt7986_wmac_gpio_setup(struct mt7915_dev *dev) 192 { 193 struct pinctrl_state *state; 194 struct pinctrl *pinctrl; 195 int ret; 196 u8 type; 197 198 type = mt7986_wmac_check_adie_type(dev); 199 pinctrl = devm_pinctrl_get(dev->mt76.dev); 200 if (IS_ERR(pinctrl)) 201 return PTR_ERR(pinctrl); 202 203 switch (type) { 204 case ADIE_SB: 205 state = pinctrl_lookup_state(pinctrl, "default"); 206 if (IS_ERR_OR_NULL(state)) 207 return -EINVAL; 208 break; 209 case ADIE_DBDC: 210 state = pinctrl_lookup_state(pinctrl, "dbdc"); 211 if (IS_ERR_OR_NULL(state)) 212 return -EINVAL; 213 break; 214 default: 215 return -EINVAL; 216 } 217 218 ret = pinctrl_select_state(pinctrl, state); 219 if (ret) 220 return ret; 221 222 usleep_range(500, 1000); 223 224 return 0; 225 } 226 227 static int mt7986_wmac_consys_lockup(struct mt7915_dev *dev, bool enable) 228 { 229 int ret; 230 u32 cur; 231 232 mt76_wmac_rmw(dev->dcm, MT_INFRACFG_AP2CONN_SLPPROT, 233 MT_INFRACFG_RX_EN_MASK, 234 FIELD_PREP(MT_INFRACFG_RX_EN_MASK, enable)); 235 ret = read_poll_timeout(readl, cur, !(cur & MT_INFRACFG_RX_EN_MASK), 236 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 237 dev->dcm + MT_INFRACFG_AP2CONN_SLPPROT); 238 if (ret) 239 return ret; 240 241 mt76_wmac_rmw(dev->dcm, MT_INFRACFG_AP2CONN_SLPPROT, 242 MT_INFRACFG_TX_EN_MASK, 243 FIELD_PREP(MT_INFRACFG_TX_EN_MASK, enable)); 244 ret = read_poll_timeout(readl, cur, !(cur & MT_INFRACFG_TX_RDY_MASK), 245 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 246 dev->dcm + MT_INFRACFG_AP2CONN_SLPPROT); 247 if (ret) 248 return ret; 249 250 mt76_wmac_rmw(dev->dcm, MT_INFRACFG_CONN2AP_SLPPROT, 251 MT_INFRACFG_RX_EN_MASK, 252 FIELD_PREP(MT_INFRACFG_RX_EN_MASK, enable)); 253 mt76_wmac_rmw(dev->dcm, MT_INFRACFG_CONN2AP_SLPPROT, 254 MT_INFRACFG_TX_EN_MASK, 255 FIELD_PREP(MT_INFRACFG_TX_EN_MASK, enable)); 256 257 return 0; 258 } 259 260 static int mt7986_wmac_coninfra_check(struct mt7915_dev *dev) 261 { 262 u32 cur; 263 264 return read_poll_timeout(mt76_rr, cur, (cur == 0x02070000), 265 USEC_PER_MSEC, 50 * USEC_PER_MSEC, 266 false, dev, MT_CONN_INFRA_BASE); 267 } 268 269 static int mt7986_wmac_coninfra_setup(struct mt7915_dev *dev) 270 { 271 struct device *pdev = dev->mt76.dev; 272 struct reserved_mem *rmem; 273 struct device_node *np; 274 u32 val; 275 276 np = of_parse_phandle(pdev->of_node, "memory-region", 0); 277 if (!np) 278 return -EINVAL; 279 280 rmem = of_reserved_mem_lookup(np); 281 of_node_put(np); 282 if (!rmem) 283 return -EINVAL; 284 285 val = (rmem->base >> 16) & MT_TOP_MCU_EMI_BASE_MASK; 286 287 /* Set conninfra subsys PLL check */ 288 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS, 289 MT_INFRA_CKGEN_BUS_RDY_SEL_MASK, 0x1); 290 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS, 291 MT_INFRA_CKGEN_BUS_RDY_SEL_MASK, 0x1); 292 293 mt76_rmw_field(dev, MT_TOP_MCU_EMI_BASE, 294 MT_TOP_MCU_EMI_BASE_MASK, val); 295 296 mt76_wr(dev, MT_INFRA_BUS_EMI_START, rmem->base); 297 mt76_wr(dev, MT_INFRA_BUS_EMI_END, rmem->size); 298 299 mt76_rr(dev, MT_CONN_INFRA_EFUSE); 300 301 /* Set conninfra sysram */ 302 mt76_wr(dev, MT_TOP_RGU_SYSRAM_PDN, 0); 303 mt76_wr(dev, MT_TOP_RGU_SYSRAM_SLP, 1); 304 305 return 0; 306 } 307 308 static int mt7986_wmac_sku_setup(struct mt7915_dev *dev, u32 *adie_type) 309 { 310 int ret; 311 u32 adie_main, adie_ext; 312 313 mt76_rmw_field(dev, MT_CONN_INFRA_ADIE_RESET, 314 MT_CONN_INFRA_ADIE1_RESET_MASK, 0x1); 315 mt76_rmw_field(dev, MT_CONN_INFRA_ADIE_RESET, 316 MT_CONN_INFRA_ADIE2_RESET_MASK, 0x1); 317 318 mt76_wmac_spi_lock(dev); 319 320 ret = mt76_wmac_spi_read(dev, 0, MT_ADIE_CHIP_ID, &adie_main); 321 if (ret) 322 goto out; 323 324 ret = mt76_wmac_spi_read(dev, 1, MT_ADIE_CHIP_ID, &adie_ext); 325 if (ret) 326 goto out; 327 328 *adie_type = FIELD_GET(MT_ADIE_CHIP_ID_MASK, adie_main) | 329 (MT_ADIE_CHIP_ID_MASK & adie_ext); 330 331 out: 332 mt76_wmac_spi_unlock(dev); 333 334 return 0; 335 } 336 337 static inline u16 mt7986_adie_idx(u8 adie, u32 adie_type) 338 { 339 if (adie == 0) 340 return u32_get_bits(adie_type, MT_ADIE_IDX0); 341 else 342 return u32_get_bits(adie_type, MT_ADIE_IDX1); 343 } 344 345 static inline bool is_7975(struct mt7915_dev *dev, u8 adie, u32 adie_type) 346 { 347 return mt7986_adie_idx(adie, adie_type) == 0x7975; 348 } 349 350 static inline bool is_7976(struct mt7915_dev *dev, u8 adie, u32 adie_type) 351 { 352 return mt7986_adie_idx(adie, adie_type) == 0x7976; 353 } 354 355 static int mt7986_wmac_adie_thermal_cal(struct mt7915_dev *dev, u8 adie) 356 { 357 int ret; 358 u32 data, val; 359 360 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_THADC_ANALOG, 361 &data); 362 if (ret || FIELD_GET(MT_ADIE_ANA_EN_MASK, data)) { 363 val = FIELD_GET(MT_ADIE_VRPI_SEL_EFUSE_MASK, data); 364 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_RG_TOP_THADC_BG, 365 MT_ADIE_VRPI_SEL_CR_MASK, 366 FIELD_PREP(MT_ADIE_VRPI_SEL_CR_MASK, val)); 367 if (ret) 368 return ret; 369 370 val = FIELD_GET(MT_ADIE_PGA_GAIN_EFUSE_MASK, data); 371 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_RG_TOP_THADC, 372 MT_ADIE_PGA_GAIN_MASK, 373 FIELD_PREP(MT_ADIE_PGA_GAIN_MASK, val)); 374 if (ret) 375 return ret; 376 } 377 378 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_THADC_SLOP, 379 &data); 380 if (ret || FIELD_GET(MT_ADIE_ANA_EN_MASK, data)) { 381 val = FIELD_GET(MT_ADIE_LDO_CTRL_EFUSE_MASK, data); 382 383 return mt76_wmac_spi_rmw(dev, adie, MT_ADIE_RG_TOP_THADC, 384 MT_ADIE_LDO_CTRL_MASK, 385 FIELD_PREP(MT_ADIE_LDO_CTRL_MASK, val)); 386 } 387 388 return 0; 389 } 390 391 static int 392 mt7986_read_efuse_xo_trim_7976(struct mt7915_dev *dev, u8 adie, 393 bool is_40m, int *result) 394 { 395 int ret; 396 u32 data, addr; 397 398 addr = is_40m ? MT_ADIE_XTAL_AXM_40M_OSC : MT_ADIE_XTAL_AXM_80M_OSC; 399 ret = mt7986_wmac_adie_efuse_read(dev, adie, addr, &data); 400 if (ret) 401 return ret; 402 403 if (!FIELD_GET(MT_ADIE_XO_TRIM_EN_MASK, data)) { 404 *result = 64; 405 } else { 406 *result = FIELD_GET(MT_ADIE_TRIM_MASK, data); 407 addr = is_40m ? MT_ADIE_XTAL_TRIM1_40M_OSC : 408 MT_ADIE_XTAL_TRIM1_80M_OSC; 409 ret = mt7986_wmac_adie_efuse_read(dev, adie, addr, &data); 410 if (ret) 411 return ret; 412 413 if (FIELD_GET(MT_ADIE_XO_TRIM_EN_MASK, data) && 414 FIELD_GET(MT_ADIE_XTAL_DECREASE_MASK, data)) 415 *result -= FIELD_GET(MT_ADIE_EFUSE_TRIM_MASK, data); 416 else if (FIELD_GET(MT_ADIE_XO_TRIM_EN_MASK, data)) 417 *result += FIELD_GET(MT_ADIE_EFUSE_TRIM_MASK, data); 418 419 *result = max(0, min(127, *result)); 420 } 421 422 return 0; 423 } 424 425 static int mt7986_wmac_adie_xtal_trim_7976(struct mt7915_dev *dev, u8 adie) 426 { 427 int ret, trim_80m, trim_40m; 428 u32 data, val, mode; 429 430 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_XO_TRIM_FLOW, 431 &data); 432 if (ret || !FIELD_GET(BIT(1), data)) 433 return 0; 434 435 ret = mt7986_read_efuse_xo_trim_7976(dev, adie, false, &trim_80m); 436 if (ret) 437 return ret; 438 439 ret = mt7986_read_efuse_xo_trim_7976(dev, adie, true, &trim_40m); 440 if (ret) 441 return ret; 442 443 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_RG_STRAP_PIN_IN, &val); 444 if (ret) 445 return ret; 446 447 mode = FIELD_PREP(GENMASK(6, 4), val); 448 if (!mode || mode == 0x2) { 449 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C1, 450 GENMASK(31, 24), 451 FIELD_PREP(GENMASK(31, 24), trim_80m)); 452 if (ret) 453 return ret; 454 455 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C2, 456 GENMASK(31, 24), 457 FIELD_PREP(GENMASK(31, 24), trim_80m)); 458 } else if (mode == 0x3 || mode == 0x4 || mode == 0x6) { 459 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C1, 460 GENMASK(23, 16), 461 FIELD_PREP(GENMASK(23, 16), trim_40m)); 462 if (ret) 463 return ret; 464 465 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C2, 466 GENMASK(23, 16), 467 FIELD_PREP(GENMASK(23, 16), trim_40m)); 468 } 469 470 return ret; 471 } 472 473 static int mt7986_wmac_adie_patch_7976(struct mt7915_dev *dev, u8 adie) 474 { 475 u32 id, version, rg_xo_01, rg_xo_03; 476 int ret; 477 478 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_CHIP_ID, &id); 479 if (ret) 480 return ret; 481 482 version = FIELD_GET(MT_ADIE_VERSION_MASK, id); 483 484 ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_RG_TOP_THADC, 0x4a563b00); 485 if (ret) 486 return ret; 487 488 if (version == 0x8a00 || version == 0x8a10 || version == 0x8b00) { 489 rg_xo_01 = 0x1d59080f; 490 rg_xo_03 = 0x34c00fe0; 491 } else { 492 rg_xo_01 = 0x1959f80f; 493 rg_xo_03 = 0x34d00fe0; 494 } 495 496 ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_RG_XO_01, rg_xo_01); 497 if (ret) 498 return ret; 499 500 return mt76_wmac_spi_write(dev, adie, MT_ADIE_RG_XO_03, rg_xo_03); 501 } 502 503 static int 504 mt7986_read_efuse_xo_trim_7975(struct mt7915_dev *dev, u8 adie, 505 u32 addr, u32 *result) 506 { 507 int ret; 508 u32 data; 509 510 ret = mt7986_wmac_adie_efuse_read(dev, adie, addr, &data); 511 if (ret) 512 return ret; 513 514 if ((data & MT_ADIE_XO_TRIM_EN_MASK)) { 515 if ((data & MT_ADIE_XTAL_DECREASE_MASK)) 516 *result -= (data & MT_ADIE_EFUSE_TRIM_MASK); 517 else 518 *result += (data & MT_ADIE_EFUSE_TRIM_MASK); 519 520 *result = (*result & MT_ADIE_TRIM_MASK); 521 } 522 523 return 0; 524 } 525 526 static int mt7986_wmac_adie_xtal_trim_7975(struct mt7915_dev *dev, u8 adie) 527 { 528 int ret; 529 u32 data, result = 0, value; 530 531 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_7975_XTAL_EN, 532 &data); 533 if (ret || !(data & BIT(1))) 534 return 0; 535 536 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_7975_XTAL_CAL, 537 &data); 538 if (ret) 539 return ret; 540 541 if (data & MT_ADIE_XO_TRIM_EN_MASK) 542 result = (data & MT_ADIE_TRIM_MASK); 543 544 ret = mt7986_read_efuse_xo_trim_7975(dev, adie, MT_ADIE_7975_XO_TRIM2, 545 &result); 546 if (ret) 547 return ret; 548 549 ret = mt7986_read_efuse_xo_trim_7975(dev, adie, MT_ADIE_7975_XO_TRIM3, 550 &result); 551 if (ret) 552 return ret; 553 554 ret = mt7986_read_efuse_xo_trim_7975(dev, adie, MT_ADIE_7975_XO_TRIM4, 555 &result); 556 if (ret) 557 return ret; 558 559 /* Update trim value to C1 and C2*/ 560 value = FIELD_GET(MT_ADIE_7975_XO_CTRL2_C1_MASK, result) | 561 FIELD_GET(MT_ADIE_7975_XO_CTRL2_C2_MASK, result); 562 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_XO_CTRL2, 563 MT_ADIE_7975_XO_CTRL2_MASK, value); 564 if (ret) 565 return ret; 566 567 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_7975_XTAL, &value); 568 if (ret) 569 return ret; 570 571 if (value & MT_ADIE_7975_XTAL_EN_MASK) { 572 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_XO_2, 573 MT_ADIE_7975_XO_2_FIX_EN, 0x0); 574 if (ret) 575 return ret; 576 } 577 578 return mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_XO_CTRL6, 579 MT_ADIE_7975_XO_CTRL6_MASK, 0x1); 580 } 581 582 static int mt7986_wmac_adie_patch_7975(struct mt7915_dev *dev, u8 adie) 583 { 584 int ret; 585 586 /* disable CAL LDO and fine tune RFDIG LDO */ 587 ret = mt76_wmac_spi_write(dev, adie, 0x348, 0x00000002); 588 if (ret) 589 return ret; 590 591 ret = mt76_wmac_spi_write(dev, adie, 0x378, 0x00000002); 592 if (ret) 593 return ret; 594 595 ret = mt76_wmac_spi_write(dev, adie, 0x3a8, 0x00000002); 596 if (ret) 597 return ret; 598 599 ret = mt76_wmac_spi_write(dev, adie, 0x3d8, 0x00000002); 600 if (ret) 601 return ret; 602 603 /* set CKA driving and filter */ 604 ret = mt76_wmac_spi_write(dev, adie, 0xa1c, 0x30000aaa); 605 if (ret) 606 return ret; 607 608 /* set CKB LDO to 1.4V */ 609 ret = mt76_wmac_spi_write(dev, adie, 0xa84, 0x8470008a); 610 if (ret) 611 return ret; 612 613 /* turn on SX0 LTBUF */ 614 ret = mt76_wmac_spi_write(dev, adie, 0x074, 0x00000002); 615 if (ret) 616 return ret; 617 618 /* CK_BUF_SW_EN = 1 (all buf in manual mode.) */ 619 ret = mt76_wmac_spi_write(dev, adie, 0xaa4, 0x01001fc0); 620 if (ret) 621 return ret; 622 623 /* BT mode/WF normal mode 00000005 */ 624 ret = mt76_wmac_spi_write(dev, adie, 0x070, 0x00000005); 625 if (ret) 626 return ret; 627 628 /* BG thermal sensor offset update */ 629 ret = mt76_wmac_spi_write(dev, adie, 0x344, 0x00000088); 630 if (ret) 631 return ret; 632 633 ret = mt76_wmac_spi_write(dev, adie, 0x374, 0x00000088); 634 if (ret) 635 return ret; 636 637 ret = mt76_wmac_spi_write(dev, adie, 0x3a4, 0x00000088); 638 if (ret) 639 return ret; 640 641 ret = mt76_wmac_spi_write(dev, adie, 0x3d4, 0x00000088); 642 if (ret) 643 return ret; 644 645 /* set WCON VDD IPTAT to "0000" */ 646 ret = mt76_wmac_spi_write(dev, adie, 0xa80, 0x44d07000); 647 if (ret) 648 return ret; 649 650 /* change back LTBUF SX3 drving to default value */ 651 ret = mt76_wmac_spi_write(dev, adie, 0xa88, 0x3900aaaa); 652 if (ret) 653 return ret; 654 655 /* SM input cap off */ 656 ret = mt76_wmac_spi_write(dev, adie, 0x2c4, 0x00000000); 657 if (ret) 658 return ret; 659 660 /* set CKB driving and filter */ 661 return mt76_wmac_spi_write(dev, adie, 0x2c8, 0x00000072); 662 } 663 664 static int mt7986_wmac_adie_cfg(struct mt7915_dev *dev, u8 adie, u32 adie_type) 665 { 666 int ret; 667 668 mt76_wmac_spi_lock(dev); 669 ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_CLK_EN, ~0); 670 if (ret) 671 goto out; 672 673 if (is_7975(dev, adie, adie_type)) { 674 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_COCLK, 675 BIT(1), 0x1); 676 if (ret) 677 goto out; 678 679 ret = mt7986_wmac_adie_thermal_cal(dev, adie); 680 if (ret) 681 goto out; 682 683 ret = mt7986_wmac_adie_xtal_trim_7975(dev, adie); 684 if (ret) 685 goto out; 686 687 ret = mt7986_wmac_adie_patch_7975(dev, adie); 688 } else if (is_7976(dev, adie, adie_type)) { 689 if (mt7986_wmac_check_adie_type(dev) == ADIE_DBDC) { 690 ret = mt76_wmac_spi_write(dev, adie, 691 MT_ADIE_WRI_CK_SEL, 0x1c); 692 if (ret) 693 goto out; 694 } 695 696 ret = mt7986_wmac_adie_thermal_cal(dev, adie); 697 if (ret) 698 goto out; 699 700 ret = mt7986_wmac_adie_xtal_trim_7976(dev, adie); 701 if (ret) 702 goto out; 703 704 ret = mt7986_wmac_adie_patch_7976(dev, adie); 705 } 706 out: 707 mt76_wmac_spi_unlock(dev); 708 709 return ret; 710 } 711 712 static int 713 mt7986_wmac_afe_cal(struct mt7915_dev *dev, u8 adie, bool dbdc, u32 adie_type) 714 { 715 int ret; 716 u8 idx; 717 718 mt76_wmac_spi_lock(dev); 719 if (is_7975(dev, adie, adie_type)) 720 ret = mt76_wmac_spi_write(dev, adie, 721 MT_AFE_RG_ENCAL_WBTAC_IF_SW, 722 0x80000000); 723 else 724 ret = mt76_wmac_spi_write(dev, adie, 725 MT_AFE_RG_ENCAL_WBTAC_IF_SW, 726 0x88888005); 727 if (ret) 728 goto out; 729 730 idx = dbdc ? ADIE_DBDC : adie; 731 732 mt76_rmw_field(dev, MT_AFE_DIG_EN_01(idx), 733 MT_AFE_RG_WBG_EN_RCK_MASK, 0x1); 734 usleep_range(60, 100); 735 736 mt76_rmw(dev, MT_AFE_DIG_EN_01(idx), 737 MT_AFE_RG_WBG_EN_RCK_MASK, 0x0); 738 739 mt76_rmw_field(dev, MT_AFE_DIG_EN_03(idx), 740 MT_AFE_RG_WBG_EN_BPLL_UP_MASK, 0x1); 741 usleep_range(30, 100); 742 743 mt76_rmw_field(dev, MT_AFE_DIG_EN_03(idx), 744 MT_AFE_RG_WBG_EN_WPLL_UP_MASK, 0x1); 745 usleep_range(60, 100); 746 747 mt76_rmw_field(dev, MT_AFE_DIG_EN_01(idx), 748 MT_AFE_RG_WBG_EN_TXCAL_MASK, 0x1f); 749 usleep_range(800, 1000); 750 751 mt76_rmw(dev, MT_AFE_DIG_EN_01(idx), 752 MT_AFE_RG_WBG_EN_TXCAL_MASK, 0x0); 753 mt76_rmw(dev, MT_AFE_DIG_EN_03(idx), 754 MT_AFE_RG_WBG_EN_PLL_UP_MASK, 0x0); 755 756 ret = mt76_wmac_spi_write(dev, adie, MT_AFE_RG_ENCAL_WBTAC_IF_SW, 757 0x5); 758 759 out: 760 mt76_wmac_spi_unlock(dev); 761 762 return ret; 763 } 764 765 static void mt7986_wmac_subsys_pll_initial(struct mt7915_dev *dev, u8 band) 766 { 767 mt76_rmw(dev, MT_AFE_PLL_STB_TIME(band), 768 MT_AFE_PLL_STB_TIME_MASK, MT_AFE_PLL_STB_TIME_VAL); 769 770 mt76_rmw(dev, MT_AFE_DIG_EN_02(band), 771 MT_AFE_PLL_CFG_MASK, MT_AFE_PLL_CFG_VAL); 772 773 mt76_rmw(dev, MT_AFE_DIG_TOP_01(band), 774 MT_AFE_DIG_TOP_01_MASK, MT_AFE_DIG_TOP_01_VAL); 775 } 776 777 static void mt7986_wmac_subsys_setting(struct mt7915_dev *dev) 778 { 779 /* Subsys pll init */ 780 mt7986_wmac_subsys_pll_initial(dev, 0); 781 mt7986_wmac_subsys_pll_initial(dev, 1); 782 783 /* Set legacy OSC control stable time*/ 784 mt76_rmw(dev, MT_CONN_INFRA_OSC_RC_EN, 785 MT_CONN_INFRA_OSC_RC_EN_MASK, 0x0); 786 mt76_rmw(dev, MT_CONN_INFRA_OSC_CTRL, 787 MT_CONN_INFRA_OSC_STB_TIME_MASK, 0x80706); 788 789 /* prevent subsys from power on/of in a short time interval */ 790 mt76_rmw(dev, MT_TOP_WFSYS_PWR, 791 MT_TOP_PWR_ACK_MASK | MT_TOP_PWR_KEY_MASK, 792 MT_TOP_PWR_KEY); 793 } 794 795 static int mt7986_wmac_bus_timeout(struct mt7915_dev *dev) 796 { 797 mt76_rmw_field(dev, MT_INFRA_BUS_OFF_TIMEOUT, 798 MT_INFRA_BUS_TIMEOUT_LIMIT_MASK, 0x2); 799 800 mt76_rmw_field(dev, MT_INFRA_BUS_OFF_TIMEOUT, 801 MT_INFRA_BUS_TIMEOUT_EN_MASK, 0xf); 802 803 mt76_rmw_field(dev, MT_INFRA_BUS_ON_TIMEOUT, 804 MT_INFRA_BUS_TIMEOUT_LIMIT_MASK, 0xc); 805 806 mt76_rmw_field(dev, MT_INFRA_BUS_ON_TIMEOUT, 807 MT_INFRA_BUS_TIMEOUT_EN_MASK, 0xf); 808 809 return mt7986_wmac_coninfra_check(dev); 810 } 811 812 static void mt7986_wmac_clock_enable(struct mt7915_dev *dev, u32 adie_type) 813 { 814 u32 cur; 815 816 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_1, 817 MT_INFRA_CKGEN_DIV_SEL_MASK, 0x1); 818 819 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_2, 820 MT_INFRA_CKGEN_DIV_SEL_MASK, 0x1); 821 822 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_1, 823 MT_INFRA_CKGEN_DIV_EN_MASK, 0x1); 824 825 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_2, 826 MT_INFRA_CKGEN_DIV_EN_MASK, 0x1); 827 828 mt76_rmw_field(dev, MT_INFRA_CKGEN_RFSPI_WPLL_DIV, 829 MT_INFRA_CKGEN_DIV_SEL_MASK, 0x8); 830 831 mt76_rmw_field(dev, MT_INFRA_CKGEN_RFSPI_WPLL_DIV, 832 MT_INFRA_CKGEN_DIV_EN_MASK, 0x1); 833 834 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS, 835 MT_INFRA_CKGEN_BUS_CLK_SEL_MASK, 0x0); 836 837 mt76_rmw_field(dev, MT_CONN_INFRA_HW_CTRL, 838 MT_CONN_INFRA_HW_CTRL_MASK, 0x1); 839 840 mt76_rmw(dev, MT_TOP_CONN_INFRA_WAKEUP, 841 MT_TOP_CONN_INFRA_WAKEUP_MASK, 0x1); 842 843 usleep_range(900, 1000); 844 845 mt76_wmac_spi_lock(dev); 846 if (is_7975(dev, 0, adie_type) || is_7976(dev, 0, adie_type)) { 847 mt76_rmw_field(dev, MT_ADIE_SLP_CTRL_CK0(0), 848 MT_SLP_CTRL_EN_MASK, 0x1); 849 850 read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_CTRL_BSY_MASK), 851 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 852 dev, MT_ADIE_SLP_CTRL_CK0(0)); 853 } 854 if (is_7975(dev, 1, adie_type) || is_7976(dev, 1, adie_type)) { 855 mt76_rmw_field(dev, MT_ADIE_SLP_CTRL_CK0(1), 856 MT_SLP_CTRL_EN_MASK, 0x1); 857 858 read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_CTRL_BSY_MASK), 859 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 860 dev, MT_ADIE_SLP_CTRL_CK0(0)); 861 } 862 mt76_wmac_spi_unlock(dev); 863 864 mt76_rmw(dev, MT_TOP_CONN_INFRA_WAKEUP, 865 MT_TOP_CONN_INFRA_WAKEUP_MASK, 0x0); 866 usleep_range(900, 1000); 867 } 868 869 static int mt7986_wmac_top_wfsys_wakeup(struct mt7915_dev *dev, bool enable) 870 { 871 mt76_rmw_field(dev, MT_TOP_WFSYS_WAKEUP, 872 MT_TOP_WFSYS_WAKEUP_MASK, enable); 873 874 usleep_range(900, 1000); 875 876 if (!enable) 877 return 0; 878 879 return mt7986_wmac_coninfra_check(dev); 880 } 881 882 static int mt7986_wmac_wm_enable(struct mt7915_dev *dev, bool enable) 883 { 884 u32 cur; 885 886 mt76_wr(dev, MT_CONNINFRA_SKU_DEC_ADDR, 0); 887 888 mt76_rmw_field(dev, MT7986_TOP_WM_RESET, 889 MT7986_TOP_WM_RESET_MASK, enable); 890 if (!enable) 891 return 0; 892 893 return read_poll_timeout(mt76_rr, cur, (cur == 0x1d1e), 894 USEC_PER_MSEC, 5000 * USEC_PER_MSEC, false, 895 dev, MT_TOP_CFG_ON_ROM_IDX); 896 } 897 898 static int mt7986_wmac_wfsys_poweron(struct mt7915_dev *dev, bool enable) 899 { 900 u32 mask = MT_TOP_PWR_EN_MASK | MT_TOP_PWR_KEY_MASK; 901 u32 cur; 902 903 mt76_rmw(dev, MT_TOP_WFSYS_PWR, mask, 904 MT_TOP_PWR_KEY | FIELD_PREP(MT_TOP_PWR_EN_MASK, enable)); 905 906 return read_poll_timeout(mt76_rr, cur, 907 (FIELD_GET(MT_TOP_WFSYS_RESET_STATUS_MASK, cur) == enable), 908 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 909 dev, MT_TOP_WFSYS_RESET_STATUS); 910 } 911 912 static int mt7986_wmac_wfsys_setting(struct mt7915_dev *dev) 913 { 914 int ret; 915 u32 cur; 916 917 /* Turn off wfsys2conn bus sleep protect */ 918 mt76_rmw(dev, MT_CONN_INFRA_WF_SLP_PROT, 919 MT_CONN_INFRA_WF_SLP_PROT_MASK, 0x0); 920 921 ret = mt7986_wmac_wfsys_poweron(dev, true); 922 if (ret) 923 return ret; 924 925 /* Check bus sleep protect */ 926 927 ret = read_poll_timeout(mt76_rr, cur, 928 !(cur & MT_CONN_INFRA_CONN_WF_MASK), 929 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 930 dev, MT_CONN_INFRA_WF_SLP_PROT_RDY); 931 if (ret) 932 return ret; 933 934 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_WFDMA2CONN_MASK), 935 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 936 dev, MT_SLP_STATUS); 937 if (ret) 938 return ret; 939 940 return read_poll_timeout(mt76_rr, cur, (cur == 0x02060000), 941 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 942 dev, MT_TOP_CFG_IP_VERSION_ADDR); 943 } 944 945 static void mt7986_wmac_wfsys_set_timeout(struct mt7915_dev *dev) 946 { 947 u32 mask = MT_MCU_BUS_TIMEOUT_SET_MASK | 948 MT_MCU_BUS_TIMEOUT_CG_EN_MASK | 949 MT_MCU_BUS_TIMEOUT_EN_MASK; 950 u32 val = FIELD_PREP(MT_MCU_BUS_TIMEOUT_SET_MASK, 1) | 951 FIELD_PREP(MT_MCU_BUS_TIMEOUT_CG_EN_MASK, 1) | 952 FIELD_PREP(MT_MCU_BUS_TIMEOUT_EN_MASK, 1); 953 954 mt76_rmw(dev, MT_MCU_BUS_TIMEOUT, mask, val); 955 956 mt76_wr(dev, MT_MCU_BUS_REMAP, 0x810f0000); 957 958 mask = MT_MCU_BUS_DBG_TIMEOUT_SET_MASK | 959 MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK | 960 MT_MCU_BUS_DBG_TIMEOUT_EN_MASK; 961 val = FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_SET_MASK, 0x3aa) | 962 FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK, 1) | 963 FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_EN_MASK, 1); 964 965 mt76_rmw(dev, MT_MCU_BUS_DBG_TIMEOUT, mask, val); 966 } 967 968 static int mt7986_wmac_sku_update(struct mt7915_dev *dev, u32 adie_type) 969 { 970 u32 val; 971 972 if (is_7976(dev, 0, adie_type) && is_7976(dev, 1, adie_type)) 973 val = 0xf; 974 else if (is_7975(dev, 0, adie_type) && is_7975(dev, 1, adie_type)) 975 val = 0xd; 976 else if (is_7976(dev, 0, adie_type)) 977 val = 0x7; 978 else if (is_7975(dev, 1, adie_type)) 979 val = 0x8; 980 else if (is_7976(dev, 1, adie_type)) 981 val = 0xa; 982 else 983 return -EINVAL; 984 985 mt76_wmac_rmw(dev->sku, MT_TOP_POS_SKU, MT_TOP_POS_SKU_MASK, 986 FIELD_PREP(MT_TOP_POS_SKU_MASK, val)); 987 988 mt76_wr(dev, MT_CONNINFRA_SKU_DEC_ADDR, val); 989 990 return 0; 991 } 992 993 static int 994 mt7986_wmac_adie_setup(struct mt7915_dev *dev, u8 adie, u32 adie_type) 995 { 996 int ret; 997 998 if (!(is_7975(dev, adie, adie_type) || is_7976(dev, adie, adie_type))) 999 return 0; 1000 1001 ret = mt7986_wmac_adie_cfg(dev, adie, adie_type); 1002 if (ret) 1003 return ret; 1004 1005 ret = mt7986_wmac_afe_cal(dev, adie, false, adie_type); 1006 if (ret) 1007 return ret; 1008 1009 if (!adie && (mt7986_wmac_check_adie_type(dev) == ADIE_DBDC)) 1010 ret = mt7986_wmac_afe_cal(dev, adie, true, adie_type); 1011 1012 return ret; 1013 } 1014 1015 static int mt7986_wmac_subsys_powerup(struct mt7915_dev *dev, u32 adie_type) 1016 { 1017 int ret; 1018 1019 mt7986_wmac_subsys_setting(dev); 1020 1021 ret = mt7986_wmac_bus_timeout(dev); 1022 if (ret) 1023 return ret; 1024 1025 mt7986_wmac_clock_enable(dev, adie_type); 1026 1027 return 0; 1028 } 1029 1030 static int mt7986_wmac_wfsys_powerup(struct mt7915_dev *dev) 1031 { 1032 int ret; 1033 1034 ret = mt7986_wmac_wm_enable(dev, false); 1035 if (ret) 1036 return ret; 1037 1038 ret = mt7986_wmac_wfsys_setting(dev); 1039 if (ret) 1040 return ret; 1041 1042 mt7986_wmac_wfsys_set_timeout(dev); 1043 1044 return mt7986_wmac_wm_enable(dev, true); 1045 } 1046 1047 int mt7986_wmac_enable(struct mt7915_dev *dev) 1048 { 1049 int ret; 1050 u32 adie_type; 1051 1052 ret = mt7986_wmac_consys_reset(dev, true); 1053 if (ret) 1054 return ret; 1055 1056 ret = mt7986_wmac_gpio_setup(dev); 1057 if (ret) 1058 return ret; 1059 1060 ret = mt7986_wmac_consys_lockup(dev, false); 1061 if (ret) 1062 return ret; 1063 1064 ret = mt7986_wmac_coninfra_check(dev); 1065 if (ret) 1066 return ret; 1067 1068 ret = mt7986_wmac_coninfra_setup(dev); 1069 if (ret) 1070 return ret; 1071 1072 ret = mt7986_wmac_sku_setup(dev, &adie_type); 1073 if (ret) 1074 return ret; 1075 1076 ret = mt7986_wmac_adie_setup(dev, 0, adie_type); 1077 if (ret) 1078 return ret; 1079 1080 ret = mt7986_wmac_adie_setup(dev, 1, adie_type); 1081 if (ret) 1082 return ret; 1083 1084 ret = mt7986_wmac_subsys_powerup(dev, adie_type); 1085 if (ret) 1086 return ret; 1087 1088 ret = mt7986_wmac_top_wfsys_wakeup(dev, true); 1089 if (ret) 1090 return ret; 1091 1092 ret = mt7986_wmac_wfsys_powerup(dev); 1093 if (ret) 1094 return ret; 1095 1096 return mt7986_wmac_sku_update(dev, adie_type); 1097 } 1098 1099 void mt7986_wmac_disable(struct mt7915_dev *dev) 1100 { 1101 u32 cur; 1102 1103 mt7986_wmac_top_wfsys_wakeup(dev, true); 1104 1105 /* Turn on wfsys2conn bus sleep protect */ 1106 mt76_rmw_field(dev, MT_CONN_INFRA_WF_SLP_PROT, 1107 MT_CONN_INFRA_WF_SLP_PROT_MASK, 0x1); 1108 1109 /* Check wfsys2conn bus sleep protect */ 1110 read_poll_timeout(mt76_rr, cur, !(cur ^ MT_CONN_INFRA_CONN), 1111 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 1112 dev, MT_CONN_INFRA_WF_SLP_PROT_RDY); 1113 1114 mt7986_wmac_wfsys_poweron(dev, false); 1115 1116 /* Turn back wpll setting */ 1117 mt76_rmw_field(dev, MT_AFE_DIG_EN_02(0), MT_AFE_MCU_BPLL_CFG_MASK, 0x2); 1118 mt76_rmw_field(dev, MT_AFE_DIG_EN_02(0), MT_AFE_WPLL_CFG_MASK, 0x2); 1119 1120 /* Reset EMI */ 1121 mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ, 1122 MT_CONN_INFRA_EMI_REQ_MASK, 0x1); 1123 mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ, 1124 MT_CONN_INFRA_EMI_REQ_MASK, 0x0); 1125 mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ, 1126 MT_CONN_INFRA_INFRA_REQ_MASK, 0x1); 1127 mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ, 1128 MT_CONN_INFRA_INFRA_REQ_MASK, 0x0); 1129 1130 mt7986_wmac_top_wfsys_wakeup(dev, false); 1131 mt7986_wmac_consys_lockup(dev, true); 1132 mt7986_wmac_consys_reset(dev, false); 1133 } 1134 1135 static int mt7986_wmac_init(struct mt7915_dev *dev) 1136 { 1137 struct device *pdev = dev->mt76.dev; 1138 struct platform_device *pfdev = to_platform_device(pdev); 1139 struct clk *mcu_clk, *ap_conn_clk; 1140 1141 mcu_clk = devm_clk_get(pdev, "mcu"); 1142 if (IS_ERR(mcu_clk)) 1143 dev_err(pdev, "mcu clock not found\n"); 1144 else if (clk_prepare_enable(mcu_clk)) 1145 dev_err(pdev, "mcu clock configuration failed\n"); 1146 1147 ap_conn_clk = devm_clk_get(pdev, "ap2conn"); 1148 if (IS_ERR(ap_conn_clk)) 1149 dev_err(pdev, "ap2conn clock not found\n"); 1150 else if (clk_prepare_enable(ap_conn_clk)) 1151 dev_err(pdev, "ap2conn clock configuration failed\n"); 1152 1153 dev->dcm = devm_platform_ioremap_resource(pfdev, 1); 1154 if (IS_ERR(dev->dcm)) 1155 return PTR_ERR(dev->dcm); 1156 1157 dev->sku = devm_platform_ioremap_resource(pfdev, 2); 1158 if (IS_ERR(dev->sku)) 1159 return PTR_ERR(dev->sku); 1160 1161 dev->rstc = devm_reset_control_get(pdev, "consys"); 1162 if (IS_ERR(dev->rstc)) 1163 return PTR_ERR(dev->rstc); 1164 1165 return 0; 1166 } 1167 1168 static int mt7986_wmac_probe(struct platform_device *pdev) 1169 { 1170 void __iomem *mem_base; 1171 struct mt7915_dev *dev; 1172 struct mt76_dev *mdev; 1173 int irq, ret; 1174 u32 chip_id; 1175 1176 chip_id = (uintptr_t)of_device_get_match_data(&pdev->dev); 1177 1178 mem_base = devm_platform_ioremap_resource(pdev, 0); 1179 if (IS_ERR(mem_base)) { 1180 dev_err(&pdev->dev, "Failed to get memory resource\n"); 1181 return PTR_ERR(mem_base); 1182 } 1183 1184 dev = mt7915_mmio_probe(&pdev->dev, mem_base, chip_id); 1185 if (IS_ERR(dev)) 1186 return PTR_ERR(dev); 1187 1188 mdev = &dev->mt76; 1189 ret = mt7915_mmio_wed_init(dev, pdev, false, &irq); 1190 if (ret < 0) 1191 goto free_device; 1192 1193 if (!ret) { 1194 irq = platform_get_irq(pdev, 0); 1195 if (irq < 0) { 1196 ret = irq; 1197 goto free_device; 1198 } 1199 } 1200 1201 ret = devm_request_irq(mdev->dev, irq, mt7915_irq_handler, 1202 IRQF_SHARED, KBUILD_MODNAME, dev); 1203 if (ret) 1204 goto free_device; 1205 1206 ret = mt7986_wmac_init(dev); 1207 if (ret) 1208 goto free_irq; 1209 1210 mt7915_wfsys_reset(dev); 1211 1212 ret = mt7915_register_device(dev); 1213 if (ret) 1214 goto free_irq; 1215 1216 return 0; 1217 1218 free_irq: 1219 devm_free_irq(mdev->dev, irq, dev); 1220 free_device: 1221 if (mtk_wed_device_active(&mdev->mmio.wed)) 1222 mtk_wed_device_detach(&mdev->mmio.wed); 1223 mt76_free_device(mdev); 1224 1225 return ret; 1226 } 1227 1228 static int mt7986_wmac_remove(struct platform_device *pdev) 1229 { 1230 struct mt7915_dev *dev = platform_get_drvdata(pdev); 1231 1232 mt7915_unregister_device(dev); 1233 1234 return 0; 1235 } 1236 1237 static const struct of_device_id mt7986_wmac_of_match[] = { 1238 { .compatible = "mediatek,mt7986-wmac", .data = (u32 *)0x7986 }, 1239 {}, 1240 }; 1241 1242 MODULE_DEVICE_TABLE(of, mt7986_wmac_of_match); 1243 1244 struct platform_driver mt7986_wmac_driver = { 1245 .driver = { 1246 .name = "mt7986-wmac", 1247 .of_match_table = mt7986_wmac_of_match, 1248 }, 1249 .probe = mt7986_wmac_probe, 1250 .remove = mt7986_wmac_remove, 1251 }; 1252 1253 MODULE_FIRMWARE(MT7986_FIRMWARE_WA); 1254 MODULE_FIRMWARE(MT7986_FIRMWARE_WM); 1255 MODULE_FIRMWARE(MT7986_FIRMWARE_WM_MT7975); 1256 MODULE_FIRMWARE(MT7986_ROM_PATCH); 1257 MODULE_FIRMWARE(MT7986_ROM_PATCH_MT7975); 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