1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2022 MediaTek Inc. */
3 
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/platform_device.h>
7 #include <linux/pinctrl/consumer.h>
8 #include <linux/of.h>
9 #include <linux/of_reserved_mem.h>
10 #include <linux/of_gpio.h>
11 #include <linux/iopoll.h>
12 #include <linux/reset.h>
13 #include <linux/of_net.h>
14 #include <linux/clk.h>
15 
16 #include "mt7915.h"
17 
18 #define MT7981_CON_INFRA_VERSION 0x02090000
19 #define MT7986_CON_INFRA_VERSION 0x02070000
20 
21 /* INFRACFG */
22 #define MT_INFRACFG_CONN2AP_SLPPROT	0x0d0
23 #define MT_INFRACFG_AP2CONN_SLPPROT	0x0d4
24 
25 #define MT_INFRACFG_RX_EN_MASK		BIT(16)
26 #define MT_INFRACFG_TX_RDY_MASK		BIT(4)
27 #define MT_INFRACFG_TX_EN_MASK		BIT(0)
28 
29 /* TOP POS */
30 #define MT_TOP_POS_FAST_CTRL		0x114
31 #define MT_TOP_POS_FAST_EN_MASK		BIT(3)
32 
33 #define MT_TOP_POS_SKU			0x21c
34 #define MT_TOP_POS_SKU_MASK		GENMASK(31, 28)
35 #define MT_TOP_POS_SKU_ADIE_DBDC_MASK	BIT(2)
36 
37 enum {
38 	ADIE_SB,
39 	ADIE_DBDC
40 };
41 
42 static int
mt76_wmac_spi_read(struct mt7915_dev * dev,u8 adie,u32 addr,u32 * val)43 mt76_wmac_spi_read(struct mt7915_dev *dev, u8 adie, u32 addr, u32 *val)
44 {
45 	int ret;
46 	u32 cur;
47 
48 	ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT),
49 				USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
50 				dev, MT_TOP_SPI_BUSY_CR(adie));
51 	if (ret)
52 		return ret;
53 
54 	mt76_wr(dev, MT_TOP_SPI_ADDR_CR(adie),
55 		MT_TOP_SPI_READ_ADDR_FORMAT | addr);
56 	mt76_wr(dev, MT_TOP_SPI_WRITE_DATA_CR(adie), 0);
57 
58 	ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT),
59 				USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
60 				dev, MT_TOP_SPI_BUSY_CR(adie));
61 	if (ret)
62 		return ret;
63 
64 	*val = mt76_rr(dev, MT_TOP_SPI_READ_DATA_CR(adie));
65 
66 	return 0;
67 }
68 
69 static int
mt76_wmac_spi_write(struct mt7915_dev * dev,u8 adie,u32 addr,u32 val)70 mt76_wmac_spi_write(struct mt7915_dev *dev, u8 adie, u32 addr, u32 val)
71 {
72 	int ret;
73 	u32 cur;
74 
75 	ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT),
76 				USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
77 				dev, MT_TOP_SPI_BUSY_CR(adie));
78 	if (ret)
79 		return ret;
80 
81 	mt76_wr(dev, MT_TOP_SPI_ADDR_CR(adie),
82 		MT_TOP_SPI_WRITE_ADDR_FORMAT | addr);
83 	mt76_wr(dev, MT_TOP_SPI_WRITE_DATA_CR(adie), val);
84 
85 	return read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT),
86 				 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
87 				 dev, MT_TOP_SPI_BUSY_CR(adie));
88 }
89 
90 static int
mt76_wmac_spi_rmw(struct mt7915_dev * dev,u8 adie,u32 addr,u32 mask,u32 val)91 mt76_wmac_spi_rmw(struct mt7915_dev *dev, u8 adie,
92 		  u32 addr, u32 mask, u32 val)
93 {
94 	u32 cur, ret;
95 
96 	ret = mt76_wmac_spi_read(dev, adie, addr, &cur);
97 	if (ret)
98 		return ret;
99 
100 	cur &= ~mask;
101 	cur |= val;
102 
103 	return mt76_wmac_spi_write(dev, adie, addr, cur);
104 }
105 
106 static int
mt7986_wmac_adie_efuse_read(struct mt7915_dev * dev,u8 adie,u32 addr,u32 * data)107 mt7986_wmac_adie_efuse_read(struct mt7915_dev *dev, u8 adie,
108 			    u32 addr, u32 *data)
109 {
110 	int ret, temp;
111 	u32 val, mask;
112 
113 	ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_EFUSE_CFG,
114 				  MT_ADIE_EFUSE_CTRL_MASK);
115 	if (ret)
116 		return ret;
117 
118 	ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_EFUSE2_CTRL, BIT(30), 0x0);
119 	if (ret)
120 		return ret;
121 
122 	mask = (MT_ADIE_EFUSE_MODE_MASK | MT_ADIE_EFUSE_ADDR_MASK |
123 		MT_ADIE_EFUSE_KICK_MASK);
124 	val = FIELD_PREP(MT_ADIE_EFUSE_MODE_MASK, 0) |
125 	      FIELD_PREP(MT_ADIE_EFUSE_ADDR_MASK, addr) |
126 	      FIELD_PREP(MT_ADIE_EFUSE_KICK_MASK, 1);
127 	ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_EFUSE2_CTRL, mask, val);
128 	if (ret)
129 		return ret;
130 
131 	ret = read_poll_timeout(mt76_wmac_spi_read, temp,
132 				!temp && !FIELD_GET(MT_ADIE_EFUSE_KICK_MASK, val),
133 				USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
134 				dev, adie, MT_ADIE_EFUSE2_CTRL, &val);
135 	if (ret)
136 		return ret;
137 
138 	ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_EFUSE2_CTRL, &val);
139 	if (ret)
140 		return ret;
141 
142 	if (FIELD_GET(MT_ADIE_EFUSE_VALID_MASK, val) == 1)
143 		ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_EFUSE_RDATA0,
144 					 data);
145 
146 	return ret;
147 }
148 
mt76_wmac_spi_lock(struct mt7915_dev * dev)149 static inline void mt76_wmac_spi_lock(struct mt7915_dev *dev)
150 {
151 	u32 cur;
152 
153 	read_poll_timeout(mt76_rr, cur,
154 			  FIELD_GET(MT_SEMA_RFSPI_STATUS_MASK, cur),
155 			  1000, 1000 * MSEC_PER_SEC, false, dev,
156 			  MT_SEMA_RFSPI_STATUS);
157 }
158 
mt76_wmac_spi_unlock(struct mt7915_dev * dev)159 static inline void mt76_wmac_spi_unlock(struct mt7915_dev *dev)
160 {
161 	mt76_wr(dev, MT_SEMA_RFSPI_RELEASE, 1);
162 }
163 
mt76_wmac_rmw(void __iomem * base,u32 offset,u32 mask,u32 val)164 static u32 mt76_wmac_rmw(void __iomem *base, u32 offset, u32 mask, u32 val)
165 {
166 	val |= readl(base + offset) & ~mask;
167 	writel(val, base + offset);
168 
169 	return val;
170 }
171 
mt798x_wmac_check_adie_type(struct mt7915_dev * dev)172 static u8 mt798x_wmac_check_adie_type(struct mt7915_dev *dev)
173 {
174 	u32 val;
175 
176 	/* Only DBDC A-die is used with MT7981 */
177 	if (is_mt7981(&dev->mt76))
178 		return ADIE_DBDC;
179 
180 	val = readl(dev->sku + MT_TOP_POS_SKU);
181 
182 	return FIELD_GET(MT_TOP_POS_SKU_ADIE_DBDC_MASK, val);
183 }
184 
mt7986_wmac_consys_reset(struct mt7915_dev * dev,bool enable)185 static int mt7986_wmac_consys_reset(struct mt7915_dev *dev, bool enable)
186 {
187 	if (!enable)
188 		return reset_control_assert(dev->rstc);
189 
190 	mt76_wmac_rmw(dev->sku, MT_TOP_POS_FAST_CTRL,
191 		      MT_TOP_POS_FAST_EN_MASK,
192 		      FIELD_PREP(MT_TOP_POS_FAST_EN_MASK, 0x1));
193 
194 	return reset_control_deassert(dev->rstc);
195 }
196 
mt7986_wmac_gpio_setup(struct mt7915_dev * dev)197 static int mt7986_wmac_gpio_setup(struct mt7915_dev *dev)
198 {
199 	struct pinctrl_state *state;
200 	struct pinctrl *pinctrl;
201 	int ret;
202 	u8 type;
203 
204 	type = mt798x_wmac_check_adie_type(dev);
205 	pinctrl = devm_pinctrl_get(dev->mt76.dev);
206 	if (IS_ERR(pinctrl))
207 		return PTR_ERR(pinctrl);
208 
209 	switch (type) {
210 	case ADIE_SB:
211 		state = pinctrl_lookup_state(pinctrl, "default");
212 		if (IS_ERR_OR_NULL(state))
213 			return -EINVAL;
214 		break;
215 	case ADIE_DBDC:
216 		state = pinctrl_lookup_state(pinctrl, "dbdc");
217 		if (IS_ERR_OR_NULL(state))
218 			return -EINVAL;
219 		break;
220 	default:
221 		return -EINVAL;
222 	}
223 
224 	ret = pinctrl_select_state(pinctrl, state);
225 	if (ret)
226 		return ret;
227 
228 	usleep_range(500, 1000);
229 
230 	return 0;
231 }
232 
mt7986_wmac_consys_lockup(struct mt7915_dev * dev,bool enable)233 static int mt7986_wmac_consys_lockup(struct mt7915_dev *dev, bool enable)
234 {
235 	int ret;
236 	u32 cur;
237 
238 	mt76_wmac_rmw(dev->dcm, MT_INFRACFG_AP2CONN_SLPPROT,
239 		      MT_INFRACFG_RX_EN_MASK,
240 		      FIELD_PREP(MT_INFRACFG_RX_EN_MASK, enable));
241 	ret = read_poll_timeout(readl, cur, !(cur & MT_INFRACFG_RX_EN_MASK),
242 				USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
243 				dev->dcm + MT_INFRACFG_AP2CONN_SLPPROT);
244 	if (ret)
245 		return ret;
246 
247 	mt76_wmac_rmw(dev->dcm, MT_INFRACFG_AP2CONN_SLPPROT,
248 		      MT_INFRACFG_TX_EN_MASK,
249 		      FIELD_PREP(MT_INFRACFG_TX_EN_MASK, enable));
250 	ret = read_poll_timeout(readl, cur, !(cur & MT_INFRACFG_TX_RDY_MASK),
251 				USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
252 				dev->dcm + MT_INFRACFG_AP2CONN_SLPPROT);
253 	if (ret)
254 		return ret;
255 
256 	mt76_wmac_rmw(dev->dcm, MT_INFRACFG_CONN2AP_SLPPROT,
257 		      MT_INFRACFG_RX_EN_MASK,
258 		      FIELD_PREP(MT_INFRACFG_RX_EN_MASK, enable));
259 	mt76_wmac_rmw(dev->dcm, MT_INFRACFG_CONN2AP_SLPPROT,
260 		      MT_INFRACFG_TX_EN_MASK,
261 		      FIELD_PREP(MT_INFRACFG_TX_EN_MASK, enable));
262 
263 	return 0;
264 }
265 
mt798x_wmac_coninfra_check(struct mt7915_dev * dev)266 static int mt798x_wmac_coninfra_check(struct mt7915_dev *dev)
267 {
268 	u32 cur;
269 	u32 con_infra_version;
270 
271 	if (is_mt7981(&dev->mt76)) {
272 		con_infra_version = MT7981_CON_INFRA_VERSION;
273 	} else if (is_mt7986(&dev->mt76)) {
274 		con_infra_version = MT7986_CON_INFRA_VERSION;
275 	} else {
276 		WARN_ON(1);
277 		return -EINVAL;
278 	}
279 
280 	return read_poll_timeout(mt76_rr, cur, (cur == con_infra_version),
281 				 USEC_PER_MSEC, 50 * USEC_PER_MSEC,
282 				 false, dev, MT_CONN_INFRA_BASE);
283 }
284 
mt798x_wmac_coninfra_setup(struct mt7915_dev * dev)285 static int mt798x_wmac_coninfra_setup(struct mt7915_dev *dev)
286 {
287 	struct device *pdev = dev->mt76.dev;
288 	struct reserved_mem *rmem;
289 	struct device_node *np;
290 	u32 val;
291 
292 	np = of_parse_phandle(pdev->of_node, "memory-region", 0);
293 	if (!np)
294 		return -EINVAL;
295 
296 	rmem = of_reserved_mem_lookup(np);
297 	of_node_put(np);
298 	if (!rmem)
299 		return -EINVAL;
300 
301 	val = (rmem->base >> 16) & MT_TOP_MCU_EMI_BASE_MASK;
302 
303 	if (is_mt7986(&dev->mt76)) {
304 		/* Set conninfra subsys PLL check */
305 		mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS,
306 			       MT_INFRA_CKGEN_BUS_RDY_SEL_MASK, 0x1);
307 		mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS,
308 			       MT_INFRA_CKGEN_BUS_RDY_SEL_MASK, 0x1);
309 	}
310 
311 	mt76_rmw_field(dev, MT_TOP_MCU_EMI_BASE,
312 		       MT_TOP_MCU_EMI_BASE_MASK, val);
313 
314 	if (is_mt7981(&dev->mt76)) {
315 		mt76_rmw_field(dev, MT_TOP_WF_AP_PERI_BASE,
316 			       MT_TOP_WF_AP_PERI_BASE_MASK, 0x300d0000 >> 16);
317 
318 		mt76_rmw_field(dev, MT_TOP_EFUSE_BASE,
319 			       MT_TOP_EFUSE_BASE_MASK, 0x11f20000 >> 16);
320 	}
321 
322 	mt76_wr(dev, MT_INFRA_BUS_EMI_START, rmem->base);
323 	mt76_wr(dev, MT_INFRA_BUS_EMI_END, rmem->size);
324 
325 	mt76_rr(dev, MT_CONN_INFRA_EFUSE);
326 
327 	/* Set conninfra sysram */
328 	mt76_wr(dev, MT_TOP_RGU_SYSRAM_PDN, 0);
329 	mt76_wr(dev, MT_TOP_RGU_SYSRAM_SLP, 1);
330 
331 	return 0;
332 }
333 
mt798x_wmac_sku_setup(struct mt7915_dev * dev,u32 * adie_type)334 static int mt798x_wmac_sku_setup(struct mt7915_dev *dev, u32 *adie_type)
335 {
336 	int ret;
337 	u32 adie_main = 0, adie_ext = 0;
338 
339 	mt76_rmw_field(dev, MT_CONN_INFRA_ADIE_RESET,
340 		       MT_CONN_INFRA_ADIE1_RESET_MASK, 0x1);
341 
342 	if (is_mt7986(&dev->mt76)) {
343 		mt76_rmw_field(dev, MT_CONN_INFRA_ADIE_RESET,
344 			       MT_CONN_INFRA_ADIE2_RESET_MASK, 0x1);
345 	}
346 
347 	mt76_wmac_spi_lock(dev);
348 
349 	ret = mt76_wmac_spi_read(dev, 0, MT_ADIE_CHIP_ID, &adie_main);
350 	if (ret)
351 		goto out;
352 
353 	if (is_mt7986(&dev->mt76)) {
354 		ret = mt76_wmac_spi_read(dev, 1, MT_ADIE_CHIP_ID, &adie_ext);
355 		if (ret)
356 			goto out;
357 	}
358 
359 	*adie_type = FIELD_GET(MT_ADIE_CHIP_ID_MASK, adie_main) |
360 		     (MT_ADIE_CHIP_ID_MASK & adie_ext);
361 
362 out:
363 	mt76_wmac_spi_unlock(dev);
364 
365 	return 0;
366 }
367 
mt7986_adie_idx(u8 adie,u32 adie_type)368 static inline u16 mt7986_adie_idx(u8 adie, u32 adie_type)
369 {
370 	if (adie == 0)
371 		return u32_get_bits(adie_type, MT_ADIE_IDX0);
372 	else
373 		return u32_get_bits(adie_type, MT_ADIE_IDX1);
374 }
375 
is_7975(struct mt7915_dev * dev,u8 adie,u32 adie_type)376 static inline bool is_7975(struct mt7915_dev *dev, u8 adie, u32 adie_type)
377 {
378 	return mt7986_adie_idx(adie, adie_type) == 0x7975;
379 }
380 
is_7976(struct mt7915_dev * dev,u8 adie,u32 adie_type)381 static inline bool is_7976(struct mt7915_dev *dev, u8 adie, u32 adie_type)
382 {
383 	return mt7986_adie_idx(adie, adie_type) == 0x7976;
384 }
385 
mt7986_wmac_adie_thermal_cal(struct mt7915_dev * dev,u8 adie)386 static int mt7986_wmac_adie_thermal_cal(struct mt7915_dev *dev, u8 adie)
387 {
388 	int ret;
389 	u32 data, val;
390 
391 	ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_THADC_ANALOG,
392 					  &data);
393 	if (ret || FIELD_GET(MT_ADIE_ANA_EN_MASK, data)) {
394 		val = FIELD_GET(MT_ADIE_VRPI_SEL_EFUSE_MASK, data);
395 		ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_RG_TOP_THADC_BG,
396 					MT_ADIE_VRPI_SEL_CR_MASK,
397 					FIELD_PREP(MT_ADIE_VRPI_SEL_CR_MASK, val));
398 		if (ret)
399 			return ret;
400 
401 		val = FIELD_GET(MT_ADIE_PGA_GAIN_EFUSE_MASK, data);
402 		ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_RG_TOP_THADC,
403 					MT_ADIE_PGA_GAIN_MASK,
404 					FIELD_PREP(MT_ADIE_PGA_GAIN_MASK, val));
405 		if (ret)
406 			return ret;
407 	}
408 
409 	ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_THADC_SLOP,
410 					  &data);
411 	if (ret || FIELD_GET(MT_ADIE_ANA_EN_MASK, data)) {
412 		val = FIELD_GET(MT_ADIE_LDO_CTRL_EFUSE_MASK, data);
413 
414 		return mt76_wmac_spi_rmw(dev, adie, MT_ADIE_RG_TOP_THADC,
415 					 MT_ADIE_LDO_CTRL_MASK,
416 					 FIELD_PREP(MT_ADIE_LDO_CTRL_MASK, val));
417 	}
418 
419 	return 0;
420 }
421 
422 static int
mt7986_read_efuse_xo_trim_7976(struct mt7915_dev * dev,u8 adie,bool is_40m,int * result)423 mt7986_read_efuse_xo_trim_7976(struct mt7915_dev *dev, u8 adie,
424 			       bool is_40m, int *result)
425 {
426 	int ret;
427 	u32 data, addr;
428 
429 	addr = is_40m ? MT_ADIE_XTAL_AXM_40M_OSC : MT_ADIE_XTAL_AXM_80M_OSC;
430 	ret = mt7986_wmac_adie_efuse_read(dev, adie, addr, &data);
431 	if (ret)
432 		return ret;
433 
434 	if (!FIELD_GET(MT_ADIE_XO_TRIM_EN_MASK, data)) {
435 		*result = 64;
436 	} else {
437 		*result = FIELD_GET(MT_ADIE_TRIM_MASK, data);
438 		addr = is_40m ? MT_ADIE_XTAL_TRIM1_40M_OSC :
439 				MT_ADIE_XTAL_TRIM1_80M_OSC;
440 		ret = mt7986_wmac_adie_efuse_read(dev, adie, addr, &data);
441 		if (ret)
442 			return ret;
443 
444 		if (FIELD_GET(MT_ADIE_XO_TRIM_EN_MASK, data) &&
445 		    FIELD_GET(MT_ADIE_XTAL_DECREASE_MASK, data))
446 			*result -= FIELD_GET(MT_ADIE_EFUSE_TRIM_MASK, data);
447 		else if (FIELD_GET(MT_ADIE_XO_TRIM_EN_MASK, data))
448 			*result += FIELD_GET(MT_ADIE_EFUSE_TRIM_MASK, data);
449 
450 		*result = max(0, min(127, *result));
451 	}
452 
453 	return 0;
454 }
455 
mt7986_wmac_adie_xtal_trim_7976(struct mt7915_dev * dev,u8 adie)456 static int mt7986_wmac_adie_xtal_trim_7976(struct mt7915_dev *dev, u8 adie)
457 {
458 	int ret, trim_80m, trim_40m;
459 	u32 data, val, mode;
460 
461 	ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_XO_TRIM_FLOW,
462 					  &data);
463 	if (ret || !FIELD_GET(BIT(1), data))
464 		return 0;
465 
466 	ret = mt7986_read_efuse_xo_trim_7976(dev, adie, false, &trim_80m);
467 	if (ret)
468 		return ret;
469 
470 	ret = mt7986_read_efuse_xo_trim_7976(dev, adie, true, &trim_40m);
471 	if (ret)
472 		return ret;
473 
474 	ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_RG_STRAP_PIN_IN, &val);
475 	if (ret)
476 		return ret;
477 
478 	mode = FIELD_PREP(GENMASK(6, 4), val);
479 	if (!mode || mode == 0x2) {
480 		ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C1,
481 					GENMASK(31, 24),
482 					FIELD_PREP(GENMASK(31, 24), trim_80m));
483 		if (ret)
484 			return ret;
485 
486 		ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C2,
487 					GENMASK(31, 24),
488 					FIELD_PREP(GENMASK(31, 24), trim_80m));
489 	} else if (mode == 0x3 || mode == 0x4 || mode == 0x6) {
490 		ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C1,
491 					GENMASK(23, 16),
492 					FIELD_PREP(GENMASK(23, 16), trim_40m));
493 		if (ret)
494 			return ret;
495 
496 		ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C2,
497 					GENMASK(23, 16),
498 					FIELD_PREP(GENMASK(23, 16), trim_40m));
499 	}
500 
501 	return ret;
502 }
503 
mt798x_wmac_adie_patch_7976(struct mt7915_dev * dev,u8 adie)504 static int mt798x_wmac_adie_patch_7976(struct mt7915_dev *dev, u8 adie)
505 {
506 	u32 id, version, rg_xo_01, rg_xo_03;
507 	int ret;
508 
509 	ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_CHIP_ID, &id);
510 	if (ret)
511 		return ret;
512 
513 	version = FIELD_GET(MT_ADIE_VERSION_MASK, id);
514 
515 	ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_RG_TOP_THADC, 0x4a563b00);
516 	if (ret)
517 		return ret;
518 
519 	if (version == 0x8a00 || version == 0x8a10 || version == 0x8b00) {
520 		rg_xo_01 = 0x1d59080f;
521 		rg_xo_03 = 0x34c00fe0;
522 	} else {
523 		if (is_mt7981(&dev->mt76)) {
524 			rg_xo_01 = 0x1959c80f;
525 		} else if (is_mt7986(&dev->mt76)) {
526 			rg_xo_01 = 0x1959f80f;
527 		} else {
528 			WARN_ON(1);
529 			return -EINVAL;
530 		}
531 		rg_xo_03 = 0x34d00fe0;
532 	}
533 
534 	ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_RG_XO_01, rg_xo_01);
535 	if (ret)
536 		return ret;
537 
538 	return mt76_wmac_spi_write(dev, adie, MT_ADIE_RG_XO_03, rg_xo_03);
539 }
540 
541 static int
mt7986_read_efuse_xo_trim_7975(struct mt7915_dev * dev,u8 adie,u32 addr,u32 * result)542 mt7986_read_efuse_xo_trim_7975(struct mt7915_dev *dev, u8 adie,
543 			       u32 addr, u32 *result)
544 {
545 	int ret;
546 	u32 data;
547 
548 	ret = mt7986_wmac_adie_efuse_read(dev, adie, addr, &data);
549 	if (ret)
550 		return ret;
551 
552 	if ((data & MT_ADIE_XO_TRIM_EN_MASK)) {
553 		if ((data & MT_ADIE_XTAL_DECREASE_MASK))
554 			*result -= (data & MT_ADIE_EFUSE_TRIM_MASK);
555 		else
556 			*result += (data & MT_ADIE_EFUSE_TRIM_MASK);
557 
558 		*result = (*result & MT_ADIE_TRIM_MASK);
559 	}
560 
561 	return 0;
562 }
563 
mt7986_wmac_adie_xtal_trim_7975(struct mt7915_dev * dev,u8 adie)564 static int mt7986_wmac_adie_xtal_trim_7975(struct mt7915_dev *dev, u8 adie)
565 {
566 	int ret;
567 	u32 data, result = 0, value;
568 
569 	ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_7975_XTAL_EN,
570 					  &data);
571 	if (ret || !(data & BIT(1)))
572 		return 0;
573 
574 	ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_7975_XTAL_CAL,
575 					  &data);
576 	if (ret)
577 		return ret;
578 
579 	if (data & MT_ADIE_XO_TRIM_EN_MASK)
580 		result = (data & MT_ADIE_TRIM_MASK);
581 
582 	ret = mt7986_read_efuse_xo_trim_7975(dev, adie, MT_ADIE_7975_XO_TRIM2,
583 					     &result);
584 	if (ret)
585 		return ret;
586 
587 	ret = mt7986_read_efuse_xo_trim_7975(dev, adie, MT_ADIE_7975_XO_TRIM3,
588 					     &result);
589 	if (ret)
590 		return ret;
591 
592 	ret = mt7986_read_efuse_xo_trim_7975(dev, adie, MT_ADIE_7975_XO_TRIM4,
593 					     &result);
594 	if (ret)
595 		return ret;
596 
597 	/* Update trim value to C1 and C2*/
598 	value = FIELD_GET(MT_ADIE_7975_XO_CTRL2_C1_MASK, result) |
599 		FIELD_GET(MT_ADIE_7975_XO_CTRL2_C2_MASK, result);
600 	ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_XO_CTRL2,
601 				MT_ADIE_7975_XO_CTRL2_MASK, value);
602 	if (ret)
603 		return ret;
604 
605 	ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_7975_XTAL, &value);
606 	if (ret)
607 		return ret;
608 
609 	if (value & MT_ADIE_7975_XTAL_EN_MASK) {
610 		ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_XO_2,
611 					MT_ADIE_7975_XO_2_FIX_EN, 0x0);
612 		if (ret)
613 			return ret;
614 	}
615 
616 	return mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_XO_CTRL6,
617 				 MT_ADIE_7975_XO_CTRL6_MASK, 0x1);
618 }
619 
mt7986_wmac_adie_patch_7975(struct mt7915_dev * dev,u8 adie)620 static int mt7986_wmac_adie_patch_7975(struct mt7915_dev *dev, u8 adie)
621 {
622 	int ret;
623 
624 	/* disable CAL LDO and fine tune RFDIG LDO */
625 	ret = mt76_wmac_spi_write(dev, adie, 0x348, 0x00000002);
626 	if (ret)
627 		return ret;
628 
629 	ret = mt76_wmac_spi_write(dev, adie, 0x378, 0x00000002);
630 	if (ret)
631 		return ret;
632 
633 	ret = mt76_wmac_spi_write(dev, adie, 0x3a8, 0x00000002);
634 	if (ret)
635 		return ret;
636 
637 	ret = mt76_wmac_spi_write(dev, adie, 0x3d8, 0x00000002);
638 	if (ret)
639 		return ret;
640 
641 	/* set CKA driving and filter */
642 	ret = mt76_wmac_spi_write(dev, adie, 0xa1c, 0x30000aaa);
643 	if (ret)
644 		return ret;
645 
646 	/* set CKB LDO to 1.4V */
647 	ret = mt76_wmac_spi_write(dev, adie, 0xa84, 0x8470008a);
648 	if (ret)
649 		return ret;
650 
651 	/* turn on SX0 LTBUF */
652 	if (is_mt7981(&dev->mt76)) {
653 		ret = mt76_wmac_spi_write(dev, adie, 0x074, 0x00000007);
654 	} else if (is_mt7986(&dev->mt76)) {
655 		ret = mt76_wmac_spi_write(dev, adie, 0x074, 0x00000002);
656 	} else {
657 		WARN_ON(1);
658 		return -EINVAL;
659 	}
660 
661 	if (ret)
662 		return ret;
663 
664 	/* CK_BUF_SW_EN = 1 (all buf in manual mode.) */
665 	ret = mt76_wmac_spi_write(dev, adie, 0xaa4, 0x01001fc0);
666 	if (ret)
667 		return ret;
668 
669 	/* BT mode/WF normal mode 00000005 */
670 	ret = mt76_wmac_spi_write(dev, adie, 0x070, 0x00000005);
671 	if (ret)
672 		return ret;
673 
674 	/* BG thermal sensor offset update */
675 	ret = mt76_wmac_spi_write(dev, adie, 0x344, 0x00000088);
676 	if (ret)
677 		return ret;
678 
679 	ret = mt76_wmac_spi_write(dev, adie, 0x374, 0x00000088);
680 	if (ret)
681 		return ret;
682 
683 	ret = mt76_wmac_spi_write(dev, adie, 0x3a4, 0x00000088);
684 	if (ret)
685 		return ret;
686 
687 	ret = mt76_wmac_spi_write(dev, adie, 0x3d4, 0x00000088);
688 	if (ret)
689 		return ret;
690 
691 	/* set WCON VDD IPTAT to "0000" */
692 	ret = mt76_wmac_spi_write(dev, adie, 0xa80, 0x44d07000);
693 	if (ret)
694 		return ret;
695 
696 	/* change back LTBUF SX3 drving to default value */
697 	ret = mt76_wmac_spi_write(dev, adie, 0xa88, 0x3900aaaa);
698 	if (ret)
699 		return ret;
700 
701 	/* SM input cap off */
702 	ret = mt76_wmac_spi_write(dev, adie, 0x2c4, 0x00000000);
703 	if (ret)
704 		return ret;
705 
706 	/* set CKB driving and filter */
707 	if (is_mt7986(&dev->mt76))
708 		return mt76_wmac_spi_write(dev, adie, 0x2c8, 0x00000072);
709 
710 	return ret;
711 }
712 
mt7986_wmac_adie_cfg(struct mt7915_dev * dev,u8 adie,u32 adie_type)713 static int mt7986_wmac_adie_cfg(struct mt7915_dev *dev, u8 adie, u32 adie_type)
714 {
715 	int ret;
716 
717 	mt76_wmac_spi_lock(dev);
718 	ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_CLK_EN, ~0);
719 	if (ret)
720 		goto out;
721 
722 	if (is_7975(dev, adie, adie_type)) {
723 		ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_COCLK,
724 					BIT(1), 0x1);
725 		if (ret)
726 			goto out;
727 
728 		ret = mt7986_wmac_adie_thermal_cal(dev, adie);
729 		if (ret)
730 			goto out;
731 
732 		ret = mt7986_wmac_adie_xtal_trim_7975(dev, adie);
733 		if (ret)
734 			goto out;
735 
736 		ret = mt7986_wmac_adie_patch_7975(dev, adie);
737 	} else if (is_7976(dev, adie, adie_type)) {
738 		if (mt798x_wmac_check_adie_type(dev) == ADIE_DBDC) {
739 			ret = mt76_wmac_spi_write(dev, adie,
740 						  MT_ADIE_WRI_CK_SEL, 0x1c);
741 			if (ret)
742 				goto out;
743 		}
744 
745 		ret = mt7986_wmac_adie_thermal_cal(dev, adie);
746 		if (ret)
747 			goto out;
748 
749 		ret = mt7986_wmac_adie_xtal_trim_7976(dev, adie);
750 		if (ret)
751 			goto out;
752 
753 		ret = mt798x_wmac_adie_patch_7976(dev, adie);
754 	}
755 out:
756 	mt76_wmac_spi_unlock(dev);
757 
758 	return ret;
759 }
760 
761 static int
mt7986_wmac_afe_cal(struct mt7915_dev * dev,u8 adie,bool dbdc,u32 adie_type)762 mt7986_wmac_afe_cal(struct mt7915_dev *dev, u8 adie, bool dbdc, u32 adie_type)
763 {
764 	int ret;
765 	u8 idx;
766 	u32 txcal;
767 
768 	mt76_wmac_spi_lock(dev);
769 	if (is_7975(dev, adie, adie_type))
770 		ret = mt76_wmac_spi_write(dev, adie,
771 					  MT_AFE_RG_ENCAL_WBTAC_IF_SW,
772 					  0x80000000);
773 	else
774 		ret = mt76_wmac_spi_write(dev, adie,
775 					  MT_AFE_RG_ENCAL_WBTAC_IF_SW,
776 					  0x88888005);
777 	if (ret)
778 		goto out;
779 
780 	idx = dbdc ? ADIE_DBDC : adie;
781 
782 	mt76_rmw_field(dev, MT_AFE_DIG_EN_01(idx),
783 		       MT_AFE_RG_WBG_EN_RCK_MASK, 0x1);
784 	usleep_range(60, 100);
785 
786 	mt76_rmw(dev, MT_AFE_DIG_EN_01(idx),
787 		 MT_AFE_RG_WBG_EN_RCK_MASK, 0x0);
788 
789 	mt76_rmw_field(dev, MT_AFE_DIG_EN_03(idx),
790 		       MT_AFE_RG_WBG_EN_BPLL_UP_MASK, 0x1);
791 	usleep_range(30, 100);
792 
793 	mt76_rmw_field(dev, MT_AFE_DIG_EN_03(idx),
794 		       MT_AFE_RG_WBG_EN_WPLL_UP_MASK, 0x1);
795 	usleep_range(60, 100);
796 
797 	txcal = (MT_AFE_RG_WBG_EN_TXCAL_BT |
798 		      MT_AFE_RG_WBG_EN_TXCAL_WF0 |
799 		      MT_AFE_RG_WBG_EN_TXCAL_WF1 |
800 		      MT_AFE_RG_WBG_EN_TXCAL_WF2 |
801 		      MT_AFE_RG_WBG_EN_TXCAL_WF3);
802 	if (is_mt7981(&dev->mt76))
803 		txcal |= MT_AFE_RG_WBG_EN_TXCAL_WF4;
804 
805 	mt76_set(dev, MT_AFE_DIG_EN_01(idx), txcal);
806 	usleep_range(800, 1000);
807 
808 	mt76_clear(dev, MT_AFE_DIG_EN_01(idx), txcal);
809 	mt76_rmw(dev, MT_AFE_DIG_EN_03(idx),
810 		 MT_AFE_RG_WBG_EN_PLL_UP_MASK, 0x0);
811 
812 	ret = mt76_wmac_spi_write(dev, adie, MT_AFE_RG_ENCAL_WBTAC_IF_SW,
813 				  0x5);
814 
815 out:
816 	mt76_wmac_spi_unlock(dev);
817 
818 	return ret;
819 }
820 
mt7986_wmac_subsys_pll_initial(struct mt7915_dev * dev,u8 band)821 static void mt7986_wmac_subsys_pll_initial(struct mt7915_dev *dev, u8 band)
822 {
823 	mt76_rmw(dev, MT_AFE_PLL_STB_TIME(band),
824 		 MT_AFE_PLL_STB_TIME_MASK, MT_AFE_PLL_STB_TIME_VAL);
825 
826 	mt76_rmw(dev, MT_AFE_DIG_EN_02(band),
827 		 MT_AFE_PLL_CFG_MASK, MT_AFE_PLL_CFG_VAL);
828 
829 	mt76_rmw(dev, MT_AFE_DIG_TOP_01(band),
830 		 MT_AFE_DIG_TOP_01_MASK, MT_AFE_DIG_TOP_01_VAL);
831 }
832 
mt7986_wmac_subsys_setting(struct mt7915_dev * dev)833 static void mt7986_wmac_subsys_setting(struct mt7915_dev *dev)
834 {
835 	/* Subsys pll init */
836 	mt7986_wmac_subsys_pll_initial(dev, 0);
837 	mt7986_wmac_subsys_pll_initial(dev, 1);
838 
839 	/* Set legacy OSC control stable time*/
840 	mt76_rmw(dev, MT_CONN_INFRA_OSC_RC_EN,
841 		 MT_CONN_INFRA_OSC_RC_EN_MASK, 0x0);
842 	mt76_rmw(dev, MT_CONN_INFRA_OSC_CTRL,
843 		 MT_CONN_INFRA_OSC_STB_TIME_MASK, 0x80706);
844 
845 	/* prevent subsys from power on/of in a short time interval */
846 	mt76_rmw(dev, MT_TOP_WFSYS_PWR,
847 		 MT_TOP_PWR_ACK_MASK | MT_TOP_PWR_KEY_MASK,
848 		 MT_TOP_PWR_KEY);
849 }
850 
mt7986_wmac_bus_timeout(struct mt7915_dev * dev)851 static int mt7986_wmac_bus_timeout(struct mt7915_dev *dev)
852 {
853 	mt76_rmw_field(dev, MT_INFRA_BUS_OFF_TIMEOUT,
854 		       MT_INFRA_BUS_TIMEOUT_LIMIT_MASK, 0x2);
855 
856 	mt76_rmw_field(dev, MT_INFRA_BUS_OFF_TIMEOUT,
857 		       MT_INFRA_BUS_TIMEOUT_EN_MASK, 0xf);
858 
859 	mt76_rmw_field(dev, MT_INFRA_BUS_ON_TIMEOUT,
860 		       MT_INFRA_BUS_TIMEOUT_LIMIT_MASK, 0xc);
861 
862 	mt76_rmw_field(dev, MT_INFRA_BUS_ON_TIMEOUT,
863 		       MT_INFRA_BUS_TIMEOUT_EN_MASK, 0xf);
864 
865 	return mt798x_wmac_coninfra_check(dev);
866 }
867 
mt7986_wmac_clock_enable(struct mt7915_dev * dev,u32 adie_type)868 static void mt7986_wmac_clock_enable(struct mt7915_dev *dev, u32 adie_type)
869 {
870 	u32 cur;
871 
872 	mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_1,
873 		       MT_INFRA_CKGEN_DIV_SEL_MASK, 0x1);
874 
875 	mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_2,
876 		       MT_INFRA_CKGEN_DIV_SEL_MASK, 0x1);
877 
878 	mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_1,
879 		       MT_INFRA_CKGEN_DIV_EN_MASK, 0x1);
880 
881 	mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_2,
882 		       MT_INFRA_CKGEN_DIV_EN_MASK, 0x1);
883 
884 	mt76_rmw_field(dev, MT_INFRA_CKGEN_RFSPI_WPLL_DIV,
885 		       MT_INFRA_CKGEN_DIV_SEL_MASK, 0x8);
886 
887 	mt76_rmw_field(dev, MT_INFRA_CKGEN_RFSPI_WPLL_DIV,
888 		       MT_INFRA_CKGEN_DIV_EN_MASK, 0x1);
889 
890 	mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS,
891 		       MT_INFRA_CKGEN_BUS_CLK_SEL_MASK, 0x0);
892 
893 	mt76_rmw_field(dev, MT_CONN_INFRA_HW_CTRL,
894 		       MT_CONN_INFRA_HW_CTRL_MASK, 0x1);
895 
896 	mt76_rmw(dev, MT_TOP_CONN_INFRA_WAKEUP,
897 		 MT_TOP_CONN_INFRA_WAKEUP_MASK, 0x1);
898 
899 	usleep_range(900, 1000);
900 
901 	mt76_wmac_spi_lock(dev);
902 	if (is_7975(dev, 0, adie_type) || is_7976(dev, 0, adie_type)) {
903 		mt76_rmw_field(dev, MT_ADIE_SLP_CTRL_CK0(0),
904 			       MT_SLP_CTRL_EN_MASK, 0x1);
905 
906 		read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_CTRL_BSY_MASK),
907 				  USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
908 				  dev, MT_ADIE_SLP_CTRL_CK0(0));
909 	}
910 	if (is_7975(dev, 1, adie_type) || is_7976(dev, 1, adie_type)) {
911 		mt76_rmw_field(dev, MT_ADIE_SLP_CTRL_CK0(1),
912 			       MT_SLP_CTRL_EN_MASK, 0x1);
913 
914 		read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_CTRL_BSY_MASK),
915 				  USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
916 				  dev, MT_ADIE_SLP_CTRL_CK0(0));
917 	}
918 	mt76_wmac_spi_unlock(dev);
919 
920 	mt76_rmw(dev, MT_TOP_CONN_INFRA_WAKEUP,
921 		 MT_TOP_CONN_INFRA_WAKEUP_MASK, 0x0);
922 	usleep_range(900, 1000);
923 }
924 
mt7986_wmac_top_wfsys_wakeup(struct mt7915_dev * dev,bool enable)925 static int mt7986_wmac_top_wfsys_wakeup(struct mt7915_dev *dev, bool enable)
926 {
927 	mt76_rmw_field(dev, MT_TOP_WFSYS_WAKEUP,
928 		       MT_TOP_WFSYS_WAKEUP_MASK, enable);
929 
930 	usleep_range(900, 1000);
931 
932 	if (!enable)
933 		return 0;
934 
935 	return mt798x_wmac_coninfra_check(dev);
936 }
937 
mt7986_wmac_wm_enable(struct mt7915_dev * dev,bool enable)938 static int mt7986_wmac_wm_enable(struct mt7915_dev *dev, bool enable)
939 {
940 	u32 cur;
941 
942 	if (is_mt7986(&dev->mt76))
943 		mt76_wr(dev, MT_CONNINFRA_SKU_DEC_ADDR, 0);
944 
945 	mt76_rmw_field(dev, MT7986_TOP_WM_RESET,
946 		       MT7986_TOP_WM_RESET_MASK, enable);
947 	if (!enable)
948 		return 0;
949 
950 	return read_poll_timeout(mt76_rr, cur, (cur == 0x1d1e),
951 				 USEC_PER_MSEC, 5000 * USEC_PER_MSEC, false,
952 				 dev, MT_TOP_CFG_ON_ROM_IDX);
953 }
954 
mt7986_wmac_wfsys_poweron(struct mt7915_dev * dev,bool enable)955 static int mt7986_wmac_wfsys_poweron(struct mt7915_dev *dev, bool enable)
956 {
957 	u32 mask = MT_TOP_PWR_EN_MASK | MT_TOP_PWR_KEY_MASK;
958 	u32 cur;
959 
960 	mt76_rmw(dev, MT_TOP_WFSYS_PWR, mask,
961 		 MT_TOP_PWR_KEY | FIELD_PREP(MT_TOP_PWR_EN_MASK, enable));
962 
963 	return read_poll_timeout(mt76_rr, cur,
964 		(FIELD_GET(MT_TOP_WFSYS_RESET_STATUS_MASK, cur) == enable),
965 		USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
966 		dev, MT_TOP_WFSYS_RESET_STATUS);
967 }
968 
mt7986_wmac_wfsys_setting(struct mt7915_dev * dev)969 static int mt7986_wmac_wfsys_setting(struct mt7915_dev *dev)
970 {
971 	int ret;
972 	u32 cur;
973 
974 	/* Turn off wfsys2conn bus sleep protect */
975 	mt76_rmw(dev, MT_CONN_INFRA_WF_SLP_PROT,
976 		 MT_CONN_INFRA_WF_SLP_PROT_MASK, 0x0);
977 
978 	ret = mt7986_wmac_wfsys_poweron(dev, true);
979 	if (ret)
980 		return ret;
981 
982 	/* Check bus sleep protect */
983 
984 	ret = read_poll_timeout(mt76_rr, cur,
985 				!(cur & MT_CONN_INFRA_CONN_WF_MASK),
986 				USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
987 				dev, MT_CONN_INFRA_WF_SLP_PROT_RDY);
988 	if (ret)
989 		return ret;
990 
991 	ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_WFDMA2CONN_MASK),
992 				USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
993 				dev, MT_SLP_STATUS);
994 	if (ret)
995 		return ret;
996 
997 	return read_poll_timeout(mt76_rr, cur, (cur == 0x02060000),
998 				 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
999 				 dev, MT_TOP_CFG_IP_VERSION_ADDR);
1000 }
1001 
mt7986_wmac_wfsys_set_timeout(struct mt7915_dev * dev)1002 static void mt7986_wmac_wfsys_set_timeout(struct mt7915_dev *dev)
1003 {
1004 	u32 mask = MT_MCU_BUS_TIMEOUT_SET_MASK |
1005 		   MT_MCU_BUS_TIMEOUT_CG_EN_MASK |
1006 		   MT_MCU_BUS_TIMEOUT_EN_MASK;
1007 	u32 val = FIELD_PREP(MT_MCU_BUS_TIMEOUT_SET_MASK, 1) |
1008 		  FIELD_PREP(MT_MCU_BUS_TIMEOUT_CG_EN_MASK, 1) |
1009 		  FIELD_PREP(MT_MCU_BUS_TIMEOUT_EN_MASK, 1);
1010 
1011 	mt76_rmw(dev, MT_MCU_BUS_TIMEOUT, mask, val);
1012 
1013 	mt76_wr(dev, MT_MCU_BUS_REMAP, 0x810f0000);
1014 
1015 	mask = MT_MCU_BUS_DBG_TIMEOUT_SET_MASK |
1016 	       MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK |
1017 	       MT_MCU_BUS_DBG_TIMEOUT_EN_MASK;
1018 	val = FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_SET_MASK, 0x3aa) |
1019 	      FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK, 1) |
1020 	      FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_EN_MASK, 1);
1021 
1022 	mt76_rmw(dev, MT_MCU_BUS_DBG_TIMEOUT, mask, val);
1023 }
1024 
mt7986_wmac_sku_update(struct mt7915_dev * dev,u32 adie_type)1025 static int mt7986_wmac_sku_update(struct mt7915_dev *dev, u32 adie_type)
1026 {
1027 	u32 val;
1028 
1029 	if (is_7976(dev, 0, adie_type) && is_7976(dev, 1, adie_type))
1030 		val = 0xf;
1031 	else if (is_7975(dev, 0, adie_type) && is_7975(dev, 1, adie_type))
1032 		val = 0xd;
1033 	else if (is_7976(dev, 0, adie_type))
1034 		val = 0x7;
1035 	else if (is_7975(dev, 1, adie_type))
1036 		val = 0x8;
1037 	else if (is_7976(dev, 1, adie_type))
1038 		val = 0xa;
1039 	else
1040 		return -EINVAL;
1041 
1042 	mt76_wmac_rmw(dev->sku, MT_TOP_POS_SKU, MT_TOP_POS_SKU_MASK,
1043 		      FIELD_PREP(MT_TOP_POS_SKU_MASK, val));
1044 
1045 	mt76_wr(dev, MT_CONNINFRA_SKU_DEC_ADDR, val);
1046 
1047 	return 0;
1048 }
1049 
1050 static int
mt7986_wmac_adie_setup(struct mt7915_dev * dev,u8 adie,u32 adie_type)1051 mt7986_wmac_adie_setup(struct mt7915_dev *dev, u8 adie, u32 adie_type)
1052 {
1053 	int ret;
1054 
1055 	if (!(is_7975(dev, adie, adie_type) || is_7976(dev, adie, adie_type)))
1056 		return 0;
1057 
1058 	ret = mt7986_wmac_adie_cfg(dev, adie, adie_type);
1059 	if (ret)
1060 		return ret;
1061 
1062 	ret = mt7986_wmac_afe_cal(dev, adie, false, adie_type);
1063 	if (ret)
1064 		return ret;
1065 
1066 	if (!adie && (mt798x_wmac_check_adie_type(dev) == ADIE_DBDC))
1067 		ret = mt7986_wmac_afe_cal(dev, adie, true, adie_type);
1068 
1069 	return ret;
1070 }
1071 
mt7986_wmac_subsys_powerup(struct mt7915_dev * dev,u32 adie_type)1072 static int mt7986_wmac_subsys_powerup(struct mt7915_dev *dev, u32 adie_type)
1073 {
1074 	int ret;
1075 
1076 	mt7986_wmac_subsys_setting(dev);
1077 
1078 	ret = mt7986_wmac_bus_timeout(dev);
1079 	if (ret)
1080 		return ret;
1081 
1082 	mt7986_wmac_clock_enable(dev, adie_type);
1083 
1084 	return 0;
1085 }
1086 
mt7986_wmac_wfsys_powerup(struct mt7915_dev * dev)1087 static int mt7986_wmac_wfsys_powerup(struct mt7915_dev *dev)
1088 {
1089 	int ret;
1090 
1091 	ret = mt7986_wmac_wm_enable(dev, false);
1092 	if (ret)
1093 		return ret;
1094 
1095 	ret = mt7986_wmac_wfsys_setting(dev);
1096 	if (ret)
1097 		return ret;
1098 
1099 	mt7986_wmac_wfsys_set_timeout(dev);
1100 
1101 	return mt7986_wmac_wm_enable(dev, true);
1102 }
1103 
mt7986_wmac_enable(struct mt7915_dev * dev)1104 int mt7986_wmac_enable(struct mt7915_dev *dev)
1105 {
1106 	int ret;
1107 	u32 adie_type;
1108 
1109 	ret = mt7986_wmac_consys_reset(dev, true);
1110 	if (ret)
1111 		return ret;
1112 
1113 	ret = mt7986_wmac_gpio_setup(dev);
1114 	if (ret)
1115 		return ret;
1116 
1117 	ret = mt7986_wmac_consys_lockup(dev, false);
1118 	if (ret)
1119 		return ret;
1120 
1121 	ret = mt798x_wmac_coninfra_check(dev);
1122 	if (ret)
1123 		return ret;
1124 
1125 	ret = mt798x_wmac_coninfra_setup(dev);
1126 	if (ret)
1127 		return ret;
1128 
1129 	ret = mt798x_wmac_sku_setup(dev, &adie_type);
1130 	if (ret)
1131 		return ret;
1132 
1133 	ret = mt7986_wmac_adie_setup(dev, 0, adie_type);
1134 	if (ret)
1135 		return ret;
1136 
1137 	/* mt7981 doesn't support a second a-die */
1138 	if (is_mt7986(&dev->mt76)) {
1139 		ret = mt7986_wmac_adie_setup(dev, 1, adie_type);
1140 		if (ret)
1141 			return ret;
1142 	}
1143 
1144 	ret = mt7986_wmac_subsys_powerup(dev, adie_type);
1145 	if (ret)
1146 		return ret;
1147 
1148 	ret = mt7986_wmac_top_wfsys_wakeup(dev, true);
1149 	if (ret)
1150 		return ret;
1151 
1152 	ret = mt7986_wmac_wfsys_powerup(dev);
1153 	if (ret)
1154 		return ret;
1155 
1156 	return mt7986_wmac_sku_update(dev, adie_type);
1157 }
1158 
mt7986_wmac_disable(struct mt7915_dev * dev)1159 void mt7986_wmac_disable(struct mt7915_dev *dev)
1160 {
1161 	u32 cur;
1162 
1163 	mt7986_wmac_top_wfsys_wakeup(dev, true);
1164 
1165 	/* Turn on wfsys2conn bus sleep protect */
1166 	mt76_rmw_field(dev, MT_CONN_INFRA_WF_SLP_PROT,
1167 		       MT_CONN_INFRA_WF_SLP_PROT_MASK, 0x1);
1168 
1169 	/* Check wfsys2conn bus sleep protect */
1170 	read_poll_timeout(mt76_rr, cur, !(cur ^ MT_CONN_INFRA_CONN),
1171 			  USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
1172 			  dev, MT_CONN_INFRA_WF_SLP_PROT_RDY);
1173 
1174 	mt7986_wmac_wfsys_poweron(dev, false);
1175 
1176 	/* Turn back wpll setting */
1177 	mt76_rmw_field(dev, MT_AFE_DIG_EN_02(0), MT_AFE_MCU_BPLL_CFG_MASK, 0x2);
1178 	mt76_rmw_field(dev, MT_AFE_DIG_EN_02(0), MT_AFE_WPLL_CFG_MASK, 0x2);
1179 
1180 	/* Reset EMI */
1181 	mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ,
1182 		       MT_CONN_INFRA_EMI_REQ_MASK, 0x1);
1183 	mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ,
1184 		       MT_CONN_INFRA_EMI_REQ_MASK, 0x0);
1185 	mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ,
1186 		       MT_CONN_INFRA_INFRA_REQ_MASK, 0x1);
1187 	mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ,
1188 		       MT_CONN_INFRA_INFRA_REQ_MASK, 0x0);
1189 
1190 	mt7986_wmac_top_wfsys_wakeup(dev, false);
1191 	mt7986_wmac_consys_lockup(dev, true);
1192 	mt7986_wmac_consys_reset(dev, false);
1193 }
1194 
mt798x_wmac_init(struct mt7915_dev * dev)1195 static int mt798x_wmac_init(struct mt7915_dev *dev)
1196 {
1197 	struct device *pdev = dev->mt76.dev;
1198 	struct platform_device *pfdev = to_platform_device(pdev);
1199 	struct clk *mcu_clk, *ap_conn_clk;
1200 
1201 	mcu_clk = devm_clk_get(pdev, "mcu");
1202 	if (IS_ERR(mcu_clk))
1203 		dev_err(pdev, "mcu clock not found\n");
1204 	else if (clk_prepare_enable(mcu_clk))
1205 		dev_err(pdev, "mcu clock configuration failed\n");
1206 
1207 	ap_conn_clk = devm_clk_get(pdev, "ap2conn");
1208 	if (IS_ERR(ap_conn_clk))
1209 		dev_err(pdev, "ap2conn clock not found\n");
1210 	else if (clk_prepare_enable(ap_conn_clk))
1211 		dev_err(pdev, "ap2conn clock configuration failed\n");
1212 
1213 	dev->dcm = devm_platform_ioremap_resource(pfdev, 1);
1214 	if (IS_ERR(dev->dcm))
1215 		return PTR_ERR(dev->dcm);
1216 
1217 	dev->sku = devm_platform_ioremap_resource(pfdev, 2);
1218 	if (IS_ERR(dev->sku))
1219 		return PTR_ERR(dev->sku);
1220 
1221 	dev->rstc = devm_reset_control_get(pdev, "consys");
1222 	if (IS_ERR(dev->rstc))
1223 		return PTR_ERR(dev->rstc);
1224 
1225 	return 0;
1226 }
1227 
mt798x_wmac_probe(struct platform_device * pdev)1228 static int mt798x_wmac_probe(struct platform_device *pdev)
1229 {
1230 	void __iomem *mem_base;
1231 	struct mt7915_dev *dev;
1232 	struct mt76_dev *mdev;
1233 	int irq, ret;
1234 	u32 chip_id;
1235 
1236 	chip_id = (uintptr_t)of_device_get_match_data(&pdev->dev);
1237 
1238 	mem_base = devm_platform_ioremap_resource(pdev, 0);
1239 	if (IS_ERR(mem_base)) {
1240 		dev_err(&pdev->dev, "Failed to get memory resource\n");
1241 		return PTR_ERR(mem_base);
1242 	}
1243 
1244 	dev = mt7915_mmio_probe(&pdev->dev, mem_base, chip_id);
1245 	if (IS_ERR(dev))
1246 		return PTR_ERR(dev);
1247 
1248 	mdev = &dev->mt76;
1249 	ret = mt7915_mmio_wed_init(dev, pdev, false, &irq);
1250 	if (ret < 0)
1251 		goto free_device;
1252 
1253 	if (!ret) {
1254 		irq = platform_get_irq(pdev, 0);
1255 		if (irq < 0) {
1256 			ret = irq;
1257 			goto free_device;
1258 		}
1259 	}
1260 
1261 	ret = devm_request_irq(mdev->dev, irq, mt7915_irq_handler,
1262 			       IRQF_SHARED, KBUILD_MODNAME, dev);
1263 	if (ret)
1264 		goto free_device;
1265 
1266 	ret = mt798x_wmac_init(dev);
1267 	if (ret)
1268 		goto free_irq;
1269 
1270 	mt7915_wfsys_reset(dev);
1271 
1272 	ret = mt7915_register_device(dev);
1273 	if (ret)
1274 		goto free_irq;
1275 
1276 	return 0;
1277 
1278 free_irq:
1279 	devm_free_irq(mdev->dev, irq, dev);
1280 free_device:
1281 	if (mtk_wed_device_active(&mdev->mmio.wed))
1282 		mtk_wed_device_detach(&mdev->mmio.wed);
1283 	mt76_free_device(mdev);
1284 
1285 	return ret;
1286 }
1287 
mt798x_wmac_remove(struct platform_device * pdev)1288 static int mt798x_wmac_remove(struct platform_device *pdev)
1289 {
1290 	struct mt7915_dev *dev = platform_get_drvdata(pdev);
1291 
1292 	mt7915_unregister_device(dev);
1293 
1294 	return 0;
1295 }
1296 
1297 static const struct of_device_id mt798x_wmac_of_match[] = {
1298 	{ .compatible = "mediatek,mt7981-wmac", .data = (u32 *)0x7981 },
1299 	{ .compatible = "mediatek,mt7986-wmac", .data = (u32 *)0x7986 },
1300 	{},
1301 };
1302 
1303 MODULE_DEVICE_TABLE(of, mt798x_wmac_of_match);
1304 
1305 struct platform_driver mt798x_wmac_driver = {
1306 	.driver = {
1307 		.name = "mt798x-wmac",
1308 		.of_match_table = mt798x_wmac_of_match,
1309 	},
1310 	.probe = mt798x_wmac_probe,
1311 	.remove = mt798x_wmac_remove,
1312 };
1313 
1314 MODULE_FIRMWARE(MT7986_FIRMWARE_WA);
1315 MODULE_FIRMWARE(MT7986_FIRMWARE_WM);
1316 MODULE_FIRMWARE(MT7986_FIRMWARE_WM_MT7975);
1317 MODULE_FIRMWARE(MT7986_ROM_PATCH);
1318 MODULE_FIRMWARE(MT7986_ROM_PATCH_MT7975);
1319 
1320 MODULE_FIRMWARE(MT7981_FIRMWARE_WA);
1321 MODULE_FIRMWARE(MT7981_FIRMWARE_WM);
1322 MODULE_FIRMWARE(MT7981_ROM_PATCH);
1323