1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2022 MediaTek Inc. */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/platform_device.h> 7 #include <linux/pinctrl/consumer.h> 8 #include <linux/of.h> 9 #include <linux/of_device.h> 10 #include <linux/of_reserved_mem.h> 11 #include <linux/of_gpio.h> 12 #include <linux/iopoll.h> 13 #include <linux/reset.h> 14 #include <linux/of_net.h> 15 16 #include "mt7915.h" 17 18 /* INFRACFG */ 19 #define MT_INFRACFG_CONN2AP_SLPPROT 0x0d0 20 #define MT_INFRACFG_AP2CONN_SLPPROT 0x0d4 21 22 #define MT_INFRACFG_RX_EN_MASK BIT(16) 23 #define MT_INFRACFG_TX_RDY_MASK BIT(4) 24 #define MT_INFRACFG_TX_EN_MASK BIT(0) 25 26 /* TOP POS */ 27 #define MT_TOP_POS_FAST_CTRL 0x114 28 #define MT_TOP_POS_FAST_EN_MASK BIT(3) 29 30 #define MT_TOP_POS_SKU 0x21c 31 #define MT_TOP_POS_SKU_MASK GENMASK(31, 28) 32 #define MT_TOP_POS_SKU_ADIE_DBDC_MASK BIT(2) 33 34 enum { 35 ADIE_SB, 36 ADIE_DBDC 37 }; 38 39 static int 40 mt76_wmac_spi_read(struct mt7915_dev *dev, u8 adie, u32 addr, u32 *val) 41 { 42 int ret; 43 u32 cur; 44 45 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT), 46 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 47 dev, MT_TOP_SPI_BUSY_CR(adie)); 48 if (ret) 49 return ret; 50 51 mt76_wr(dev, MT_TOP_SPI_ADDR_CR(adie), 52 MT_TOP_SPI_READ_ADDR_FORMAT | addr); 53 mt76_wr(dev, MT_TOP_SPI_WRITE_DATA_CR(adie), 0); 54 55 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT), 56 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 57 dev, MT_TOP_SPI_BUSY_CR(adie)); 58 if (ret) 59 return ret; 60 61 *val = mt76_rr(dev, MT_TOP_SPI_READ_DATA_CR(adie)); 62 63 return 0; 64 } 65 66 static int 67 mt76_wmac_spi_write(struct mt7915_dev *dev, u8 adie, u32 addr, u32 val) 68 { 69 int ret; 70 u32 cur; 71 72 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT), 73 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 74 dev, MT_TOP_SPI_BUSY_CR(adie)); 75 if (ret) 76 return ret; 77 78 mt76_wr(dev, MT_TOP_SPI_ADDR_CR(adie), 79 MT_TOP_SPI_WRITE_ADDR_FORMAT | addr); 80 mt76_wr(dev, MT_TOP_SPI_WRITE_DATA_CR(adie), val); 81 82 return read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT), 83 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 84 dev, MT_TOP_SPI_BUSY_CR(adie)); 85 } 86 87 static int 88 mt76_wmac_spi_rmw(struct mt7915_dev *dev, u8 adie, 89 u32 addr, u32 mask, u32 val) 90 { 91 u32 cur, ret; 92 93 ret = mt76_wmac_spi_read(dev, adie, addr, &cur); 94 if (ret) 95 return ret; 96 97 cur &= ~mask; 98 cur |= val; 99 100 return mt76_wmac_spi_write(dev, adie, addr, cur); 101 } 102 103 static int 104 mt7986_wmac_adie_efuse_read(struct mt7915_dev *dev, u8 adie, 105 u32 addr, u32 *data) 106 { 107 int ret, temp; 108 u32 val, mask; 109 110 ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_EFUSE_CFG, 111 MT_ADIE_EFUSE_CTRL_MASK); 112 if (ret) 113 return ret; 114 115 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_EFUSE2_CTRL, BIT(30), 0x0); 116 if (ret) 117 return ret; 118 119 mask = (MT_ADIE_EFUSE_MODE_MASK | MT_ADIE_EFUSE_ADDR_MASK | 120 MT_ADIE_EFUSE_KICK_MASK); 121 val = FIELD_PREP(MT_ADIE_EFUSE_MODE_MASK, 0) | 122 FIELD_PREP(MT_ADIE_EFUSE_ADDR_MASK, addr) | 123 FIELD_PREP(MT_ADIE_EFUSE_KICK_MASK, 1); 124 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_EFUSE2_CTRL, mask, val); 125 if (ret) 126 return ret; 127 128 ret = read_poll_timeout(mt76_wmac_spi_read, temp, 129 !temp && !FIELD_GET(MT_ADIE_EFUSE_KICK_MASK, val), 130 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 131 dev, adie, MT_ADIE_EFUSE2_CTRL, &val); 132 if (ret) 133 return ret; 134 135 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_EFUSE2_CTRL, &val); 136 if (ret) 137 return ret; 138 139 if (FIELD_GET(MT_ADIE_EFUSE_VALID_MASK, val) == 1) 140 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_EFUSE_RDATA0, 141 data); 142 143 return ret; 144 } 145 146 static inline void mt76_wmac_spi_lock(struct mt7915_dev *dev) 147 { 148 u32 cur; 149 150 read_poll_timeout(mt76_rr, cur, 151 FIELD_GET(MT_SEMA_RFSPI_STATUS_MASK, cur), 152 1000, 1000 * MSEC_PER_SEC, false, dev, 153 MT_SEMA_RFSPI_STATUS); 154 } 155 156 static inline void mt76_wmac_spi_unlock(struct mt7915_dev *dev) 157 { 158 mt76_wr(dev, MT_SEMA_RFSPI_RELEASE, 1); 159 } 160 161 static u32 mt76_wmac_rmw(void __iomem *base, u32 offset, u32 mask, u32 val) 162 { 163 val |= readl(base + offset) & ~mask; 164 writel(val, base + offset); 165 166 return val; 167 } 168 169 static u8 mt7986_wmac_check_adie_type(struct mt7915_dev *dev) 170 { 171 u32 val; 172 173 val = readl(dev->sku + MT_TOP_POS_SKU); 174 175 return FIELD_GET(MT_TOP_POS_SKU_ADIE_DBDC_MASK, val); 176 } 177 178 static int mt7986_wmac_consys_reset(struct mt7915_dev *dev, bool enable) 179 { 180 if (!enable) 181 return reset_control_assert(dev->rstc); 182 183 mt76_wmac_rmw(dev->sku, MT_TOP_POS_FAST_CTRL, 184 MT_TOP_POS_FAST_EN_MASK, 185 FIELD_PREP(MT_TOP_POS_FAST_EN_MASK, 0x1)); 186 187 return reset_control_deassert(dev->rstc); 188 } 189 190 static int mt7986_wmac_gpio_setup(struct mt7915_dev *dev) 191 { 192 struct pinctrl_state *state; 193 struct pinctrl *pinctrl; 194 int ret; 195 u8 type; 196 197 type = mt7986_wmac_check_adie_type(dev); 198 pinctrl = devm_pinctrl_get(dev->mt76.dev); 199 if (IS_ERR(pinctrl)) 200 return PTR_ERR(pinctrl); 201 202 switch (type) { 203 case ADIE_SB: 204 state = pinctrl_lookup_state(pinctrl, "default"); 205 if (IS_ERR_OR_NULL(state)) 206 return -EINVAL; 207 break; 208 case ADIE_DBDC: 209 state = pinctrl_lookup_state(pinctrl, "dbdc"); 210 if (IS_ERR_OR_NULL(state)) 211 return -EINVAL; 212 break; 213 } 214 215 ret = pinctrl_select_state(pinctrl, state); 216 if (ret) 217 return ret; 218 219 usleep_range(500, 1000); 220 221 return 0; 222 } 223 224 static int mt7986_wmac_consys_lockup(struct mt7915_dev *dev, bool enable) 225 { 226 int ret; 227 u32 cur; 228 229 mt76_wmac_rmw(dev->dcm, MT_INFRACFG_AP2CONN_SLPPROT, 230 MT_INFRACFG_RX_EN_MASK, 231 FIELD_PREP(MT_INFRACFG_RX_EN_MASK, enable)); 232 ret = read_poll_timeout(readl, cur, !(cur & MT_INFRACFG_RX_EN_MASK), 233 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 234 dev->dcm + MT_INFRACFG_AP2CONN_SLPPROT); 235 if (ret) 236 return ret; 237 238 mt76_wmac_rmw(dev->dcm, MT_INFRACFG_AP2CONN_SLPPROT, 239 MT_INFRACFG_TX_EN_MASK, 240 FIELD_PREP(MT_INFRACFG_TX_EN_MASK, enable)); 241 ret = read_poll_timeout(readl, cur, !(cur & MT_INFRACFG_TX_RDY_MASK), 242 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 243 dev->dcm + MT_INFRACFG_AP2CONN_SLPPROT); 244 if (ret) 245 return ret; 246 247 mt76_wmac_rmw(dev->dcm, MT_INFRACFG_CONN2AP_SLPPROT, 248 MT_INFRACFG_RX_EN_MASK, 249 FIELD_PREP(MT_INFRACFG_RX_EN_MASK, enable)); 250 mt76_wmac_rmw(dev->dcm, MT_INFRACFG_CONN2AP_SLPPROT, 251 MT_INFRACFG_TX_EN_MASK, 252 FIELD_PREP(MT_INFRACFG_TX_EN_MASK, enable)); 253 254 return 0; 255 } 256 257 static int mt7986_wmac_coninfra_check(struct mt7915_dev *dev) 258 { 259 u32 cur; 260 261 return read_poll_timeout(mt76_rr, cur, (cur == 0x02070000), 262 USEC_PER_MSEC, 50 * USEC_PER_MSEC, 263 false, dev, MT_CONN_INFRA_BASE); 264 } 265 266 static int mt7986_wmac_coninfra_setup(struct mt7915_dev *dev) 267 { 268 struct device *pdev = dev->mt76.dev; 269 struct reserved_mem *rmem; 270 struct device_node *np; 271 u32 val; 272 273 np = of_parse_phandle(pdev->of_node, "memory-region", 0); 274 if (!np) 275 return -EINVAL; 276 277 rmem = of_reserved_mem_lookup(np); 278 if (!rmem) 279 return -EINVAL; 280 281 val = (rmem->base >> 16) & MT_TOP_MCU_EMI_BASE_MASK; 282 283 /* Set conninfra subsys PLL check */ 284 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS, 285 MT_INFRA_CKGEN_BUS_RDY_SEL_MASK, 0x1); 286 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS, 287 MT_INFRA_CKGEN_BUS_RDY_SEL_MASK, 0x1); 288 289 mt76_rmw_field(dev, MT_TOP_MCU_EMI_BASE, 290 MT_TOP_MCU_EMI_BASE_MASK, val); 291 292 mt76_wr(dev, MT_INFRA_BUS_EMI_START, rmem->base); 293 mt76_wr(dev, MT_INFRA_BUS_EMI_END, rmem->size); 294 295 mt76_rr(dev, MT_CONN_INFRA_EFUSE); 296 297 /* Set conninfra sysram */ 298 mt76_wr(dev, MT_TOP_RGU_SYSRAM_PDN, 0); 299 mt76_wr(dev, MT_TOP_RGU_SYSRAM_SLP, 1); 300 301 return 0; 302 } 303 304 static int mt7986_wmac_sku_setup(struct mt7915_dev *dev, u32 *adie_type) 305 { 306 int ret; 307 u32 adie_main, adie_ext; 308 309 mt76_rmw_field(dev, MT_CONN_INFRA_ADIE_RESET, 310 MT_CONN_INFRA_ADIE1_RESET_MASK, 0x1); 311 mt76_rmw_field(dev, MT_CONN_INFRA_ADIE_RESET, 312 MT_CONN_INFRA_ADIE2_RESET_MASK, 0x1); 313 314 mt76_wmac_spi_lock(dev); 315 316 ret = mt76_wmac_spi_read(dev, 0, MT_ADIE_CHIP_ID, &adie_main); 317 if (ret) 318 goto out; 319 320 ret = mt76_wmac_spi_read(dev, 1, MT_ADIE_CHIP_ID, &adie_ext); 321 if (ret) 322 goto out; 323 324 *adie_type = FIELD_GET(MT_ADIE_CHIP_ID_MASK, adie_main) | 325 (MT_ADIE_CHIP_ID_MASK & adie_ext); 326 327 out: 328 mt76_wmac_spi_unlock(dev); 329 330 return 0; 331 } 332 333 static inline u16 mt7986_adie_idx(u8 adie, u32 adie_type) 334 { 335 if (adie == 0) 336 return u32_get_bits(adie_type, MT_ADIE_IDX0); 337 else 338 return u32_get_bits(adie_type, MT_ADIE_IDX1); 339 } 340 341 static inline bool is_7975(struct mt7915_dev *dev, u8 adie, u32 adie_type) 342 { 343 return mt7986_adie_idx(adie, adie_type) == 0x7975; 344 } 345 346 static inline bool is_7976(struct mt7915_dev *dev, u8 adie, u32 adie_type) 347 { 348 return mt7986_adie_idx(adie, adie_type) == 0x7976; 349 } 350 351 static int mt7986_wmac_adie_thermal_cal(struct mt7915_dev *dev, u8 adie) 352 { 353 int ret; 354 u32 data, val; 355 356 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_THADC_ANALOG, 357 &data); 358 if (ret || FIELD_GET(MT_ADIE_ANA_EN_MASK, data)) { 359 val = FIELD_GET(MT_ADIE_VRPI_SEL_EFUSE_MASK, data); 360 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_RG_TOP_THADC_BG, 361 MT_ADIE_VRPI_SEL_CR_MASK, 362 FIELD_PREP(MT_ADIE_VRPI_SEL_CR_MASK, val)); 363 if (ret) 364 return ret; 365 366 val = FIELD_GET(MT_ADIE_PGA_GAIN_EFUSE_MASK, data); 367 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_RG_TOP_THADC, 368 MT_ADIE_PGA_GAIN_MASK, 369 FIELD_PREP(MT_ADIE_PGA_GAIN_MASK, val)); 370 if (ret) 371 return ret; 372 } 373 374 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_THADC_SLOP, 375 &data); 376 if (ret || FIELD_GET(MT_ADIE_ANA_EN_MASK, data)) { 377 val = FIELD_GET(MT_ADIE_LDO_CTRL_EFUSE_MASK, data); 378 379 return mt76_wmac_spi_rmw(dev, adie, MT_ADIE_RG_TOP_THADC, 380 MT_ADIE_LDO_CTRL_MASK, 381 FIELD_PREP(MT_ADIE_LDO_CTRL_MASK, val)); 382 } 383 384 return 0; 385 } 386 387 static int 388 mt7986_read_efuse_xo_trim_7976(struct mt7915_dev *dev, u8 adie, 389 bool is_40m, int *result) 390 { 391 int ret; 392 u32 data, addr; 393 394 addr = is_40m ? MT_ADIE_XTAL_AXM_40M_OSC : MT_ADIE_XTAL_AXM_80M_OSC; 395 ret = mt7986_wmac_adie_efuse_read(dev, adie, addr, &data); 396 if (ret) 397 return ret; 398 399 if (!FIELD_GET(MT_ADIE_XO_TRIM_EN_MASK, data)) { 400 *result = 64; 401 } else { 402 *result = FIELD_GET(MT_ADIE_TRIM_MASK, data); 403 addr = is_40m ? MT_ADIE_XTAL_TRIM1_40M_OSC : 404 MT_ADIE_XTAL_TRIM1_80M_OSC; 405 ret = mt7986_wmac_adie_efuse_read(dev, adie, addr, &data); 406 if (ret) 407 return ret; 408 409 if (FIELD_GET(MT_ADIE_XO_TRIM_EN_MASK, data) && 410 FIELD_GET(MT_ADIE_XTAL_DECREASE_MASK, data)) 411 *result -= FIELD_GET(MT_ADIE_EFUSE_TRIM_MASK, data); 412 else if (FIELD_GET(MT_ADIE_XO_TRIM_EN_MASK, data)) 413 *result += FIELD_GET(MT_ADIE_EFUSE_TRIM_MASK, data); 414 415 *result = max(0, min(127, *result)); 416 } 417 418 return 0; 419 } 420 421 static int mt7986_wmac_adie_xtal_trim_7976(struct mt7915_dev *dev, u8 adie) 422 { 423 int ret, trim_80m, trim_40m; 424 u32 data, val, mode; 425 426 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_XO_TRIM_FLOW, 427 &data); 428 if (ret || !FIELD_GET(BIT(1), data)) 429 return 0; 430 431 ret = mt7986_read_efuse_xo_trim_7976(dev, adie, false, &trim_80m); 432 if (ret) 433 return ret; 434 435 ret = mt7986_read_efuse_xo_trim_7976(dev, adie, true, &trim_40m); 436 if (ret) 437 return ret; 438 439 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_RG_STRAP_PIN_IN, &val); 440 if (ret) 441 return ret; 442 443 mode = FIELD_PREP(GENMASK(6, 4), val); 444 if (!mode || mode == 0x2) { 445 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C1, 446 GENMASK(31, 24), 447 FIELD_PREP(GENMASK(31, 24), trim_80m)); 448 if (ret) 449 return ret; 450 451 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C2, 452 GENMASK(31, 24), 453 FIELD_PREP(GENMASK(31, 24), trim_80m)); 454 } else if (mode == 0x3 || mode == 0x4 || mode == 0x6) { 455 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C1, 456 GENMASK(23, 16), 457 FIELD_PREP(GENMASK(23, 16), trim_40m)); 458 if (ret) 459 return ret; 460 461 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C2, 462 GENMASK(23, 16), 463 FIELD_PREP(GENMASK(23, 16), trim_40m)); 464 } 465 466 return ret; 467 } 468 469 static int mt7986_wmac_adie_patch_7976(struct mt7915_dev *dev, u8 adie) 470 { 471 int ret; 472 473 ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_RG_TOP_THADC, 0x4a563b00); 474 if (ret) 475 return ret; 476 477 ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_RG_XO_01, 0x1d59080f); 478 if (ret) 479 return ret; 480 481 return mt76_wmac_spi_write(dev, adie, MT_ADIE_RG_XO_03, 0x34c00fe0); 482 } 483 484 static int 485 mt7986_read_efuse_xo_trim_7975(struct mt7915_dev *dev, u8 adie, 486 u32 addr, u32 *result) 487 { 488 int ret; 489 u32 data; 490 491 ret = mt7986_wmac_adie_efuse_read(dev, adie, addr, &data); 492 if (ret) 493 return ret; 494 495 if ((data & MT_ADIE_XO_TRIM_EN_MASK)) { 496 if ((data & MT_ADIE_XTAL_DECREASE_MASK)) 497 *result -= (data & MT_ADIE_EFUSE_TRIM_MASK); 498 else 499 *result += (data & MT_ADIE_EFUSE_TRIM_MASK); 500 501 *result = (*result & MT_ADIE_TRIM_MASK); 502 } 503 504 return 0; 505 } 506 507 static int mt7986_wmac_adie_xtal_trim_7975(struct mt7915_dev *dev, u8 adie) 508 { 509 int ret; 510 u32 data, result = 0, value; 511 512 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_7975_XTAL_EN, 513 &data); 514 if (ret || !(data & BIT(1))) 515 return 0; 516 517 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_7975_XTAL_CAL, 518 &data); 519 if (ret) 520 return ret; 521 522 if (data & MT_ADIE_XO_TRIM_EN_MASK) 523 result = (data & MT_ADIE_TRIM_MASK); 524 525 ret = mt7986_read_efuse_xo_trim_7975(dev, adie, MT_ADIE_7975_XO_TRIM2, 526 &result); 527 if (ret) 528 return ret; 529 530 ret = mt7986_read_efuse_xo_trim_7975(dev, adie, MT_ADIE_7975_XO_TRIM3, 531 &result); 532 if (ret) 533 return ret; 534 535 ret = mt7986_read_efuse_xo_trim_7975(dev, adie, MT_ADIE_7975_XO_TRIM4, 536 &result); 537 if (ret) 538 return ret; 539 540 /* Update trim value to C1 and C2*/ 541 value = FIELD_GET(MT_ADIE_7975_XO_CTRL2_C1_MASK, result) | 542 FIELD_GET(MT_ADIE_7975_XO_CTRL2_C2_MASK, result); 543 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_XO_CTRL2, 544 MT_ADIE_7975_XO_CTRL2_MASK, value); 545 if (ret) 546 return ret; 547 548 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_7975_XTAL, &value); 549 if (ret) 550 return ret; 551 552 if (value & MT_ADIE_7975_XTAL_EN_MASK) { 553 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_XO_2, 554 MT_ADIE_7975_XO_2_FIX_EN, 0x0); 555 if (ret) 556 return ret; 557 } 558 559 return mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_XO_CTRL6, 560 MT_ADIE_7975_XO_CTRL6_MASK, 0x1); 561 } 562 563 static int mt7986_wmac_adie_patch_7975(struct mt7915_dev *dev, u8 adie) 564 { 565 int ret; 566 567 /* disable CAL LDO and fine tune RFDIG LDO */ 568 ret = mt76_wmac_spi_write(dev, adie, 0x348, 0x00000002); 569 if (ret) 570 return ret; 571 572 ret = mt76_wmac_spi_write(dev, adie, 0x378, 0x00000002); 573 if (ret) 574 return ret; 575 576 ret = mt76_wmac_spi_write(dev, adie, 0x3a8, 0x00000002); 577 if (ret) 578 return ret; 579 580 ret = mt76_wmac_spi_write(dev, adie, 0x3d8, 0x00000002); 581 if (ret) 582 return ret; 583 584 /* set CKA driving and filter */ 585 ret = mt76_wmac_spi_write(dev, adie, 0xa1c, 0x30000aaa); 586 if (ret) 587 return ret; 588 589 /* set CKB LDO to 1.4V */ 590 ret = mt76_wmac_spi_write(dev, adie, 0xa84, 0x8470008a); 591 if (ret) 592 return ret; 593 594 /* turn on SX0 LTBUF */ 595 ret = mt76_wmac_spi_write(dev, adie, 0x074, 0x00000002); 596 if (ret) 597 return ret; 598 599 /* CK_BUF_SW_EN = 1 (all buf in manual mode.) */ 600 ret = mt76_wmac_spi_write(dev, adie, 0xaa4, 0x01001fc0); 601 if (ret) 602 return ret; 603 604 /* BT mode/WF normal mode 00000005 */ 605 ret = mt76_wmac_spi_write(dev, adie, 0x070, 0x00000005); 606 if (ret) 607 return ret; 608 609 /* BG thermal sensor offset update */ 610 ret = mt76_wmac_spi_write(dev, adie, 0x344, 0x00000088); 611 if (ret) 612 return ret; 613 614 ret = mt76_wmac_spi_write(dev, adie, 0x374, 0x00000088); 615 if (ret) 616 return ret; 617 618 ret = mt76_wmac_spi_write(dev, adie, 0x3a4, 0x00000088); 619 if (ret) 620 return ret; 621 622 ret = mt76_wmac_spi_write(dev, adie, 0x3d4, 0x00000088); 623 if (ret) 624 return ret; 625 626 /* set WCON VDD IPTAT to "0000" */ 627 ret = mt76_wmac_spi_write(dev, adie, 0xa80, 0x44d07000); 628 if (ret) 629 return ret; 630 631 /* change back LTBUF SX3 drving to default value */ 632 ret = mt76_wmac_spi_write(dev, adie, 0xa88, 0x3900aaaa); 633 if (ret) 634 return ret; 635 636 /* SM input cap off */ 637 ret = mt76_wmac_spi_write(dev, adie, 0x2c4, 0x00000000); 638 if (ret) 639 return ret; 640 641 /* set CKB driving and filter */ 642 return mt76_wmac_spi_write(dev, adie, 0x2c8, 0x00000072); 643 } 644 645 static int mt7986_wmac_adie_cfg(struct mt7915_dev *dev, u8 adie, u32 adie_type) 646 { 647 int ret; 648 649 mt76_wmac_spi_lock(dev); 650 ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_CLK_EN, ~0); 651 if (ret) 652 goto out; 653 654 if (is_7975(dev, adie, adie_type)) { 655 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_COCLK, 656 BIT(1), 0x1); 657 if (ret) 658 goto out; 659 660 ret = mt7986_wmac_adie_thermal_cal(dev, adie); 661 if (ret) 662 goto out; 663 664 ret = mt7986_wmac_adie_xtal_trim_7975(dev, adie); 665 if (ret) 666 goto out; 667 668 ret = mt7986_wmac_adie_patch_7975(dev, adie); 669 } else if (is_7976(dev, adie, adie_type)) { 670 if (mt7986_wmac_check_adie_type(dev) == ADIE_DBDC) { 671 ret = mt76_wmac_spi_write(dev, adie, 672 MT_ADIE_WRI_CK_SEL, 0x1c); 673 if (ret) 674 goto out; 675 } 676 677 ret = mt7986_wmac_adie_thermal_cal(dev, adie); 678 if (ret) 679 goto out; 680 681 ret = mt7986_wmac_adie_xtal_trim_7976(dev, adie); 682 if (ret) 683 goto out; 684 685 ret = mt7986_wmac_adie_patch_7976(dev, adie); 686 } 687 out: 688 mt76_wmac_spi_unlock(dev); 689 690 return ret; 691 } 692 693 static int 694 mt7986_wmac_afe_cal(struct mt7915_dev *dev, u8 adie, bool dbdc, u32 adie_type) 695 { 696 int ret; 697 u8 idx; 698 699 mt76_wmac_spi_lock(dev); 700 if (is_7975(dev, adie, adie_type)) 701 ret = mt76_wmac_spi_write(dev, adie, 702 MT_AFE_RG_ENCAL_WBTAC_IF_SW, 703 0x80000000); 704 else 705 ret = mt76_wmac_spi_write(dev, adie, 706 MT_AFE_RG_ENCAL_WBTAC_IF_SW, 707 0x88888005); 708 if (ret) 709 goto out; 710 711 idx = dbdc ? ADIE_DBDC : adie; 712 713 mt76_rmw_field(dev, MT_AFE_DIG_EN_01(idx), 714 MT_AFE_RG_WBG_EN_RCK_MASK, 0x1); 715 usleep_range(60, 100); 716 717 mt76_rmw(dev, MT_AFE_DIG_EN_01(idx), 718 MT_AFE_RG_WBG_EN_RCK_MASK, 0x0); 719 720 mt76_rmw_field(dev, MT_AFE_DIG_EN_03(idx), 721 MT_AFE_RG_WBG_EN_BPLL_UP_MASK, 0x1); 722 usleep_range(30, 100); 723 724 mt76_rmw_field(dev, MT_AFE_DIG_EN_03(idx), 725 MT_AFE_RG_WBG_EN_WPLL_UP_MASK, 0x1); 726 usleep_range(60, 100); 727 728 mt76_rmw_field(dev, MT_AFE_DIG_EN_01(idx), 729 MT_AFE_RG_WBG_EN_TXCAL_MASK, 0x1f); 730 usleep_range(800, 1000); 731 732 mt76_rmw(dev, MT_AFE_DIG_EN_01(idx), 733 MT_AFE_RG_WBG_EN_TXCAL_MASK, 0x0); 734 mt76_rmw(dev, MT_AFE_DIG_EN_03(idx), 735 MT_AFE_RG_WBG_EN_PLL_UP_MASK, 0x0); 736 737 ret = mt76_wmac_spi_write(dev, adie, MT_AFE_RG_ENCAL_WBTAC_IF_SW, 738 0x5); 739 740 out: 741 mt76_wmac_spi_unlock(dev); 742 743 return ret; 744 } 745 746 static void mt7986_wmac_subsys_pll_initial(struct mt7915_dev *dev, u8 band) 747 { 748 mt76_rmw(dev, MT_AFE_PLL_STB_TIME(band), 749 MT_AFE_PLL_STB_TIME_MASK, MT_AFE_PLL_STB_TIME_VAL); 750 751 mt76_rmw(dev, MT_AFE_DIG_EN_02(band), 752 MT_AFE_PLL_CFG_MASK, MT_AFE_PLL_CFG_VAL); 753 754 mt76_rmw(dev, MT_AFE_DIG_TOP_01(band), 755 MT_AFE_DIG_TOP_01_MASK, MT_AFE_DIG_TOP_01_VAL); 756 } 757 758 static void mt7986_wmac_subsys_setting(struct mt7915_dev *dev) 759 { 760 /* Subsys pll init */ 761 mt7986_wmac_subsys_pll_initial(dev, 0); 762 mt7986_wmac_subsys_pll_initial(dev, 1); 763 764 /* Set legacy OSC control stable time*/ 765 mt76_rmw(dev, MT_CONN_INFRA_OSC_RC_EN, 766 MT_CONN_INFRA_OSC_RC_EN_MASK, 0x0); 767 mt76_rmw(dev, MT_CONN_INFRA_OSC_CTRL, 768 MT_CONN_INFRA_OSC_STB_TIME_MASK, 0x80706); 769 770 /* prevent subsys from power on/of in a short time interval */ 771 mt76_rmw(dev, MT_TOP_WFSYS_PWR, 772 MT_TOP_PWR_ACK_MASK | MT_TOP_PWR_KEY_MASK, 773 MT_TOP_PWR_KEY); 774 } 775 776 static int mt7986_wmac_bus_timeout(struct mt7915_dev *dev) 777 { 778 mt76_rmw_field(dev, MT_INFRA_BUS_OFF_TIMEOUT, 779 MT_INFRA_BUS_TIMEOUT_LIMIT_MASK, 0x2); 780 781 mt76_rmw_field(dev, MT_INFRA_BUS_OFF_TIMEOUT, 782 MT_INFRA_BUS_TIMEOUT_EN_MASK, 0xf); 783 784 mt76_rmw_field(dev, MT_INFRA_BUS_ON_TIMEOUT, 785 MT_INFRA_BUS_TIMEOUT_LIMIT_MASK, 0xc); 786 787 mt76_rmw_field(dev, MT_INFRA_BUS_ON_TIMEOUT, 788 MT_INFRA_BUS_TIMEOUT_EN_MASK, 0xf); 789 790 return mt7986_wmac_coninfra_check(dev); 791 } 792 793 static void mt7986_wmac_clock_enable(struct mt7915_dev *dev, u32 adie_type) 794 { 795 u32 cur; 796 797 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_1, 798 MT_INFRA_CKGEN_DIV_SEL_MASK, 0x1); 799 800 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_2, 801 MT_INFRA_CKGEN_DIV_SEL_MASK, 0x1); 802 803 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_1, 804 MT_INFRA_CKGEN_DIV_EN_MASK, 0x1); 805 806 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_2, 807 MT_INFRA_CKGEN_DIV_EN_MASK, 0x1); 808 809 mt76_rmw_field(dev, MT_INFRA_CKGEN_RFSPI_WPLL_DIV, 810 MT_INFRA_CKGEN_DIV_SEL_MASK, 0x8); 811 812 mt76_rmw_field(dev, MT_INFRA_CKGEN_RFSPI_WPLL_DIV, 813 MT_INFRA_CKGEN_DIV_EN_MASK, 0x1); 814 815 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS, 816 MT_INFRA_CKGEN_BUS_CLK_SEL_MASK, 0x0); 817 818 mt76_rmw_field(dev, MT_CONN_INFRA_HW_CTRL, 819 MT_CONN_INFRA_HW_CTRL_MASK, 0x1); 820 821 mt76_rmw(dev, MT_TOP_CONN_INFRA_WAKEUP, 822 MT_TOP_CONN_INFRA_WAKEUP_MASK, 0x1); 823 824 usleep_range(900, 1000); 825 826 mt76_wmac_spi_lock(dev); 827 if (is_7975(dev, 0, adie_type) || is_7976(dev, 0, adie_type)) { 828 mt76_rmw_field(dev, MT_ADIE_SLP_CTRL_CK0(0), 829 MT_SLP_CTRL_EN_MASK, 0x1); 830 831 read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_CTRL_BSY_MASK), 832 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 833 dev, MT_ADIE_SLP_CTRL_CK0(0)); 834 } 835 if (is_7975(dev, 1, adie_type) || is_7976(dev, 1, adie_type)) { 836 mt76_rmw_field(dev, MT_ADIE_SLP_CTRL_CK0(1), 837 MT_SLP_CTRL_EN_MASK, 0x1); 838 839 read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_CTRL_BSY_MASK), 840 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 841 dev, MT_ADIE_SLP_CTRL_CK0(0)); 842 } 843 mt76_wmac_spi_unlock(dev); 844 845 mt76_rmw(dev, MT_TOP_CONN_INFRA_WAKEUP, 846 MT_TOP_CONN_INFRA_WAKEUP_MASK, 0x0); 847 usleep_range(900, 1000); 848 } 849 850 static int mt7986_wmac_top_wfsys_wakeup(struct mt7915_dev *dev, bool enable) 851 { 852 mt76_rmw_field(dev, MT_TOP_WFSYS_WAKEUP, 853 MT_TOP_WFSYS_WAKEUP_MASK, enable); 854 855 usleep_range(900, 1000); 856 857 if (!enable) 858 return 0; 859 860 return mt7986_wmac_coninfra_check(dev); 861 } 862 863 static int mt7986_wmac_wm_enable(struct mt7915_dev *dev, bool enable) 864 { 865 u32 cur; 866 867 mt76_rmw_field(dev, MT7986_TOP_WM_RESET, 868 MT7986_TOP_WM_RESET_MASK, enable); 869 if (!enable) 870 return 0; 871 872 return read_poll_timeout(mt76_rr, cur, (cur == 0x1d1e), 873 USEC_PER_MSEC, 5000 * USEC_PER_MSEC, false, 874 dev, MT_TOP_CFG_ON_ROM_IDX); 875 } 876 877 static int mt7986_wmac_wfsys_poweron(struct mt7915_dev *dev, bool enable) 878 { 879 u32 mask = MT_TOP_PWR_EN_MASK | MT_TOP_PWR_KEY_MASK; 880 u32 cur; 881 882 mt76_rmw(dev, MT_TOP_WFSYS_PWR, mask, 883 MT_TOP_PWR_KEY | FIELD_PREP(MT_TOP_PWR_EN_MASK, enable)); 884 885 return read_poll_timeout(mt76_rr, cur, 886 (FIELD_GET(MT_TOP_WFSYS_RESET_STATUS_MASK, cur) == enable), 887 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 888 dev, MT_TOP_WFSYS_RESET_STATUS); 889 } 890 891 static int mt7986_wmac_wfsys_setting(struct mt7915_dev *dev) 892 { 893 int ret; 894 u32 cur; 895 896 /* Turn off wfsys2conn bus sleep protect */ 897 mt76_rmw(dev, MT_CONN_INFRA_WF_SLP_PROT, 898 MT_CONN_INFRA_WF_SLP_PROT_MASK, 0x0); 899 900 ret = mt7986_wmac_wfsys_poweron(dev, true); 901 if (ret) 902 return ret; 903 904 /* Check bus sleep protect */ 905 906 ret = read_poll_timeout(mt76_rr, cur, 907 !(cur & MT_CONN_INFRA_CONN_WF_MASK), 908 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 909 dev, MT_CONN_INFRA_WF_SLP_PROT_RDY); 910 if (ret) 911 return ret; 912 913 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_WFDMA2CONN_MASK), 914 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 915 dev, MT_SLP_STATUS); 916 if (ret) 917 return ret; 918 919 return read_poll_timeout(mt76_rr, cur, (cur == 0x02060000), 920 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 921 dev, MT_TOP_CFG_IP_VERSION_ADDR); 922 } 923 924 static void mt7986_wmac_wfsys_set_timeout(struct mt7915_dev *dev) 925 { 926 u32 mask = MT_MCU_BUS_TIMEOUT_SET_MASK | 927 MT_MCU_BUS_TIMEOUT_CG_EN_MASK | 928 MT_MCU_BUS_TIMEOUT_EN_MASK; 929 u32 val = FIELD_PREP(MT_MCU_BUS_TIMEOUT_SET_MASK, 1) | 930 FIELD_PREP(MT_MCU_BUS_TIMEOUT_CG_EN_MASK, 1) | 931 FIELD_PREP(MT_MCU_BUS_TIMEOUT_EN_MASK, 1); 932 933 mt76_rmw(dev, MT_MCU_BUS_TIMEOUT, mask, val); 934 935 mt76_wr(dev, MT_MCU_BUS_REMAP, 0x810f0000); 936 937 mask = MT_MCU_BUS_DBG_TIMEOUT_SET_MASK | 938 MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK | 939 MT_MCU_BUS_DBG_TIMEOUT_EN_MASK; 940 val = FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_SET_MASK, 0x3aa) | 941 FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK, 1) | 942 FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_EN_MASK, 1); 943 944 mt76_rmw(dev, MT_MCU_BUS_DBG_TIMEOUT, mask, val); 945 } 946 947 static int mt7986_wmac_sku_update(struct mt7915_dev *dev, u32 adie_type) 948 { 949 u32 val; 950 951 if (is_7976(dev, 0, adie_type) && is_7976(dev, 1, adie_type)) 952 val = 0xf; 953 else if (is_7975(dev, 0, adie_type) && is_7975(dev, 1, adie_type)) 954 val = 0xd; 955 else if (is_7976(dev, 0, adie_type)) 956 val = 0x7; 957 else if (is_7975(dev, 1, adie_type)) 958 val = 0x8; 959 else if (is_7976(dev, 1, adie_type)) 960 val = 0xa; 961 else 962 return -EINVAL; 963 964 mt76_wmac_rmw(dev->sku, MT_TOP_POS_SKU, MT_TOP_POS_SKU_MASK, 965 FIELD_PREP(MT_TOP_POS_SKU_MASK, val)); 966 967 mt76_wr(dev, MT_CONNINFRA_SKU_DEC_ADDR, val); 968 969 return 0; 970 } 971 972 static int 973 mt7986_wmac_adie_setup(struct mt7915_dev *dev, u8 adie, u32 adie_type) 974 { 975 int ret; 976 977 if (!(is_7975(dev, adie, adie_type) || is_7976(dev, adie, adie_type))) 978 return 0; 979 980 ret = mt7986_wmac_adie_cfg(dev, adie, adie_type); 981 if (ret) 982 return ret; 983 984 ret = mt7986_wmac_afe_cal(dev, adie, false, adie_type); 985 if (ret) 986 return ret; 987 988 if (!adie && (mt7986_wmac_check_adie_type(dev) == ADIE_DBDC)) 989 ret = mt7986_wmac_afe_cal(dev, adie, true, adie_type); 990 991 return ret; 992 } 993 994 static int mt7986_wmac_subsys_powerup(struct mt7915_dev *dev, u32 adie_type) 995 { 996 int ret; 997 998 mt7986_wmac_subsys_setting(dev); 999 1000 ret = mt7986_wmac_bus_timeout(dev); 1001 if (ret) 1002 return ret; 1003 1004 mt7986_wmac_clock_enable(dev, adie_type); 1005 1006 return 0; 1007 } 1008 1009 static int mt7986_wmac_wfsys_powerup(struct mt7915_dev *dev) 1010 { 1011 int ret; 1012 1013 ret = mt7986_wmac_wm_enable(dev, false); 1014 if (ret) 1015 return ret; 1016 1017 ret = mt7986_wmac_wfsys_setting(dev); 1018 if (ret) 1019 return ret; 1020 1021 mt7986_wmac_wfsys_set_timeout(dev); 1022 1023 return mt7986_wmac_wm_enable(dev, true); 1024 } 1025 1026 int mt7986_wmac_enable(struct mt7915_dev *dev) 1027 { 1028 int ret; 1029 u32 adie_type; 1030 1031 ret = mt7986_wmac_consys_reset(dev, true); 1032 if (ret) 1033 return ret; 1034 1035 ret = mt7986_wmac_gpio_setup(dev); 1036 if (ret) 1037 return ret; 1038 1039 ret = mt7986_wmac_consys_lockup(dev, false); 1040 if (ret) 1041 return ret; 1042 1043 ret = mt7986_wmac_coninfra_check(dev); 1044 if (ret) 1045 return ret; 1046 1047 ret = mt7986_wmac_coninfra_setup(dev); 1048 if (ret) 1049 return ret; 1050 1051 ret = mt7986_wmac_sku_setup(dev, &adie_type); 1052 if (ret) 1053 return ret; 1054 1055 ret = mt7986_wmac_adie_setup(dev, 0, adie_type); 1056 if (ret) 1057 return ret; 1058 1059 ret = mt7986_wmac_adie_setup(dev, 1, adie_type); 1060 if (ret) 1061 return ret; 1062 1063 ret = mt7986_wmac_subsys_powerup(dev, adie_type); 1064 if (ret) 1065 return ret; 1066 1067 ret = mt7986_wmac_top_wfsys_wakeup(dev, true); 1068 if (ret) 1069 return ret; 1070 1071 ret = mt7986_wmac_wfsys_powerup(dev); 1072 if (ret) 1073 return ret; 1074 1075 return mt7986_wmac_sku_update(dev, adie_type); 1076 } 1077 1078 void mt7986_wmac_disable(struct mt7915_dev *dev) 1079 { 1080 u32 cur; 1081 1082 mt7986_wmac_top_wfsys_wakeup(dev, true); 1083 1084 /* Turn on wfsys2conn bus sleep protect */ 1085 mt76_rmw_field(dev, MT_CONN_INFRA_WF_SLP_PROT, 1086 MT_CONN_INFRA_WF_SLP_PROT_MASK, 0x1); 1087 1088 /* Check wfsys2conn bus sleep protect */ 1089 read_poll_timeout(mt76_rr, cur, !(cur ^ MT_CONN_INFRA_CONN), 1090 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 1091 dev, MT_CONN_INFRA_WF_SLP_PROT_RDY); 1092 1093 mt7986_wmac_wfsys_poweron(dev, false); 1094 1095 /* Turn back wpll setting */ 1096 mt76_rmw_field(dev, MT_AFE_DIG_EN_02(0), MT_AFE_MCU_BPLL_CFG_MASK, 0x2); 1097 mt76_rmw_field(dev, MT_AFE_DIG_EN_02(0), MT_AFE_WPLL_CFG_MASK, 0x2); 1098 1099 /* Reset EMI */ 1100 mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ, 1101 MT_CONN_INFRA_EMI_REQ_MASK, 0x1); 1102 mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ, 1103 MT_CONN_INFRA_EMI_REQ_MASK, 0x0); 1104 mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ, 1105 MT_CONN_INFRA_INFRA_REQ_MASK, 0x1); 1106 mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ, 1107 MT_CONN_INFRA_INFRA_REQ_MASK, 0x0); 1108 1109 mt7986_wmac_top_wfsys_wakeup(dev, false); 1110 mt7986_wmac_consys_lockup(dev, true); 1111 mt7986_wmac_consys_reset(dev, false); 1112 } 1113 1114 static int mt7986_wmac_init(struct mt7915_dev *dev) 1115 { 1116 struct device *pdev = dev->mt76.dev; 1117 struct platform_device *pfdev = to_platform_device(pdev); 1118 1119 dev->dcm = devm_platform_ioremap_resource(pfdev, 1); 1120 if (IS_ERR(dev->dcm)) 1121 return PTR_ERR(dev->dcm); 1122 1123 dev->sku = devm_platform_ioremap_resource(pfdev, 2); 1124 if (IS_ERR(dev->sku)) 1125 return PTR_ERR(dev->sku); 1126 1127 dev->rstc = devm_reset_control_get(pdev, "consys"); 1128 if (IS_ERR(dev->rstc)) 1129 return PTR_ERR(dev->rstc); 1130 1131 return mt7986_wmac_enable(dev); 1132 } 1133 1134 static int mt7986_wmac_probe(struct platform_device *pdev) 1135 { 1136 void __iomem *mem_base; 1137 struct mt7915_dev *dev; 1138 struct mt76_dev *mdev; 1139 int irq, ret; 1140 u32 chip_id; 1141 1142 chip_id = (uintptr_t)of_device_get_match_data(&pdev->dev); 1143 1144 irq = platform_get_irq(pdev, 0); 1145 if (irq < 0) 1146 return irq; 1147 1148 mem_base = devm_platform_ioremap_resource(pdev, 0); 1149 if (IS_ERR(mem_base)) { 1150 dev_err(&pdev->dev, "Failed to get memory resource\n"); 1151 return PTR_ERR(mem_base); 1152 } 1153 1154 dev = mt7915_mmio_probe(&pdev->dev, mem_base, chip_id); 1155 if (IS_ERR(dev)) 1156 return PTR_ERR(dev); 1157 1158 mdev = &dev->mt76; 1159 ret = devm_request_irq(mdev->dev, irq, mt7915_irq_handler, 1160 IRQF_SHARED, KBUILD_MODNAME, dev); 1161 if (ret) 1162 goto free_device; 1163 1164 mt76_wr(dev, MT_INT_MASK_CSR, 0); 1165 1166 ret = mt7986_wmac_init(dev); 1167 if (ret) 1168 goto free_irq; 1169 1170 ret = mt7915_register_device(dev); 1171 if (ret) 1172 goto free_irq; 1173 1174 return 0; 1175 1176 free_irq: 1177 devm_free_irq(mdev->dev, irq, dev); 1178 1179 free_device: 1180 mt76_free_device(&dev->mt76); 1181 1182 return ret; 1183 } 1184 1185 static int mt7986_wmac_remove(struct platform_device *pdev) 1186 { 1187 struct mt7915_dev *dev = platform_get_drvdata(pdev); 1188 1189 mt7915_unregister_device(dev); 1190 1191 return 0; 1192 } 1193 1194 static const struct of_device_id mt7986_wmac_of_match[] = { 1195 { .compatible = "mediatek,mt7986-wmac", .data = (u32 *)0x7986 }, 1196 {}, 1197 }; 1198 1199 struct platform_driver mt7986_wmac_driver = { 1200 .driver = { 1201 .name = "mt7986-wmac", 1202 .of_match_table = mt7986_wmac_of_match, 1203 }, 1204 .probe = mt7986_wmac_probe, 1205 .remove = mt7986_wmac_remove, 1206 }; 1207 1208 MODULE_FIRMWARE(MT7986_FIRMWARE_WA); 1209 MODULE_FIRMWARE(MT7986_FIRMWARE_WM); 1210 MODULE_FIRMWARE(MT7986_FIRMWARE_WM_MT7975); 1211 MODULE_FIRMWARE(MT7986_ROM_PATCH); 1212 MODULE_FIRMWARE(MT7986_ROM_PATCH_MT7975); 1213