1 /* SPDX-License-Identifier: ISC */
2 /* Copyright (C) 2020 MediaTek Inc. */
3 
4 #ifndef __MT76_CONNAC_MCU_H
5 #define __MT76_CONNAC_MCU_H
6 
7 #include "mt76_connac.h"
8 
9 #define FW_FEATURE_SET_ENCRYPT		BIT(0)
10 #define FW_FEATURE_SET_KEY_IDX		GENMASK(2, 1)
11 #define FW_FEATURE_ENCRY_MODE		BIT(4)
12 #define FW_FEATURE_OVERRIDE_ADDR	BIT(5)
13 #define FW_FEATURE_NON_DL		BIT(6)
14 
15 #define DL_MODE_ENCRYPT			BIT(0)
16 #define DL_MODE_KEY_IDX			GENMASK(2, 1)
17 #define DL_MODE_RESET_SEC_IV		BIT(3)
18 #define DL_MODE_WORKING_PDA_CR4		BIT(4)
19 #define DL_MODE_VALID_RAM_ENTRY         BIT(5)
20 #define DL_CONFIG_ENCRY_MODE_SEL	BIT(6)
21 #define DL_MODE_NEED_RSP		BIT(31)
22 
23 #define FW_START_OVERRIDE		BIT(0)
24 #define FW_START_WORKING_PDA_CR4	BIT(2)
25 
26 #define PATCH_SEC_NOT_SUPPORT		GENMASK(31, 0)
27 #define PATCH_SEC_TYPE_MASK		GENMASK(15, 0)
28 #define PATCH_SEC_TYPE_INFO		0x2
29 
30 #define PATCH_SEC_ENC_TYPE_MASK			GENMASK(31, 24)
31 #define PATCH_SEC_ENC_TYPE_PLAIN		0x00
32 #define PATCH_SEC_ENC_TYPE_AES			0x01
33 #define PATCH_SEC_ENC_TYPE_SCRAMBLE		0x02
34 #define PATCH_SEC_ENC_SCRAMBLE_INFO_MASK	GENMASK(15, 0)
35 #define PATCH_SEC_ENC_AES_KEY_MASK		GENMASK(7, 0)
36 
37 enum {
38 	FW_TYPE_DEFAULT = 0,
39 	FW_TYPE_CLC = 2,
40 	FW_TYPE_MAX_NUM = 255
41 };
42 
43 #define MCU_PQ_ID(p, q)		(((p) << 15) | ((q) << 10))
44 #define MCU_PKT_ID		0xa0
45 
46 struct mt76_connac2_mcu_txd {
47 	__le32 txd[8];
48 
49 	__le16 len;
50 	__le16 pq_id;
51 
52 	u8 cid;
53 	u8 pkt_type;
54 	u8 set_query; /* FW don't care */
55 	u8 seq;
56 
57 	u8 uc_d2b0_rev;
58 	u8 ext_cid;
59 	u8 s2d_index;
60 	u8 ext_cid_ack;
61 
62 	u32 rsv[5];
63 } __packed __aligned(4);
64 
65 /**
66  * struct mt76_connac2_mcu_uni_txd - mcu command descriptor for connac2 and connac3
67  * @txd: hardware descriptor
68  * @len: total length not including txd
69  * @cid: command identifier
70  * @pkt_type: must be 0xa0 (cmd packet by long format)
71  * @frag_n: fragment number
72  * @seq: sequence number
73  * @checksum: 0 mean there is no checksum
74  * @s2d_index: index for command source and destination
75  *  Definition              | value | note
76  *  CMD_S2D_IDX_H2N         | 0x00  | command from HOST to WM
77  *  CMD_S2D_IDX_C2N         | 0x01  | command from WA to WM
78  *  CMD_S2D_IDX_H2C         | 0x02  | command from HOST to WA
79  *  CMD_S2D_IDX_H2N_AND_H2C | 0x03  | command from HOST to WA and WM
80  *
81  * @option: command option
82  *  BIT[0]: UNI_CMD_OPT_BIT_ACK
83  *          set to 1 to request a fw reply
84  *          if UNI_CMD_OPT_BIT_0_ACK is set and UNI_CMD_OPT_BIT_2_SET_QUERY
85  *          is set, mcu firmware will send response event EID = 0x01
86  *          (UNI_EVENT_ID_CMD_RESULT) to the host.
87  *  BIT[1]: UNI_CMD_OPT_BIT_UNI_CMD
88  *          0: original command
89  *          1: unified command
90  *  BIT[2]: UNI_CMD_OPT_BIT_SET_QUERY
91  *          0: QUERY command
92  *          1: SET command
93  */
94 struct mt76_connac2_mcu_uni_txd {
95 	__le32 txd[8];
96 
97 	/* DW1 */
98 	__le16 len;
99 	__le16 cid;
100 
101 	/* DW2 */
102 	u8 rsv;
103 	u8 pkt_type;
104 	u8 frag_n;
105 	u8 seq;
106 
107 	/* DW3 */
108 	__le16 checksum;
109 	u8 s2d_index;
110 	u8 option;
111 
112 	/* DW4 */
113 	u8 rsv1[4];
114 } __packed __aligned(4);
115 
116 struct mt76_connac2_mcu_rxd {
117 	__le32 rxd[6];
118 
119 	__le16 len;
120 	__le16 pkt_type_id;
121 
122 	u8 eid;
123 	u8 seq;
124 	u8 option;
125 	u8 rsv;
126 	u8 ext_eid;
127 	u8 rsv1[2];
128 	u8 s2d_index;
129 
130 	u8 tlv[0];
131 };
132 
133 struct mt76_connac2_patch_hdr {
134 	char build_date[16];
135 	char platform[4];
136 	__be32 hw_sw_ver;
137 	__be32 patch_ver;
138 	__be16 checksum;
139 	u16 rsv;
140 	struct {
141 		__be32 patch_ver;
142 		__be32 subsys;
143 		__be32 feature;
144 		__be32 n_region;
145 		__be32 crc;
146 		u32 rsv[11];
147 	} desc;
148 } __packed;
149 
150 struct mt76_connac2_patch_sec {
151 	__be32 type;
152 	__be32 offs;
153 	__be32 size;
154 	union {
155 		__be32 spec[13];
156 		struct {
157 			__be32 addr;
158 			__be32 len;
159 			__be32 sec_key_idx;
160 			__be32 align_len;
161 			u32 rsv[9];
162 		} info;
163 	};
164 } __packed;
165 
166 struct mt76_connac2_fw_trailer {
167 	u8 chip_id;
168 	u8 eco_code;
169 	u8 n_region;
170 	u8 format_ver;
171 	u8 format_flag;
172 	u8 rsv[2];
173 	char fw_ver[10];
174 	char build_date[15];
175 	__le32 crc;
176 } __packed;
177 
178 struct mt76_connac2_fw_region {
179 	__le32 decomp_crc;
180 	__le32 decomp_len;
181 	__le32 decomp_blk_sz;
182 	u8 rsv[4];
183 	__le32 addr;
184 	__le32 len;
185 	u8 feature_set;
186 	u8 type;
187 	u8 rsv1[14];
188 } __packed;
189 
190 struct tlv {
191 	__le16 tag;
192 	__le16 len;
193 } __packed;
194 
195 struct bss_info_omac {
196 	__le16 tag;
197 	__le16 len;
198 	u8 hw_bss_idx;
199 	u8 omac_idx;
200 	u8 band_idx;
201 	u8 rsv0;
202 	__le32 conn_type;
203 	u32 rsv1;
204 } __packed;
205 
206 struct bss_info_basic {
207 	__le16 tag;
208 	__le16 len;
209 	__le32 network_type;
210 	u8 active;
211 	u8 rsv0;
212 	__le16 bcn_interval;
213 	u8 bssid[ETH_ALEN];
214 	u8 wmm_idx;
215 	u8 dtim_period;
216 	u8 bmc_wcid_lo;
217 	u8 cipher;
218 	u8 phy_mode;
219 	u8 max_bssid;	/* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */
220 	u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */
221 	u8 bmc_wcid_hi;	/* high Byte and version */
222 	u8 rsv[2];
223 } __packed;
224 
225 struct bss_info_rf_ch {
226 	__le16 tag;
227 	__le16 len;
228 	u8 pri_ch;
229 	u8 center_ch0;
230 	u8 center_ch1;
231 	u8 bw;
232 	u8 he_ru26_block;	/* 1: don't send HETB in RU26, 0: allow */
233 	u8 he_all_disable;	/* 1: disallow all HETB, 0: allow */
234 	u8 rsv[2];
235 } __packed;
236 
237 struct bss_info_ext_bss {
238 	__le16 tag;
239 	__le16 len;
240 	__le32 mbss_tsf_offset; /* in unit of us */
241 	u8 rsv[8];
242 } __packed;
243 
244 enum {
245 	BSS_INFO_OMAC,
246 	BSS_INFO_BASIC,
247 	BSS_INFO_RF_CH,		/* optional, for BT/LTE coex */
248 	BSS_INFO_PM,		/* sta only */
249 	BSS_INFO_UAPSD,		/* sta only */
250 	BSS_INFO_ROAM_DETECT,	/* obsoleted */
251 	BSS_INFO_LQ_RM,		/* obsoleted */
252 	BSS_INFO_EXT_BSS,
253 	BSS_INFO_BMC_RATE,	/* for bmc rate control in CR4 */
254 	BSS_INFO_SYNC_MODE,	/* obsoleted */
255 	BSS_INFO_RA,
256 	BSS_INFO_HW_AMSDU,
257 	BSS_INFO_BSS_COLOR,
258 	BSS_INFO_HE_BASIC,
259 	BSS_INFO_PROTECT_INFO,
260 	BSS_INFO_OFFLOAD,
261 	BSS_INFO_11V_MBSSID,
262 	BSS_INFO_MAX_NUM
263 };
264 
265 /* sta_rec */
266 
267 struct sta_ntlv_hdr {
268 	u8 rsv[2];
269 	__le16 tlv_num;
270 } __packed;
271 
272 struct sta_req_hdr {
273 	u8 bss_idx;
274 	u8 wlan_idx_lo;
275 	__le16 tlv_num;
276 	u8 is_tlv_append;
277 	u8 muar_idx;
278 	u8 wlan_idx_hi;
279 	u8 rsv;
280 } __packed;
281 
282 struct sta_rec_basic {
283 	__le16 tag;
284 	__le16 len;
285 	__le32 conn_type;
286 	u8 conn_state;
287 	u8 qos;
288 	__le16 aid;
289 	u8 peer_addr[ETH_ALEN];
290 #define EXTRA_INFO_VER	BIT(0)
291 #define EXTRA_INFO_NEW	BIT(1)
292 	__le16 extra_info;
293 } __packed;
294 
295 struct sta_rec_ht {
296 	__le16 tag;
297 	__le16 len;
298 	__le16 ht_cap;
299 	u16 rsv;
300 } __packed;
301 
302 struct sta_rec_vht {
303 	__le16 tag;
304 	__le16 len;
305 	__le32 vht_cap;
306 	__le16 vht_rx_mcs_map;
307 	__le16 vht_tx_mcs_map;
308 	/* mt7915 - mt7921 */
309 	u8 rts_bw_sig;
310 	u8 rsv[3];
311 } __packed;
312 
313 struct sta_rec_uapsd {
314 	__le16 tag;
315 	__le16 len;
316 	u8 dac_map;
317 	u8 tac_map;
318 	u8 max_sp;
319 	u8 rsv0;
320 	__le16 listen_interval;
321 	u8 rsv1[2];
322 } __packed;
323 
324 struct sta_rec_ba {
325 	__le16 tag;
326 	__le16 len;
327 	u8 tid;
328 	u8 ba_type;
329 	u8 amsdu;
330 	u8 ba_en;
331 	__le16 ssn;
332 	__le16 winsize;
333 } __packed;
334 
335 struct sta_rec_he {
336 	__le16 tag;
337 	__le16 len;
338 
339 	__le32 he_cap;
340 
341 	u8 t_frame_dur;
342 	u8 max_ampdu_exp;
343 	u8 bw_set;
344 	u8 device_class;
345 	u8 dcm_tx_mode;
346 	u8 dcm_tx_max_nss;
347 	u8 dcm_rx_mode;
348 	u8 dcm_rx_max_nss;
349 	u8 dcm_max_ru;
350 	u8 punc_pream_rx;
351 	u8 pkt_ext;
352 	u8 rsv1;
353 
354 	__le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
355 
356 	u8 rsv2[2];
357 } __packed;
358 
359 struct sta_rec_he_v2 {
360 	__le16 tag;
361 	__le16 len;
362 	u8 he_mac_cap[6];
363 	u8 he_phy_cap[11];
364 	u8 pkt_ext;
365 	/* 0: BW80, 1: BW160, 2: BW8080 */
366 	__le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
367 } __packed;
368 
369 struct sta_rec_amsdu {
370 	__le16 tag;
371 	__le16 len;
372 	u8 max_amsdu_num;
373 	u8 max_mpdu_size;
374 	u8 amsdu_en;
375 	u8 rsv;
376 } __packed;
377 
378 struct sta_rec_state {
379 	__le16 tag;
380 	__le16 len;
381 	__le32 flags;
382 	u8 state;
383 	u8 vht_opmode;
384 	u8 action;
385 	u8 rsv[1];
386 } __packed;
387 
388 #define RA_LEGACY_OFDM GENMASK(13, 6)
389 #define RA_LEGACY_CCK  GENMASK(3, 0)
390 #define HT_MCS_MASK_NUM 10
391 struct sta_rec_ra_info {
392 	__le16 tag;
393 	__le16 len;
394 	__le16 legacy;
395 	u8 rx_mcs_bitmask[HT_MCS_MASK_NUM];
396 } __packed;
397 
398 struct sta_rec_phy {
399 	__le16 tag;
400 	__le16 len;
401 	__le16 basic_rate;
402 	u8 phy_type;
403 	u8 ampdu;
404 	u8 rts_policy;
405 	u8 rcpi;
406 	u8 max_ampdu_len; /* connac3 */
407 	u8 rsv[1];
408 } __packed;
409 
410 struct sta_rec_he_6g_capa {
411 	__le16 tag;
412 	__le16 len;
413 	__le16 capa;
414 	u8 rsv[2];
415 } __packed;
416 
417 struct sec_key {
418 	u8 cipher_id;
419 	u8 cipher_len;
420 	u8 key_id;
421 	u8 key_len;
422 	u8 key[32];
423 } __packed;
424 
425 struct sta_rec_sec {
426 	__le16 tag;
427 	__le16 len;
428 	u8 add;
429 	u8 n_cipher;
430 	u8 rsv[2];
431 
432 	struct sec_key key[2];
433 } __packed;
434 
435 struct sta_rec_bf {
436 	__le16 tag;
437 	__le16 len;
438 
439 	__le16 pfmu;		/* 0xffff: no access right for PFMU */
440 	bool su_mu;		/* 0: SU, 1: MU */
441 	u8 bf_cap;		/* 0: iBF, 1: eBF */
442 	u8 sounding_phy;	/* 0: legacy, 1: OFDM, 2: HT, 4: VHT */
443 	u8 ndpa_rate;
444 	u8 ndp_rate;
445 	u8 rept_poll_rate;
446 	u8 tx_mode;		/* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */
447 	u8 ncol;
448 	u8 nrow;
449 	u8 bw;			/* 0: 20M, 1: 40M, 2: 80M, 3: 160M */
450 
451 	u8 mem_total;
452 	u8 mem_20m;
453 	struct {
454 		u8 row;
455 		u8 col: 6, row_msb: 2;
456 	} mem[4];
457 
458 	__le16 smart_ant;
459 	u8 se_idx;
460 	u8 auto_sounding;	/* b7: low traffic indicator
461 				 * b6: Stop sounding for this entry
462 				 * b5 ~ b0: postpone sounding
463 				 */
464 	u8 ibf_timeout;
465 	u8 ibf_dbw;
466 	u8 ibf_ncol;
467 	u8 ibf_nrow;
468 	u8 nrow_gt_bw80;
469 	u8 ncol_gt_bw80;
470 	u8 ru_start_idx;
471 	u8 ru_end_idx;
472 
473 	bool trigger_su;
474 	bool trigger_mu;
475 	bool ng16_su;
476 	bool ng16_mu;
477 	bool codebook42_su;
478 	bool codebook75_mu;
479 
480 	u8 he_ltf;
481 	u8 rsv[3];
482 } __packed;
483 
484 struct sta_rec_bfee {
485 	__le16 tag;
486 	__le16 len;
487 	bool fb_identity_matrix;	/* 1: feedback identity matrix */
488 	bool ignore_feedback;		/* 1: ignore */
489 	u8 rsv[2];
490 } __packed;
491 
492 struct sta_rec_muru {
493 	__le16 tag;
494 	__le16 len;
495 
496 	struct {
497 		bool ofdma_dl_en;
498 		bool ofdma_ul_en;
499 		bool mimo_dl_en;
500 		bool mimo_ul_en;
501 		u8 rsv[4];
502 	} cfg;
503 
504 	struct {
505 		u8 punc_pream_rx;
506 		bool he_20m_in_40m_2g;
507 		bool he_20m_in_160m;
508 		bool he_80m_in_160m;
509 		bool lt16_sigb;
510 		bool rx_su_comp_sigb;
511 		bool rx_su_non_comp_sigb;
512 		u8 rsv;
513 	} ofdma_dl;
514 
515 	struct {
516 		u8 t_frame_dur;
517 		u8 mu_cascading;
518 		u8 uo_ra;
519 		u8 he_2x996_tone;
520 		u8 rx_t_frame_11ac;
521 		u8 rsv[3];
522 	} ofdma_ul;
523 
524 	struct {
525 		bool vht_mu_bfee;
526 		bool partial_bw_dl_mimo;
527 		u8 rsv[2];
528 	} mimo_dl;
529 
530 	struct {
531 		bool full_ul_mimo;
532 		bool partial_ul_mimo;
533 		u8 rsv[2];
534 	} mimo_ul;
535 } __packed;
536 
537 struct sta_phy {
538 	u8 type;
539 	u8 flag;
540 	u8 stbc;
541 	u8 sgi;
542 	u8 bw;
543 	u8 ldpc;
544 	u8 mcs;
545 	u8 nss;
546 	u8 he_ltf;
547 };
548 
549 struct sta_rec_ra {
550 	__le16 tag;
551 	__le16 len;
552 
553 	u8 valid;
554 	u8 auto_rate;
555 	u8 phy_mode;
556 	u8 channel;
557 	u8 bw;
558 	u8 disable_cck;
559 	u8 ht_mcs32;
560 	u8 ht_gf;
561 	u8 ht_mcs[4];
562 	u8 mmps_mode;
563 	u8 gband_256;
564 	u8 af;
565 	u8 auth_wapi_mode;
566 	u8 rate_len;
567 
568 	u8 supp_mode;
569 	u8 supp_cck_rate;
570 	u8 supp_ofdm_rate;
571 	__le32 supp_ht_mcs;
572 	__le16 supp_vht_mcs[4];
573 
574 	u8 op_mode;
575 	u8 op_vht_chan_width;
576 	u8 op_vht_rx_nss;
577 	u8 op_vht_rx_nss_type;
578 
579 	__le32 sta_cap;
580 
581 	struct sta_phy phy;
582 } __packed;
583 
584 struct sta_rec_ra_fixed {
585 	__le16 tag;
586 	__le16 len;
587 
588 	__le32 field;
589 	u8 op_mode;
590 	u8 op_vht_chan_width;
591 	u8 op_vht_rx_nss;
592 	u8 op_vht_rx_nss_type;
593 
594 	struct sta_phy phy;
595 
596 	u8 spe_idx;
597 	u8 short_preamble;
598 	u8 is_5g;
599 	u8 mmps_mode;
600 } __packed;
601 
602 /* wtbl_rec */
603 
604 struct wtbl_req_hdr {
605 	u8 wlan_idx_lo;
606 	u8 operation;
607 	__le16 tlv_num;
608 	u8 wlan_idx_hi;
609 	u8 rsv[3];
610 } __packed;
611 
612 struct wtbl_generic {
613 	__le16 tag;
614 	__le16 len;
615 	u8 peer_addr[ETH_ALEN];
616 	u8 muar_idx;
617 	u8 skip_tx;
618 	u8 cf_ack;
619 	u8 qos;
620 	u8 mesh;
621 	u8 adm;
622 	__le16 partial_aid;
623 	u8 baf_en;
624 	u8 aad_om;
625 } __packed;
626 
627 struct wtbl_rx {
628 	__le16 tag;
629 	__le16 len;
630 	u8 rcid;
631 	u8 rca1;
632 	u8 rca2;
633 	u8 rv;
634 	u8 rsv[4];
635 } __packed;
636 
637 struct wtbl_ht {
638 	__le16 tag;
639 	__le16 len;
640 	u8 ht;
641 	u8 ldpc;
642 	u8 af;
643 	u8 mm;
644 	u8 rsv[4];
645 } __packed;
646 
647 struct wtbl_vht {
648 	__le16 tag;
649 	__le16 len;
650 	u8 ldpc;
651 	u8 dyn_bw;
652 	u8 vht;
653 	u8 txop_ps;
654 	u8 rsv[4];
655 } __packed;
656 
657 struct wtbl_tx_ps {
658 	__le16 tag;
659 	__le16 len;
660 	u8 txps;
661 	u8 rsv[3];
662 } __packed;
663 
664 struct wtbl_hdr_trans {
665 	__le16 tag;
666 	__le16 len;
667 	u8 to_ds;
668 	u8 from_ds;
669 	u8 no_rx_trans;
670 	u8 rsv;
671 } __packed;
672 
673 struct wtbl_ba {
674 	__le16 tag;
675 	__le16 len;
676 	/* common */
677 	u8 tid;
678 	u8 ba_type;
679 	u8 rsv0[2];
680 	/* originator only */
681 	__le16 sn;
682 	u8 ba_en;
683 	u8 ba_winsize_idx;
684 	/* originator & recipient */
685 	__le16 ba_winsize;
686 	/* recipient only */
687 	u8 peer_addr[ETH_ALEN];
688 	u8 rst_ba_tid;
689 	u8 rst_ba_sel;
690 	u8 rst_ba_sb;
691 	u8 band_idx;
692 	u8 rsv1[4];
693 } __packed;
694 
695 struct wtbl_smps {
696 	__le16 tag;
697 	__le16 len;
698 	u8 smps;
699 	u8 rsv[3];
700 } __packed;
701 
702 /* mt7615 only */
703 
704 struct wtbl_bf {
705 	__le16 tag;
706 	__le16 len;
707 	u8 ibf;
708 	u8 ebf;
709 	u8 ibf_vht;
710 	u8 ebf_vht;
711 	u8 gid;
712 	u8 pfmu_idx;
713 	u8 rsv[2];
714 } __packed;
715 
716 struct wtbl_pn {
717 	__le16 tag;
718 	__le16 len;
719 	u8 pn[6];
720 	u8 rsv[2];
721 } __packed;
722 
723 struct wtbl_spe {
724 	__le16 tag;
725 	__le16 len;
726 	u8 spe_idx;
727 	u8 rsv[3];
728 } __packed;
729 
730 struct wtbl_raw {
731 	__le16 tag;
732 	__le16 len;
733 	u8 wtbl_idx;
734 	u8 dw;
735 	u8 rsv[2];
736 	__le32 msk;
737 	__le32 val;
738 } __packed;
739 
740 #define MT76_CONNAC_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) +	\
741 					  sizeof(struct wtbl_generic) +	\
742 					  sizeof(struct wtbl_rx) +	\
743 					  sizeof(struct wtbl_ht) +	\
744 					  sizeof(struct wtbl_vht) +	\
745 					  sizeof(struct wtbl_tx_ps) +	\
746 					  sizeof(struct wtbl_hdr_trans) +\
747 					  sizeof(struct wtbl_ba) +	\
748 					  sizeof(struct wtbl_bf) +	\
749 					  sizeof(struct wtbl_smps) +	\
750 					  sizeof(struct wtbl_pn) +	\
751 					  sizeof(struct wtbl_spe))
752 
753 #define MT76_CONNAC_STA_UPDATE_MAX_SIZE	(sizeof(struct sta_req_hdr) +	\
754 					 sizeof(struct sta_rec_basic) +	\
755 					 sizeof(struct sta_rec_bf) +	\
756 					 sizeof(struct sta_rec_ht) +	\
757 					 sizeof(struct sta_rec_he) +	\
758 					 sizeof(struct sta_rec_ba) +	\
759 					 sizeof(struct sta_rec_vht) +	\
760 					 sizeof(struct sta_rec_uapsd) + \
761 					 sizeof(struct sta_rec_amsdu) +	\
762 					 sizeof(struct sta_rec_muru) +	\
763 					 sizeof(struct sta_rec_bfee) +	\
764 					 sizeof(struct sta_rec_ra) +	\
765 					 sizeof(struct sta_rec_sec) +	\
766 					 sizeof(struct sta_rec_ra_fixed) + \
767 					 sizeof(struct sta_rec_he_6g_capa) + \
768 					 sizeof(struct tlv) +		\
769 					 MT76_CONNAC_WTBL_UPDATE_MAX_SIZE)
770 
771 enum {
772 	STA_REC_BASIC,
773 	STA_REC_RA,
774 	STA_REC_RA_CMM_INFO,
775 	STA_REC_RA_UPDATE,
776 	STA_REC_BF,
777 	STA_REC_AMSDU,
778 	STA_REC_BA,
779 	STA_REC_STATE,
780 	STA_REC_TX_PROC,	/* for hdr trans and CSO in CR4 */
781 	STA_REC_HT,
782 	STA_REC_VHT,
783 	STA_REC_APPS,
784 	STA_REC_KEY,
785 	STA_REC_WTBL,
786 	STA_REC_HE,
787 	STA_REC_HW_AMSDU,
788 	STA_REC_WTBL_AADOM,
789 	STA_REC_KEY_V2,
790 	STA_REC_MURU,
791 	STA_REC_MUEDCA,
792 	STA_REC_BFEE,
793 	STA_REC_PHY = 0x15,
794 	STA_REC_HE_6G = 0x17,
795 	STA_REC_HE_V2 = 0x19,
796 	STA_REC_HDRT = 0x28,
797 	STA_REC_HDR_TRANS = 0x2B,
798 	STA_REC_MAX_NUM
799 };
800 
801 enum {
802 	WTBL_GENERIC,
803 	WTBL_RX,
804 	WTBL_HT,
805 	WTBL_VHT,
806 	WTBL_PEER_PS,		/* not used */
807 	WTBL_TX_PS,
808 	WTBL_HDR_TRANS,
809 	WTBL_SEC_KEY,
810 	WTBL_BA,
811 	WTBL_RDG,		/* obsoleted */
812 	WTBL_PROTECT,		/* not used */
813 	WTBL_CLEAR,		/* not used */
814 	WTBL_BF,
815 	WTBL_SMPS,
816 	WTBL_RAW_DATA,		/* debug only */
817 	WTBL_PN,
818 	WTBL_SPE,
819 	WTBL_MAX_NUM
820 };
821 
822 #define STA_TYPE_STA			BIT(0)
823 #define STA_TYPE_AP			BIT(1)
824 #define STA_TYPE_ADHOC			BIT(2)
825 #define STA_TYPE_WDS			BIT(4)
826 #define STA_TYPE_BC			BIT(5)
827 
828 #define NETWORK_INFRA			BIT(16)
829 #define NETWORK_P2P			BIT(17)
830 #define NETWORK_IBSS			BIT(18)
831 #define NETWORK_WDS			BIT(21)
832 
833 #define SCAN_FUNC_RANDOM_MAC		BIT(0)
834 #define SCAN_FUNC_SPLIT_SCAN		BIT(5)
835 
836 #define CONNECTION_INFRA_STA		(STA_TYPE_STA | NETWORK_INFRA)
837 #define CONNECTION_INFRA_AP		(STA_TYPE_AP | NETWORK_INFRA)
838 #define CONNECTION_P2P_GC		(STA_TYPE_STA | NETWORK_P2P)
839 #define CONNECTION_P2P_GO		(STA_TYPE_AP | NETWORK_P2P)
840 #define CONNECTION_IBSS_ADHOC		(STA_TYPE_ADHOC | NETWORK_IBSS)
841 #define CONNECTION_WDS			(STA_TYPE_WDS | NETWORK_WDS)
842 #define CONNECTION_INFRA_BC		(STA_TYPE_BC | NETWORK_INFRA)
843 
844 #define CONN_STATE_DISCONNECT		0
845 #define CONN_STATE_CONNECT		1
846 #define CONN_STATE_PORT_SECURE		2
847 
848 /* HE MAC */
849 #define STA_REC_HE_CAP_HTC			BIT(0)
850 #define STA_REC_HE_CAP_BQR			BIT(1)
851 #define STA_REC_HE_CAP_BSR			BIT(2)
852 #define STA_REC_HE_CAP_OM			BIT(3)
853 #define STA_REC_HE_CAP_AMSDU_IN_AMPDU		BIT(4)
854 /* HE PHY */
855 #define STA_REC_HE_CAP_DUAL_BAND		BIT(5)
856 #define STA_REC_HE_CAP_LDPC			BIT(6)
857 #define STA_REC_HE_CAP_TRIG_CQI_FK		BIT(7)
858 #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE	BIT(8)
859 /* STBC */
860 #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC	BIT(9)
861 #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC	BIT(10)
862 #define STA_REC_HE_CAP_GT_80M_TX_STBC		BIT(11)
863 #define STA_REC_HE_CAP_GT_80M_RX_STBC		BIT(12)
864 /* GI */
865 #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI	BIT(13)
866 #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI	BIT(14)
867 #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI	BIT(15)
868 #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI	BIT(16)
869 #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI	BIT(17)
870 /* 242 TONE */
871 #define STA_REC_HE_CAP_BW20_RU242_SUPPORT	BIT(18)
872 #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242	BIT(19)
873 #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242	BIT(20)
874 
875 #define PHY_MODE_A				BIT(0)
876 #define PHY_MODE_B				BIT(1)
877 #define PHY_MODE_G				BIT(2)
878 #define PHY_MODE_GN				BIT(3)
879 #define PHY_MODE_AN				BIT(4)
880 #define PHY_MODE_AC				BIT(5)
881 #define PHY_MODE_AX_24G				BIT(6)
882 #define PHY_MODE_AX_5G				BIT(7)
883 
884 #define PHY_MODE_AX_6G				BIT(0) /* phymode_ext */
885 
886 #define MODE_CCK				BIT(0)
887 #define MODE_OFDM				BIT(1)
888 #define MODE_HT					BIT(2)
889 #define MODE_VHT				BIT(3)
890 #define MODE_HE					BIT(4)
891 
892 #define STA_CAP_WMM				BIT(0)
893 #define STA_CAP_SGI_20				BIT(4)
894 #define STA_CAP_SGI_40				BIT(5)
895 #define STA_CAP_TX_STBC				BIT(6)
896 #define STA_CAP_RX_STBC				BIT(7)
897 #define STA_CAP_VHT_SGI_80			BIT(16)
898 #define STA_CAP_VHT_SGI_160			BIT(17)
899 #define STA_CAP_VHT_TX_STBC			BIT(18)
900 #define STA_CAP_VHT_RX_STBC			BIT(19)
901 #define STA_CAP_VHT_LDPC			BIT(23)
902 #define STA_CAP_LDPC				BIT(24)
903 #define STA_CAP_HT				BIT(26)
904 #define STA_CAP_VHT				BIT(27)
905 #define STA_CAP_HE				BIT(28)
906 
907 enum {
908 	PHY_TYPE_HR_DSSS_INDEX = 0,
909 	PHY_TYPE_ERP_INDEX,
910 	PHY_TYPE_ERP_P2P_INDEX,
911 	PHY_TYPE_OFDM_INDEX,
912 	PHY_TYPE_HT_INDEX,
913 	PHY_TYPE_VHT_INDEX,
914 	PHY_TYPE_HE_INDEX,
915 	PHY_TYPE_INDEX_NUM
916 };
917 
918 #define PHY_TYPE_BIT_HR_DSSS			BIT(PHY_TYPE_HR_DSSS_INDEX)
919 #define PHY_TYPE_BIT_ERP			BIT(PHY_TYPE_ERP_INDEX)
920 #define PHY_TYPE_BIT_OFDM			BIT(PHY_TYPE_OFDM_INDEX)
921 #define PHY_TYPE_BIT_HT				BIT(PHY_TYPE_HT_INDEX)
922 #define PHY_TYPE_BIT_VHT			BIT(PHY_TYPE_VHT_INDEX)
923 #define PHY_TYPE_BIT_HE				BIT(PHY_TYPE_HE_INDEX)
924 
925 #define MT_WTBL_RATE_TX_MODE			GENMASK(9, 6)
926 #define MT_WTBL_RATE_MCS			GENMASK(5, 0)
927 #define MT_WTBL_RATE_NSS			GENMASK(12, 10)
928 #define MT_WTBL_RATE_HE_GI			GENMASK(7, 4)
929 #define MT_WTBL_RATE_GI				GENMASK(3, 0)
930 
931 #define MT_WTBL_W5_CHANGE_BW_RATE		GENMASK(7, 5)
932 #define MT_WTBL_W5_SHORT_GI_20			BIT(8)
933 #define MT_WTBL_W5_SHORT_GI_40			BIT(9)
934 #define MT_WTBL_W5_SHORT_GI_80			BIT(10)
935 #define MT_WTBL_W5_SHORT_GI_160			BIT(11)
936 #define MT_WTBL_W5_BW_CAP			GENMASK(13, 12)
937 #define MT_WTBL_W5_MPDU_FAIL_COUNT		GENMASK(25, 23)
938 #define MT_WTBL_W5_MPDU_OK_COUNT		GENMASK(28, 26)
939 #define MT_WTBL_W5_RATE_IDX			GENMASK(31, 29)
940 
941 enum {
942 	WTBL_RESET_AND_SET = 1,
943 	WTBL_SET,
944 	WTBL_QUERY,
945 	WTBL_RESET_ALL
946 };
947 
948 enum {
949 	MT_BA_TYPE_INVALID,
950 	MT_BA_TYPE_ORIGINATOR,
951 	MT_BA_TYPE_RECIPIENT
952 };
953 
954 enum {
955 	RST_BA_MAC_TID_MATCH,
956 	RST_BA_MAC_MATCH,
957 	RST_BA_NO_MATCH
958 };
959 
960 enum {
961 	DEV_INFO_ACTIVE,
962 	DEV_INFO_MAX_NUM
963 };
964 
965 #define MCU_UNI_CMD_EVENT                       BIT(1)
966 #define MCU_UNI_CMD_UNSOLICITED_EVENT           BIT(2)
967 
968 /* event table */
969 enum {
970 	MCU_EVENT_TARGET_ADDRESS_LEN = 0x01,
971 	MCU_EVENT_FW_START = 0x01,
972 	MCU_EVENT_GENERIC = 0x01,
973 	MCU_EVENT_ACCESS_REG = 0x02,
974 	MCU_EVENT_MT_PATCH_SEM = 0x04,
975 	MCU_EVENT_REG_ACCESS = 0x05,
976 	MCU_EVENT_LP_INFO = 0x07,
977 	MCU_EVENT_SCAN_DONE = 0x0d,
978 	MCU_EVENT_TX_DONE = 0x0f,
979 	MCU_EVENT_ROC = 0x10,
980 	MCU_EVENT_BSS_ABSENCE  = 0x11,
981 	MCU_EVENT_BSS_BEACON_LOSS = 0x13,
982 	MCU_EVENT_CH_PRIVILEGE = 0x18,
983 	MCU_EVENT_SCHED_SCAN_DONE = 0x23,
984 	MCU_EVENT_DBG_MSG = 0x27,
985 	MCU_EVENT_TXPWR = 0xd0,
986 	MCU_EVENT_EXT = 0xed,
987 	MCU_EVENT_RESTART_DL = 0xef,
988 	MCU_EVENT_COREDUMP = 0xf0,
989 };
990 
991 /* ext event table */
992 enum {
993 	MCU_EXT_EVENT_PS_SYNC = 0x5,
994 	MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13,
995 	MCU_EXT_EVENT_THERMAL_PROTECT = 0x22,
996 	MCU_EXT_EVENT_ASSERT_DUMP = 0x23,
997 	MCU_EXT_EVENT_RDD_REPORT = 0x3a,
998 	MCU_EXT_EVENT_CSA_NOTIFY = 0x4f,
999 	MCU_EXT_EVENT_BCC_NOTIFY = 0x75,
1000 	MCU_EXT_EVENT_MURU_CTRL = 0x9f,
1001 };
1002 
1003 /* unified event table */
1004 enum {
1005 	MCU_UNI_EVENT_RESULT = 0x01,
1006 	MCU_UNI_EVENT_FW_LOG_2_HOST = 0x04,
1007 	MCU_UNI_EVENT_IE_COUNTDOWN = 0x09,
1008 	MCU_UNI_EVENT_RDD_REPORT = 0x11,
1009 };
1010 
1011 #define MCU_UNI_CMD_EVENT			BIT(1)
1012 #define MCU_UNI_CMD_UNSOLICITED_EVENT		BIT(2)
1013 
1014 enum {
1015 	MCU_Q_QUERY,
1016 	MCU_Q_SET,
1017 	MCU_Q_RESERVED,
1018 	MCU_Q_NA
1019 };
1020 
1021 enum {
1022 	MCU_S2D_H2N,
1023 	MCU_S2D_C2N,
1024 	MCU_S2D_H2C,
1025 	MCU_S2D_H2CN
1026 };
1027 
1028 enum {
1029 	PATCH_NOT_DL_SEM_FAIL,
1030 	PATCH_IS_DL,
1031 	PATCH_NOT_DL_SEM_SUCCESS,
1032 	PATCH_REL_SEM_SUCCESS
1033 };
1034 
1035 enum {
1036 	FW_STATE_INITIAL,
1037 	FW_STATE_FW_DOWNLOAD,
1038 	FW_STATE_NORMAL_OPERATION,
1039 	FW_STATE_NORMAL_TRX,
1040 	FW_STATE_RDY = 7
1041 };
1042 
1043 enum {
1044 	CH_SWITCH_NORMAL = 0,
1045 	CH_SWITCH_SCAN = 3,
1046 	CH_SWITCH_MCC = 4,
1047 	CH_SWITCH_DFS = 5,
1048 	CH_SWITCH_BACKGROUND_SCAN_START = 6,
1049 	CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7,
1050 	CH_SWITCH_BACKGROUND_SCAN_STOP = 8,
1051 	CH_SWITCH_SCAN_BYPASS_DPD = 9
1052 };
1053 
1054 enum {
1055 	THERMAL_SENSOR_TEMP_QUERY,
1056 	THERMAL_SENSOR_MANUAL_CTRL,
1057 	THERMAL_SENSOR_INFO_QUERY,
1058 	THERMAL_SENSOR_TASK_CTRL,
1059 };
1060 
1061 enum mcu_cipher_type {
1062 	MCU_CIPHER_NONE = 0,
1063 	MCU_CIPHER_WEP40,
1064 	MCU_CIPHER_WEP104,
1065 	MCU_CIPHER_WEP128,
1066 	MCU_CIPHER_TKIP,
1067 	MCU_CIPHER_AES_CCMP,
1068 	MCU_CIPHER_CCMP_256,
1069 	MCU_CIPHER_GCMP,
1070 	MCU_CIPHER_GCMP_256,
1071 	MCU_CIPHER_WAPI,
1072 	MCU_CIPHER_BIP_CMAC_128,
1073 };
1074 
1075 enum {
1076 	EE_MODE_EFUSE,
1077 	EE_MODE_BUFFER,
1078 };
1079 
1080 enum {
1081 	EE_FORMAT_BIN,
1082 	EE_FORMAT_WHOLE,
1083 	EE_FORMAT_MULTIPLE,
1084 };
1085 
1086 enum {
1087 	MCU_PHY_STATE_TX_RATE,
1088 	MCU_PHY_STATE_RX_RATE,
1089 	MCU_PHY_STATE_RSSI,
1090 	MCU_PHY_STATE_CONTENTION_RX_RATE,
1091 	MCU_PHY_STATE_OFDMLQ_CNINFO,
1092 };
1093 
1094 #define MCU_CMD_ACK				BIT(0)
1095 #define MCU_CMD_UNI				BIT(1)
1096 #define MCU_CMD_SET				BIT(2)
1097 
1098 #define MCU_CMD_UNI_EXT_ACK			(MCU_CMD_ACK | MCU_CMD_UNI | \
1099 						 MCU_CMD_SET)
1100 #define MCU_CMD_UNI_QUERY_ACK			(MCU_CMD_ACK | MCU_CMD_UNI)
1101 
1102 #define __MCU_CMD_FIELD_ID			GENMASK(7, 0)
1103 #define __MCU_CMD_FIELD_EXT_ID			GENMASK(15, 8)
1104 #define __MCU_CMD_FIELD_QUERY			BIT(16)
1105 #define __MCU_CMD_FIELD_UNI			BIT(17)
1106 #define __MCU_CMD_FIELD_CE			BIT(18)
1107 #define __MCU_CMD_FIELD_WA			BIT(19)
1108 #define __MCU_CMD_FIELD_WM			BIT(20)
1109 
1110 #define MCU_CMD(_t)				FIELD_PREP(__MCU_CMD_FIELD_ID,		\
1111 							   MCU_CMD_##_t)
1112 #define MCU_EXT_CMD(_t)				(MCU_CMD(EXT_CID) | \
1113 						 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID,	\
1114 							    MCU_EXT_CMD_##_t))
1115 #define MCU_EXT_QUERY(_t)			(MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_QUERY)
1116 #define MCU_UNI_CMD(_t)				(__MCU_CMD_FIELD_UNI |			\
1117 						 FIELD_PREP(__MCU_CMD_FIELD_ID,		\
1118 							    MCU_UNI_CMD_##_t))
1119 #define MCU_CE_CMD(_t)				(__MCU_CMD_FIELD_CE |			\
1120 						 FIELD_PREP(__MCU_CMD_FIELD_ID,		\
1121 							   MCU_CE_CMD_##_t))
1122 #define MCU_CE_QUERY(_t)			(MCU_CE_CMD(_t) | __MCU_CMD_FIELD_QUERY)
1123 
1124 #define MCU_WA_CMD(_t)				(MCU_CMD(_t) | __MCU_CMD_FIELD_WA)
1125 #define MCU_WA_EXT_CMD(_t)			(MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_WA)
1126 #define MCU_WA_PARAM_CMD(_t)			(MCU_WA_CMD(WA_PARAM) | \
1127 						 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \
1128 							    MCU_WA_PARAM_CMD_##_t))
1129 
1130 #define MCU_WM_UNI_CMD(_t)			(MCU_UNI_CMD(_t) |		\
1131 						 __MCU_CMD_FIELD_WM)
1132 #define MCU_WM_UNI_CMD_QUERY(_t)		(MCU_UNI_CMD(_t) |		\
1133 						 __MCU_CMD_FIELD_QUERY |	\
1134 						 __MCU_CMD_FIELD_WM)
1135 #define MCU_WA_UNI_CMD(_t)			(MCU_UNI_CMD(_t) |		\
1136 						 __MCU_CMD_FIELD_WA)
1137 #define MCU_WMWA_UNI_CMD(_t)			(MCU_WM_UNI_CMD(_t) |		\
1138 						 __MCU_CMD_FIELD_WA)
1139 
1140 enum {
1141 	MCU_EXT_CMD_EFUSE_ACCESS = 0x01,
1142 	MCU_EXT_CMD_RF_REG_ACCESS = 0x02,
1143 	MCU_EXT_CMD_RF_TEST = 0x04,
1144 	MCU_EXT_CMD_PM_STATE_CTRL = 0x07,
1145 	MCU_EXT_CMD_CHANNEL_SWITCH = 0x08,
1146 	MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11,
1147 	MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
1148 	MCU_EXT_CMD_TXBF_ACTION = 0x1e,
1149 	MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
1150 	MCU_EXT_CMD_THERMAL_PROT = 0x23,
1151 	MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
1152 	MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26,
1153 	MCU_EXT_CMD_EDCA_UPDATE = 0x27,
1154 	MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A,
1155 	MCU_EXT_CMD_THERMAL_CTRL = 0x2c,
1156 	MCU_EXT_CMD_WTBL_UPDATE = 0x32,
1157 	MCU_EXT_CMD_SET_DRR_CTRL = 0x36,
1158 	MCU_EXT_CMD_SET_RDD_CTRL = 0x3a,
1159 	MCU_EXT_CMD_ATE_CTRL = 0x3d,
1160 	MCU_EXT_CMD_PROTECT_CTRL = 0x3e,
1161 	MCU_EXT_CMD_DBDC_CTRL = 0x45,
1162 	MCU_EXT_CMD_MAC_INIT_CTRL = 0x46,
1163 	MCU_EXT_CMD_RX_HDR_TRANS = 0x47,
1164 	MCU_EXT_CMD_MUAR_UPDATE = 0x48,
1165 	MCU_EXT_CMD_BCN_OFFLOAD = 0x49,
1166 	MCU_EXT_CMD_RX_AIRTIME_CTRL = 0x4a,
1167 	MCU_EXT_CMD_SET_RX_PATH = 0x4e,
1168 	MCU_EXT_CMD_EFUSE_FREE_BLOCK = 0x4f,
1169 	MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
1170 	MCU_EXT_CMD_RXDCOC_CAL = 0x59,
1171 	MCU_EXT_CMD_GET_MIB_INFO = 0x5a,
1172 	MCU_EXT_CMD_TXDPD_CAL = 0x60,
1173 	MCU_EXT_CMD_CAL_CACHE = 0x67,
1174 	MCU_EXT_CMD_SET_RADAR_TH = 0x7c,
1175 	MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d,
1176 	MCU_EXT_CMD_MWDS_SUPPORT = 0x80,
1177 	MCU_EXT_CMD_SET_SER_TRIGGER = 0x81,
1178 	MCU_EXT_CMD_TWT_AGRT_UPDATE = 0x94,
1179 	MCU_EXT_CMD_FW_DBG_CTRL = 0x95,
1180 	MCU_EXT_CMD_OFFCH_SCAN_CTRL = 0x9a,
1181 	MCU_EXT_CMD_SET_RDD_TH = 0x9d,
1182 	MCU_EXT_CMD_MURU_CTRL = 0x9f,
1183 	MCU_EXT_CMD_SET_SPR = 0xa8,
1184 	MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab,
1185 	MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac,
1186 	MCU_EXT_CMD_PHY_STAT_INFO = 0xad,
1187 };
1188 
1189 enum {
1190 	MCU_UNI_CMD_DEV_INFO_UPDATE = 0x01,
1191 	MCU_UNI_CMD_BSS_INFO_UPDATE = 0x02,
1192 	MCU_UNI_CMD_STA_REC_UPDATE = 0x03,
1193 	MCU_UNI_CMD_EDCA_UPDATE = 0x04,
1194 	MCU_UNI_CMD_SUSPEND = 0x05,
1195 	MCU_UNI_CMD_OFFLOAD = 0x06,
1196 	MCU_UNI_CMD_HIF_CTRL = 0x07,
1197 	MCU_UNI_CMD_BAND_CONFIG = 0x08,
1198 	MCU_UNI_CMD_REPT_MUAR = 0x09,
1199 	MCU_UNI_CMD_WSYS_CONFIG = 0x0b,
1200 	MCU_UNI_CMD_REG_ACCESS = 0x0d,
1201 	MCU_UNI_CMD_POWER_CREL = 0x0f,
1202 	MCU_UNI_CMD_RX_HDR_TRANS = 0x12,
1203 	MCU_UNI_CMD_SER = 0x13,
1204 	MCU_UNI_CMD_TWT = 0x14,
1205 	MCU_UNI_CMD_RDD_CTRL = 0x19,
1206 	MCU_UNI_CMD_GET_MIB_INFO = 0x22,
1207 	MCU_UNI_CMD_SNIFFER = 0x24,
1208 	MCU_UNI_CMD_SR = 0x25,
1209 	MCU_UNI_CMD_ROC = 0x27,
1210 	MCU_UNI_CMD_TXPOWER = 0x2b,
1211 	MCU_UNI_CMD_EFUSE_CTRL = 0x2d,
1212 	MCU_UNI_CMD_RA = 0x2f,
1213 	MCU_UNI_CMD_MURU = 0x31,
1214 	MCU_UNI_CMD_BF = 0x33,
1215 	MCU_UNI_CMD_CHANNEL_SWITCH = 0x34,
1216 	MCU_UNI_CMD_THERMAL = 0x35,
1217 	MCU_UNI_CMD_VOW = 0x37,
1218 	MCU_UNI_CMD_RRO = 0x57,
1219 	MCU_UNI_CMD_OFFCH_SCAN_CTRL = 0x58,
1220 };
1221 
1222 enum {
1223 	MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01,
1224 	MCU_CMD_FW_START_REQ = 0x02,
1225 	MCU_CMD_INIT_ACCESS_REG = 0x3,
1226 	MCU_CMD_NIC_POWER_CTRL = 0x4,
1227 	MCU_CMD_PATCH_START_REQ = 0x05,
1228 	MCU_CMD_PATCH_FINISH_REQ = 0x07,
1229 	MCU_CMD_PATCH_SEM_CONTROL = 0x10,
1230 	MCU_CMD_WA_PARAM = 0xc4,
1231 	MCU_CMD_EXT_CID = 0xed,
1232 	MCU_CMD_FW_SCATTER = 0xee,
1233 	MCU_CMD_RESTART_DL_REQ = 0xef,
1234 };
1235 
1236 /* offload mcu commands */
1237 enum {
1238 	MCU_CE_CMD_TEST_CTRL = 0x01,
1239 	MCU_CE_CMD_START_HW_SCAN = 0x03,
1240 	MCU_CE_CMD_SET_PS_PROFILE = 0x05,
1241 	MCU_CE_CMD_SET_CHAN_DOMAIN = 0x0f,
1242 	MCU_CE_CMD_SET_BSS_CONNECTED = 0x16,
1243 	MCU_CE_CMD_SET_BSS_ABORT = 0x17,
1244 	MCU_CE_CMD_CANCEL_HW_SCAN = 0x1b,
1245 	MCU_CE_CMD_SET_ROC = 0x1c,
1246 	MCU_CE_CMD_SET_EDCA_PARMS = 0x1d,
1247 	MCU_CE_CMD_SET_P2P_OPPPS = 0x33,
1248 	MCU_CE_CMD_SET_CLC = 0x5c,
1249 	MCU_CE_CMD_SET_RATE_TX_POWER = 0x5d,
1250 	MCU_CE_CMD_SCHED_SCAN_ENABLE = 0x61,
1251 	MCU_CE_CMD_SCHED_SCAN_REQ = 0x62,
1252 	MCU_CE_CMD_GET_NIC_CAPAB = 0x8a,
1253 	MCU_CE_CMD_SET_MU_EDCA_PARMS = 0xb0,
1254 	MCU_CE_CMD_REG_WRITE = 0xc0,
1255 	MCU_CE_CMD_REG_READ = 0xc0,
1256 	MCU_CE_CMD_CHIP_CONFIG = 0xca,
1257 	MCU_CE_CMD_FWLOG_2_HOST = 0xc5,
1258 	MCU_CE_CMD_GET_WTBL = 0xcd,
1259 	MCU_CE_CMD_GET_TXPWR = 0xd0,
1260 };
1261 
1262 enum {
1263 	PATCH_SEM_RELEASE,
1264 	PATCH_SEM_GET
1265 };
1266 
1267 enum {
1268 	UNI_BSS_INFO_BASIC = 0,
1269 	UNI_BSS_INFO_RA = 1,
1270 	UNI_BSS_INFO_RLM = 2,
1271 	UNI_BSS_INFO_BSS_COLOR = 4,
1272 	UNI_BSS_INFO_HE_BASIC = 5,
1273 	UNI_BSS_INFO_BCN_CONTENT = 7,
1274 	UNI_BSS_INFO_BCN_CSA = 8,
1275 	UNI_BSS_INFO_BCN_BCC = 9,
1276 	UNI_BSS_INFO_BCN_MBSSID = 10,
1277 	UNI_BSS_INFO_RATE = 11,
1278 	UNI_BSS_INFO_QBSS = 15,
1279 	UNI_BSS_INFO_SEC = 16,
1280 	UNI_BSS_INFO_TXCMD = 18,
1281 	UNI_BSS_INFO_UAPSD = 19,
1282 	UNI_BSS_INFO_PS = 21,
1283 	UNI_BSS_INFO_BCNFT = 22,
1284 	UNI_BSS_INFO_OFFLOAD = 25,
1285 	UNI_BSS_INFO_MLD = 26,
1286 };
1287 
1288 enum {
1289 	UNI_OFFLOAD_OFFLOAD_ARP,
1290 	UNI_OFFLOAD_OFFLOAD_ND,
1291 	UNI_OFFLOAD_OFFLOAD_GTK_REKEY,
1292 	UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT,
1293 };
1294 
1295 enum {
1296 	MT_NIC_CAP_TX_RESOURCE,
1297 	MT_NIC_CAP_TX_EFUSE_ADDR,
1298 	MT_NIC_CAP_COEX,
1299 	MT_NIC_CAP_SINGLE_SKU,
1300 	MT_NIC_CAP_CSUM_OFFLOAD,
1301 	MT_NIC_CAP_HW_VER,
1302 	MT_NIC_CAP_SW_VER,
1303 	MT_NIC_CAP_MAC_ADDR,
1304 	MT_NIC_CAP_PHY,
1305 	MT_NIC_CAP_MAC,
1306 	MT_NIC_CAP_FRAME_BUF,
1307 	MT_NIC_CAP_BEAM_FORM,
1308 	MT_NIC_CAP_LOCATION,
1309 	MT_NIC_CAP_MUMIMO,
1310 	MT_NIC_CAP_BUFFER_MODE_INFO,
1311 	MT_NIC_CAP_HW_ADIE_VERSION = 0x14,
1312 	MT_NIC_CAP_ANTSWP = 0x16,
1313 	MT_NIC_CAP_WFDMA_REALLOC,
1314 	MT_NIC_CAP_6G,
1315 };
1316 
1317 #define UNI_WOW_DETECT_TYPE_MAGIC		BIT(0)
1318 #define UNI_WOW_DETECT_TYPE_ANY			BIT(1)
1319 #define UNI_WOW_DETECT_TYPE_DISCONNECT		BIT(2)
1320 #define UNI_WOW_DETECT_TYPE_GTK_REKEY_FAIL	BIT(3)
1321 #define UNI_WOW_DETECT_TYPE_BCN_LOST		BIT(4)
1322 #define UNI_WOW_DETECT_TYPE_SCH_SCAN_HIT	BIT(5)
1323 #define UNI_WOW_DETECT_TYPE_BITMAP		BIT(6)
1324 
1325 enum {
1326 	UNI_SUSPEND_MODE_SETTING,
1327 	UNI_SUSPEND_WOW_CTRL,
1328 	UNI_SUSPEND_WOW_GPIO_PARAM,
1329 	UNI_SUSPEND_WOW_WAKEUP_PORT,
1330 	UNI_SUSPEND_WOW_PATTERN,
1331 };
1332 
1333 enum {
1334 	WOW_USB = 1,
1335 	WOW_PCIE = 2,
1336 	WOW_GPIO = 3,
1337 };
1338 
1339 struct mt76_connac_bss_basic_tlv {
1340 	__le16 tag;
1341 	__le16 len;
1342 	u8 active;
1343 	u8 omac_idx;
1344 	u8 hw_bss_idx;
1345 	u8 band_idx;
1346 	__le32 conn_type;
1347 	u8 conn_state;
1348 	u8 wmm_idx;
1349 	u8 bssid[ETH_ALEN];
1350 	__le16 bmc_tx_wlan_idx;
1351 	__le16 bcn_interval;
1352 	u8 dtim_period;
1353 	u8 phymode; /* bit(0): A
1354 		     * bit(1): B
1355 		     * bit(2): G
1356 		     * bit(3): GN
1357 		     * bit(4): AN
1358 		     * bit(5): AC
1359 		     * bit(6): AX2
1360 		     * bit(7): AX5
1361 		     * bit(8): AX6
1362 		     */
1363 	__le16 sta_idx;
1364 	__le16 nonht_basic_phy;
1365 	u8 phymode_ext; /* bit(0) AX_6G */
1366 	u8 pad[1];
1367 } __packed;
1368 
1369 struct mt76_connac_bss_qos_tlv {
1370 	__le16 tag;
1371 	__le16 len;
1372 	u8 qos;
1373 	u8 pad[3];
1374 } __packed;
1375 
1376 struct mt76_connac_beacon_loss_event {
1377 	u8 bss_idx;
1378 	u8 reason;
1379 	u8 pad[2];
1380 } __packed;
1381 
1382 struct mt76_connac_mcu_bss_event {
1383 	u8 bss_idx;
1384 	u8 is_absent;
1385 	u8 free_quota;
1386 	u8 pad;
1387 } __packed;
1388 
1389 struct mt76_connac_mcu_scan_ssid {
1390 	__le32 ssid_len;
1391 	u8 ssid[IEEE80211_MAX_SSID_LEN];
1392 } __packed;
1393 
1394 struct mt76_connac_mcu_scan_channel {
1395 	u8 band; /* 1: 2.4GHz
1396 		  * 2: 5.0GHz
1397 		  * Others: Reserved
1398 		  */
1399 	u8 channel_num;
1400 } __packed;
1401 
1402 struct mt76_connac_mcu_scan_match {
1403 	__le32 rssi_th;
1404 	u8 ssid[IEEE80211_MAX_SSID_LEN];
1405 	u8 ssid_len;
1406 	u8 rsv[3];
1407 } __packed;
1408 
1409 struct mt76_connac_hw_scan_req {
1410 	u8 seq_num;
1411 	u8 bss_idx;
1412 	u8 scan_type; /* 0: PASSIVE SCAN
1413 		       * 1: ACTIVE SCAN
1414 		       */
1415 	u8 ssid_type; /* BIT(0) wildcard SSID
1416 		       * BIT(1) P2P wildcard SSID
1417 		       * BIT(2) specified SSID + wildcard SSID
1418 		       * BIT(2) + ssid_type_ext BIT(0) specified SSID only
1419 		       */
1420 	u8 ssids_num;
1421 	u8 probe_req_num; /* Number of probe request for each SSID */
1422 	u8 scan_func; /* BIT(0) Enable random MAC scan
1423 		       * BIT(1) Disable DBDC scan type 1~3.
1424 		       * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan).
1425 		       */
1426 	u8 version; /* 0: Not support fields after ies.
1427 		     * 1: Support fields after ies.
1428 		     */
1429 	struct mt76_connac_mcu_scan_ssid ssids[4];
1430 	__le16 probe_delay_time;
1431 	__le16 channel_dwell_time; /* channel Dwell interval */
1432 	__le16 timeout_value;
1433 	u8 channel_type; /* 0: Full channels
1434 			  * 1: Only 2.4GHz channels
1435 			  * 2: Only 5GHz channels
1436 			  * 3: P2P social channel only (channel #1, #6 and #11)
1437 			  * 4: Specified channels
1438 			  * Others: Reserved
1439 			  */
1440 	u8 channels_num; /* valid when channel_type is 4 */
1441 	/* valid when channels_num is set */
1442 	struct mt76_connac_mcu_scan_channel channels[32];
1443 	__le16 ies_len;
1444 	u8 ies[MT76_CONNAC_SCAN_IE_LEN];
1445 	/* following fields are valid if version > 0 */
1446 	u8 ext_channels_num;
1447 	u8 ext_ssids_num;
1448 	__le16 channel_min_dwell_time;
1449 	struct mt76_connac_mcu_scan_channel ext_channels[32];
1450 	struct mt76_connac_mcu_scan_ssid ext_ssids[6];
1451 	u8 bssid[ETH_ALEN];
1452 	u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */
1453 	u8 pad[63];
1454 	u8 ssid_type_ext;
1455 } __packed;
1456 
1457 #define MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM		64
1458 
1459 struct mt76_connac_hw_scan_done {
1460 	u8 seq_num;
1461 	u8 sparse_channel_num;
1462 	struct mt76_connac_mcu_scan_channel sparse_channel;
1463 	u8 complete_channel_num;
1464 	u8 current_state;
1465 	u8 version;
1466 	u8 pad;
1467 	__le32 beacon_scan_num;
1468 	u8 pno_enabled;
1469 	u8 pad2[3];
1470 	u8 sparse_channel_valid_num;
1471 	u8 pad3[3];
1472 	u8 channel_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1473 	/* idle format for channel_idle_time
1474 	 * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms)
1475 	 * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms)
1476 	 * 2: dwell time (16us)
1477 	 */
1478 	__le16 channel_idle_time[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1479 	/* beacon and probe response count */
1480 	u8 beacon_probe_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1481 	u8 mdrdy_count[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1482 	__le32 beacon_2g_num;
1483 	__le32 beacon_5g_num;
1484 } __packed;
1485 
1486 struct mt76_connac_sched_scan_req {
1487 	u8 version;
1488 	u8 seq_num;
1489 	u8 stop_on_match;
1490 	u8 ssids_num;
1491 	u8 match_num;
1492 	u8 pad;
1493 	__le16 ie_len;
1494 	struct mt76_connac_mcu_scan_ssid ssids[MT76_CONNAC_MAX_SCHED_SCAN_SSID];
1495 	struct mt76_connac_mcu_scan_match match[MT76_CONNAC_MAX_SCAN_MATCH];
1496 	u8 channel_type;
1497 	u8 channels_num;
1498 	u8 intervals_num;
1499 	u8 scan_func; /* MT7663: BIT(0) eable random mac address */
1500 	struct mt76_connac_mcu_scan_channel channels[64];
1501 	__le16 intervals[MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL];
1502 	union {
1503 		struct {
1504 			u8 random_mac[ETH_ALEN];
1505 			u8 pad2[58];
1506 		} mt7663;
1507 		struct {
1508 			u8 bss_idx;
1509 			u8 pad1[3];
1510 			__le32 delay;
1511 			u8 pad2[12];
1512 			u8 random_mac[ETH_ALEN];
1513 			u8 pad3[38];
1514 		} mt7921;
1515 	};
1516 } __packed;
1517 
1518 struct mt76_connac_sched_scan_done {
1519 	u8 seq_num;
1520 	u8 status; /* 0: ssid found */
1521 	__le16 pad;
1522 } __packed;
1523 
1524 struct bss_info_uni_bss_color {
1525 	__le16 tag;
1526 	__le16 len;
1527 	u8 enable;
1528 	u8 bss_color;
1529 	u8 rsv[2];
1530 } __packed;
1531 
1532 struct bss_info_uni_he {
1533 	__le16 tag;
1534 	__le16 len;
1535 	__le16 he_rts_thres;
1536 	u8 he_pe_duration;
1537 	u8 su_disable;
1538 	__le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
1539 	u8 rsv[2];
1540 } __packed;
1541 
1542 struct mt76_connac_gtk_rekey_tlv {
1543 	__le16 tag;
1544 	__le16 len;
1545 	u8 kek[NL80211_KEK_LEN];
1546 	u8 kck[NL80211_KCK_LEN];
1547 	u8 replay_ctr[NL80211_REPLAY_CTR_LEN];
1548 	u8 rekey_mode; /* 0: rekey offload enable
1549 			* 1: rekey offload disable
1550 			* 2: rekey update
1551 			*/
1552 	u8 keyid;
1553 	u8 option; /* 1: rekey data update without enabling offload */
1554 	u8 pad[1];
1555 	__le32 proto; /* WPA-RSN-WAPI-OPSN */
1556 	__le32 pairwise_cipher;
1557 	__le32 group_cipher;
1558 	__le32 key_mgmt; /* NONE-PSK-IEEE802.1X */
1559 	__le32 mgmt_group_cipher;
1560 	u8 reserverd[4];
1561 } __packed;
1562 
1563 #define MT76_CONNAC_WOW_MASK_MAX_LEN			16
1564 #define MT76_CONNAC_WOW_PATTEN_MAX_LEN			128
1565 
1566 struct mt76_connac_wow_pattern_tlv {
1567 	__le16 tag;
1568 	__le16 len;
1569 	u8 index; /* pattern index */
1570 	u8 enable; /* 0: disable
1571 		    * 1: enable
1572 		    */
1573 	u8 data_len; /* pattern length */
1574 	u8 pad;
1575 	u8 mask[MT76_CONNAC_WOW_MASK_MAX_LEN];
1576 	u8 pattern[MT76_CONNAC_WOW_PATTEN_MAX_LEN];
1577 	u8 rsv[4];
1578 } __packed;
1579 
1580 struct mt76_connac_wow_ctrl_tlv {
1581 	__le16 tag;
1582 	__le16 len;
1583 	u8 cmd; /* 0x1: PM_WOWLAN_REQ_START
1584 		 * 0x2: PM_WOWLAN_REQ_STOP
1585 		 * 0x3: PM_WOWLAN_PARAM_CLEAR
1586 		 */
1587 	u8 trigger; /* 0: NONE
1588 		     * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT
1589 		     * BIT(1): NL80211_WOWLAN_TRIG_ANY
1590 		     * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT
1591 		     * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE
1592 		     * BIT(4): BEACON_LOST
1593 		     * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT
1594 		     */
1595 	u8 wakeup_hif; /* 0x0: HIF_SDIO
1596 			* 0x1: HIF_USB
1597 			* 0x2: HIF_PCIE
1598 			* 0x3: HIF_GPIO
1599 			*/
1600 	u8 pad;
1601 	u8 rsv[4];
1602 } __packed;
1603 
1604 struct mt76_connac_wow_gpio_param_tlv {
1605 	__le16 tag;
1606 	__le16 len;
1607 	u8 gpio_pin;
1608 	u8 trigger_lvl;
1609 	u8 pad[2];
1610 	__le32 gpio_interval;
1611 	u8 rsv[4];
1612 } __packed;
1613 
1614 struct mt76_connac_arpns_tlv {
1615 	__le16 tag;
1616 	__le16 len;
1617 	u8 mode;
1618 	u8 ips_num;
1619 	u8 option;
1620 	u8 pad[1];
1621 } __packed;
1622 
1623 struct mt76_connac_suspend_tlv {
1624 	__le16 tag;
1625 	__le16 len;
1626 	u8 enable; /* 0: suspend mode disabled
1627 		    * 1: suspend mode enabled
1628 		    */
1629 	u8 mdtim; /* LP parameter */
1630 	u8 wow_suspend; /* 0: update by origin policy
1631 			 * 1: update by wow dtim
1632 			 */
1633 	u8 pad[5];
1634 } __packed;
1635 
1636 enum mt76_sta_info_state {
1637 	MT76_STA_INFO_STATE_NONE,
1638 	MT76_STA_INFO_STATE_AUTH,
1639 	MT76_STA_INFO_STATE_ASSOC
1640 };
1641 
1642 struct mt76_sta_cmd_info {
1643 	struct ieee80211_sta *sta;
1644 	struct mt76_wcid *wcid;
1645 
1646 	struct ieee80211_vif *vif;
1647 
1648 	bool offload_fw;
1649 	bool enable;
1650 	bool newly;
1651 	int cmd;
1652 	u8 rcpi;
1653 	u8 state;
1654 };
1655 
1656 #define MT_SKU_POWER_LIMIT	161
1657 
1658 struct mt76_connac_sku_tlv {
1659 	u8 channel;
1660 	s8 pwr_limit[MT_SKU_POWER_LIMIT];
1661 } __packed;
1662 
1663 struct mt76_connac_tx_power_limit_tlv {
1664 	/* DW0 - common info*/
1665 	u8 ver;
1666 	u8 pad0;
1667 	__le16 len;
1668 	/* DW1 - cmd hint */
1669 	u8 n_chan; /* # channel */
1670 	u8 band; /* 2.4GHz - 5GHz - 6GHz */
1671 	u8 last_msg;
1672 	u8 pad1;
1673 	/* DW3 */
1674 	u8 alpha2[4]; /* regulatory_request.alpha2 */
1675 	u8 pad2[32];
1676 } __packed;
1677 
1678 struct mt76_connac_config {
1679 	__le16 id;
1680 	u8 type;
1681 	u8 resp_type;
1682 	__le16 data_size;
1683 	__le16 resv;
1684 	u8 data[320];
1685 } __packed;
1686 
1687 static inline enum mcu_cipher_type
1688 mt76_connac_mcu_get_cipher(int cipher)
1689 {
1690 	switch (cipher) {
1691 	case WLAN_CIPHER_SUITE_WEP40:
1692 		return MCU_CIPHER_WEP40;
1693 	case WLAN_CIPHER_SUITE_WEP104:
1694 		return MCU_CIPHER_WEP104;
1695 	case WLAN_CIPHER_SUITE_TKIP:
1696 		return MCU_CIPHER_TKIP;
1697 	case WLAN_CIPHER_SUITE_AES_CMAC:
1698 		return MCU_CIPHER_BIP_CMAC_128;
1699 	case WLAN_CIPHER_SUITE_CCMP:
1700 		return MCU_CIPHER_AES_CCMP;
1701 	case WLAN_CIPHER_SUITE_CCMP_256:
1702 		return MCU_CIPHER_CCMP_256;
1703 	case WLAN_CIPHER_SUITE_GCMP:
1704 		return MCU_CIPHER_GCMP;
1705 	case WLAN_CIPHER_SUITE_GCMP_256:
1706 		return MCU_CIPHER_GCMP_256;
1707 	case WLAN_CIPHER_SUITE_SMS4:
1708 		return MCU_CIPHER_WAPI;
1709 	default:
1710 		return MCU_CIPHER_NONE;
1711 	}
1712 }
1713 
1714 static inline u32
1715 mt76_connac_mcu_gen_dl_mode(struct mt76_dev *dev, u8 feature_set, bool is_wa)
1716 {
1717 	u32 ret = 0;
1718 
1719 	ret |= feature_set & FW_FEATURE_SET_ENCRYPT ?
1720 	       DL_MODE_ENCRYPT | DL_MODE_RESET_SEC_IV : 0;
1721 	if (is_mt7921(dev))
1722 		ret |= feature_set & FW_FEATURE_ENCRY_MODE ?
1723 		       DL_CONFIG_ENCRY_MODE_SEL : 0;
1724 	ret |= FIELD_PREP(DL_MODE_KEY_IDX,
1725 			  FIELD_GET(FW_FEATURE_SET_KEY_IDX, feature_set));
1726 	ret |= DL_MODE_NEED_RSP;
1727 	ret |= is_wa ? DL_MODE_WORKING_PDA_CR4 : 0;
1728 
1729 	return ret;
1730 }
1731 
1732 #define to_wcid_lo(id)		FIELD_GET(GENMASK(7, 0), (u16)id)
1733 #define to_wcid_hi(id)		FIELD_GET(GENMASK(9, 8), (u16)id)
1734 
1735 static inline void
1736 mt76_connac_mcu_get_wlan_idx(struct mt76_dev *dev, struct mt76_wcid *wcid,
1737 			     u8 *wlan_idx_lo, u8 *wlan_idx_hi)
1738 {
1739 	*wlan_idx_hi = 0;
1740 
1741 	if (!is_connac_v1(dev)) {
1742 		*wlan_idx_lo = wcid ? to_wcid_lo(wcid->idx) : 0;
1743 		*wlan_idx_hi = wcid ? to_wcid_hi(wcid->idx) : 0;
1744 	} else {
1745 		*wlan_idx_lo = wcid ? wcid->idx : 0;
1746 	}
1747 }
1748 
1749 struct sk_buff *
1750 __mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif,
1751 				struct mt76_wcid *wcid, int len);
1752 static inline struct sk_buff *
1753 mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif,
1754 			      struct mt76_wcid *wcid)
1755 {
1756 	return __mt76_connac_mcu_alloc_sta_req(dev, mvif, wcid,
1757 					       MT76_CONNAC_STA_UPDATE_MAX_SIZE);
1758 }
1759 
1760 struct wtbl_req_hdr *
1761 mt76_connac_mcu_alloc_wtbl_req(struct mt76_dev *dev, struct mt76_wcid *wcid,
1762 			       int cmd, void *sta_wtbl, struct sk_buff **skb);
1763 struct tlv *mt76_connac_mcu_add_nested_tlv(struct sk_buff *skb, int tag,
1764 					   int len, void *sta_ntlv,
1765 					   void *sta_wtbl);
1766 static inline struct tlv *
1767 mt76_connac_mcu_add_tlv(struct sk_buff *skb, int tag, int len)
1768 {
1769 	return mt76_connac_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL);
1770 }
1771 
1772 int mt76_connac_mcu_set_channel_domain(struct mt76_phy *phy);
1773 int mt76_connac_mcu_set_vif_ps(struct mt76_dev *dev, struct ieee80211_vif *vif);
1774 void mt76_connac_mcu_sta_basic_tlv(struct sk_buff *skb,
1775 				   struct ieee80211_vif *vif,
1776 				   struct ieee80211_sta *sta, bool enable,
1777 				   bool newly);
1778 void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1779 				      struct ieee80211_vif *vif,
1780 				      struct ieee80211_sta *sta, void *sta_wtbl,
1781 				      void *wtbl_tlv);
1782 void mt76_connac_mcu_wtbl_hdr_trans_tlv(struct sk_buff *skb,
1783 					struct ieee80211_vif *vif,
1784 					struct mt76_wcid *wcid,
1785 					void *sta_wtbl, void *wtbl_tlv);
1786 int mt76_connac_mcu_sta_update_hdr_trans(struct mt76_dev *dev,
1787 					 struct ieee80211_vif *vif,
1788 					 struct mt76_wcid *wcid, int cmd);
1789 int mt76_connac_mcu_wtbl_update_hdr_trans(struct mt76_dev *dev,
1790 					  struct ieee80211_vif *vif,
1791 					  struct ieee80211_sta *sta);
1792 void mt76_connac_mcu_sta_tlv(struct mt76_phy *mphy, struct sk_buff *skb,
1793 			     struct ieee80211_sta *sta,
1794 			     struct ieee80211_vif *vif,
1795 			     u8 rcpi, u8 state);
1796 void mt76_connac_mcu_wtbl_ht_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1797 				 struct ieee80211_sta *sta, void *sta_wtbl,
1798 				 void *wtbl_tlv, bool ht_ldpc, bool vht_ldpc);
1799 void mt76_connac_mcu_wtbl_ba_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1800 				 struct ieee80211_ampdu_params *params,
1801 				 bool enable, bool tx, void *sta_wtbl,
1802 				 void *wtbl_tlv);
1803 void mt76_connac_mcu_sta_ba_tlv(struct sk_buff *skb,
1804 				struct ieee80211_ampdu_params *params,
1805 				bool enable, bool tx);
1806 int mt76_connac_mcu_uni_add_dev(struct mt76_phy *phy,
1807 				struct ieee80211_vif *vif,
1808 				struct mt76_wcid *wcid,
1809 				bool enable);
1810 int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
1811 			   struct ieee80211_ampdu_params *params,
1812 			   int cmd, bool enable, bool tx);
1813 int mt76_connac_mcu_uni_set_chctx(struct mt76_phy *phy,
1814 				  struct mt76_vif *vif,
1815 				  struct ieee80211_chanctx_conf *ctx);
1816 int mt76_connac_mcu_uni_add_bss(struct mt76_phy *phy,
1817 				struct ieee80211_vif *vif,
1818 				struct mt76_wcid *wcid,
1819 				bool enable,
1820 				struct ieee80211_chanctx_conf *ctx);
1821 int mt76_connac_mcu_sta_cmd(struct mt76_phy *phy,
1822 			    struct mt76_sta_cmd_info *info);
1823 void mt76_connac_mcu_beacon_loss_iter(void *priv, u8 *mac,
1824 				      struct ieee80211_vif *vif);
1825 int mt76_connac_mcu_set_rts_thresh(struct mt76_dev *dev, u32 val, u8 band);
1826 int mt76_connac_mcu_set_mac_enable(struct mt76_dev *dev, int band, bool enable,
1827 				   bool hdr_trans);
1828 int mt76_connac_mcu_init_download(struct mt76_dev *dev, u32 addr, u32 len,
1829 				  u32 mode);
1830 int mt76_connac_mcu_start_patch(struct mt76_dev *dev);
1831 int mt76_connac_mcu_patch_sem_ctrl(struct mt76_dev *dev, bool get);
1832 int mt76_connac_mcu_start_firmware(struct mt76_dev *dev, u32 addr, u32 option);
1833 int mt76_connac_mcu_get_nic_capability(struct mt76_phy *phy);
1834 
1835 int mt76_connac_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif,
1836 			    struct ieee80211_scan_request *scan_req);
1837 int mt76_connac_mcu_cancel_hw_scan(struct mt76_phy *phy,
1838 				   struct ieee80211_vif *vif);
1839 int mt76_connac_mcu_sched_scan_req(struct mt76_phy *phy,
1840 				   struct ieee80211_vif *vif,
1841 				   struct cfg80211_sched_scan_request *sreq);
1842 int mt76_connac_mcu_sched_scan_enable(struct mt76_phy *phy,
1843 				      struct ieee80211_vif *vif,
1844 				      bool enable);
1845 int mt76_connac_mcu_update_arp_filter(struct mt76_dev *dev,
1846 				      struct mt76_vif *vif,
1847 				      struct ieee80211_bss_conf *info);
1848 int mt76_connac_mcu_update_gtk_rekey(struct ieee80211_hw *hw,
1849 				     struct ieee80211_vif *vif,
1850 				     struct cfg80211_gtk_rekey_data *key);
1851 int mt76_connac_mcu_set_hif_suspend(struct mt76_dev *dev, bool suspend);
1852 void mt76_connac_mcu_set_suspend_iter(void *priv, u8 *mac,
1853 				      struct ieee80211_vif *vif);
1854 int mt76_connac_sta_state_dp(struct mt76_dev *dev,
1855 			     enum ieee80211_sta_state old_state,
1856 			     enum ieee80211_sta_state new_state);
1857 int mt76_connac_mcu_chip_config(struct mt76_dev *dev);
1858 int mt76_connac_mcu_set_deep_sleep(struct mt76_dev *dev, bool enable);
1859 void mt76_connac_mcu_coredump_event(struct mt76_dev *dev, struct sk_buff *skb,
1860 				    struct mt76_connac_coredump *coredump);
1861 int mt76_connac_mcu_set_rate_txpower(struct mt76_phy *phy);
1862 int mt76_connac_mcu_set_p2p_oppps(struct ieee80211_hw *hw,
1863 				  struct ieee80211_vif *vif);
1864 u32 mt76_connac_mcu_reg_rr(struct mt76_dev *dev, u32 offset);
1865 void mt76_connac_mcu_reg_wr(struct mt76_dev *dev, u32 offset, u32 val);
1866 
1867 const struct ieee80211_sta_he_cap *
1868 mt76_connac_get_he_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif);
1869 u8 mt76_connac_get_phy_mode(struct mt76_phy *phy, struct ieee80211_vif *vif,
1870 			    enum nl80211_band band, struct ieee80211_sta *sta);
1871 
1872 int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
1873 			    struct mt76_connac_sta_key_conf *sta_key_conf,
1874 			    struct ieee80211_key_conf *key, int mcu_cmd,
1875 			    struct mt76_wcid *wcid, enum set_key_cmd cmd);
1876 
1877 void mt76_connac_mcu_bss_ext_tlv(struct sk_buff *skb, struct mt76_vif *mvif);
1878 void mt76_connac_mcu_bss_omac_tlv(struct sk_buff *skb,
1879 				  struct ieee80211_vif *vif);
1880 int mt76_connac_mcu_bss_basic_tlv(struct sk_buff *skb,
1881 				  struct ieee80211_vif *vif,
1882 				  struct ieee80211_sta *sta,
1883 				  struct mt76_phy *phy, u16 wlan_idx,
1884 				  bool enable);
1885 void mt76_connac_mcu_sta_uapsd(struct sk_buff *skb, struct ieee80211_vif *vif,
1886 			       struct ieee80211_sta *sta);
1887 void mt76_connac_mcu_wtbl_smps_tlv(struct sk_buff *skb,
1888 				   struct ieee80211_sta *sta,
1889 				   void *sta_wtbl, void *wtbl_tlv);
1890 int mt76_connac_mcu_set_pm(struct mt76_dev *dev, int band, int enter);
1891 int mt76_connac_mcu_restart(struct mt76_dev *dev);
1892 int mt76_connac_mcu_rdd_cmd(struct mt76_dev *dev, int cmd, u8 index,
1893 			    u8 rx_sel, u8 val);
1894 int mt76_connac_mcu_sta_wed_update(struct mt76_dev *dev, struct sk_buff *skb);
1895 int mt76_connac2_load_ram(struct mt76_dev *dev, const char *fw_wm,
1896 			  const char *fw_wa);
1897 int mt76_connac2_load_patch(struct mt76_dev *dev, const char *fw_name);
1898 int mt76_connac2_mcu_fill_message(struct mt76_dev *mdev, struct sk_buff *skb,
1899 				  int cmd, int *wait_seq);
1900 #endif /* __MT76_CONNAC_MCU_H */
1901