1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT76_CONNAC_MCU_H 5 #define __MT76_CONNAC_MCU_H 6 7 #include "mt76_connac.h" 8 9 #define FW_FEATURE_SET_ENCRYPT BIT(0) 10 #define FW_FEATURE_SET_KEY_IDX GENMASK(2, 1) 11 #define FW_FEATURE_ENCRY_MODE BIT(4) 12 #define FW_FEATURE_OVERRIDE_ADDR BIT(5) 13 14 #define DL_MODE_ENCRYPT BIT(0) 15 #define DL_MODE_KEY_IDX GENMASK(2, 1) 16 #define DL_MODE_RESET_SEC_IV BIT(3) 17 #define DL_MODE_WORKING_PDA_CR4 BIT(4) 18 #define DL_MODE_VALID_RAM_ENTRY BIT(5) 19 #define DL_CONFIG_ENCRY_MODE_SEL BIT(6) 20 #define DL_MODE_NEED_RSP BIT(31) 21 22 #define FW_START_OVERRIDE BIT(0) 23 #define FW_START_WORKING_PDA_CR4 BIT(2) 24 25 #define PATCH_SEC_NOT_SUPPORT GENMASK(31, 0) 26 #define PATCH_SEC_TYPE_MASK GENMASK(15, 0) 27 #define PATCH_SEC_TYPE_INFO 0x2 28 29 struct mt76_connac2_patch_hdr { 30 char build_date[16]; 31 char platform[4]; 32 __be32 hw_sw_ver; 33 __be32 patch_ver; 34 __be16 checksum; 35 u16 rsv; 36 struct { 37 __be32 patch_ver; 38 __be32 subsys; 39 __be32 feature; 40 __be32 n_region; 41 __be32 crc; 42 u32 rsv[11]; 43 } desc; 44 } __packed; 45 46 struct mt76_connac2_patch_sec { 47 __be32 type; 48 __be32 offs; 49 __be32 size; 50 union { 51 __be32 spec[13]; 52 struct { 53 __be32 addr; 54 __be32 len; 55 __be32 sec_key_idx; 56 __be32 align_len; 57 u32 rsv[9]; 58 } info; 59 }; 60 } __packed; 61 62 struct mt76_connac2_fw_trailer { 63 u8 chip_id; 64 u8 eco_code; 65 u8 n_region; 66 u8 format_ver; 67 u8 format_flag; 68 u8 rsv[2]; 69 char fw_ver[10]; 70 char build_date[15]; 71 __le32 crc; 72 } __packed; 73 74 struct mt76_connac2_fw_region { 75 __le32 decomp_crc; 76 __le32 decomp_len; 77 __le32 decomp_blk_sz; 78 u8 rsv[4]; 79 __le32 addr; 80 __le32 len; 81 u8 feature_set; 82 u8 rsv1[15]; 83 } __packed; 84 85 struct tlv { 86 __le16 tag; 87 __le16 len; 88 } __packed; 89 90 struct bss_info_omac { 91 __le16 tag; 92 __le16 len; 93 u8 hw_bss_idx; 94 u8 omac_idx; 95 u8 band_idx; 96 u8 rsv0; 97 __le32 conn_type; 98 u32 rsv1; 99 } __packed; 100 101 struct bss_info_basic { 102 __le16 tag; 103 __le16 len; 104 __le32 network_type; 105 u8 active; 106 u8 rsv0; 107 __le16 bcn_interval; 108 u8 bssid[ETH_ALEN]; 109 u8 wmm_idx; 110 u8 dtim_period; 111 u8 bmc_wcid_lo; 112 u8 cipher; 113 u8 phy_mode; 114 u8 max_bssid; /* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */ 115 u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */ 116 u8 bmc_wcid_hi; /* high Byte and version */ 117 u8 rsv[2]; 118 } __packed; 119 120 struct bss_info_rf_ch { 121 __le16 tag; 122 __le16 len; 123 u8 pri_ch; 124 u8 center_ch0; 125 u8 center_ch1; 126 u8 bw; 127 u8 he_ru26_block; /* 1: don't send HETB in RU26, 0: allow */ 128 u8 he_all_disable; /* 1: disallow all HETB, 0: allow */ 129 u8 rsv[2]; 130 } __packed; 131 132 struct bss_info_ext_bss { 133 __le16 tag; 134 __le16 len; 135 __le32 mbss_tsf_offset; /* in unit of us */ 136 u8 rsv[8]; 137 } __packed; 138 139 enum { 140 BSS_INFO_OMAC, 141 BSS_INFO_BASIC, 142 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */ 143 BSS_INFO_PM, /* sta only */ 144 BSS_INFO_UAPSD, /* sta only */ 145 BSS_INFO_ROAM_DETECT, /* obsoleted */ 146 BSS_INFO_LQ_RM, /* obsoleted */ 147 BSS_INFO_EXT_BSS, 148 BSS_INFO_BMC_RATE, /* for bmc rate control in CR4 */ 149 BSS_INFO_SYNC_MODE, /* obsoleted */ 150 BSS_INFO_RA, 151 BSS_INFO_HW_AMSDU, 152 BSS_INFO_BSS_COLOR, 153 BSS_INFO_HE_BASIC, 154 BSS_INFO_PROTECT_INFO, 155 BSS_INFO_OFFLOAD, 156 BSS_INFO_11V_MBSSID, 157 BSS_INFO_MAX_NUM 158 }; 159 160 /* sta_rec */ 161 162 struct sta_ntlv_hdr { 163 u8 rsv[2]; 164 __le16 tlv_num; 165 } __packed; 166 167 struct sta_req_hdr { 168 u8 bss_idx; 169 u8 wlan_idx_lo; 170 __le16 tlv_num; 171 u8 is_tlv_append; 172 u8 muar_idx; 173 u8 wlan_idx_hi; 174 u8 rsv; 175 } __packed; 176 177 struct sta_rec_basic { 178 __le16 tag; 179 __le16 len; 180 __le32 conn_type; 181 u8 conn_state; 182 u8 qos; 183 __le16 aid; 184 u8 peer_addr[ETH_ALEN]; 185 #define EXTRA_INFO_VER BIT(0) 186 #define EXTRA_INFO_NEW BIT(1) 187 __le16 extra_info; 188 } __packed; 189 190 struct sta_rec_ht { 191 __le16 tag; 192 __le16 len; 193 __le16 ht_cap; 194 u16 rsv; 195 } __packed; 196 197 struct sta_rec_vht { 198 __le16 tag; 199 __le16 len; 200 __le32 vht_cap; 201 __le16 vht_rx_mcs_map; 202 __le16 vht_tx_mcs_map; 203 /* mt7915 - mt7921 */ 204 u8 rts_bw_sig; 205 u8 rsv[3]; 206 } __packed; 207 208 struct sta_rec_uapsd { 209 __le16 tag; 210 __le16 len; 211 u8 dac_map; 212 u8 tac_map; 213 u8 max_sp; 214 u8 rsv0; 215 __le16 listen_interval; 216 u8 rsv1[2]; 217 } __packed; 218 219 struct sta_rec_ba { 220 __le16 tag; 221 __le16 len; 222 u8 tid; 223 u8 ba_type; 224 u8 amsdu; 225 u8 ba_en; 226 __le16 ssn; 227 __le16 winsize; 228 } __packed; 229 230 struct sta_rec_he { 231 __le16 tag; 232 __le16 len; 233 234 __le32 he_cap; 235 236 u8 t_frame_dur; 237 u8 max_ampdu_exp; 238 u8 bw_set; 239 u8 device_class; 240 u8 dcm_tx_mode; 241 u8 dcm_tx_max_nss; 242 u8 dcm_rx_mode; 243 u8 dcm_rx_max_nss; 244 u8 dcm_max_ru; 245 u8 punc_pream_rx; 246 u8 pkt_ext; 247 u8 rsv1; 248 249 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 250 251 u8 rsv2[2]; 252 } __packed; 253 254 struct sta_rec_amsdu { 255 __le16 tag; 256 __le16 len; 257 u8 max_amsdu_num; 258 u8 max_mpdu_size; 259 u8 amsdu_en; 260 u8 rsv; 261 } __packed; 262 263 struct sta_rec_state { 264 __le16 tag; 265 __le16 len; 266 __le32 flags; 267 u8 state; 268 u8 vht_opmode; 269 u8 action; 270 u8 rsv[1]; 271 } __packed; 272 273 #define RA_LEGACY_OFDM GENMASK(13, 6) 274 #define RA_LEGACY_CCK GENMASK(3, 0) 275 #define HT_MCS_MASK_NUM 10 276 struct sta_rec_ra_info { 277 __le16 tag; 278 __le16 len; 279 __le16 legacy; 280 u8 rx_mcs_bitmask[HT_MCS_MASK_NUM]; 281 } __packed; 282 283 struct sta_rec_phy { 284 __le16 tag; 285 __le16 len; 286 __le16 basic_rate; 287 u8 phy_type; 288 u8 ampdu; 289 u8 rts_policy; 290 u8 rcpi; 291 u8 rsv[2]; 292 } __packed; 293 294 struct sta_rec_he_6g_capa { 295 __le16 tag; 296 __le16 len; 297 __le16 capa; 298 u8 rsv[2]; 299 } __packed; 300 301 struct sec_key { 302 u8 cipher_id; 303 u8 cipher_len; 304 u8 key_id; 305 u8 key_len; 306 u8 key[32]; 307 } __packed; 308 309 struct sta_rec_sec { 310 __le16 tag; 311 __le16 len; 312 u8 add; 313 u8 n_cipher; 314 u8 rsv[2]; 315 316 struct sec_key key[2]; 317 } __packed; 318 319 struct sta_rec_bf { 320 __le16 tag; 321 __le16 len; 322 323 __le16 pfmu; /* 0xffff: no access right for PFMU */ 324 bool su_mu; /* 0: SU, 1: MU */ 325 u8 bf_cap; /* 0: iBF, 1: eBF */ 326 u8 sounding_phy; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT */ 327 u8 ndpa_rate; 328 u8 ndp_rate; 329 u8 rept_poll_rate; 330 u8 tx_mode; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */ 331 u8 ncol; 332 u8 nrow; 333 u8 bw; /* 0: 20M, 1: 40M, 2: 80M, 3: 160M */ 334 335 u8 mem_total; 336 u8 mem_20m; 337 struct { 338 u8 row; 339 u8 col: 6, row_msb: 2; 340 } mem[4]; 341 342 __le16 smart_ant; 343 u8 se_idx; 344 u8 auto_sounding; /* b7: low traffic indicator 345 * b6: Stop sounding for this entry 346 * b5 ~ b0: postpone sounding 347 */ 348 u8 ibf_timeout; 349 u8 ibf_dbw; 350 u8 ibf_ncol; 351 u8 ibf_nrow; 352 u8 nrow_bw160; 353 u8 ncol_bw160; 354 u8 ru_start_idx; 355 u8 ru_end_idx; 356 357 bool trigger_su; 358 bool trigger_mu; 359 bool ng16_su; 360 bool ng16_mu; 361 bool codebook42_su; 362 bool codebook75_mu; 363 364 u8 he_ltf; 365 u8 rsv[3]; 366 } __packed; 367 368 struct sta_rec_bfee { 369 __le16 tag; 370 __le16 len; 371 bool fb_identity_matrix; /* 1: feedback identity matrix */ 372 bool ignore_feedback; /* 1: ignore */ 373 u8 rsv[2]; 374 } __packed; 375 376 struct sta_rec_muru { 377 __le16 tag; 378 __le16 len; 379 380 struct { 381 bool ofdma_dl_en; 382 bool ofdma_ul_en; 383 bool mimo_dl_en; 384 bool mimo_ul_en; 385 u8 rsv[4]; 386 } cfg; 387 388 struct { 389 u8 punc_pream_rx; 390 bool he_20m_in_40m_2g; 391 bool he_20m_in_160m; 392 bool he_80m_in_160m; 393 bool lt16_sigb; 394 bool rx_su_comp_sigb; 395 bool rx_su_non_comp_sigb; 396 u8 rsv; 397 } ofdma_dl; 398 399 struct { 400 u8 t_frame_dur; 401 u8 mu_cascading; 402 u8 uo_ra; 403 u8 he_2x996_tone; 404 u8 rx_t_frame_11ac; 405 u8 rsv[3]; 406 } ofdma_ul; 407 408 struct { 409 bool vht_mu_bfee; 410 bool partial_bw_dl_mimo; 411 u8 rsv[2]; 412 } mimo_dl; 413 414 struct { 415 bool full_ul_mimo; 416 bool partial_ul_mimo; 417 u8 rsv[2]; 418 } mimo_ul; 419 } __packed; 420 421 struct sta_phy { 422 u8 type; 423 u8 flag; 424 u8 stbc; 425 u8 sgi; 426 u8 bw; 427 u8 ldpc; 428 u8 mcs; 429 u8 nss; 430 u8 he_ltf; 431 }; 432 433 struct sta_rec_ra { 434 __le16 tag; 435 __le16 len; 436 437 u8 valid; 438 u8 auto_rate; 439 u8 phy_mode; 440 u8 channel; 441 u8 bw; 442 u8 disable_cck; 443 u8 ht_mcs32; 444 u8 ht_gf; 445 u8 ht_mcs[4]; 446 u8 mmps_mode; 447 u8 gband_256; 448 u8 af; 449 u8 auth_wapi_mode; 450 u8 rate_len; 451 452 u8 supp_mode; 453 u8 supp_cck_rate; 454 u8 supp_ofdm_rate; 455 __le32 supp_ht_mcs; 456 __le16 supp_vht_mcs[4]; 457 458 u8 op_mode; 459 u8 op_vht_chan_width; 460 u8 op_vht_rx_nss; 461 u8 op_vht_rx_nss_type; 462 463 __le32 sta_cap; 464 465 struct sta_phy phy; 466 } __packed; 467 468 struct sta_rec_ra_fixed { 469 __le16 tag; 470 __le16 len; 471 472 __le32 field; 473 u8 op_mode; 474 u8 op_vht_chan_width; 475 u8 op_vht_rx_nss; 476 u8 op_vht_rx_nss_type; 477 478 struct sta_phy phy; 479 480 u8 spe_en; 481 u8 short_preamble; 482 u8 is_5g; 483 u8 mmps_mode; 484 } __packed; 485 486 /* wtbl_rec */ 487 488 struct wtbl_req_hdr { 489 u8 wlan_idx_lo; 490 u8 operation; 491 __le16 tlv_num; 492 u8 wlan_idx_hi; 493 u8 rsv[3]; 494 } __packed; 495 496 struct wtbl_generic { 497 __le16 tag; 498 __le16 len; 499 u8 peer_addr[ETH_ALEN]; 500 u8 muar_idx; 501 u8 skip_tx; 502 u8 cf_ack; 503 u8 qos; 504 u8 mesh; 505 u8 adm; 506 __le16 partial_aid; 507 u8 baf_en; 508 u8 aad_om; 509 } __packed; 510 511 struct wtbl_rx { 512 __le16 tag; 513 __le16 len; 514 u8 rcid; 515 u8 rca1; 516 u8 rca2; 517 u8 rv; 518 u8 rsv[4]; 519 } __packed; 520 521 struct wtbl_ht { 522 __le16 tag; 523 __le16 len; 524 u8 ht; 525 u8 ldpc; 526 u8 af; 527 u8 mm; 528 u8 rsv[4]; 529 } __packed; 530 531 struct wtbl_vht { 532 __le16 tag; 533 __le16 len; 534 u8 ldpc; 535 u8 dyn_bw; 536 u8 vht; 537 u8 txop_ps; 538 u8 rsv[4]; 539 } __packed; 540 541 struct wtbl_tx_ps { 542 __le16 tag; 543 __le16 len; 544 u8 txps; 545 u8 rsv[3]; 546 } __packed; 547 548 struct wtbl_hdr_trans { 549 __le16 tag; 550 __le16 len; 551 u8 to_ds; 552 u8 from_ds; 553 u8 no_rx_trans; 554 u8 rsv; 555 } __packed; 556 557 struct wtbl_ba { 558 __le16 tag; 559 __le16 len; 560 /* common */ 561 u8 tid; 562 u8 ba_type; 563 u8 rsv0[2]; 564 /* originator only */ 565 __le16 sn; 566 u8 ba_en; 567 u8 ba_winsize_idx; 568 /* originator & recipient */ 569 __le16 ba_winsize; 570 /* recipient only */ 571 u8 peer_addr[ETH_ALEN]; 572 u8 rst_ba_tid; 573 u8 rst_ba_sel; 574 u8 rst_ba_sb; 575 u8 band_idx; 576 u8 rsv1[4]; 577 } __packed; 578 579 struct wtbl_smps { 580 __le16 tag; 581 __le16 len; 582 u8 smps; 583 u8 rsv[3]; 584 } __packed; 585 586 /* mt7615 only */ 587 588 struct wtbl_bf { 589 __le16 tag; 590 __le16 len; 591 u8 ibf; 592 u8 ebf; 593 u8 ibf_vht; 594 u8 ebf_vht; 595 u8 gid; 596 u8 pfmu_idx; 597 u8 rsv[2]; 598 } __packed; 599 600 struct wtbl_pn { 601 __le16 tag; 602 __le16 len; 603 u8 pn[6]; 604 u8 rsv[2]; 605 } __packed; 606 607 struct wtbl_spe { 608 __le16 tag; 609 __le16 len; 610 u8 spe_idx; 611 u8 rsv[3]; 612 } __packed; 613 614 struct wtbl_raw { 615 __le16 tag; 616 __le16 len; 617 u8 wtbl_idx; 618 u8 dw; 619 u8 rsv[2]; 620 __le32 msk; 621 __le32 val; 622 } __packed; 623 624 #define MT76_CONNAC_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \ 625 sizeof(struct wtbl_generic) + \ 626 sizeof(struct wtbl_rx) + \ 627 sizeof(struct wtbl_ht) + \ 628 sizeof(struct wtbl_vht) + \ 629 sizeof(struct wtbl_tx_ps) + \ 630 sizeof(struct wtbl_hdr_trans) +\ 631 sizeof(struct wtbl_ba) + \ 632 sizeof(struct wtbl_bf) + \ 633 sizeof(struct wtbl_smps) + \ 634 sizeof(struct wtbl_pn) + \ 635 sizeof(struct wtbl_spe)) 636 637 #define MT76_CONNAC_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 638 sizeof(struct sta_rec_basic) + \ 639 sizeof(struct sta_rec_bf) + \ 640 sizeof(struct sta_rec_ht) + \ 641 sizeof(struct sta_rec_he) + \ 642 sizeof(struct sta_rec_ba) + \ 643 sizeof(struct sta_rec_vht) + \ 644 sizeof(struct sta_rec_uapsd) + \ 645 sizeof(struct sta_rec_amsdu) + \ 646 sizeof(struct sta_rec_muru) + \ 647 sizeof(struct sta_rec_bfee) + \ 648 sizeof(struct sta_rec_ra) + \ 649 sizeof(struct sta_rec_sec) + \ 650 sizeof(struct sta_rec_ra_fixed) + \ 651 sizeof(struct sta_rec_he_6g_capa) + \ 652 sizeof(struct tlv) + \ 653 MT76_CONNAC_WTBL_UPDATE_MAX_SIZE) 654 655 enum { 656 STA_REC_BASIC, 657 STA_REC_RA, 658 STA_REC_RA_CMM_INFO, 659 STA_REC_RA_UPDATE, 660 STA_REC_BF, 661 STA_REC_AMSDU, 662 STA_REC_BA, 663 STA_REC_STATE, 664 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */ 665 STA_REC_HT, 666 STA_REC_VHT, 667 STA_REC_APPS, 668 STA_REC_KEY, 669 STA_REC_WTBL, 670 STA_REC_HE, 671 STA_REC_HW_AMSDU, 672 STA_REC_WTBL_AADOM, 673 STA_REC_KEY_V2, 674 STA_REC_MURU, 675 STA_REC_MUEDCA, 676 STA_REC_BFEE, 677 STA_REC_PHY = 0x15, 678 STA_REC_HE_6G = 0x17, 679 STA_REC_MAX_NUM 680 }; 681 682 enum { 683 WTBL_GENERIC, 684 WTBL_RX, 685 WTBL_HT, 686 WTBL_VHT, 687 WTBL_PEER_PS, /* not used */ 688 WTBL_TX_PS, 689 WTBL_HDR_TRANS, 690 WTBL_SEC_KEY, 691 WTBL_BA, 692 WTBL_RDG, /* obsoleted */ 693 WTBL_PROTECT, /* not used */ 694 WTBL_CLEAR, /* not used */ 695 WTBL_BF, 696 WTBL_SMPS, 697 WTBL_RAW_DATA, /* debug only */ 698 WTBL_PN, 699 WTBL_SPE, 700 WTBL_MAX_NUM 701 }; 702 703 #define STA_TYPE_STA BIT(0) 704 #define STA_TYPE_AP BIT(1) 705 #define STA_TYPE_ADHOC BIT(2) 706 #define STA_TYPE_WDS BIT(4) 707 #define STA_TYPE_BC BIT(5) 708 709 #define NETWORK_INFRA BIT(16) 710 #define NETWORK_P2P BIT(17) 711 #define NETWORK_IBSS BIT(18) 712 #define NETWORK_WDS BIT(21) 713 714 #define SCAN_FUNC_RANDOM_MAC BIT(0) 715 #define SCAN_FUNC_SPLIT_SCAN BIT(5) 716 717 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA) 718 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA) 719 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P) 720 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P) 721 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS) 722 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS) 723 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA) 724 725 #define CONN_STATE_DISCONNECT 0 726 #define CONN_STATE_CONNECT 1 727 #define CONN_STATE_PORT_SECURE 2 728 729 /* HE MAC */ 730 #define STA_REC_HE_CAP_HTC BIT(0) 731 #define STA_REC_HE_CAP_BQR BIT(1) 732 #define STA_REC_HE_CAP_BSR BIT(2) 733 #define STA_REC_HE_CAP_OM BIT(3) 734 #define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4) 735 /* HE PHY */ 736 #define STA_REC_HE_CAP_DUAL_BAND BIT(5) 737 #define STA_REC_HE_CAP_LDPC BIT(6) 738 #define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7) 739 #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8) 740 /* STBC */ 741 #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9) 742 #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10) 743 #define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11) 744 #define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12) 745 /* GI */ 746 #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13) 747 #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14) 748 #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15) 749 #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16) 750 #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17) 751 /* 242 TONE */ 752 #define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18) 753 #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19) 754 #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20) 755 756 #define PHY_MODE_A BIT(0) 757 #define PHY_MODE_B BIT(1) 758 #define PHY_MODE_G BIT(2) 759 #define PHY_MODE_GN BIT(3) 760 #define PHY_MODE_AN BIT(4) 761 #define PHY_MODE_AC BIT(5) 762 #define PHY_MODE_AX_24G BIT(6) 763 #define PHY_MODE_AX_5G BIT(7) 764 765 #define PHY_MODE_AX_6G BIT(0) /* phymode_ext */ 766 767 #define MODE_CCK BIT(0) 768 #define MODE_OFDM BIT(1) 769 #define MODE_HT BIT(2) 770 #define MODE_VHT BIT(3) 771 #define MODE_HE BIT(4) 772 773 #define STA_CAP_WMM BIT(0) 774 #define STA_CAP_SGI_20 BIT(4) 775 #define STA_CAP_SGI_40 BIT(5) 776 #define STA_CAP_TX_STBC BIT(6) 777 #define STA_CAP_RX_STBC BIT(7) 778 #define STA_CAP_VHT_SGI_80 BIT(16) 779 #define STA_CAP_VHT_SGI_160 BIT(17) 780 #define STA_CAP_VHT_TX_STBC BIT(18) 781 #define STA_CAP_VHT_RX_STBC BIT(19) 782 #define STA_CAP_VHT_LDPC BIT(23) 783 #define STA_CAP_LDPC BIT(24) 784 #define STA_CAP_HT BIT(26) 785 #define STA_CAP_VHT BIT(27) 786 #define STA_CAP_HE BIT(28) 787 788 enum { 789 PHY_TYPE_HR_DSSS_INDEX = 0, 790 PHY_TYPE_ERP_INDEX, 791 PHY_TYPE_ERP_P2P_INDEX, 792 PHY_TYPE_OFDM_INDEX, 793 PHY_TYPE_HT_INDEX, 794 PHY_TYPE_VHT_INDEX, 795 PHY_TYPE_HE_INDEX, 796 PHY_TYPE_INDEX_NUM 797 }; 798 799 #define PHY_TYPE_BIT_HR_DSSS BIT(PHY_TYPE_HR_DSSS_INDEX) 800 #define PHY_TYPE_BIT_ERP BIT(PHY_TYPE_ERP_INDEX) 801 #define PHY_TYPE_BIT_OFDM BIT(PHY_TYPE_OFDM_INDEX) 802 #define PHY_TYPE_BIT_HT BIT(PHY_TYPE_HT_INDEX) 803 #define PHY_TYPE_BIT_VHT BIT(PHY_TYPE_VHT_INDEX) 804 #define PHY_TYPE_BIT_HE BIT(PHY_TYPE_HE_INDEX) 805 806 #define MT_WTBL_RATE_TX_MODE GENMASK(9, 6) 807 #define MT_WTBL_RATE_MCS GENMASK(5, 0) 808 #define MT_WTBL_RATE_NSS GENMASK(12, 10) 809 #define MT_WTBL_RATE_HE_GI GENMASK(7, 4) 810 #define MT_WTBL_RATE_GI GENMASK(3, 0) 811 812 #define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5) 813 #define MT_WTBL_W5_SHORT_GI_20 BIT(8) 814 #define MT_WTBL_W5_SHORT_GI_40 BIT(9) 815 #define MT_WTBL_W5_SHORT_GI_80 BIT(10) 816 #define MT_WTBL_W5_SHORT_GI_160 BIT(11) 817 #define MT_WTBL_W5_BW_CAP GENMASK(13, 12) 818 #define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23) 819 #define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26) 820 #define MT_WTBL_W5_RATE_IDX GENMASK(31, 29) 821 822 enum { 823 WTBL_RESET_AND_SET = 1, 824 WTBL_SET, 825 WTBL_QUERY, 826 WTBL_RESET_ALL 827 }; 828 829 enum { 830 MT_BA_TYPE_INVALID, 831 MT_BA_TYPE_ORIGINATOR, 832 MT_BA_TYPE_RECIPIENT 833 }; 834 835 enum { 836 RST_BA_MAC_TID_MATCH, 837 RST_BA_MAC_MATCH, 838 RST_BA_NO_MATCH 839 }; 840 841 enum { 842 DEV_INFO_ACTIVE, 843 DEV_INFO_MAX_NUM 844 }; 845 846 /* event table */ 847 enum { 848 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01, 849 MCU_EVENT_FW_START = 0x01, 850 MCU_EVENT_GENERIC = 0x01, 851 MCU_EVENT_ACCESS_REG = 0x02, 852 MCU_EVENT_MT_PATCH_SEM = 0x04, 853 MCU_EVENT_REG_ACCESS = 0x05, 854 MCU_EVENT_LP_INFO = 0x07, 855 MCU_EVENT_SCAN_DONE = 0x0d, 856 MCU_EVENT_TX_DONE = 0x0f, 857 MCU_EVENT_ROC = 0x10, 858 MCU_EVENT_BSS_ABSENCE = 0x11, 859 MCU_EVENT_BSS_BEACON_LOSS = 0x13, 860 MCU_EVENT_CH_PRIVILEGE = 0x18, 861 MCU_EVENT_SCHED_SCAN_DONE = 0x23, 862 MCU_EVENT_DBG_MSG = 0x27, 863 MCU_EVENT_TXPWR = 0xd0, 864 MCU_EVENT_EXT = 0xed, 865 MCU_EVENT_RESTART_DL = 0xef, 866 MCU_EVENT_COREDUMP = 0xf0, 867 }; 868 869 /* ext event table */ 870 enum { 871 MCU_EXT_EVENT_PS_SYNC = 0x5, 872 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13, 873 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22, 874 MCU_EXT_EVENT_ASSERT_DUMP = 0x23, 875 MCU_EXT_EVENT_RDD_REPORT = 0x3a, 876 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f, 877 MCU_EXT_EVENT_BCC_NOTIFY = 0x75, 878 MCU_EXT_EVENT_MURU_CTRL = 0x9f, 879 }; 880 881 enum { 882 MCU_Q_QUERY, 883 MCU_Q_SET, 884 MCU_Q_RESERVED, 885 MCU_Q_NA 886 }; 887 888 enum { 889 MCU_S2D_H2N, 890 MCU_S2D_C2N, 891 MCU_S2D_H2C, 892 MCU_S2D_H2CN 893 }; 894 895 enum { 896 PATCH_NOT_DL_SEM_FAIL, 897 PATCH_IS_DL, 898 PATCH_NOT_DL_SEM_SUCCESS, 899 PATCH_REL_SEM_SUCCESS 900 }; 901 902 enum { 903 FW_STATE_INITIAL, 904 FW_STATE_FW_DOWNLOAD, 905 FW_STATE_NORMAL_OPERATION, 906 FW_STATE_NORMAL_TRX, 907 FW_STATE_RDY = 7 908 }; 909 910 enum { 911 CH_SWITCH_NORMAL = 0, 912 CH_SWITCH_SCAN = 3, 913 CH_SWITCH_MCC = 4, 914 CH_SWITCH_DFS = 5, 915 CH_SWITCH_BACKGROUND_SCAN_START = 6, 916 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7, 917 CH_SWITCH_BACKGROUND_SCAN_STOP = 8, 918 CH_SWITCH_SCAN_BYPASS_DPD = 9 919 }; 920 921 enum { 922 THERMAL_SENSOR_TEMP_QUERY, 923 THERMAL_SENSOR_MANUAL_CTRL, 924 THERMAL_SENSOR_INFO_QUERY, 925 THERMAL_SENSOR_TASK_CTRL, 926 }; 927 928 enum mcu_cipher_type { 929 MCU_CIPHER_NONE = 0, 930 MCU_CIPHER_WEP40, 931 MCU_CIPHER_WEP104, 932 MCU_CIPHER_WEP128, 933 MCU_CIPHER_TKIP, 934 MCU_CIPHER_AES_CCMP, 935 MCU_CIPHER_CCMP_256, 936 MCU_CIPHER_GCMP, 937 MCU_CIPHER_GCMP_256, 938 MCU_CIPHER_WAPI, 939 MCU_CIPHER_BIP_CMAC_128, 940 }; 941 942 enum { 943 EE_MODE_EFUSE, 944 EE_MODE_BUFFER, 945 }; 946 947 enum { 948 EE_FORMAT_BIN, 949 EE_FORMAT_WHOLE, 950 EE_FORMAT_MULTIPLE, 951 }; 952 953 enum { 954 MCU_PHY_STATE_TX_RATE, 955 MCU_PHY_STATE_RX_RATE, 956 MCU_PHY_STATE_RSSI, 957 MCU_PHY_STATE_CONTENTION_RX_RATE, 958 MCU_PHY_STATE_OFDMLQ_CNINFO, 959 }; 960 961 #define MCU_CMD_ACK BIT(0) 962 #define MCU_CMD_UNI BIT(1) 963 #define MCU_CMD_QUERY BIT(2) 964 965 #define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | \ 966 MCU_CMD_QUERY) 967 968 #define __MCU_CMD_FIELD_ID GENMASK(7, 0) 969 #define __MCU_CMD_FIELD_EXT_ID GENMASK(15, 8) 970 #define __MCU_CMD_FIELD_QUERY BIT(16) 971 #define __MCU_CMD_FIELD_UNI BIT(17) 972 #define __MCU_CMD_FIELD_CE BIT(18) 973 #define __MCU_CMD_FIELD_WA BIT(19) 974 975 #define MCU_CMD(_t) FIELD_PREP(__MCU_CMD_FIELD_ID, \ 976 MCU_CMD_##_t) 977 #define MCU_EXT_CMD(_t) (MCU_CMD(EXT_CID) | \ 978 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ 979 MCU_EXT_CMD_##_t)) 980 #define MCU_EXT_QUERY(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_QUERY) 981 #define MCU_UNI_CMD(_t) (__MCU_CMD_FIELD_UNI | \ 982 FIELD_PREP(__MCU_CMD_FIELD_ID, \ 983 MCU_UNI_CMD_##_t)) 984 #define MCU_CE_CMD(_t) (__MCU_CMD_FIELD_CE | \ 985 FIELD_PREP(__MCU_CMD_FIELD_ID, \ 986 MCU_CE_CMD_##_t)) 987 #define MCU_CE_QUERY(_t) (MCU_CE_CMD(_t) | __MCU_CMD_FIELD_QUERY) 988 989 #define MCU_WA_CMD(_t) (MCU_CMD(_t) | __MCU_CMD_FIELD_WA) 990 #define MCU_WA_EXT_CMD(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_WA) 991 #define MCU_WA_PARAM_CMD(_t) (MCU_WA_CMD(WA_PARAM) | \ 992 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ 993 MCU_WA_PARAM_CMD_##_t)) 994 995 enum { 996 MCU_EXT_CMD_EFUSE_ACCESS = 0x01, 997 MCU_EXT_CMD_RF_REG_ACCESS = 0x02, 998 MCU_EXT_CMD_RF_TEST = 0x04, 999 MCU_EXT_CMD_PM_STATE_CTRL = 0x07, 1000 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08, 1001 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11, 1002 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13, 1003 MCU_EXT_CMD_TXBF_ACTION = 0x1e, 1004 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21, 1005 MCU_EXT_CMD_THERMAL_PROT = 0x23, 1006 MCU_EXT_CMD_STA_REC_UPDATE = 0x25, 1007 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26, 1008 MCU_EXT_CMD_EDCA_UPDATE = 0x27, 1009 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A, 1010 MCU_EXT_CMD_THERMAL_CTRL = 0x2c, 1011 MCU_EXT_CMD_WTBL_UPDATE = 0x32, 1012 MCU_EXT_CMD_SET_DRR_CTRL = 0x36, 1013 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a, 1014 MCU_EXT_CMD_ATE_CTRL = 0x3d, 1015 MCU_EXT_CMD_PROTECT_CTRL = 0x3e, 1016 MCU_EXT_CMD_DBDC_CTRL = 0x45, 1017 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46, 1018 MCU_EXT_CMD_RX_HDR_TRANS = 0x47, 1019 MCU_EXT_CMD_MUAR_UPDATE = 0x48, 1020 MCU_EXT_CMD_BCN_OFFLOAD = 0x49, 1021 MCU_EXT_CMD_RX_AIRTIME_CTRL = 0x4a, 1022 MCU_EXT_CMD_SET_RX_PATH = 0x4e, 1023 MCU_EXT_CMD_EFUSE_FREE_BLOCK = 0x4f, 1024 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58, 1025 MCU_EXT_CMD_RXDCOC_CAL = 0x59, 1026 MCU_EXT_CMD_GET_MIB_INFO = 0x5a, 1027 MCU_EXT_CMD_TXDPD_CAL = 0x60, 1028 MCU_EXT_CMD_CAL_CACHE = 0x67, 1029 MCU_EXT_CMD_SET_RADAR_TH = 0x7c, 1030 MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d, 1031 MCU_EXT_CMD_MWDS_SUPPORT = 0x80, 1032 MCU_EXT_CMD_SET_SER_TRIGGER = 0x81, 1033 MCU_EXT_CMD_TWT_AGRT_UPDATE = 0x94, 1034 MCU_EXT_CMD_FW_DBG_CTRL = 0x95, 1035 MCU_EXT_CMD_OFFCH_SCAN_CTRL = 0x9a, 1036 MCU_EXT_CMD_SET_RDD_TH = 0x9d, 1037 MCU_EXT_CMD_MURU_CTRL = 0x9f, 1038 MCU_EXT_CMD_SET_SPR = 0xa8, 1039 MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab, 1040 MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac, 1041 MCU_EXT_CMD_PHY_STAT_INFO = 0xad, 1042 }; 1043 1044 enum { 1045 MCU_UNI_CMD_DEV_INFO_UPDATE = 0x01, 1046 MCU_UNI_CMD_BSS_INFO_UPDATE = 0x02, 1047 MCU_UNI_CMD_STA_REC_UPDATE = 0x03, 1048 MCU_UNI_CMD_SUSPEND = 0x05, 1049 MCU_UNI_CMD_OFFLOAD = 0x06, 1050 MCU_UNI_CMD_HIF_CTRL = 0x07, 1051 MCU_UNI_CMD_SNIFFER = 0x24, 1052 }; 1053 1054 enum { 1055 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01, 1056 MCU_CMD_FW_START_REQ = 0x02, 1057 MCU_CMD_INIT_ACCESS_REG = 0x3, 1058 MCU_CMD_NIC_POWER_CTRL = 0x4, 1059 MCU_CMD_PATCH_START_REQ = 0x05, 1060 MCU_CMD_PATCH_FINISH_REQ = 0x07, 1061 MCU_CMD_PATCH_SEM_CONTROL = 0x10, 1062 MCU_CMD_WA_PARAM = 0xc4, 1063 MCU_CMD_EXT_CID = 0xed, 1064 MCU_CMD_FW_SCATTER = 0xee, 1065 MCU_CMD_RESTART_DL_REQ = 0xef, 1066 }; 1067 1068 /* offload mcu commands */ 1069 enum { 1070 MCU_CE_CMD_TEST_CTRL = 0x01, 1071 MCU_CE_CMD_START_HW_SCAN = 0x03, 1072 MCU_CE_CMD_SET_PS_PROFILE = 0x05, 1073 MCU_CE_CMD_SET_CHAN_DOMAIN = 0x0f, 1074 MCU_CE_CMD_SET_BSS_CONNECTED = 0x16, 1075 MCU_CE_CMD_SET_BSS_ABORT = 0x17, 1076 MCU_CE_CMD_CANCEL_HW_SCAN = 0x1b, 1077 MCU_CE_CMD_SET_ROC = 0x1c, 1078 MCU_CE_CMD_SET_EDCA_PARMS = 0x1d, 1079 MCU_CE_CMD_SET_P2P_OPPPS = 0x33, 1080 MCU_CE_CMD_SET_RATE_TX_POWER = 0x5d, 1081 MCU_CE_CMD_SCHED_SCAN_ENABLE = 0x61, 1082 MCU_CE_CMD_SCHED_SCAN_REQ = 0x62, 1083 MCU_CE_CMD_GET_NIC_CAPAB = 0x8a, 1084 MCU_CE_CMD_SET_MU_EDCA_PARMS = 0xb0, 1085 MCU_CE_CMD_REG_WRITE = 0xc0, 1086 MCU_CE_CMD_REG_READ = 0xc0, 1087 MCU_CE_CMD_CHIP_CONFIG = 0xca, 1088 MCU_CE_CMD_FWLOG_2_HOST = 0xc5, 1089 MCU_CE_CMD_GET_WTBL = 0xcd, 1090 MCU_CE_CMD_GET_TXPWR = 0xd0, 1091 }; 1092 1093 enum { 1094 PATCH_SEM_RELEASE, 1095 PATCH_SEM_GET 1096 }; 1097 1098 enum { 1099 UNI_BSS_INFO_BASIC = 0, 1100 UNI_BSS_INFO_RLM = 2, 1101 UNI_BSS_INFO_BSS_COLOR = 4, 1102 UNI_BSS_INFO_HE_BASIC = 5, 1103 UNI_BSS_INFO_BCN_CONTENT = 7, 1104 UNI_BSS_INFO_QBSS = 15, 1105 UNI_BSS_INFO_UAPSD = 19, 1106 UNI_BSS_INFO_PS = 21, 1107 UNI_BSS_INFO_BCNFT = 22, 1108 }; 1109 1110 enum { 1111 UNI_OFFLOAD_OFFLOAD_ARP, 1112 UNI_OFFLOAD_OFFLOAD_ND, 1113 UNI_OFFLOAD_OFFLOAD_GTK_REKEY, 1114 UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT, 1115 }; 1116 1117 enum { 1118 MT_NIC_CAP_TX_RESOURCE, 1119 MT_NIC_CAP_TX_EFUSE_ADDR, 1120 MT_NIC_CAP_COEX, 1121 MT_NIC_CAP_SINGLE_SKU, 1122 MT_NIC_CAP_CSUM_OFFLOAD, 1123 MT_NIC_CAP_HW_VER, 1124 MT_NIC_CAP_SW_VER, 1125 MT_NIC_CAP_MAC_ADDR, 1126 MT_NIC_CAP_PHY, 1127 MT_NIC_CAP_MAC, 1128 MT_NIC_CAP_FRAME_BUF, 1129 MT_NIC_CAP_BEAM_FORM, 1130 MT_NIC_CAP_LOCATION, 1131 MT_NIC_CAP_MUMIMO, 1132 MT_NIC_CAP_BUFFER_MODE_INFO, 1133 MT_NIC_CAP_HW_ADIE_VERSION = 0x14, 1134 MT_NIC_CAP_ANTSWP = 0x16, 1135 MT_NIC_CAP_WFDMA_REALLOC, 1136 MT_NIC_CAP_6G, 1137 }; 1138 1139 #define UNI_WOW_DETECT_TYPE_MAGIC BIT(0) 1140 #define UNI_WOW_DETECT_TYPE_ANY BIT(1) 1141 #define UNI_WOW_DETECT_TYPE_DISCONNECT BIT(2) 1142 #define UNI_WOW_DETECT_TYPE_GTK_REKEY_FAIL BIT(3) 1143 #define UNI_WOW_DETECT_TYPE_BCN_LOST BIT(4) 1144 #define UNI_WOW_DETECT_TYPE_SCH_SCAN_HIT BIT(5) 1145 #define UNI_WOW_DETECT_TYPE_BITMAP BIT(6) 1146 1147 enum { 1148 UNI_SUSPEND_MODE_SETTING, 1149 UNI_SUSPEND_WOW_CTRL, 1150 UNI_SUSPEND_WOW_GPIO_PARAM, 1151 UNI_SUSPEND_WOW_WAKEUP_PORT, 1152 UNI_SUSPEND_WOW_PATTERN, 1153 }; 1154 1155 enum { 1156 WOW_USB = 1, 1157 WOW_PCIE = 2, 1158 WOW_GPIO = 3, 1159 }; 1160 1161 struct mt76_connac_bss_basic_tlv { 1162 __le16 tag; 1163 __le16 len; 1164 u8 active; 1165 u8 omac_idx; 1166 u8 hw_bss_idx; 1167 u8 band_idx; 1168 __le32 conn_type; 1169 u8 conn_state; 1170 u8 wmm_idx; 1171 u8 bssid[ETH_ALEN]; 1172 __le16 bmc_tx_wlan_idx; 1173 __le16 bcn_interval; 1174 u8 dtim_period; 1175 u8 phymode; /* bit(0): A 1176 * bit(1): B 1177 * bit(2): G 1178 * bit(3): GN 1179 * bit(4): AN 1180 * bit(5): AC 1181 * bit(6): AX2 1182 * bit(7): AX5 1183 * bit(8): AX6 1184 */ 1185 __le16 sta_idx; 1186 __le16 nonht_basic_phy; 1187 u8 phymode_ext; /* bit(0) AX_6G */ 1188 u8 pad[1]; 1189 } __packed; 1190 1191 struct mt76_connac_bss_qos_tlv { 1192 __le16 tag; 1193 __le16 len; 1194 u8 qos; 1195 u8 pad[3]; 1196 } __packed; 1197 1198 struct mt76_connac_beacon_loss_event { 1199 u8 bss_idx; 1200 u8 reason; 1201 u8 pad[2]; 1202 } __packed; 1203 1204 struct mt76_connac_mcu_bss_event { 1205 u8 bss_idx; 1206 u8 is_absent; 1207 u8 free_quota; 1208 u8 pad; 1209 } __packed; 1210 1211 struct mt76_connac_mcu_scan_ssid { 1212 __le32 ssid_len; 1213 u8 ssid[IEEE80211_MAX_SSID_LEN]; 1214 } __packed; 1215 1216 struct mt76_connac_mcu_scan_channel { 1217 u8 band; /* 1: 2.4GHz 1218 * 2: 5.0GHz 1219 * Others: Reserved 1220 */ 1221 u8 channel_num; 1222 } __packed; 1223 1224 struct mt76_connac_mcu_scan_match { 1225 __le32 rssi_th; 1226 u8 ssid[IEEE80211_MAX_SSID_LEN]; 1227 u8 ssid_len; 1228 u8 rsv[3]; 1229 } __packed; 1230 1231 struct mt76_connac_hw_scan_req { 1232 u8 seq_num; 1233 u8 bss_idx; 1234 u8 scan_type; /* 0: PASSIVE SCAN 1235 * 1: ACTIVE SCAN 1236 */ 1237 u8 ssid_type; /* BIT(0) wildcard SSID 1238 * BIT(1) P2P wildcard SSID 1239 * BIT(2) specified SSID + wildcard SSID 1240 * BIT(2) + ssid_type_ext BIT(0) specified SSID only 1241 */ 1242 u8 ssids_num; 1243 u8 probe_req_num; /* Number of probe request for each SSID */ 1244 u8 scan_func; /* BIT(0) Enable random MAC scan 1245 * BIT(1) Disable DBDC scan type 1~3. 1246 * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan). 1247 */ 1248 u8 version; /* 0: Not support fields after ies. 1249 * 1: Support fields after ies. 1250 */ 1251 struct mt76_connac_mcu_scan_ssid ssids[4]; 1252 __le16 probe_delay_time; 1253 __le16 channel_dwell_time; /* channel Dwell interval */ 1254 __le16 timeout_value; 1255 u8 channel_type; /* 0: Full channels 1256 * 1: Only 2.4GHz channels 1257 * 2: Only 5GHz channels 1258 * 3: P2P social channel only (channel #1, #6 and #11) 1259 * 4: Specified channels 1260 * Others: Reserved 1261 */ 1262 u8 channels_num; /* valid when channel_type is 4 */ 1263 /* valid when channels_num is set */ 1264 struct mt76_connac_mcu_scan_channel channels[32]; 1265 __le16 ies_len; 1266 u8 ies[MT76_CONNAC_SCAN_IE_LEN]; 1267 /* following fields are valid if version > 0 */ 1268 u8 ext_channels_num; 1269 u8 ext_ssids_num; 1270 __le16 channel_min_dwell_time; 1271 struct mt76_connac_mcu_scan_channel ext_channels[32]; 1272 struct mt76_connac_mcu_scan_ssid ext_ssids[6]; 1273 u8 bssid[ETH_ALEN]; 1274 u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */ 1275 u8 pad[63]; 1276 u8 ssid_type_ext; 1277 } __packed; 1278 1279 #define MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM 64 1280 1281 struct mt76_connac_hw_scan_done { 1282 u8 seq_num; 1283 u8 sparse_channel_num; 1284 struct mt76_connac_mcu_scan_channel sparse_channel; 1285 u8 complete_channel_num; 1286 u8 current_state; 1287 u8 version; 1288 u8 pad; 1289 __le32 beacon_scan_num; 1290 u8 pno_enabled; 1291 u8 pad2[3]; 1292 u8 sparse_channel_valid_num; 1293 u8 pad3[3]; 1294 u8 channel_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1295 /* idle format for channel_idle_time 1296 * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms) 1297 * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms) 1298 * 2: dwell time (16us) 1299 */ 1300 __le16 channel_idle_time[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1301 /* beacon and probe response count */ 1302 u8 beacon_probe_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1303 u8 mdrdy_count[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1304 __le32 beacon_2g_num; 1305 __le32 beacon_5g_num; 1306 } __packed; 1307 1308 struct mt76_connac_sched_scan_req { 1309 u8 version; 1310 u8 seq_num; 1311 u8 stop_on_match; 1312 u8 ssids_num; 1313 u8 match_num; 1314 u8 pad; 1315 __le16 ie_len; 1316 struct mt76_connac_mcu_scan_ssid ssids[MT76_CONNAC_MAX_SCHED_SCAN_SSID]; 1317 struct mt76_connac_mcu_scan_match match[MT76_CONNAC_MAX_SCAN_MATCH]; 1318 u8 channel_type; 1319 u8 channels_num; 1320 u8 intervals_num; 1321 u8 scan_func; /* MT7663: BIT(0) eable random mac address */ 1322 struct mt76_connac_mcu_scan_channel channels[64]; 1323 __le16 intervals[MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL]; 1324 union { 1325 struct { 1326 u8 random_mac[ETH_ALEN]; 1327 u8 pad2[58]; 1328 } mt7663; 1329 struct { 1330 u8 bss_idx; 1331 u8 pad1[3]; 1332 __le32 delay; 1333 u8 pad2[12]; 1334 u8 random_mac[ETH_ALEN]; 1335 u8 pad3[38]; 1336 } mt7921; 1337 }; 1338 } __packed; 1339 1340 struct mt76_connac_sched_scan_done { 1341 u8 seq_num; 1342 u8 status; /* 0: ssid found */ 1343 __le16 pad; 1344 } __packed; 1345 1346 struct bss_info_uni_bss_color { 1347 __le16 tag; 1348 __le16 len; 1349 u8 enable; 1350 u8 bss_color; 1351 u8 rsv[2]; 1352 } __packed; 1353 1354 struct bss_info_uni_he { 1355 __le16 tag; 1356 __le16 len; 1357 __le16 he_rts_thres; 1358 u8 he_pe_duration; 1359 u8 su_disable; 1360 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 1361 u8 rsv[2]; 1362 } __packed; 1363 1364 struct mt76_connac_gtk_rekey_tlv { 1365 __le16 tag; 1366 __le16 len; 1367 u8 kek[NL80211_KEK_LEN]; 1368 u8 kck[NL80211_KCK_LEN]; 1369 u8 replay_ctr[NL80211_REPLAY_CTR_LEN]; 1370 u8 rekey_mode; /* 0: rekey offload enable 1371 * 1: rekey offload disable 1372 * 2: rekey update 1373 */ 1374 u8 keyid; 1375 u8 option; /* 1: rekey data update without enabling offload */ 1376 u8 pad[1]; 1377 __le32 proto; /* WPA-RSN-WAPI-OPSN */ 1378 __le32 pairwise_cipher; 1379 __le32 group_cipher; 1380 __le32 key_mgmt; /* NONE-PSK-IEEE802.1X */ 1381 __le32 mgmt_group_cipher; 1382 u8 reserverd[4]; 1383 } __packed; 1384 1385 #define MT76_CONNAC_WOW_MASK_MAX_LEN 16 1386 #define MT76_CONNAC_WOW_PATTEN_MAX_LEN 128 1387 1388 struct mt76_connac_wow_pattern_tlv { 1389 __le16 tag; 1390 __le16 len; 1391 u8 index; /* pattern index */ 1392 u8 enable; /* 0: disable 1393 * 1: enable 1394 */ 1395 u8 data_len; /* pattern length */ 1396 u8 pad; 1397 u8 mask[MT76_CONNAC_WOW_MASK_MAX_LEN]; 1398 u8 pattern[MT76_CONNAC_WOW_PATTEN_MAX_LEN]; 1399 u8 rsv[4]; 1400 } __packed; 1401 1402 struct mt76_connac_wow_ctrl_tlv { 1403 __le16 tag; 1404 __le16 len; 1405 u8 cmd; /* 0x1: PM_WOWLAN_REQ_START 1406 * 0x2: PM_WOWLAN_REQ_STOP 1407 * 0x3: PM_WOWLAN_PARAM_CLEAR 1408 */ 1409 u8 trigger; /* 0: NONE 1410 * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT 1411 * BIT(1): NL80211_WOWLAN_TRIG_ANY 1412 * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT 1413 * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE 1414 * BIT(4): BEACON_LOST 1415 * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT 1416 */ 1417 u8 wakeup_hif; /* 0x0: HIF_SDIO 1418 * 0x1: HIF_USB 1419 * 0x2: HIF_PCIE 1420 * 0x3: HIF_GPIO 1421 */ 1422 u8 pad; 1423 u8 rsv[4]; 1424 } __packed; 1425 1426 struct mt76_connac_wow_gpio_param_tlv { 1427 __le16 tag; 1428 __le16 len; 1429 u8 gpio_pin; 1430 u8 trigger_lvl; 1431 u8 pad[2]; 1432 __le32 gpio_interval; 1433 u8 rsv[4]; 1434 } __packed; 1435 1436 struct mt76_connac_arpns_tlv { 1437 __le16 tag; 1438 __le16 len; 1439 u8 mode; 1440 u8 ips_num; 1441 u8 option; 1442 u8 pad[1]; 1443 } __packed; 1444 1445 struct mt76_connac_suspend_tlv { 1446 __le16 tag; 1447 __le16 len; 1448 u8 enable; /* 0: suspend mode disabled 1449 * 1: suspend mode enabled 1450 */ 1451 u8 mdtim; /* LP parameter */ 1452 u8 wow_suspend; /* 0: update by origin policy 1453 * 1: update by wow dtim 1454 */ 1455 u8 pad[5]; 1456 } __packed; 1457 1458 enum mt76_sta_info_state { 1459 MT76_STA_INFO_STATE_NONE, 1460 MT76_STA_INFO_STATE_AUTH, 1461 MT76_STA_INFO_STATE_ASSOC 1462 }; 1463 1464 struct mt76_sta_cmd_info { 1465 struct ieee80211_sta *sta; 1466 struct mt76_wcid *wcid; 1467 1468 struct ieee80211_vif *vif; 1469 1470 bool offload_fw; 1471 bool enable; 1472 bool newly; 1473 int cmd; 1474 u8 rcpi; 1475 u8 state; 1476 }; 1477 1478 #define MT_SKU_POWER_LIMIT 161 1479 1480 struct mt76_connac_sku_tlv { 1481 u8 channel; 1482 s8 pwr_limit[MT_SKU_POWER_LIMIT]; 1483 } __packed; 1484 1485 struct mt76_connac_tx_power_limit_tlv { 1486 /* DW0 - common info*/ 1487 u8 ver; 1488 u8 pad0; 1489 __le16 len; 1490 /* DW1 - cmd hint */ 1491 u8 n_chan; /* # channel */ 1492 u8 band; /* 2.4GHz - 5GHz - 6GHz */ 1493 u8 last_msg; 1494 u8 pad1; 1495 /* DW3 */ 1496 u8 alpha2[4]; /* regulatory_request.alpha2 */ 1497 u8 pad2[32]; 1498 } __packed; 1499 1500 struct mt76_connac_config { 1501 __le16 id; 1502 u8 type; 1503 u8 resp_type; 1504 __le16 data_size; 1505 __le16 resv; 1506 u8 data[320]; 1507 } __packed; 1508 1509 static inline enum mcu_cipher_type 1510 mt76_connac_mcu_get_cipher(int cipher) 1511 { 1512 switch (cipher) { 1513 case WLAN_CIPHER_SUITE_WEP40: 1514 return MCU_CIPHER_WEP40; 1515 case WLAN_CIPHER_SUITE_WEP104: 1516 return MCU_CIPHER_WEP104; 1517 case WLAN_CIPHER_SUITE_TKIP: 1518 return MCU_CIPHER_TKIP; 1519 case WLAN_CIPHER_SUITE_AES_CMAC: 1520 return MCU_CIPHER_BIP_CMAC_128; 1521 case WLAN_CIPHER_SUITE_CCMP: 1522 return MCU_CIPHER_AES_CCMP; 1523 case WLAN_CIPHER_SUITE_CCMP_256: 1524 return MCU_CIPHER_CCMP_256; 1525 case WLAN_CIPHER_SUITE_GCMP: 1526 return MCU_CIPHER_GCMP; 1527 case WLAN_CIPHER_SUITE_GCMP_256: 1528 return MCU_CIPHER_GCMP_256; 1529 case WLAN_CIPHER_SUITE_SMS4: 1530 return MCU_CIPHER_WAPI; 1531 default: 1532 return MCU_CIPHER_NONE; 1533 } 1534 } 1535 1536 static inline u32 1537 mt76_connac_mcu_gen_dl_mode(struct mt76_dev *dev, u8 feature_set, bool is_wa) 1538 { 1539 u32 ret = 0; 1540 1541 ret |= feature_set & FW_FEATURE_SET_ENCRYPT ? 1542 DL_MODE_ENCRYPT | DL_MODE_RESET_SEC_IV : 0; 1543 if (is_mt7921(dev)) 1544 ret |= feature_set & FW_FEATURE_ENCRY_MODE ? 1545 DL_CONFIG_ENCRY_MODE_SEL : 0; 1546 ret |= FIELD_PREP(DL_MODE_KEY_IDX, 1547 FIELD_GET(FW_FEATURE_SET_KEY_IDX, feature_set)); 1548 ret |= DL_MODE_NEED_RSP; 1549 ret |= is_wa ? DL_MODE_WORKING_PDA_CR4 : 0; 1550 1551 return ret; 1552 } 1553 1554 #define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id) 1555 #define to_wcid_hi(id) FIELD_GET(GENMASK(9, 8), (u16)id) 1556 1557 static inline void 1558 mt76_connac_mcu_get_wlan_idx(struct mt76_dev *dev, struct mt76_wcid *wcid, 1559 u8 *wlan_idx_lo, u8 *wlan_idx_hi) 1560 { 1561 *wlan_idx_hi = 0; 1562 1563 if (!is_connac_v1(dev)) { 1564 *wlan_idx_lo = wcid ? to_wcid_lo(wcid->idx) : 0; 1565 *wlan_idx_hi = wcid ? to_wcid_hi(wcid->idx) : 0; 1566 } else { 1567 *wlan_idx_lo = wcid ? wcid->idx : 0; 1568 } 1569 } 1570 1571 struct sk_buff * 1572 __mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif, 1573 struct mt76_wcid *wcid, int len); 1574 static inline struct sk_buff * 1575 mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif, 1576 struct mt76_wcid *wcid) 1577 { 1578 return __mt76_connac_mcu_alloc_sta_req(dev, mvif, wcid, 1579 MT76_CONNAC_STA_UPDATE_MAX_SIZE); 1580 } 1581 1582 struct wtbl_req_hdr * 1583 mt76_connac_mcu_alloc_wtbl_req(struct mt76_dev *dev, struct mt76_wcid *wcid, 1584 int cmd, void *sta_wtbl, struct sk_buff **skb); 1585 struct tlv *mt76_connac_mcu_add_nested_tlv(struct sk_buff *skb, int tag, 1586 int len, void *sta_ntlv, 1587 void *sta_wtbl); 1588 static inline struct tlv * 1589 mt76_connac_mcu_add_tlv(struct sk_buff *skb, int tag, int len) 1590 { 1591 return mt76_connac_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL); 1592 } 1593 1594 int mt76_connac_mcu_set_channel_domain(struct mt76_phy *phy); 1595 int mt76_connac_mcu_set_vif_ps(struct mt76_dev *dev, struct ieee80211_vif *vif); 1596 void mt76_connac_mcu_sta_basic_tlv(struct sk_buff *skb, 1597 struct ieee80211_vif *vif, 1598 struct ieee80211_sta *sta, bool enable, 1599 bool newly); 1600 void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1601 struct ieee80211_vif *vif, 1602 struct ieee80211_sta *sta, void *sta_wtbl, 1603 void *wtbl_tlv); 1604 void mt76_connac_mcu_wtbl_hdr_trans_tlv(struct sk_buff *skb, 1605 struct ieee80211_vif *vif, 1606 struct mt76_wcid *wcid, 1607 void *sta_wtbl, void *wtbl_tlv); 1608 int mt76_connac_mcu_sta_update_hdr_trans(struct mt76_dev *dev, 1609 struct ieee80211_vif *vif, 1610 struct mt76_wcid *wcid, int cmd); 1611 int mt76_connac_mcu_wtbl_update_hdr_trans(struct mt76_dev *dev, 1612 struct ieee80211_vif *vif, 1613 struct ieee80211_sta *sta); 1614 void mt76_connac_mcu_sta_tlv(struct mt76_phy *mphy, struct sk_buff *skb, 1615 struct ieee80211_sta *sta, 1616 struct ieee80211_vif *vif, 1617 u8 rcpi, u8 state); 1618 void mt76_connac_mcu_wtbl_ht_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1619 struct ieee80211_sta *sta, void *sta_wtbl, 1620 void *wtbl_tlv, bool ht_ldpc, bool vht_ldpc); 1621 void mt76_connac_mcu_wtbl_ba_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1622 struct ieee80211_ampdu_params *params, 1623 bool enable, bool tx, void *sta_wtbl, 1624 void *wtbl_tlv); 1625 void mt76_connac_mcu_sta_ba_tlv(struct sk_buff *skb, 1626 struct ieee80211_ampdu_params *params, 1627 bool enable, bool tx); 1628 int mt76_connac_mcu_uni_add_dev(struct mt76_phy *phy, 1629 struct ieee80211_vif *vif, 1630 struct mt76_wcid *wcid, 1631 bool enable); 1632 int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif, 1633 struct ieee80211_ampdu_params *params, 1634 int cmd, bool enable, bool tx); 1635 int mt76_connac_mcu_uni_add_bss(struct mt76_phy *phy, 1636 struct ieee80211_vif *vif, 1637 struct mt76_wcid *wcid, 1638 bool enable); 1639 int mt76_connac_mcu_sta_cmd(struct mt76_phy *phy, 1640 struct mt76_sta_cmd_info *info); 1641 void mt76_connac_mcu_beacon_loss_iter(void *priv, u8 *mac, 1642 struct ieee80211_vif *vif); 1643 int mt76_connac_mcu_set_rts_thresh(struct mt76_dev *dev, u32 val, u8 band); 1644 int mt76_connac_mcu_set_mac_enable(struct mt76_dev *dev, int band, bool enable, 1645 bool hdr_trans); 1646 int mt76_connac_mcu_init_download(struct mt76_dev *dev, u32 addr, u32 len, 1647 u32 mode); 1648 int mt76_connac_mcu_start_patch(struct mt76_dev *dev); 1649 int mt76_connac_mcu_patch_sem_ctrl(struct mt76_dev *dev, bool get); 1650 int mt76_connac_mcu_start_firmware(struct mt76_dev *dev, u32 addr, u32 option); 1651 int mt76_connac_mcu_get_nic_capability(struct mt76_phy *phy); 1652 1653 int mt76_connac_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif, 1654 struct ieee80211_scan_request *scan_req); 1655 int mt76_connac_mcu_cancel_hw_scan(struct mt76_phy *phy, 1656 struct ieee80211_vif *vif); 1657 int mt76_connac_mcu_sched_scan_req(struct mt76_phy *phy, 1658 struct ieee80211_vif *vif, 1659 struct cfg80211_sched_scan_request *sreq); 1660 int mt76_connac_mcu_sched_scan_enable(struct mt76_phy *phy, 1661 struct ieee80211_vif *vif, 1662 bool enable); 1663 int mt76_connac_mcu_update_arp_filter(struct mt76_dev *dev, 1664 struct mt76_vif *vif, 1665 struct ieee80211_bss_conf *info); 1666 int mt76_connac_mcu_update_gtk_rekey(struct ieee80211_hw *hw, 1667 struct ieee80211_vif *vif, 1668 struct cfg80211_gtk_rekey_data *key); 1669 int mt76_connac_mcu_set_hif_suspend(struct mt76_dev *dev, bool suspend); 1670 void mt76_connac_mcu_set_suspend_iter(void *priv, u8 *mac, 1671 struct ieee80211_vif *vif); 1672 int mt76_connac_sta_state_dp(struct mt76_dev *dev, 1673 enum ieee80211_sta_state old_state, 1674 enum ieee80211_sta_state new_state); 1675 int mt76_connac_mcu_chip_config(struct mt76_dev *dev); 1676 int mt76_connac_mcu_set_deep_sleep(struct mt76_dev *dev, bool enable); 1677 void mt76_connac_mcu_coredump_event(struct mt76_dev *dev, struct sk_buff *skb, 1678 struct mt76_connac_coredump *coredump); 1679 int mt76_connac_mcu_set_rate_txpower(struct mt76_phy *phy); 1680 int mt76_connac_mcu_set_p2p_oppps(struct ieee80211_hw *hw, 1681 struct ieee80211_vif *vif); 1682 u32 mt76_connac_mcu_reg_rr(struct mt76_dev *dev, u32 offset); 1683 void mt76_connac_mcu_reg_wr(struct mt76_dev *dev, u32 offset, u32 val); 1684 1685 const struct ieee80211_sta_he_cap * 1686 mt76_connac_get_he_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif); 1687 u8 mt76_connac_get_phy_mode(struct mt76_phy *phy, struct ieee80211_vif *vif, 1688 enum nl80211_band band, struct ieee80211_sta *sta); 1689 1690 int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif, 1691 struct mt76_connac_sta_key_conf *sta_key_conf, 1692 struct ieee80211_key_conf *key, int mcu_cmd, 1693 struct mt76_wcid *wcid, enum set_key_cmd cmd); 1694 1695 void mt76_connac_mcu_bss_ext_tlv(struct sk_buff *skb, struct mt76_vif *mvif); 1696 void mt76_connac_mcu_bss_omac_tlv(struct sk_buff *skb, 1697 struct ieee80211_vif *vif); 1698 int mt76_connac_mcu_bss_basic_tlv(struct sk_buff *skb, 1699 struct ieee80211_vif *vif, 1700 struct ieee80211_sta *sta, 1701 struct mt76_phy *phy, u16 wlan_idx, 1702 bool enable); 1703 void mt76_connac_mcu_sta_uapsd(struct sk_buff *skb, struct ieee80211_vif *vif, 1704 struct ieee80211_sta *sta); 1705 void mt76_connac_mcu_wtbl_smps_tlv(struct sk_buff *skb, 1706 struct ieee80211_sta *sta, 1707 void *sta_wtbl, void *wtbl_tlv); 1708 int mt76_connac_mcu_set_pm(struct mt76_dev *dev, int band, int enter); 1709 int mt76_connac_mcu_restart(struct mt76_dev *dev); 1710 int mt76_connac_mcu_rdd_cmd(struct mt76_dev *dev, int cmd, u8 index, 1711 u8 rx_sel, u8 val); 1712 int mt76_connac2_load_ram(struct mt76_dev *dev, const char *fw_wm, 1713 const char *fw_wa); 1714 #endif /* __MT76_CONNAC_MCU_H */ 1715