1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT76_CONNAC_MCU_H 5 #define __MT76_CONNAC_MCU_H 6 7 #include "mt76_connac.h" 8 9 struct tlv { 10 __le16 tag; 11 __le16 len; 12 } __packed; 13 14 struct bss_info_omac { 15 __le16 tag; 16 __le16 len; 17 u8 hw_bss_idx; 18 u8 omac_idx; 19 u8 band_idx; 20 u8 rsv0; 21 __le32 conn_type; 22 u32 rsv1; 23 } __packed; 24 25 struct bss_info_basic { 26 __le16 tag; 27 __le16 len; 28 __le32 network_type; 29 u8 active; 30 u8 rsv0; 31 __le16 bcn_interval; 32 u8 bssid[ETH_ALEN]; 33 u8 wmm_idx; 34 u8 dtim_period; 35 u8 bmc_wcid_lo; 36 u8 cipher; 37 u8 phy_mode; 38 u8 max_bssid; /* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */ 39 u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */ 40 u8 bmc_wcid_hi; /* high Byte and version */ 41 u8 rsv[2]; 42 } __packed; 43 44 struct bss_info_rf_ch { 45 __le16 tag; 46 __le16 len; 47 u8 pri_ch; 48 u8 center_ch0; 49 u8 center_ch1; 50 u8 bw; 51 u8 he_ru26_block; /* 1: don't send HETB in RU26, 0: allow */ 52 u8 he_all_disable; /* 1: disallow all HETB, 0: allow */ 53 u8 rsv[2]; 54 } __packed; 55 56 struct bss_info_ext_bss { 57 __le16 tag; 58 __le16 len; 59 __le32 mbss_tsf_offset; /* in unit of us */ 60 u8 rsv[8]; 61 } __packed; 62 63 enum { 64 BSS_INFO_OMAC, 65 BSS_INFO_BASIC, 66 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */ 67 BSS_INFO_PM, /* sta only */ 68 BSS_INFO_UAPSD, /* sta only */ 69 BSS_INFO_ROAM_DETECT, /* obsoleted */ 70 BSS_INFO_LQ_RM, /* obsoleted */ 71 BSS_INFO_EXT_BSS, 72 BSS_INFO_BMC_RATE, /* for bmc rate control in CR4 */ 73 BSS_INFO_SYNC_MODE, /* obsoleted */ 74 BSS_INFO_RA, 75 BSS_INFO_HW_AMSDU, 76 BSS_INFO_BSS_COLOR, 77 BSS_INFO_HE_BASIC, 78 BSS_INFO_PROTECT_INFO, 79 BSS_INFO_OFFLOAD, 80 BSS_INFO_11V_MBSSID, 81 BSS_INFO_MAX_NUM 82 }; 83 84 /* sta_rec */ 85 86 struct sta_ntlv_hdr { 87 u8 rsv[2]; 88 __le16 tlv_num; 89 } __packed; 90 91 struct sta_req_hdr { 92 u8 bss_idx; 93 u8 wlan_idx_lo; 94 __le16 tlv_num; 95 u8 is_tlv_append; 96 u8 muar_idx; 97 u8 wlan_idx_hi; 98 u8 rsv; 99 } __packed; 100 101 struct sta_rec_basic { 102 __le16 tag; 103 __le16 len; 104 __le32 conn_type; 105 u8 conn_state; 106 u8 qos; 107 __le16 aid; 108 u8 peer_addr[ETH_ALEN]; 109 #define EXTRA_INFO_VER BIT(0) 110 #define EXTRA_INFO_NEW BIT(1) 111 __le16 extra_info; 112 } __packed; 113 114 struct sta_rec_ht { 115 __le16 tag; 116 __le16 len; 117 __le16 ht_cap; 118 u16 rsv; 119 } __packed; 120 121 struct sta_rec_vht { 122 __le16 tag; 123 __le16 len; 124 __le32 vht_cap; 125 __le16 vht_rx_mcs_map; 126 __le16 vht_tx_mcs_map; 127 /* mt7915 - mt7921 */ 128 u8 rts_bw_sig; 129 u8 rsv[3]; 130 } __packed; 131 132 struct sta_rec_uapsd { 133 __le16 tag; 134 __le16 len; 135 u8 dac_map; 136 u8 tac_map; 137 u8 max_sp; 138 u8 rsv0; 139 __le16 listen_interval; 140 u8 rsv1[2]; 141 } __packed; 142 143 struct sta_rec_ba { 144 __le16 tag; 145 __le16 len; 146 u8 tid; 147 u8 ba_type; 148 u8 amsdu; 149 u8 ba_en; 150 __le16 ssn; 151 __le16 winsize; 152 } __packed; 153 154 struct sta_rec_he { 155 __le16 tag; 156 __le16 len; 157 158 __le32 he_cap; 159 160 u8 t_frame_dur; 161 u8 max_ampdu_exp; 162 u8 bw_set; 163 u8 device_class; 164 u8 dcm_tx_mode; 165 u8 dcm_tx_max_nss; 166 u8 dcm_rx_mode; 167 u8 dcm_rx_max_nss; 168 u8 dcm_max_ru; 169 u8 punc_pream_rx; 170 u8 pkt_ext; 171 u8 rsv1; 172 173 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 174 175 u8 rsv2[2]; 176 } __packed; 177 178 struct sta_rec_amsdu { 179 __le16 tag; 180 __le16 len; 181 u8 max_amsdu_num; 182 u8 max_mpdu_size; 183 u8 amsdu_en; 184 u8 rsv; 185 } __packed; 186 187 struct sta_rec_state { 188 __le16 tag; 189 __le16 len; 190 __le32 flags; 191 u8 state; 192 u8 vht_opmode; 193 u8 action; 194 u8 rsv[1]; 195 } __packed; 196 197 #define RA_LEGACY_OFDM GENMASK(13, 6) 198 #define RA_LEGACY_CCK GENMASK(3, 0) 199 #define HT_MCS_MASK_NUM 10 200 struct sta_rec_ra_info { 201 __le16 tag; 202 __le16 len; 203 __le16 legacy; 204 u8 rx_mcs_bitmask[HT_MCS_MASK_NUM]; 205 } __packed; 206 207 struct sta_rec_phy { 208 __le16 tag; 209 __le16 len; 210 __le16 basic_rate; 211 u8 phy_type; 212 u8 ampdu; 213 u8 rts_policy; 214 u8 rcpi; 215 u8 rsv[2]; 216 } __packed; 217 218 struct sta_rec_he_6g_capa { 219 __le16 tag; 220 __le16 len; 221 __le16 capa; 222 u8 rsv[2]; 223 } __packed; 224 225 struct sec_key { 226 u8 cipher_id; 227 u8 cipher_len; 228 u8 key_id; 229 u8 key_len; 230 u8 key[32]; 231 } __packed; 232 233 struct sta_rec_sec { 234 __le16 tag; 235 __le16 len; 236 u8 add; 237 u8 n_cipher; 238 u8 rsv[2]; 239 240 struct sec_key key[2]; 241 } __packed; 242 243 struct sta_rec_bf { 244 __le16 tag; 245 __le16 len; 246 247 __le16 pfmu; /* 0xffff: no access right for PFMU */ 248 bool su_mu; /* 0: SU, 1: MU */ 249 u8 bf_cap; /* 0: iBF, 1: eBF */ 250 u8 sounding_phy; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT */ 251 u8 ndpa_rate; 252 u8 ndp_rate; 253 u8 rept_poll_rate; 254 u8 tx_mode; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */ 255 u8 ncol; 256 u8 nrow; 257 u8 bw; /* 0: 20M, 1: 40M, 2: 80M, 3: 160M */ 258 259 u8 mem_total; 260 u8 mem_20m; 261 struct { 262 u8 row; 263 u8 col: 6, row_msb: 2; 264 } mem[4]; 265 266 __le16 smart_ant; 267 u8 se_idx; 268 u8 auto_sounding; /* b7: low traffic indicator 269 * b6: Stop sounding for this entry 270 * b5 ~ b0: postpone sounding 271 */ 272 u8 ibf_timeout; 273 u8 ibf_dbw; 274 u8 ibf_ncol; 275 u8 ibf_nrow; 276 u8 nrow_bw160; 277 u8 ncol_bw160; 278 u8 ru_start_idx; 279 u8 ru_end_idx; 280 281 bool trigger_su; 282 bool trigger_mu; 283 bool ng16_su; 284 bool ng16_mu; 285 bool codebook42_su; 286 bool codebook75_mu; 287 288 u8 he_ltf; 289 u8 rsv[3]; 290 } __packed; 291 292 struct sta_rec_bfee { 293 __le16 tag; 294 __le16 len; 295 bool fb_identity_matrix; /* 1: feedback identity matrix */ 296 bool ignore_feedback; /* 1: ignore */ 297 u8 rsv[2]; 298 } __packed; 299 300 struct sta_rec_muru { 301 __le16 tag; 302 __le16 len; 303 304 struct { 305 bool ofdma_dl_en; 306 bool ofdma_ul_en; 307 bool mimo_dl_en; 308 bool mimo_ul_en; 309 u8 rsv[4]; 310 } cfg; 311 312 struct { 313 u8 punc_pream_rx; 314 bool he_20m_in_40m_2g; 315 bool he_20m_in_160m; 316 bool he_80m_in_160m; 317 bool lt16_sigb; 318 bool rx_su_comp_sigb; 319 bool rx_su_non_comp_sigb; 320 u8 rsv; 321 } ofdma_dl; 322 323 struct { 324 u8 t_frame_dur; 325 u8 mu_cascading; 326 u8 uo_ra; 327 u8 he_2x996_tone; 328 u8 rx_t_frame_11ac; 329 u8 rsv[3]; 330 } ofdma_ul; 331 332 struct { 333 bool vht_mu_bfee; 334 bool partial_bw_dl_mimo; 335 u8 rsv[2]; 336 } mimo_dl; 337 338 struct { 339 bool full_ul_mimo; 340 bool partial_ul_mimo; 341 u8 rsv[2]; 342 } mimo_ul; 343 } __packed; 344 345 struct sta_phy { 346 u8 type; 347 u8 flag; 348 u8 stbc; 349 u8 sgi; 350 u8 bw; 351 u8 ldpc; 352 u8 mcs; 353 u8 nss; 354 u8 he_ltf; 355 }; 356 357 struct sta_rec_ra { 358 __le16 tag; 359 __le16 len; 360 361 u8 valid; 362 u8 auto_rate; 363 u8 phy_mode; 364 u8 channel; 365 u8 bw; 366 u8 disable_cck; 367 u8 ht_mcs32; 368 u8 ht_gf; 369 u8 ht_mcs[4]; 370 u8 mmps_mode; 371 u8 gband_256; 372 u8 af; 373 u8 auth_wapi_mode; 374 u8 rate_len; 375 376 u8 supp_mode; 377 u8 supp_cck_rate; 378 u8 supp_ofdm_rate; 379 __le32 supp_ht_mcs; 380 __le16 supp_vht_mcs[4]; 381 382 u8 op_mode; 383 u8 op_vht_chan_width; 384 u8 op_vht_rx_nss; 385 u8 op_vht_rx_nss_type; 386 387 __le32 sta_cap; 388 389 struct sta_phy phy; 390 } __packed; 391 392 struct sta_rec_ra_fixed { 393 __le16 tag; 394 __le16 len; 395 396 __le32 field; 397 u8 op_mode; 398 u8 op_vht_chan_width; 399 u8 op_vht_rx_nss; 400 u8 op_vht_rx_nss_type; 401 402 struct sta_phy phy; 403 404 u8 spe_en; 405 u8 short_preamble; 406 u8 is_5g; 407 u8 mmps_mode; 408 } __packed; 409 410 /* wtbl_rec */ 411 412 struct wtbl_req_hdr { 413 u8 wlan_idx_lo; 414 u8 operation; 415 __le16 tlv_num; 416 u8 wlan_idx_hi; 417 u8 rsv[3]; 418 } __packed; 419 420 struct wtbl_generic { 421 __le16 tag; 422 __le16 len; 423 u8 peer_addr[ETH_ALEN]; 424 u8 muar_idx; 425 u8 skip_tx; 426 u8 cf_ack; 427 u8 qos; 428 u8 mesh; 429 u8 adm; 430 __le16 partial_aid; 431 u8 baf_en; 432 u8 aad_om; 433 } __packed; 434 435 struct wtbl_rx { 436 __le16 tag; 437 __le16 len; 438 u8 rcid; 439 u8 rca1; 440 u8 rca2; 441 u8 rv; 442 u8 rsv[4]; 443 } __packed; 444 445 struct wtbl_ht { 446 __le16 tag; 447 __le16 len; 448 u8 ht; 449 u8 ldpc; 450 u8 af; 451 u8 mm; 452 u8 rsv[4]; 453 } __packed; 454 455 struct wtbl_vht { 456 __le16 tag; 457 __le16 len; 458 u8 ldpc; 459 u8 dyn_bw; 460 u8 vht; 461 u8 txop_ps; 462 u8 rsv[4]; 463 } __packed; 464 465 struct wtbl_tx_ps { 466 __le16 tag; 467 __le16 len; 468 u8 txps; 469 u8 rsv[3]; 470 } __packed; 471 472 struct wtbl_hdr_trans { 473 __le16 tag; 474 __le16 len; 475 u8 to_ds; 476 u8 from_ds; 477 u8 no_rx_trans; 478 u8 rsv; 479 } __packed; 480 481 struct wtbl_ba { 482 __le16 tag; 483 __le16 len; 484 /* common */ 485 u8 tid; 486 u8 ba_type; 487 u8 rsv0[2]; 488 /* originator only */ 489 __le16 sn; 490 u8 ba_en; 491 u8 ba_winsize_idx; 492 /* originator & recipient */ 493 __le16 ba_winsize; 494 /* recipient only */ 495 u8 peer_addr[ETH_ALEN]; 496 u8 rst_ba_tid; 497 u8 rst_ba_sel; 498 u8 rst_ba_sb; 499 u8 band_idx; 500 u8 rsv1[4]; 501 } __packed; 502 503 struct wtbl_smps { 504 __le16 tag; 505 __le16 len; 506 u8 smps; 507 u8 rsv[3]; 508 } __packed; 509 510 /* mt7615 only */ 511 512 struct wtbl_bf { 513 __le16 tag; 514 __le16 len; 515 u8 ibf; 516 u8 ebf; 517 u8 ibf_vht; 518 u8 ebf_vht; 519 u8 gid; 520 u8 pfmu_idx; 521 u8 rsv[2]; 522 } __packed; 523 524 struct wtbl_pn { 525 __le16 tag; 526 __le16 len; 527 u8 pn[6]; 528 u8 rsv[2]; 529 } __packed; 530 531 struct wtbl_spe { 532 __le16 tag; 533 __le16 len; 534 u8 spe_idx; 535 u8 rsv[3]; 536 } __packed; 537 538 struct wtbl_raw { 539 __le16 tag; 540 __le16 len; 541 u8 wtbl_idx; 542 u8 dw; 543 u8 rsv[2]; 544 __le32 msk; 545 __le32 val; 546 } __packed; 547 548 #define MT76_CONNAC_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \ 549 sizeof(struct wtbl_generic) + \ 550 sizeof(struct wtbl_rx) + \ 551 sizeof(struct wtbl_ht) + \ 552 sizeof(struct wtbl_vht) + \ 553 sizeof(struct wtbl_tx_ps) + \ 554 sizeof(struct wtbl_hdr_trans) +\ 555 sizeof(struct wtbl_ba) + \ 556 sizeof(struct wtbl_bf) + \ 557 sizeof(struct wtbl_smps) + \ 558 sizeof(struct wtbl_pn) + \ 559 sizeof(struct wtbl_spe)) 560 561 #define MT76_CONNAC_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 562 sizeof(struct sta_rec_basic) + \ 563 sizeof(struct sta_rec_bf) + \ 564 sizeof(struct sta_rec_ht) + \ 565 sizeof(struct sta_rec_he) + \ 566 sizeof(struct sta_rec_ba) + \ 567 sizeof(struct sta_rec_vht) + \ 568 sizeof(struct sta_rec_uapsd) + \ 569 sizeof(struct sta_rec_amsdu) + \ 570 sizeof(struct sta_rec_muru) + \ 571 sizeof(struct sta_rec_bfee) + \ 572 sizeof(struct sta_rec_ra) + \ 573 sizeof(struct sta_rec_ra_fixed) + \ 574 sizeof(struct sta_rec_he_6g_capa) + \ 575 sizeof(struct tlv) + \ 576 MT76_CONNAC_WTBL_UPDATE_MAX_SIZE) 577 578 enum { 579 STA_REC_BASIC, 580 STA_REC_RA, 581 STA_REC_RA_CMM_INFO, 582 STA_REC_RA_UPDATE, 583 STA_REC_BF, 584 STA_REC_AMSDU, 585 STA_REC_BA, 586 STA_REC_STATE, 587 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */ 588 STA_REC_HT, 589 STA_REC_VHT, 590 STA_REC_APPS, 591 STA_REC_KEY, 592 STA_REC_WTBL, 593 STA_REC_HE, 594 STA_REC_HW_AMSDU, 595 STA_REC_WTBL_AADOM, 596 STA_REC_KEY_V2, 597 STA_REC_MURU, 598 STA_REC_MUEDCA, 599 STA_REC_BFEE, 600 STA_REC_PHY = 0x15, 601 STA_REC_HE_6G = 0x17, 602 STA_REC_MAX_NUM 603 }; 604 605 enum { 606 WTBL_GENERIC, 607 WTBL_RX, 608 WTBL_HT, 609 WTBL_VHT, 610 WTBL_PEER_PS, /* not used */ 611 WTBL_TX_PS, 612 WTBL_HDR_TRANS, 613 WTBL_SEC_KEY, 614 WTBL_BA, 615 WTBL_RDG, /* obsoleted */ 616 WTBL_PROTECT, /* not used */ 617 WTBL_CLEAR, /* not used */ 618 WTBL_BF, 619 WTBL_SMPS, 620 WTBL_RAW_DATA, /* debug only */ 621 WTBL_PN, 622 WTBL_SPE, 623 WTBL_MAX_NUM 624 }; 625 626 #define STA_TYPE_STA BIT(0) 627 #define STA_TYPE_AP BIT(1) 628 #define STA_TYPE_ADHOC BIT(2) 629 #define STA_TYPE_WDS BIT(4) 630 #define STA_TYPE_BC BIT(5) 631 632 #define NETWORK_INFRA BIT(16) 633 #define NETWORK_P2P BIT(17) 634 #define NETWORK_IBSS BIT(18) 635 #define NETWORK_WDS BIT(21) 636 637 #define SCAN_FUNC_RANDOM_MAC BIT(0) 638 #define SCAN_FUNC_SPLIT_SCAN BIT(5) 639 640 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA) 641 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA) 642 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P) 643 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P) 644 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS) 645 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS) 646 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA) 647 648 #define CONN_STATE_DISCONNECT 0 649 #define CONN_STATE_CONNECT 1 650 #define CONN_STATE_PORT_SECURE 2 651 652 /* HE MAC */ 653 #define STA_REC_HE_CAP_HTC BIT(0) 654 #define STA_REC_HE_CAP_BQR BIT(1) 655 #define STA_REC_HE_CAP_BSR BIT(2) 656 #define STA_REC_HE_CAP_OM BIT(3) 657 #define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4) 658 /* HE PHY */ 659 #define STA_REC_HE_CAP_DUAL_BAND BIT(5) 660 #define STA_REC_HE_CAP_LDPC BIT(6) 661 #define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7) 662 #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8) 663 /* STBC */ 664 #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9) 665 #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10) 666 #define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11) 667 #define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12) 668 /* GI */ 669 #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13) 670 #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14) 671 #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15) 672 #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16) 673 #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17) 674 /* 242 TONE */ 675 #define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18) 676 #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19) 677 #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20) 678 679 #define PHY_MODE_A BIT(0) 680 #define PHY_MODE_B BIT(1) 681 #define PHY_MODE_G BIT(2) 682 #define PHY_MODE_GN BIT(3) 683 #define PHY_MODE_AN BIT(4) 684 #define PHY_MODE_AC BIT(5) 685 #define PHY_MODE_AX_24G BIT(6) 686 #define PHY_MODE_AX_5G BIT(7) 687 688 #define PHY_MODE_AX_6G BIT(0) /* phymode_ext */ 689 690 #define MODE_CCK BIT(0) 691 #define MODE_OFDM BIT(1) 692 #define MODE_HT BIT(2) 693 #define MODE_VHT BIT(3) 694 #define MODE_HE BIT(4) 695 696 #define STA_CAP_WMM BIT(0) 697 #define STA_CAP_SGI_20 BIT(4) 698 #define STA_CAP_SGI_40 BIT(5) 699 #define STA_CAP_TX_STBC BIT(6) 700 #define STA_CAP_RX_STBC BIT(7) 701 #define STA_CAP_VHT_SGI_80 BIT(16) 702 #define STA_CAP_VHT_SGI_160 BIT(17) 703 #define STA_CAP_VHT_TX_STBC BIT(18) 704 #define STA_CAP_VHT_RX_STBC BIT(19) 705 #define STA_CAP_VHT_LDPC BIT(23) 706 #define STA_CAP_LDPC BIT(24) 707 #define STA_CAP_HT BIT(26) 708 #define STA_CAP_VHT BIT(27) 709 #define STA_CAP_HE BIT(28) 710 711 enum { 712 PHY_TYPE_HR_DSSS_INDEX = 0, 713 PHY_TYPE_ERP_INDEX, 714 PHY_TYPE_ERP_P2P_INDEX, 715 PHY_TYPE_OFDM_INDEX, 716 PHY_TYPE_HT_INDEX, 717 PHY_TYPE_VHT_INDEX, 718 PHY_TYPE_HE_INDEX, 719 PHY_TYPE_INDEX_NUM 720 }; 721 722 #define PHY_TYPE_BIT_HR_DSSS BIT(PHY_TYPE_HR_DSSS_INDEX) 723 #define PHY_TYPE_BIT_ERP BIT(PHY_TYPE_ERP_INDEX) 724 #define PHY_TYPE_BIT_OFDM BIT(PHY_TYPE_OFDM_INDEX) 725 #define PHY_TYPE_BIT_HT BIT(PHY_TYPE_HT_INDEX) 726 #define PHY_TYPE_BIT_VHT BIT(PHY_TYPE_VHT_INDEX) 727 #define PHY_TYPE_BIT_HE BIT(PHY_TYPE_HE_INDEX) 728 729 #define MT_WTBL_RATE_TX_MODE GENMASK(9, 6) 730 #define MT_WTBL_RATE_MCS GENMASK(5, 0) 731 #define MT_WTBL_RATE_NSS GENMASK(12, 10) 732 #define MT_WTBL_RATE_HE_GI GENMASK(7, 4) 733 #define MT_WTBL_RATE_GI GENMASK(3, 0) 734 735 #define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5) 736 #define MT_WTBL_W5_SHORT_GI_20 BIT(8) 737 #define MT_WTBL_W5_SHORT_GI_40 BIT(9) 738 #define MT_WTBL_W5_SHORT_GI_80 BIT(10) 739 #define MT_WTBL_W5_SHORT_GI_160 BIT(11) 740 #define MT_WTBL_W5_BW_CAP GENMASK(13, 12) 741 #define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23) 742 #define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26) 743 #define MT_WTBL_W5_RATE_IDX GENMASK(31, 29) 744 745 enum { 746 WTBL_RESET_AND_SET = 1, 747 WTBL_SET, 748 WTBL_QUERY, 749 WTBL_RESET_ALL 750 }; 751 752 enum { 753 MT_BA_TYPE_INVALID, 754 MT_BA_TYPE_ORIGINATOR, 755 MT_BA_TYPE_RECIPIENT 756 }; 757 758 enum { 759 RST_BA_MAC_TID_MATCH, 760 RST_BA_MAC_MATCH, 761 RST_BA_NO_MATCH 762 }; 763 764 enum { 765 DEV_INFO_ACTIVE, 766 DEV_INFO_MAX_NUM 767 }; 768 769 /* event table */ 770 enum { 771 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01, 772 MCU_EVENT_FW_START = 0x01, 773 MCU_EVENT_GENERIC = 0x01, 774 MCU_EVENT_ACCESS_REG = 0x02, 775 MCU_EVENT_MT_PATCH_SEM = 0x04, 776 MCU_EVENT_REG_ACCESS = 0x05, 777 MCU_EVENT_LP_INFO = 0x07, 778 MCU_EVENT_SCAN_DONE = 0x0d, 779 MCU_EVENT_TX_DONE = 0x0f, 780 MCU_EVENT_ROC = 0x10, 781 MCU_EVENT_BSS_ABSENCE = 0x11, 782 MCU_EVENT_BSS_BEACON_LOSS = 0x13, 783 MCU_EVENT_CH_PRIVILEGE = 0x18, 784 MCU_EVENT_SCHED_SCAN_DONE = 0x23, 785 MCU_EVENT_DBG_MSG = 0x27, 786 MCU_EVENT_TXPWR = 0xd0, 787 MCU_EVENT_EXT = 0xed, 788 MCU_EVENT_RESTART_DL = 0xef, 789 MCU_EVENT_COREDUMP = 0xf0, 790 }; 791 792 /* ext event table */ 793 enum { 794 MCU_EXT_EVENT_PS_SYNC = 0x5, 795 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13, 796 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22, 797 MCU_EXT_EVENT_ASSERT_DUMP = 0x23, 798 MCU_EXT_EVENT_RDD_REPORT = 0x3a, 799 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f, 800 MCU_EXT_EVENT_BCC_NOTIFY = 0x75, 801 MCU_EXT_EVENT_MURU_CTRL = 0x9f, 802 }; 803 804 enum { 805 MCU_Q_QUERY, 806 MCU_Q_SET, 807 MCU_Q_RESERVED, 808 MCU_Q_NA 809 }; 810 811 enum { 812 MCU_S2D_H2N, 813 MCU_S2D_C2N, 814 MCU_S2D_H2C, 815 MCU_S2D_H2CN 816 }; 817 818 enum { 819 PATCH_NOT_DL_SEM_FAIL, 820 PATCH_IS_DL, 821 PATCH_NOT_DL_SEM_SUCCESS, 822 PATCH_REL_SEM_SUCCESS 823 }; 824 825 enum { 826 FW_STATE_INITIAL, 827 FW_STATE_FW_DOWNLOAD, 828 FW_STATE_NORMAL_OPERATION, 829 FW_STATE_NORMAL_TRX, 830 FW_STATE_RDY = 7 831 }; 832 833 enum { 834 CH_SWITCH_NORMAL = 0, 835 CH_SWITCH_SCAN = 3, 836 CH_SWITCH_MCC = 4, 837 CH_SWITCH_DFS = 5, 838 CH_SWITCH_BACKGROUND_SCAN_START = 6, 839 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7, 840 CH_SWITCH_BACKGROUND_SCAN_STOP = 8, 841 CH_SWITCH_SCAN_BYPASS_DPD = 9 842 }; 843 844 enum { 845 THERMAL_SENSOR_TEMP_QUERY, 846 THERMAL_SENSOR_MANUAL_CTRL, 847 THERMAL_SENSOR_INFO_QUERY, 848 THERMAL_SENSOR_TASK_CTRL, 849 }; 850 851 enum mcu_cipher_type { 852 MCU_CIPHER_NONE = 0, 853 MCU_CIPHER_WEP40, 854 MCU_CIPHER_WEP104, 855 MCU_CIPHER_WEP128, 856 MCU_CIPHER_TKIP, 857 MCU_CIPHER_AES_CCMP, 858 MCU_CIPHER_CCMP_256, 859 MCU_CIPHER_GCMP, 860 MCU_CIPHER_GCMP_256, 861 MCU_CIPHER_WAPI, 862 MCU_CIPHER_BIP_CMAC_128, 863 }; 864 865 enum { 866 EE_MODE_EFUSE, 867 EE_MODE_BUFFER, 868 }; 869 870 enum { 871 EE_FORMAT_BIN, 872 EE_FORMAT_WHOLE, 873 EE_FORMAT_MULTIPLE, 874 }; 875 876 enum { 877 MCU_PHY_STATE_TX_RATE, 878 MCU_PHY_STATE_RX_RATE, 879 MCU_PHY_STATE_RSSI, 880 MCU_PHY_STATE_CONTENTION_RX_RATE, 881 MCU_PHY_STATE_OFDMLQ_CNINFO, 882 }; 883 884 #define MCU_CMD_ACK BIT(0) 885 #define MCU_CMD_UNI BIT(1) 886 #define MCU_CMD_QUERY BIT(2) 887 888 #define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | \ 889 MCU_CMD_QUERY) 890 891 #define __MCU_CMD_FIELD_ID GENMASK(7, 0) 892 #define __MCU_CMD_FIELD_EXT_ID GENMASK(15, 8) 893 #define __MCU_CMD_FIELD_QUERY BIT(16) 894 #define __MCU_CMD_FIELD_UNI BIT(17) 895 #define __MCU_CMD_FIELD_CE BIT(18) 896 #define __MCU_CMD_FIELD_WA BIT(19) 897 898 #define MCU_CMD(_t) FIELD_PREP(__MCU_CMD_FIELD_ID, \ 899 MCU_CMD_##_t) 900 #define MCU_EXT_CMD(_t) (MCU_CMD(EXT_CID) | \ 901 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ 902 MCU_EXT_CMD_##_t)) 903 #define MCU_EXT_QUERY(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_QUERY) 904 #define MCU_UNI_CMD(_t) (__MCU_CMD_FIELD_UNI | \ 905 FIELD_PREP(__MCU_CMD_FIELD_ID, \ 906 MCU_UNI_CMD_##_t)) 907 #define MCU_CE_CMD(_t) (__MCU_CMD_FIELD_CE | \ 908 FIELD_PREP(__MCU_CMD_FIELD_ID, \ 909 MCU_CE_CMD_##_t)) 910 #define MCU_CE_QUERY(_t) (MCU_CE_CMD(_t) | __MCU_CMD_FIELD_QUERY) 911 912 #define MCU_WA_CMD(_t) (MCU_CMD(_t) | __MCU_CMD_FIELD_WA) 913 #define MCU_WA_EXT_CMD(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_WA) 914 #define MCU_WA_PARAM_CMD(_t) (MCU_WA_CMD(WA_PARAM) | \ 915 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ 916 MCU_WA_PARAM_CMD_##_t)) 917 918 enum { 919 MCU_EXT_CMD_EFUSE_ACCESS = 0x01, 920 MCU_EXT_CMD_RF_REG_ACCESS = 0x02, 921 MCU_EXT_CMD_RF_TEST = 0x04, 922 MCU_EXT_CMD_PM_STATE_CTRL = 0x07, 923 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08, 924 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11, 925 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13, 926 MCU_EXT_CMD_TXBF_ACTION = 0x1e, 927 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21, 928 MCU_EXT_CMD_THERMAL_PROT = 0x23, 929 MCU_EXT_CMD_STA_REC_UPDATE = 0x25, 930 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26, 931 MCU_EXT_CMD_EDCA_UPDATE = 0x27, 932 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A, 933 MCU_EXT_CMD_THERMAL_CTRL = 0x2c, 934 MCU_EXT_CMD_WTBL_UPDATE = 0x32, 935 MCU_EXT_CMD_SET_DRR_CTRL = 0x36, 936 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a, 937 MCU_EXT_CMD_ATE_CTRL = 0x3d, 938 MCU_EXT_CMD_PROTECT_CTRL = 0x3e, 939 MCU_EXT_CMD_DBDC_CTRL = 0x45, 940 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46, 941 MCU_EXT_CMD_RX_HDR_TRANS = 0x47, 942 MCU_EXT_CMD_MUAR_UPDATE = 0x48, 943 MCU_EXT_CMD_BCN_OFFLOAD = 0x49, 944 MCU_EXT_CMD_RX_AIRTIME_CTRL = 0x4a, 945 MCU_EXT_CMD_SET_RX_PATH = 0x4e, 946 MCU_EXT_CMD_EFUSE_FREE_BLOCK = 0x4f, 947 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58, 948 MCU_EXT_CMD_RXDCOC_CAL = 0x59, 949 MCU_EXT_CMD_GET_MIB_INFO = 0x5a, 950 MCU_EXT_CMD_TXDPD_CAL = 0x60, 951 MCU_EXT_CMD_CAL_CACHE = 0x67, 952 MCU_EXT_CMD_SET_RADAR_TH = 0x7c, 953 MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d, 954 MCU_EXT_CMD_MWDS_SUPPORT = 0x80, 955 MCU_EXT_CMD_SET_SER_TRIGGER = 0x81, 956 MCU_EXT_CMD_SCS_CTRL = 0x82, 957 MCU_EXT_CMD_TWT_AGRT_UPDATE = 0x94, 958 MCU_EXT_CMD_FW_DBG_CTRL = 0x95, 959 MCU_EXT_CMD_SET_RDD_TH = 0x9d, 960 MCU_EXT_CMD_MURU_CTRL = 0x9f, 961 MCU_EXT_CMD_SET_SPR = 0xa8, 962 MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab, 963 MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac, 964 MCU_EXT_CMD_PHY_STAT_INFO = 0xad, 965 }; 966 967 enum { 968 MCU_UNI_CMD_DEV_INFO_UPDATE = 0x01, 969 MCU_UNI_CMD_BSS_INFO_UPDATE = 0x02, 970 MCU_UNI_CMD_STA_REC_UPDATE = 0x03, 971 MCU_UNI_CMD_SUSPEND = 0x05, 972 MCU_UNI_CMD_OFFLOAD = 0x06, 973 MCU_UNI_CMD_HIF_CTRL = 0x07, 974 }; 975 976 enum { 977 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01, 978 MCU_CMD_FW_START_REQ = 0x02, 979 MCU_CMD_INIT_ACCESS_REG = 0x3, 980 MCU_CMD_NIC_POWER_CTRL = 0x4, 981 MCU_CMD_PATCH_START_REQ = 0x05, 982 MCU_CMD_PATCH_FINISH_REQ = 0x07, 983 MCU_CMD_PATCH_SEM_CONTROL = 0x10, 984 MCU_CMD_WA_PARAM = 0xc4, 985 MCU_CMD_EXT_CID = 0xed, 986 MCU_CMD_FW_SCATTER = 0xee, 987 MCU_CMD_RESTART_DL_REQ = 0xef, 988 }; 989 990 /* offload mcu commands */ 991 enum { 992 MCU_CE_CMD_TEST_CTRL = 0x01, 993 MCU_CE_CMD_START_HW_SCAN = 0x03, 994 MCU_CE_CMD_SET_PS_PROFILE = 0x05, 995 MCU_CE_CMD_SET_CHAN_DOMAIN = 0x0f, 996 MCU_CE_CMD_SET_BSS_CONNECTED = 0x16, 997 MCU_CE_CMD_SET_BSS_ABORT = 0x17, 998 MCU_CE_CMD_CANCEL_HW_SCAN = 0x1b, 999 MCU_CE_CMD_SET_ROC = 0x1d, 1000 MCU_CE_CMD_SET_P2P_OPPPS = 0x33, 1001 MCU_CE_CMD_SET_RATE_TX_POWER = 0x5d, 1002 MCU_CE_CMD_SCHED_SCAN_ENABLE = 0x61, 1003 MCU_CE_CMD_SCHED_SCAN_REQ = 0x62, 1004 MCU_CE_CMD_GET_NIC_CAPAB = 0x8a, 1005 MCU_CE_CMD_SET_MU_EDCA_PARMS = 0xb0, 1006 MCU_CE_CMD_REG_WRITE = 0xc0, 1007 MCU_CE_CMD_REG_READ = 0xc0, 1008 MCU_CE_CMD_CHIP_CONFIG = 0xca, 1009 MCU_CE_CMD_FWLOG_2_HOST = 0xc5, 1010 MCU_CE_CMD_GET_WTBL = 0xcd, 1011 MCU_CE_CMD_GET_TXPWR = 0xd0, 1012 }; 1013 1014 enum { 1015 PATCH_SEM_RELEASE, 1016 PATCH_SEM_GET 1017 }; 1018 1019 enum { 1020 UNI_BSS_INFO_BASIC = 0, 1021 UNI_BSS_INFO_RLM = 2, 1022 UNI_BSS_INFO_BSS_COLOR = 4, 1023 UNI_BSS_INFO_HE_BASIC = 5, 1024 UNI_BSS_INFO_BCN_CONTENT = 7, 1025 UNI_BSS_INFO_QBSS = 15, 1026 UNI_BSS_INFO_UAPSD = 19, 1027 UNI_BSS_INFO_PS = 21, 1028 UNI_BSS_INFO_BCNFT = 22, 1029 }; 1030 1031 enum { 1032 UNI_OFFLOAD_OFFLOAD_ARP, 1033 UNI_OFFLOAD_OFFLOAD_ND, 1034 UNI_OFFLOAD_OFFLOAD_GTK_REKEY, 1035 UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT, 1036 }; 1037 1038 enum { 1039 MT_NIC_CAP_TX_RESOURCE, 1040 MT_NIC_CAP_TX_EFUSE_ADDR, 1041 MT_NIC_CAP_COEX, 1042 MT_NIC_CAP_SINGLE_SKU, 1043 MT_NIC_CAP_CSUM_OFFLOAD, 1044 MT_NIC_CAP_HW_VER, 1045 MT_NIC_CAP_SW_VER, 1046 MT_NIC_CAP_MAC_ADDR, 1047 MT_NIC_CAP_PHY, 1048 MT_NIC_CAP_MAC, 1049 MT_NIC_CAP_FRAME_BUF, 1050 MT_NIC_CAP_BEAM_FORM, 1051 MT_NIC_CAP_LOCATION, 1052 MT_NIC_CAP_MUMIMO, 1053 MT_NIC_CAP_BUFFER_MODE_INFO, 1054 MT_NIC_CAP_HW_ADIE_VERSION = 0x14, 1055 MT_NIC_CAP_ANTSWP = 0x16, 1056 MT_NIC_CAP_WFDMA_REALLOC, 1057 MT_NIC_CAP_6G, 1058 }; 1059 1060 #define UNI_WOW_DETECT_TYPE_MAGIC BIT(0) 1061 #define UNI_WOW_DETECT_TYPE_ANY BIT(1) 1062 #define UNI_WOW_DETECT_TYPE_DISCONNECT BIT(2) 1063 #define UNI_WOW_DETECT_TYPE_GTK_REKEY_FAIL BIT(3) 1064 #define UNI_WOW_DETECT_TYPE_BCN_LOST BIT(4) 1065 #define UNI_WOW_DETECT_TYPE_SCH_SCAN_HIT BIT(5) 1066 #define UNI_WOW_DETECT_TYPE_BITMAP BIT(6) 1067 1068 enum { 1069 UNI_SUSPEND_MODE_SETTING, 1070 UNI_SUSPEND_WOW_CTRL, 1071 UNI_SUSPEND_WOW_GPIO_PARAM, 1072 UNI_SUSPEND_WOW_WAKEUP_PORT, 1073 UNI_SUSPEND_WOW_PATTERN, 1074 }; 1075 1076 enum { 1077 WOW_USB = 1, 1078 WOW_PCIE = 2, 1079 WOW_GPIO = 3, 1080 }; 1081 1082 struct mt76_connac_bss_basic_tlv { 1083 __le16 tag; 1084 __le16 len; 1085 u8 active; 1086 u8 omac_idx; 1087 u8 hw_bss_idx; 1088 u8 band_idx; 1089 __le32 conn_type; 1090 u8 conn_state; 1091 u8 wmm_idx; 1092 u8 bssid[ETH_ALEN]; 1093 __le16 bmc_tx_wlan_idx; 1094 __le16 bcn_interval; 1095 u8 dtim_period; 1096 u8 phymode; /* bit(0): A 1097 * bit(1): B 1098 * bit(2): G 1099 * bit(3): GN 1100 * bit(4): AN 1101 * bit(5): AC 1102 * bit(6): AX2 1103 * bit(7): AX5 1104 * bit(8): AX6 1105 */ 1106 __le16 sta_idx; 1107 __le16 nonht_basic_phy; 1108 u8 phymode_ext; /* bit(0) AX_6G */ 1109 u8 pad[1]; 1110 } __packed; 1111 1112 struct mt76_connac_bss_qos_tlv { 1113 __le16 tag; 1114 __le16 len; 1115 u8 qos; 1116 u8 pad[3]; 1117 } __packed; 1118 1119 struct mt76_connac_beacon_loss_event { 1120 u8 bss_idx; 1121 u8 reason; 1122 u8 pad[2]; 1123 } __packed; 1124 1125 struct mt76_connac_mcu_bss_event { 1126 u8 bss_idx; 1127 u8 is_absent; 1128 u8 free_quota; 1129 u8 pad; 1130 } __packed; 1131 1132 struct mt76_connac_mcu_scan_ssid { 1133 __le32 ssid_len; 1134 u8 ssid[IEEE80211_MAX_SSID_LEN]; 1135 } __packed; 1136 1137 struct mt76_connac_mcu_scan_channel { 1138 u8 band; /* 1: 2.4GHz 1139 * 2: 5.0GHz 1140 * Others: Reserved 1141 */ 1142 u8 channel_num; 1143 } __packed; 1144 1145 struct mt76_connac_mcu_scan_match { 1146 __le32 rssi_th; 1147 u8 ssid[IEEE80211_MAX_SSID_LEN]; 1148 u8 ssid_len; 1149 u8 rsv[3]; 1150 } __packed; 1151 1152 struct mt76_connac_hw_scan_req { 1153 u8 seq_num; 1154 u8 bss_idx; 1155 u8 scan_type; /* 0: PASSIVE SCAN 1156 * 1: ACTIVE SCAN 1157 */ 1158 u8 ssid_type; /* BIT(0) wildcard SSID 1159 * BIT(1) P2P wildcard SSID 1160 * BIT(2) specified SSID + wildcard SSID 1161 * BIT(2) + ssid_type_ext BIT(0) specified SSID only 1162 */ 1163 u8 ssids_num; 1164 u8 probe_req_num; /* Number of probe request for each SSID */ 1165 u8 scan_func; /* BIT(0) Enable random MAC scan 1166 * BIT(1) Disable DBDC scan type 1~3. 1167 * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan). 1168 */ 1169 u8 version; /* 0: Not support fields after ies. 1170 * 1: Support fields after ies. 1171 */ 1172 struct mt76_connac_mcu_scan_ssid ssids[4]; 1173 __le16 probe_delay_time; 1174 __le16 channel_dwell_time; /* channel Dwell interval */ 1175 __le16 timeout_value; 1176 u8 channel_type; /* 0: Full channels 1177 * 1: Only 2.4GHz channels 1178 * 2: Only 5GHz channels 1179 * 3: P2P social channel only (channel #1, #6 and #11) 1180 * 4: Specified channels 1181 * Others: Reserved 1182 */ 1183 u8 channels_num; /* valid when channel_type is 4 */ 1184 /* valid when channels_num is set */ 1185 struct mt76_connac_mcu_scan_channel channels[32]; 1186 __le16 ies_len; 1187 u8 ies[MT76_CONNAC_SCAN_IE_LEN]; 1188 /* following fields are valid if version > 0 */ 1189 u8 ext_channels_num; 1190 u8 ext_ssids_num; 1191 __le16 channel_min_dwell_time; 1192 struct mt76_connac_mcu_scan_channel ext_channels[32]; 1193 struct mt76_connac_mcu_scan_ssid ext_ssids[6]; 1194 u8 bssid[ETH_ALEN]; 1195 u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */ 1196 u8 pad[63]; 1197 u8 ssid_type_ext; 1198 } __packed; 1199 1200 #define MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM 64 1201 1202 struct mt76_connac_hw_scan_done { 1203 u8 seq_num; 1204 u8 sparse_channel_num; 1205 struct mt76_connac_mcu_scan_channel sparse_channel; 1206 u8 complete_channel_num; 1207 u8 current_state; 1208 u8 version; 1209 u8 pad; 1210 __le32 beacon_scan_num; 1211 u8 pno_enabled; 1212 u8 pad2[3]; 1213 u8 sparse_channel_valid_num; 1214 u8 pad3[3]; 1215 u8 channel_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1216 /* idle format for channel_idle_time 1217 * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms) 1218 * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms) 1219 * 2: dwell time (16us) 1220 */ 1221 __le16 channel_idle_time[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1222 /* beacon and probe response count */ 1223 u8 beacon_probe_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1224 u8 mdrdy_count[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1225 __le32 beacon_2g_num; 1226 __le32 beacon_5g_num; 1227 } __packed; 1228 1229 struct mt76_connac_sched_scan_req { 1230 u8 version; 1231 u8 seq_num; 1232 u8 stop_on_match; 1233 u8 ssids_num; 1234 u8 match_num; 1235 u8 pad; 1236 __le16 ie_len; 1237 struct mt76_connac_mcu_scan_ssid ssids[MT76_CONNAC_MAX_SCHED_SCAN_SSID]; 1238 struct mt76_connac_mcu_scan_match match[MT76_CONNAC_MAX_SCAN_MATCH]; 1239 u8 channel_type; 1240 u8 channels_num; 1241 u8 intervals_num; 1242 u8 scan_func; /* MT7663: BIT(0) eable random mac address */ 1243 struct mt76_connac_mcu_scan_channel channels[64]; 1244 __le16 intervals[MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL]; 1245 union { 1246 struct { 1247 u8 random_mac[ETH_ALEN]; 1248 u8 pad2[58]; 1249 } mt7663; 1250 struct { 1251 u8 bss_idx; 1252 u8 pad1[3]; 1253 __le32 delay; 1254 u8 pad2[12]; 1255 u8 random_mac[ETH_ALEN]; 1256 u8 pad3[38]; 1257 } mt7921; 1258 }; 1259 } __packed; 1260 1261 struct mt76_connac_sched_scan_done { 1262 u8 seq_num; 1263 u8 status; /* 0: ssid found */ 1264 __le16 pad; 1265 } __packed; 1266 1267 struct bss_info_uni_bss_color { 1268 __le16 tag; 1269 __le16 len; 1270 u8 enable; 1271 u8 bss_color; 1272 u8 rsv[2]; 1273 } __packed; 1274 1275 struct bss_info_uni_he { 1276 __le16 tag; 1277 __le16 len; 1278 __le16 he_rts_thres; 1279 u8 he_pe_duration; 1280 u8 su_disable; 1281 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 1282 u8 rsv[2]; 1283 } __packed; 1284 1285 struct mt76_connac_gtk_rekey_tlv { 1286 __le16 tag; 1287 __le16 len; 1288 u8 kek[NL80211_KEK_LEN]; 1289 u8 kck[NL80211_KCK_LEN]; 1290 u8 replay_ctr[NL80211_REPLAY_CTR_LEN]; 1291 u8 rekey_mode; /* 0: rekey offload enable 1292 * 1: rekey offload disable 1293 * 2: rekey update 1294 */ 1295 u8 keyid; 1296 u8 option; /* 1: rekey data update without enabling offload */ 1297 u8 pad[1]; 1298 __le32 proto; /* WPA-RSN-WAPI-OPSN */ 1299 __le32 pairwise_cipher; 1300 __le32 group_cipher; 1301 __le32 key_mgmt; /* NONE-PSK-IEEE802.1X */ 1302 __le32 mgmt_group_cipher; 1303 u8 reserverd[4]; 1304 } __packed; 1305 1306 #define MT76_CONNAC_WOW_MASK_MAX_LEN 16 1307 #define MT76_CONNAC_WOW_PATTEN_MAX_LEN 128 1308 1309 struct mt76_connac_wow_pattern_tlv { 1310 __le16 tag; 1311 __le16 len; 1312 u8 index; /* pattern index */ 1313 u8 enable; /* 0: disable 1314 * 1: enable 1315 */ 1316 u8 data_len; /* pattern length */ 1317 u8 pad; 1318 u8 mask[MT76_CONNAC_WOW_MASK_MAX_LEN]; 1319 u8 pattern[MT76_CONNAC_WOW_PATTEN_MAX_LEN]; 1320 u8 rsv[4]; 1321 } __packed; 1322 1323 struct mt76_connac_wow_ctrl_tlv { 1324 __le16 tag; 1325 __le16 len; 1326 u8 cmd; /* 0x1: PM_WOWLAN_REQ_START 1327 * 0x2: PM_WOWLAN_REQ_STOP 1328 * 0x3: PM_WOWLAN_PARAM_CLEAR 1329 */ 1330 u8 trigger; /* 0: NONE 1331 * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT 1332 * BIT(1): NL80211_WOWLAN_TRIG_ANY 1333 * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT 1334 * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE 1335 * BIT(4): BEACON_LOST 1336 * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT 1337 */ 1338 u8 wakeup_hif; /* 0x0: HIF_SDIO 1339 * 0x1: HIF_USB 1340 * 0x2: HIF_PCIE 1341 * 0x3: HIF_GPIO 1342 */ 1343 u8 pad; 1344 u8 rsv[4]; 1345 } __packed; 1346 1347 struct mt76_connac_wow_gpio_param_tlv { 1348 __le16 tag; 1349 __le16 len; 1350 u8 gpio_pin; 1351 u8 trigger_lvl; 1352 u8 pad[2]; 1353 __le32 gpio_interval; 1354 u8 rsv[4]; 1355 } __packed; 1356 1357 struct mt76_connac_arpns_tlv { 1358 __le16 tag; 1359 __le16 len; 1360 u8 mode; 1361 u8 ips_num; 1362 u8 option; 1363 u8 pad[1]; 1364 } __packed; 1365 1366 struct mt76_connac_suspend_tlv { 1367 __le16 tag; 1368 __le16 len; 1369 u8 enable; /* 0: suspend mode disabled 1370 * 1: suspend mode enabled 1371 */ 1372 u8 mdtim; /* LP parameter */ 1373 u8 wow_suspend; /* 0: update by origin policy 1374 * 1: update by wow dtim 1375 */ 1376 u8 pad[5]; 1377 } __packed; 1378 1379 enum mt76_sta_info_state { 1380 MT76_STA_INFO_STATE_NONE, 1381 MT76_STA_INFO_STATE_AUTH, 1382 MT76_STA_INFO_STATE_ASSOC 1383 }; 1384 1385 struct mt76_sta_cmd_info { 1386 struct ieee80211_sta *sta; 1387 struct mt76_wcid *wcid; 1388 1389 struct ieee80211_vif *vif; 1390 1391 bool offload_fw; 1392 bool enable; 1393 bool newly; 1394 int cmd; 1395 u8 rcpi; 1396 u8 state; 1397 }; 1398 1399 #define MT_SKU_POWER_LIMIT 161 1400 1401 struct mt76_connac_sku_tlv { 1402 u8 channel; 1403 s8 pwr_limit[MT_SKU_POWER_LIMIT]; 1404 } __packed; 1405 1406 struct mt76_connac_tx_power_limit_tlv { 1407 /* DW0 - common info*/ 1408 u8 ver; 1409 u8 pad0; 1410 __le16 len; 1411 /* DW1 - cmd hint */ 1412 u8 n_chan; /* # channel */ 1413 u8 band; /* 2.4GHz - 5GHz - 6GHz */ 1414 u8 last_msg; 1415 u8 pad1; 1416 /* DW3 */ 1417 u8 alpha2[4]; /* regulatory_request.alpha2 */ 1418 u8 pad2[32]; 1419 } __packed; 1420 1421 struct mt76_connac_config { 1422 __le16 id; 1423 u8 type; 1424 u8 resp_type; 1425 __le16 data_size; 1426 __le16 resv; 1427 u8 data[320]; 1428 } __packed; 1429 1430 #define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id) 1431 #define to_wcid_hi(id) FIELD_GET(GENMASK(9, 8), (u16)id) 1432 1433 static inline void 1434 mt76_connac_mcu_get_wlan_idx(struct mt76_dev *dev, struct mt76_wcid *wcid, 1435 u8 *wlan_idx_lo, u8 *wlan_idx_hi) 1436 { 1437 *wlan_idx_hi = 0; 1438 1439 if (is_mt7921(dev)) { 1440 *wlan_idx_lo = wcid ? to_wcid_lo(wcid->idx) : 0; 1441 *wlan_idx_hi = wcid ? to_wcid_hi(wcid->idx) : 0; 1442 } else { 1443 *wlan_idx_lo = wcid ? wcid->idx : 0; 1444 } 1445 } 1446 1447 struct sk_buff * 1448 mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif, 1449 struct mt76_wcid *wcid); 1450 struct wtbl_req_hdr * 1451 mt76_connac_mcu_alloc_wtbl_req(struct mt76_dev *dev, struct mt76_wcid *wcid, 1452 int cmd, void *sta_wtbl, struct sk_buff **skb); 1453 struct tlv *mt76_connac_mcu_add_nested_tlv(struct sk_buff *skb, int tag, 1454 int len, void *sta_ntlv, 1455 void *sta_wtbl); 1456 static inline struct tlv * 1457 mt76_connac_mcu_add_tlv(struct sk_buff *skb, int tag, int len) 1458 { 1459 return mt76_connac_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL); 1460 } 1461 1462 int mt76_connac_mcu_set_channel_domain(struct mt76_phy *phy); 1463 int mt76_connac_mcu_set_vif_ps(struct mt76_dev *dev, struct ieee80211_vif *vif); 1464 void mt76_connac_mcu_sta_basic_tlv(struct sk_buff *skb, 1465 struct ieee80211_vif *vif, 1466 struct ieee80211_sta *sta, bool enable, 1467 bool newly); 1468 void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1469 struct ieee80211_vif *vif, 1470 struct ieee80211_sta *sta, void *sta_wtbl, 1471 void *wtbl_tlv); 1472 void mt76_connac_mcu_wtbl_hdr_trans_tlv(struct sk_buff *skb, 1473 struct ieee80211_vif *vif, 1474 struct mt76_wcid *wcid, 1475 void *sta_wtbl, void *wtbl_tlv); 1476 int mt76_connac_mcu_sta_update_hdr_trans(struct mt76_dev *dev, 1477 struct ieee80211_vif *vif, 1478 struct mt76_wcid *wcid, int cmd); 1479 void mt76_connac_mcu_sta_tlv(struct mt76_phy *mphy, struct sk_buff *skb, 1480 struct ieee80211_sta *sta, 1481 struct ieee80211_vif *vif, 1482 u8 rcpi, u8 state); 1483 void mt76_connac_mcu_wtbl_ht_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1484 struct ieee80211_sta *sta, void *sta_wtbl, 1485 void *wtbl_tlv); 1486 void mt76_connac_mcu_wtbl_ba_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1487 struct ieee80211_ampdu_params *params, 1488 bool enable, bool tx, void *sta_wtbl, 1489 void *wtbl_tlv); 1490 void mt76_connac_mcu_sta_ba_tlv(struct sk_buff *skb, 1491 struct ieee80211_ampdu_params *params, 1492 bool enable, bool tx); 1493 int mt76_connac_mcu_uni_add_dev(struct mt76_phy *phy, 1494 struct ieee80211_vif *vif, 1495 struct mt76_wcid *wcid, 1496 bool enable); 1497 int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif, 1498 struct ieee80211_ampdu_params *params, 1499 bool enable, bool tx); 1500 int mt76_connac_mcu_uni_add_bss(struct mt76_phy *phy, 1501 struct ieee80211_vif *vif, 1502 struct mt76_wcid *wcid, 1503 bool enable); 1504 int mt76_connac_mcu_sta_cmd(struct mt76_phy *phy, 1505 struct mt76_sta_cmd_info *info); 1506 void mt76_connac_mcu_beacon_loss_iter(void *priv, u8 *mac, 1507 struct ieee80211_vif *vif); 1508 int mt76_connac_mcu_set_rts_thresh(struct mt76_dev *dev, u32 val, u8 band); 1509 int mt76_connac_mcu_set_mac_enable(struct mt76_dev *dev, int band, bool enable, 1510 bool hdr_trans); 1511 int mt76_connac_mcu_init_download(struct mt76_dev *dev, u32 addr, u32 len, 1512 u32 mode); 1513 int mt76_connac_mcu_start_patch(struct mt76_dev *dev); 1514 int mt76_connac_mcu_patch_sem_ctrl(struct mt76_dev *dev, bool get); 1515 int mt76_connac_mcu_start_firmware(struct mt76_dev *dev, u32 addr, u32 option); 1516 int mt76_connac_mcu_get_nic_capability(struct mt76_phy *phy); 1517 1518 int mt76_connac_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif, 1519 struct ieee80211_scan_request *scan_req); 1520 int mt76_connac_mcu_cancel_hw_scan(struct mt76_phy *phy, 1521 struct ieee80211_vif *vif); 1522 int mt76_connac_mcu_sched_scan_req(struct mt76_phy *phy, 1523 struct ieee80211_vif *vif, 1524 struct cfg80211_sched_scan_request *sreq); 1525 int mt76_connac_mcu_sched_scan_enable(struct mt76_phy *phy, 1526 struct ieee80211_vif *vif, 1527 bool enable); 1528 int mt76_connac_mcu_update_arp_filter(struct mt76_dev *dev, 1529 struct mt76_vif *vif, 1530 struct ieee80211_bss_conf *info); 1531 int mt76_connac_mcu_update_gtk_rekey(struct ieee80211_hw *hw, 1532 struct ieee80211_vif *vif, 1533 struct cfg80211_gtk_rekey_data *key); 1534 int mt76_connac_mcu_set_hif_suspend(struct mt76_dev *dev, bool suspend); 1535 void mt76_connac_mcu_set_suspend_iter(void *priv, u8 *mac, 1536 struct ieee80211_vif *vif); 1537 int mt76_connac_sta_state_dp(struct mt76_dev *dev, 1538 enum ieee80211_sta_state old_state, 1539 enum ieee80211_sta_state new_state); 1540 int mt76_connac_mcu_chip_config(struct mt76_dev *dev); 1541 int mt76_connac_mcu_set_deep_sleep(struct mt76_dev *dev, bool enable); 1542 void mt76_connac_mcu_coredump_event(struct mt76_dev *dev, struct sk_buff *skb, 1543 struct mt76_connac_coredump *coredump); 1544 int mt76_connac_mcu_set_rate_txpower(struct mt76_phy *phy); 1545 int mt76_connac_mcu_set_p2p_oppps(struct ieee80211_hw *hw, 1546 struct ieee80211_vif *vif); 1547 u32 mt76_connac_mcu_reg_rr(struct mt76_dev *dev, u32 offset); 1548 void mt76_connac_mcu_reg_wr(struct mt76_dev *dev, u32 offset, u32 val); 1549 #endif /* __MT76_CONNAC_MCU_H */ 1550