1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT76_CONNAC_MCU_H 5 #define __MT76_CONNAC_MCU_H 6 7 #include "mt76_connac.h" 8 9 struct tlv { 10 __le16 tag; 11 __le16 len; 12 } __packed; 13 14 /* sta_rec */ 15 16 struct sta_ntlv_hdr { 17 u8 rsv[2]; 18 __le16 tlv_num; 19 } __packed; 20 21 struct sta_req_hdr { 22 u8 bss_idx; 23 u8 wlan_idx_lo; 24 __le16 tlv_num; 25 u8 is_tlv_append; 26 u8 muar_idx; 27 u8 wlan_idx_hi; 28 u8 rsv; 29 } __packed; 30 31 struct sta_rec_basic { 32 __le16 tag; 33 __le16 len; 34 __le32 conn_type; 35 u8 conn_state; 36 u8 qos; 37 __le16 aid; 38 u8 peer_addr[ETH_ALEN]; 39 #define EXTRA_INFO_VER BIT(0) 40 #define EXTRA_INFO_NEW BIT(1) 41 __le16 extra_info; 42 } __packed; 43 44 struct sta_rec_ht { 45 __le16 tag; 46 __le16 len; 47 __le16 ht_cap; 48 u16 rsv; 49 } __packed; 50 51 struct sta_rec_vht { 52 __le16 tag; 53 __le16 len; 54 __le32 vht_cap; 55 __le16 vht_rx_mcs_map; 56 __le16 vht_tx_mcs_map; 57 /* mt7921 */ 58 u8 rts_bw_sig; 59 u8 rsv[3]; 60 } __packed; 61 62 struct sta_rec_uapsd { 63 __le16 tag; 64 __le16 len; 65 u8 dac_map; 66 u8 tac_map; 67 u8 max_sp; 68 u8 rsv0; 69 __le16 listen_interval; 70 u8 rsv1[2]; 71 } __packed; 72 73 struct sta_rec_ba { 74 __le16 tag; 75 __le16 len; 76 u8 tid; 77 u8 ba_type; 78 u8 amsdu; 79 u8 ba_en; 80 __le16 ssn; 81 __le16 winsize; 82 } __packed; 83 84 struct sta_rec_he { 85 __le16 tag; 86 __le16 len; 87 88 __le32 he_cap; 89 90 u8 t_frame_dur; 91 u8 max_ampdu_exp; 92 u8 bw_set; 93 u8 device_class; 94 u8 dcm_tx_mode; 95 u8 dcm_tx_max_nss; 96 u8 dcm_rx_mode; 97 u8 dcm_rx_max_nss; 98 u8 dcm_max_ru; 99 u8 punc_pream_rx; 100 u8 pkt_ext; 101 u8 rsv1; 102 103 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 104 105 u8 rsv2[2]; 106 } __packed; 107 108 struct sta_rec_amsdu { 109 __le16 tag; 110 __le16 len; 111 u8 max_amsdu_num; 112 u8 max_mpdu_size; 113 u8 amsdu_en; 114 u8 rsv; 115 } __packed; 116 117 struct sta_rec_state { 118 __le16 tag; 119 __le16 len; 120 __le32 flags; 121 u8 state; 122 u8 vht_opmode; 123 u8 action; 124 u8 rsv[1]; 125 } __packed; 126 127 #define HT_MCS_MASK_NUM 10 128 struct sta_rec_ra_info { 129 __le16 tag; 130 __le16 len; 131 __le16 legacy; 132 u8 rx_mcs_bitmask[HT_MCS_MASK_NUM]; 133 } __packed; 134 135 struct sta_rec_phy { 136 __le16 tag; 137 __le16 len; 138 __le16 basic_rate; 139 u8 phy_type; 140 u8 ampdu; 141 u8 rts_policy; 142 u8 rcpi; 143 u8 rsv[2]; 144 } __packed; 145 146 /* wtbl_rec */ 147 148 struct wtbl_req_hdr { 149 u8 wlan_idx_lo; 150 u8 operation; 151 __le16 tlv_num; 152 u8 wlan_idx_hi; 153 u8 rsv[3]; 154 } __packed; 155 156 struct wtbl_generic { 157 __le16 tag; 158 __le16 len; 159 u8 peer_addr[ETH_ALEN]; 160 u8 muar_idx; 161 u8 skip_tx; 162 u8 cf_ack; 163 u8 qos; 164 u8 mesh; 165 u8 adm; 166 __le16 partial_aid; 167 u8 baf_en; 168 u8 aad_om; 169 } __packed; 170 171 struct wtbl_rx { 172 __le16 tag; 173 __le16 len; 174 u8 rcid; 175 u8 rca1; 176 u8 rca2; 177 u8 rv; 178 u8 rsv[4]; 179 } __packed; 180 181 struct wtbl_ht { 182 __le16 tag; 183 __le16 len; 184 u8 ht; 185 u8 ldpc; 186 u8 af; 187 u8 mm; 188 u8 rsv[4]; 189 } __packed; 190 191 struct wtbl_vht { 192 __le16 tag; 193 __le16 len; 194 u8 ldpc; 195 u8 dyn_bw; 196 u8 vht; 197 u8 txop_ps; 198 u8 rsv[4]; 199 } __packed; 200 201 struct wtbl_tx_ps { 202 __le16 tag; 203 __le16 len; 204 u8 txps; 205 u8 rsv[3]; 206 } __packed; 207 208 struct wtbl_hdr_trans { 209 __le16 tag; 210 __le16 len; 211 u8 to_ds; 212 u8 from_ds; 213 u8 no_rx_trans; 214 u8 rsv; 215 } __packed; 216 217 struct wtbl_ba { 218 __le16 tag; 219 __le16 len; 220 /* common */ 221 u8 tid; 222 u8 ba_type; 223 u8 rsv0[2]; 224 /* originator only */ 225 __le16 sn; 226 u8 ba_en; 227 u8 ba_winsize_idx; 228 __le16 ba_winsize; 229 /* recipient only */ 230 u8 peer_addr[ETH_ALEN]; 231 u8 rst_ba_tid; 232 u8 rst_ba_sel; 233 u8 rst_ba_sb; 234 u8 band_idx; 235 u8 rsv1[4]; 236 } __packed; 237 238 struct wtbl_smps { 239 __le16 tag; 240 __le16 len; 241 u8 smps; 242 u8 rsv[3]; 243 } __packed; 244 245 /* mt7615 only */ 246 247 struct wtbl_bf { 248 __le16 tag; 249 __le16 len; 250 u8 ibf; 251 u8 ebf; 252 u8 ibf_vht; 253 u8 ebf_vht; 254 u8 gid; 255 u8 pfmu_idx; 256 u8 rsv[2]; 257 } __packed; 258 259 struct wtbl_pn { 260 __le16 tag; 261 __le16 len; 262 u8 pn[6]; 263 u8 rsv[2]; 264 } __packed; 265 266 struct wtbl_spe { 267 __le16 tag; 268 __le16 len; 269 u8 spe_idx; 270 u8 rsv[3]; 271 } __packed; 272 273 struct wtbl_raw { 274 __le16 tag; 275 __le16 len; 276 u8 wtbl_idx; 277 u8 dw; 278 u8 rsv[2]; 279 __le32 msk; 280 __le32 val; 281 } __packed; 282 283 #define MT76_CONNAC_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \ 284 sizeof(struct wtbl_generic) + \ 285 sizeof(struct wtbl_rx) + \ 286 sizeof(struct wtbl_ht) + \ 287 sizeof(struct wtbl_vht) + \ 288 sizeof(struct wtbl_tx_ps) + \ 289 sizeof(struct wtbl_hdr_trans) +\ 290 sizeof(struct wtbl_ba) + \ 291 sizeof(struct wtbl_bf) + \ 292 sizeof(struct wtbl_smps) + \ 293 sizeof(struct wtbl_pn) + \ 294 sizeof(struct wtbl_spe)) 295 296 #define MT76_CONNAC_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 297 sizeof(struct sta_rec_basic) + \ 298 sizeof(struct sta_rec_ht) + \ 299 sizeof(struct sta_rec_he) + \ 300 sizeof(struct sta_rec_ba) + \ 301 sizeof(struct sta_rec_vht) + \ 302 sizeof(struct sta_rec_uapsd) + \ 303 sizeof(struct sta_rec_amsdu) + \ 304 sizeof(struct tlv) + \ 305 MT76_CONNAC_WTBL_UPDATE_MAX_SIZE) 306 307 enum { 308 STA_REC_BASIC, 309 STA_REC_RA, 310 STA_REC_RA_CMM_INFO, 311 STA_REC_RA_UPDATE, 312 STA_REC_BF, 313 STA_REC_AMSDU, 314 STA_REC_BA, 315 STA_REC_STATE, 316 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */ 317 STA_REC_HT, 318 STA_REC_VHT, 319 STA_REC_APPS, 320 STA_REC_KEY, 321 STA_REC_WTBL, 322 STA_REC_HE, 323 STA_REC_HW_AMSDU, 324 STA_REC_WTBL_AADOM, 325 STA_REC_KEY_V2, 326 STA_REC_MURU, 327 STA_REC_MUEDCA, 328 STA_REC_BFEE, 329 STA_REC_PHY = 0x15, 330 STA_REC_MAX_NUM 331 }; 332 333 enum { 334 WTBL_GENERIC, 335 WTBL_RX, 336 WTBL_HT, 337 WTBL_VHT, 338 WTBL_PEER_PS, /* not used */ 339 WTBL_TX_PS, 340 WTBL_HDR_TRANS, 341 WTBL_SEC_KEY, 342 WTBL_BA, 343 WTBL_RDG, /* obsoleted */ 344 WTBL_PROTECT, /* not used */ 345 WTBL_CLEAR, /* not used */ 346 WTBL_BF, 347 WTBL_SMPS, 348 WTBL_RAW_DATA, /* debug only */ 349 WTBL_PN, 350 WTBL_SPE, 351 WTBL_MAX_NUM 352 }; 353 354 #define STA_TYPE_STA BIT(0) 355 #define STA_TYPE_AP BIT(1) 356 #define STA_TYPE_ADHOC BIT(2) 357 #define STA_TYPE_WDS BIT(4) 358 #define STA_TYPE_BC BIT(5) 359 360 #define NETWORK_INFRA BIT(16) 361 #define NETWORK_P2P BIT(17) 362 #define NETWORK_IBSS BIT(18) 363 #define NETWORK_WDS BIT(21) 364 365 #define SCAN_FUNC_RANDOM_MAC BIT(0) 366 #define SCAN_FUNC_SPLIT_SCAN BIT(5) 367 368 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA) 369 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA) 370 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P) 371 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P) 372 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS) 373 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS) 374 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA) 375 376 #define CONN_STATE_DISCONNECT 0 377 #define CONN_STATE_CONNECT 1 378 #define CONN_STATE_PORT_SECURE 2 379 380 /* HE MAC */ 381 #define STA_REC_HE_CAP_HTC BIT(0) 382 #define STA_REC_HE_CAP_BQR BIT(1) 383 #define STA_REC_HE_CAP_BSR BIT(2) 384 #define STA_REC_HE_CAP_OM BIT(3) 385 #define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4) 386 /* HE PHY */ 387 #define STA_REC_HE_CAP_DUAL_BAND BIT(5) 388 #define STA_REC_HE_CAP_LDPC BIT(6) 389 #define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7) 390 #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8) 391 /* STBC */ 392 #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9) 393 #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10) 394 #define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11) 395 #define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12) 396 /* GI */ 397 #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13) 398 #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14) 399 #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15) 400 #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16) 401 #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17) 402 /* 242 TONE */ 403 #define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18) 404 #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19) 405 #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20) 406 407 #define PHY_MODE_A BIT(0) 408 #define PHY_MODE_B BIT(1) 409 #define PHY_MODE_G BIT(2) 410 #define PHY_MODE_GN BIT(3) 411 #define PHY_MODE_AN BIT(4) 412 #define PHY_MODE_AC BIT(5) 413 #define PHY_MODE_AX_24G BIT(6) 414 #define PHY_MODE_AX_5G BIT(7) 415 #define PHY_MODE_AX_6G BIT(8) 416 417 #define MODE_CCK BIT(0) 418 #define MODE_OFDM BIT(1) 419 #define MODE_HT BIT(2) 420 #define MODE_VHT BIT(3) 421 #define MODE_HE BIT(4) 422 423 enum { 424 PHY_TYPE_HR_DSSS_INDEX = 0, 425 PHY_TYPE_ERP_INDEX, 426 PHY_TYPE_ERP_P2P_INDEX, 427 PHY_TYPE_OFDM_INDEX, 428 PHY_TYPE_HT_INDEX, 429 PHY_TYPE_VHT_INDEX, 430 PHY_TYPE_HE_INDEX, 431 PHY_TYPE_INDEX_NUM 432 }; 433 434 #define PHY_TYPE_BIT_HR_DSSS BIT(PHY_TYPE_HR_DSSS_INDEX) 435 #define PHY_TYPE_BIT_ERP BIT(PHY_TYPE_ERP_INDEX) 436 #define PHY_TYPE_BIT_OFDM BIT(PHY_TYPE_OFDM_INDEX) 437 #define PHY_TYPE_BIT_HT BIT(PHY_TYPE_HT_INDEX) 438 #define PHY_TYPE_BIT_VHT BIT(PHY_TYPE_VHT_INDEX) 439 #define PHY_TYPE_BIT_HE BIT(PHY_TYPE_HE_INDEX) 440 441 #define MT_WTBL_RATE_TX_MODE GENMASK(9, 6) 442 #define MT_WTBL_RATE_MCS GENMASK(5, 0) 443 #define MT_WTBL_RATE_NSS GENMASK(12, 10) 444 #define MT_WTBL_RATE_HE_GI GENMASK(7, 4) 445 #define MT_WTBL_RATE_GI GENMASK(3, 0) 446 447 #define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5) 448 #define MT_WTBL_W5_SHORT_GI_20 BIT(8) 449 #define MT_WTBL_W5_SHORT_GI_40 BIT(9) 450 #define MT_WTBL_W5_SHORT_GI_80 BIT(10) 451 #define MT_WTBL_W5_SHORT_GI_160 BIT(11) 452 #define MT_WTBL_W5_BW_CAP GENMASK(13, 12) 453 #define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23) 454 #define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26) 455 #define MT_WTBL_W5_RATE_IDX GENMASK(31, 29) 456 457 enum { 458 WTBL_RESET_AND_SET = 1, 459 WTBL_SET, 460 WTBL_QUERY, 461 WTBL_RESET_ALL 462 }; 463 464 enum { 465 MT_BA_TYPE_INVALID, 466 MT_BA_TYPE_ORIGINATOR, 467 MT_BA_TYPE_RECIPIENT 468 }; 469 470 enum { 471 RST_BA_MAC_TID_MATCH, 472 RST_BA_MAC_MATCH, 473 RST_BA_NO_MATCH 474 }; 475 476 enum { 477 DEV_INFO_ACTIVE, 478 DEV_INFO_MAX_NUM 479 }; 480 481 #define MCU_CMD_ACK BIT(0) 482 #define MCU_CMD_UNI BIT(1) 483 #define MCU_CMD_QUERY BIT(2) 484 485 #define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | \ 486 MCU_CMD_QUERY) 487 488 #define MCU_FW_PREFIX BIT(31) 489 #define MCU_UNI_PREFIX BIT(30) 490 #define MCU_CE_PREFIX BIT(29) 491 #define MCU_QUERY_PREFIX BIT(28) 492 #define MCU_CMD_MASK ~(MCU_FW_PREFIX | MCU_UNI_PREFIX | \ 493 MCU_CE_PREFIX | MCU_QUERY_PREFIX) 494 495 #define MCU_QUERY_MASK BIT(16) 496 497 enum { 498 MCU_EXT_CMD_EFUSE_ACCESS = 0x01, 499 MCU_EXT_CMD_RF_REG_ACCESS = 0x02, 500 MCU_EXT_CMD_PM_STATE_CTRL = 0x07, 501 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08, 502 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11, 503 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13, 504 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21, 505 MCU_EXT_CMD_STA_REC_UPDATE = 0x25, 506 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26, 507 MCU_EXT_CMD_EDCA_UPDATE = 0x27, 508 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A, 509 MCU_EXT_CMD_GET_TEMP = 0x2c, 510 MCU_EXT_CMD_WTBL_UPDATE = 0x32, 511 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a, 512 MCU_EXT_CMD_ATE_CTRL = 0x3d, 513 MCU_EXT_CMD_PROTECT_CTRL = 0x3e, 514 MCU_EXT_CMD_DBDC_CTRL = 0x45, 515 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46, 516 MCU_EXT_CMD_RX_HDR_TRANS = 0x47, 517 MCU_EXT_CMD_MUAR_UPDATE = 0x48, 518 MCU_EXT_CMD_BCN_OFFLOAD = 0x49, 519 MCU_EXT_CMD_SET_RX_PATH = 0x4e, 520 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58, 521 MCU_EXT_CMD_RXDCOC_CAL = 0x59, 522 MCU_EXT_CMD_TXDPD_CAL = 0x60, 523 MCU_EXT_CMD_SET_RDD_TH = 0x7c, 524 MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d, 525 }; 526 527 enum { 528 MCU_UNI_CMD_DEV_INFO_UPDATE = MCU_UNI_PREFIX | 0x01, 529 MCU_UNI_CMD_BSS_INFO_UPDATE = MCU_UNI_PREFIX | 0x02, 530 MCU_UNI_CMD_STA_REC_UPDATE = MCU_UNI_PREFIX | 0x03, 531 MCU_UNI_CMD_SUSPEND = MCU_UNI_PREFIX | 0x05, 532 MCU_UNI_CMD_OFFLOAD = MCU_UNI_PREFIX | 0x06, 533 MCU_UNI_CMD_HIF_CTRL = MCU_UNI_PREFIX | 0x07, 534 }; 535 536 enum { 537 MCU_CMD_TARGET_ADDRESS_LEN_REQ = MCU_FW_PREFIX | 0x01, 538 MCU_CMD_FW_START_REQ = MCU_FW_PREFIX | 0x02, 539 MCU_CMD_INIT_ACCESS_REG = 0x3, 540 MCU_CMD_NIC_POWER_CTRL = MCU_FW_PREFIX | 0x4, 541 MCU_CMD_PATCH_START_REQ = MCU_FW_PREFIX | 0x05, 542 MCU_CMD_PATCH_FINISH_REQ = MCU_FW_PREFIX | 0x07, 543 MCU_CMD_PATCH_SEM_CONTROL = MCU_FW_PREFIX | 0x10, 544 MCU_CMD_EXT_CID = 0xed, 545 MCU_CMD_FW_SCATTER = MCU_FW_PREFIX | 0xee, 546 MCU_CMD_RESTART_DL_REQ = MCU_FW_PREFIX | 0xef, 547 }; 548 549 /* offload mcu commands */ 550 enum { 551 MCU_CMD_START_HW_SCAN = MCU_CE_PREFIX | 0x03, 552 MCU_CMD_SET_PS_PROFILE = MCU_CE_PREFIX | 0x05, 553 MCU_CMD_SET_CHAN_DOMAIN = MCU_CE_PREFIX | 0x0f, 554 MCU_CMD_SET_BSS_CONNECTED = MCU_CE_PREFIX | 0x16, 555 MCU_CMD_SET_BSS_ABORT = MCU_CE_PREFIX | 0x17, 556 MCU_CMD_CANCEL_HW_SCAN = MCU_CE_PREFIX | 0x1b, 557 MCU_CMD_SET_ROC = MCU_CE_PREFIX | 0x1d, 558 MCU_CMD_SET_P2P_OPPPS = MCU_CE_PREFIX | 0x33, 559 MCU_CMD_SET_RATE_TX_POWER = MCU_CE_PREFIX | 0x5d, 560 MCU_CMD_SCHED_SCAN_ENABLE = MCU_CE_PREFIX | 0x61, 561 MCU_CMD_SCHED_SCAN_REQ = MCU_CE_PREFIX | 0x62, 562 MCU_CMD_GET_NIC_CAPAB = MCU_CE_PREFIX | 0x8a, 563 MCU_CMD_REG_WRITE = MCU_CE_PREFIX | 0xc0, 564 MCU_CMD_REG_READ = MCU_CE_PREFIX | MCU_QUERY_MASK | 0xc0, 565 MCU_CMD_CHIP_CONFIG = MCU_CE_PREFIX | 0xca, 566 MCU_CMD_FWLOG_2_HOST = MCU_CE_PREFIX | 0xc5, 567 MCU_CMD_GET_WTBL = MCU_CE_PREFIX | 0xcd, 568 MCU_CMD_GET_TXPWR = MCU_CE_PREFIX | 0xd0, 569 }; 570 571 enum { 572 PATCH_SEM_RELEASE, 573 PATCH_SEM_GET 574 }; 575 576 enum { 577 UNI_BSS_INFO_BASIC = 0, 578 UNI_BSS_INFO_RLM = 2, 579 UNI_BSS_INFO_BSS_COLOR = 4, 580 UNI_BSS_INFO_HE_BASIC = 5, 581 UNI_BSS_INFO_BCN_CONTENT = 7, 582 UNI_BSS_INFO_QBSS = 15, 583 UNI_BSS_INFO_UAPSD = 19, 584 UNI_BSS_INFO_PS = 21, 585 UNI_BSS_INFO_BCNFT = 22, 586 }; 587 588 enum { 589 UNI_OFFLOAD_OFFLOAD_ARP, 590 UNI_OFFLOAD_OFFLOAD_ND, 591 UNI_OFFLOAD_OFFLOAD_GTK_REKEY, 592 UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT, 593 }; 594 595 enum { 596 MT_NIC_CAP_TX_RESOURCE, 597 MT_NIC_CAP_TX_EFUSE_ADDR, 598 MT_NIC_CAP_COEX, 599 MT_NIC_CAP_SINGLE_SKU, 600 MT_NIC_CAP_CSUM_OFFLOAD, 601 MT_NIC_CAP_HW_VER, 602 MT_NIC_CAP_SW_VER, 603 MT_NIC_CAP_MAC_ADDR, 604 MT_NIC_CAP_PHY, 605 MT_NIC_CAP_MAC, 606 MT_NIC_CAP_FRAME_BUF, 607 MT_NIC_CAP_BEAM_FORM, 608 MT_NIC_CAP_LOCATION, 609 MT_NIC_CAP_MUMIMO, 610 MT_NIC_CAP_BUFFER_MODE_INFO, 611 MT_NIC_CAP_HW_ADIE_VERSION = 0x14, 612 MT_NIC_CAP_ANTSWP = 0x16, 613 MT_NIC_CAP_WFDMA_REALLOC, 614 MT_NIC_CAP_6G, 615 }; 616 617 #define UNI_WOW_DETECT_TYPE_MAGIC BIT(0) 618 #define UNI_WOW_DETECT_TYPE_ANY BIT(1) 619 #define UNI_WOW_DETECT_TYPE_DISCONNECT BIT(2) 620 #define UNI_WOW_DETECT_TYPE_GTK_REKEY_FAIL BIT(3) 621 #define UNI_WOW_DETECT_TYPE_BCN_LOST BIT(4) 622 #define UNI_WOW_DETECT_TYPE_SCH_SCAN_HIT BIT(5) 623 #define UNI_WOW_DETECT_TYPE_BITMAP BIT(6) 624 625 enum { 626 UNI_SUSPEND_MODE_SETTING, 627 UNI_SUSPEND_WOW_CTRL, 628 UNI_SUSPEND_WOW_GPIO_PARAM, 629 UNI_SUSPEND_WOW_WAKEUP_PORT, 630 UNI_SUSPEND_WOW_PATTERN, 631 }; 632 633 enum { 634 WOW_USB = 1, 635 WOW_PCIE = 2, 636 WOW_GPIO = 3, 637 }; 638 639 struct mt76_connac_bss_basic_tlv { 640 __le16 tag; 641 __le16 len; 642 u8 active; 643 u8 omac_idx; 644 u8 hw_bss_idx; 645 u8 band_idx; 646 __le32 conn_type; 647 u8 conn_state; 648 u8 wmm_idx; 649 u8 bssid[ETH_ALEN]; 650 __le16 bmc_tx_wlan_idx; 651 __le16 bcn_interval; 652 u8 dtim_period; 653 u8 phymode; /* bit(0): A 654 * bit(1): B 655 * bit(2): G 656 * bit(3): GN 657 * bit(4): AN 658 * bit(5): AC 659 */ 660 __le16 sta_idx; 661 u8 nonht_basic_phy; 662 u8 pad[3]; 663 } __packed; 664 665 struct mt76_connac_bss_qos_tlv { 666 __le16 tag; 667 __le16 len; 668 u8 qos; 669 u8 pad[3]; 670 } __packed; 671 672 struct mt76_connac_beacon_loss_event { 673 u8 bss_idx; 674 u8 reason; 675 u8 pad[2]; 676 } __packed; 677 678 struct mt76_connac_mcu_bss_event { 679 u8 bss_idx; 680 u8 is_absent; 681 u8 free_quota; 682 u8 pad; 683 } __packed; 684 685 struct mt76_connac_mcu_scan_ssid { 686 __le32 ssid_len; 687 u8 ssid[IEEE80211_MAX_SSID_LEN]; 688 } __packed; 689 690 struct mt76_connac_mcu_scan_channel { 691 u8 band; /* 1: 2.4GHz 692 * 2: 5.0GHz 693 * Others: Reserved 694 */ 695 u8 channel_num; 696 } __packed; 697 698 struct mt76_connac_mcu_scan_match { 699 __le32 rssi_th; 700 u8 ssid[IEEE80211_MAX_SSID_LEN]; 701 u8 ssid_len; 702 u8 rsv[3]; 703 } __packed; 704 705 struct mt76_connac_hw_scan_req { 706 u8 seq_num; 707 u8 bss_idx; 708 u8 scan_type; /* 0: PASSIVE SCAN 709 * 1: ACTIVE SCAN 710 */ 711 u8 ssid_type; /* BIT(0) wildcard SSID 712 * BIT(1) P2P wildcard SSID 713 * BIT(2) specified SSID + wildcard SSID 714 * BIT(2) + ssid_type_ext BIT(0) specified SSID only 715 */ 716 u8 ssids_num; 717 u8 probe_req_num; /* Number of probe request for each SSID */ 718 u8 scan_func; /* BIT(0) Enable random MAC scan 719 * BIT(1) Disable DBDC scan type 1~3. 720 * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan). 721 */ 722 u8 version; /* 0: Not support fields after ies. 723 * 1: Support fields after ies. 724 */ 725 struct mt76_connac_mcu_scan_ssid ssids[4]; 726 __le16 probe_delay_time; 727 __le16 channel_dwell_time; /* channel Dwell interval */ 728 __le16 timeout_value; 729 u8 channel_type; /* 0: Full channels 730 * 1: Only 2.4GHz channels 731 * 2: Only 5GHz channels 732 * 3: P2P social channel only (channel #1, #6 and #11) 733 * 4: Specified channels 734 * Others: Reserved 735 */ 736 u8 channels_num; /* valid when channel_type is 4 */ 737 /* valid when channels_num is set */ 738 struct mt76_connac_mcu_scan_channel channels[32]; 739 __le16 ies_len; 740 u8 ies[MT76_CONNAC_SCAN_IE_LEN]; 741 /* following fields are valid if version > 0 */ 742 u8 ext_channels_num; 743 u8 ext_ssids_num; 744 __le16 channel_min_dwell_time; 745 struct mt76_connac_mcu_scan_channel ext_channels[32]; 746 struct mt76_connac_mcu_scan_ssid ext_ssids[6]; 747 u8 bssid[ETH_ALEN]; 748 u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */ 749 u8 pad[63]; 750 u8 ssid_type_ext; 751 } __packed; 752 753 #define MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM 64 754 755 struct mt76_connac_hw_scan_done { 756 u8 seq_num; 757 u8 sparse_channel_num; 758 struct mt76_connac_mcu_scan_channel sparse_channel; 759 u8 complete_channel_num; 760 u8 current_state; 761 u8 version; 762 u8 pad; 763 __le32 beacon_scan_num; 764 u8 pno_enabled; 765 u8 pad2[3]; 766 u8 sparse_channel_valid_num; 767 u8 pad3[3]; 768 u8 channel_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 769 /* idle format for channel_idle_time 770 * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms) 771 * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms) 772 * 2: dwell time (16us) 773 */ 774 __le16 channel_idle_time[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 775 /* beacon and probe response count */ 776 u8 beacon_probe_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 777 u8 mdrdy_count[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 778 __le32 beacon_2g_num; 779 __le32 beacon_5g_num; 780 } __packed; 781 782 struct mt76_connac_sched_scan_req { 783 u8 version; 784 u8 seq_num; 785 u8 stop_on_match; 786 u8 ssids_num; 787 u8 match_num; 788 u8 pad; 789 __le16 ie_len; 790 struct mt76_connac_mcu_scan_ssid ssids[MT76_CONNAC_MAX_SCHED_SCAN_SSID]; 791 struct mt76_connac_mcu_scan_match match[MT76_CONNAC_MAX_SCAN_MATCH]; 792 u8 channel_type; 793 u8 channels_num; 794 u8 intervals_num; 795 u8 scan_func; /* MT7663: BIT(0) eable random mac address */ 796 struct mt76_connac_mcu_scan_channel channels[64]; 797 __le16 intervals[MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL]; 798 union { 799 struct { 800 u8 random_mac[ETH_ALEN]; 801 u8 pad2[58]; 802 } mt7663; 803 struct { 804 u8 bss_idx; 805 u8 pad2[19]; 806 u8 random_mac[ETH_ALEN]; 807 u8 pad3[38]; 808 } mt7921; 809 }; 810 } __packed; 811 812 struct mt76_connac_sched_scan_done { 813 u8 seq_num; 814 u8 status; /* 0: ssid found */ 815 __le16 pad; 816 } __packed; 817 818 struct bss_info_uni_bss_color { 819 __le16 tag; 820 __le16 len; 821 u8 enable; 822 u8 bss_color; 823 u8 rsv[2]; 824 } __packed; 825 826 struct bss_info_uni_he { 827 __le16 tag; 828 __le16 len; 829 __le16 he_rts_thres; 830 u8 he_pe_duration; 831 u8 su_disable; 832 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 833 u8 rsv[2]; 834 } __packed; 835 836 struct mt76_connac_gtk_rekey_tlv { 837 __le16 tag; 838 __le16 len; 839 u8 kek[NL80211_KEK_LEN]; 840 u8 kck[NL80211_KCK_LEN]; 841 u8 replay_ctr[NL80211_REPLAY_CTR_LEN]; 842 u8 rekey_mode; /* 0: rekey offload enable 843 * 1: rekey offload disable 844 * 2: rekey update 845 */ 846 u8 keyid; 847 u8 pad[2]; 848 __le32 proto; /* WPA-RSN-WAPI-OPSN */ 849 __le32 pairwise_cipher; 850 __le32 group_cipher; 851 __le32 key_mgmt; /* NONE-PSK-IEEE802.1X */ 852 __le32 mgmt_group_cipher; 853 u8 option; /* 1: rekey data update without enabling offload */ 854 u8 reserverd[3]; 855 } __packed; 856 857 #define MT76_CONNAC_WOW_MASK_MAX_LEN 16 858 #define MT76_CONNAC_WOW_PATTEN_MAX_LEN 128 859 860 struct mt76_connac_wow_pattern_tlv { 861 __le16 tag; 862 __le16 len; 863 u8 index; /* pattern index */ 864 u8 enable; /* 0: disable 865 * 1: enable 866 */ 867 u8 data_len; /* pattern length */ 868 u8 pad; 869 u8 mask[MT76_CONNAC_WOW_MASK_MAX_LEN]; 870 u8 pattern[MT76_CONNAC_WOW_PATTEN_MAX_LEN]; 871 u8 rsv[4]; 872 } __packed; 873 874 struct mt76_connac_wow_ctrl_tlv { 875 __le16 tag; 876 __le16 len; 877 u8 cmd; /* 0x1: PM_WOWLAN_REQ_START 878 * 0x2: PM_WOWLAN_REQ_STOP 879 * 0x3: PM_WOWLAN_PARAM_CLEAR 880 */ 881 u8 trigger; /* 0: NONE 882 * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT 883 * BIT(1): NL80211_WOWLAN_TRIG_ANY 884 * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT 885 * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE 886 * BIT(4): BEACON_LOST 887 * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT 888 */ 889 u8 wakeup_hif; /* 0x0: HIF_SDIO 890 * 0x1: HIF_USB 891 * 0x2: HIF_PCIE 892 * 0x3: HIF_GPIO 893 */ 894 u8 pad; 895 u8 rsv[4]; 896 } __packed; 897 898 struct mt76_connac_wow_gpio_param_tlv { 899 __le16 tag; 900 __le16 len; 901 u8 gpio_pin; 902 u8 trigger_lvl; 903 u8 pad[2]; 904 __le32 gpio_interval; 905 u8 rsv[4]; 906 } __packed; 907 908 struct mt76_connac_arpns_tlv { 909 __le16 tag; 910 __le16 len; 911 u8 mode; 912 u8 ips_num; 913 u8 option; 914 u8 pad[1]; 915 } __packed; 916 917 struct mt76_connac_suspend_tlv { 918 __le16 tag; 919 __le16 len; 920 u8 enable; /* 0: suspend mode disabled 921 * 1: suspend mode enabled 922 */ 923 u8 mdtim; /* LP parameter */ 924 u8 wow_suspend; /* 0: update by origin policy 925 * 1: update by wow dtim 926 */ 927 u8 pad[5]; 928 } __packed; 929 930 enum mt76_sta_info_state { 931 MT76_STA_INFO_STATE_NONE, 932 MT76_STA_INFO_STATE_AUTH, 933 MT76_STA_INFO_STATE_ASSOC 934 }; 935 936 struct mt76_sta_cmd_info { 937 struct ieee80211_sta *sta; 938 struct mt76_wcid *wcid; 939 940 struct ieee80211_vif *vif; 941 942 bool offload_fw; 943 bool enable; 944 bool newly; 945 int cmd; 946 u8 rcpi; 947 u8 state; 948 }; 949 950 #define MT_SKU_POWER_LIMIT 161 951 952 struct mt76_connac_sku_tlv { 953 u8 channel; 954 s8 pwr_limit[MT_SKU_POWER_LIMIT]; 955 } __packed; 956 957 struct mt76_connac_tx_power_limit_tlv { 958 /* DW0 - common info*/ 959 u8 ver; 960 u8 pad0; 961 __le16 len; 962 /* DW1 - cmd hint */ 963 u8 n_chan; /* # channel */ 964 u8 band; /* 2.4GHz - 5GHz */ 965 u8 last_msg; 966 u8 pad1; 967 /* DW3 */ 968 u8 alpha2[4]; /* regulatory_request.alpha2 */ 969 u8 pad2[32]; 970 } __packed; 971 972 struct mt76_connac_config { 973 __le16 id; 974 u8 type; 975 u8 resp_type; 976 __le16 data_size; 977 __le16 resv; 978 u8 data[320]; 979 } __packed; 980 981 #define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id) 982 #define to_wcid_hi(id) FIELD_GET(GENMASK(9, 8), (u16)id) 983 984 static inline void 985 mt76_connac_mcu_get_wlan_idx(struct mt76_dev *dev, struct mt76_wcid *wcid, 986 u8 *wlan_idx_lo, u8 *wlan_idx_hi) 987 { 988 *wlan_idx_hi = 0; 989 990 if (is_mt7921(dev)) { 991 *wlan_idx_lo = wcid ? to_wcid_lo(wcid->idx) : 0; 992 *wlan_idx_hi = wcid ? to_wcid_hi(wcid->idx) : 0; 993 } else { 994 *wlan_idx_lo = wcid ? wcid->idx : 0; 995 } 996 } 997 998 struct sk_buff * 999 mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif, 1000 struct mt76_wcid *wcid); 1001 struct wtbl_req_hdr * 1002 mt76_connac_mcu_alloc_wtbl_req(struct mt76_dev *dev, struct mt76_wcid *wcid, 1003 int cmd, void *sta_wtbl, struct sk_buff **skb); 1004 struct tlv *mt76_connac_mcu_add_nested_tlv(struct sk_buff *skb, int tag, 1005 int len, void *sta_ntlv, 1006 void *sta_wtbl); 1007 static inline struct tlv * 1008 mt76_connac_mcu_add_tlv(struct sk_buff *skb, int tag, int len) 1009 { 1010 return mt76_connac_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL); 1011 } 1012 1013 int mt76_connac_mcu_set_channel_domain(struct mt76_phy *phy); 1014 int mt76_connac_mcu_set_vif_ps(struct mt76_dev *dev, struct ieee80211_vif *vif); 1015 void mt76_connac_mcu_sta_basic_tlv(struct sk_buff *skb, 1016 struct ieee80211_vif *vif, 1017 struct ieee80211_sta *sta, bool enable, 1018 bool newly); 1019 void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1020 struct ieee80211_vif *vif, 1021 struct ieee80211_sta *sta, void *sta_wtbl, 1022 void *wtbl_tlv); 1023 void mt76_connac_mcu_wtbl_hdr_trans_tlv(struct sk_buff *skb, 1024 struct ieee80211_vif *vif, 1025 struct mt76_wcid *wcid, 1026 void *sta_wtbl, void *wtbl_tlv); 1027 int mt76_connac_mcu_sta_update_hdr_trans(struct mt76_dev *dev, 1028 struct ieee80211_vif *vif, 1029 struct mt76_wcid *wcid, int cmd); 1030 void mt76_connac_mcu_sta_tlv(struct mt76_phy *mphy, struct sk_buff *skb, 1031 struct ieee80211_sta *sta, 1032 struct ieee80211_vif *vif, 1033 u8 rcpi, u8 state); 1034 void mt76_connac_mcu_wtbl_ht_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1035 struct ieee80211_sta *sta, void *sta_wtbl, 1036 void *wtbl_tlv); 1037 void mt76_connac_mcu_wtbl_ba_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1038 struct ieee80211_ampdu_params *params, 1039 bool enable, bool tx, void *sta_wtbl, 1040 void *wtbl_tlv); 1041 void mt76_connac_mcu_sta_ba_tlv(struct sk_buff *skb, 1042 struct ieee80211_ampdu_params *params, 1043 bool enable, bool tx); 1044 int mt76_connac_mcu_uni_add_dev(struct mt76_phy *phy, 1045 struct ieee80211_vif *vif, 1046 struct mt76_wcid *wcid, 1047 bool enable); 1048 int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif, 1049 struct ieee80211_ampdu_params *params, 1050 bool enable, bool tx); 1051 int mt76_connac_mcu_uni_add_bss(struct mt76_phy *phy, 1052 struct ieee80211_vif *vif, 1053 struct mt76_wcid *wcid, 1054 bool enable); 1055 int mt76_connac_mcu_sta_cmd(struct mt76_phy *phy, 1056 struct mt76_sta_cmd_info *info); 1057 void mt76_connac_mcu_beacon_loss_iter(void *priv, u8 *mac, 1058 struct ieee80211_vif *vif); 1059 int mt76_connac_mcu_set_rts_thresh(struct mt76_dev *dev, u32 val, u8 band); 1060 int mt76_connac_mcu_set_mac_enable(struct mt76_dev *dev, int band, bool enable, 1061 bool hdr_trans); 1062 int mt76_connac_mcu_init_download(struct mt76_dev *dev, u32 addr, u32 len, 1063 u32 mode); 1064 int mt76_connac_mcu_start_patch(struct mt76_dev *dev); 1065 int mt76_connac_mcu_patch_sem_ctrl(struct mt76_dev *dev, bool get); 1066 int mt76_connac_mcu_start_firmware(struct mt76_dev *dev, u32 addr, u32 option); 1067 int mt76_connac_mcu_get_nic_capability(struct mt76_phy *phy); 1068 1069 int mt76_connac_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif, 1070 struct ieee80211_scan_request *scan_req); 1071 int mt76_connac_mcu_cancel_hw_scan(struct mt76_phy *phy, 1072 struct ieee80211_vif *vif); 1073 int mt76_connac_mcu_sched_scan_req(struct mt76_phy *phy, 1074 struct ieee80211_vif *vif, 1075 struct cfg80211_sched_scan_request *sreq); 1076 int mt76_connac_mcu_sched_scan_enable(struct mt76_phy *phy, 1077 struct ieee80211_vif *vif, 1078 bool enable); 1079 int mt76_connac_mcu_update_arp_filter(struct mt76_dev *dev, 1080 struct mt76_vif *vif, 1081 struct ieee80211_bss_conf *info); 1082 int mt76_connac_mcu_update_gtk_rekey(struct ieee80211_hw *hw, 1083 struct ieee80211_vif *vif, 1084 struct cfg80211_gtk_rekey_data *key); 1085 int mt76_connac_mcu_set_hif_suspend(struct mt76_dev *dev, bool suspend); 1086 void mt76_connac_mcu_set_suspend_iter(void *priv, u8 *mac, 1087 struct ieee80211_vif *vif); 1088 int mt76_connac_sta_state_dp(struct mt76_dev *dev, 1089 enum ieee80211_sta_state old_state, 1090 enum ieee80211_sta_state new_state); 1091 int mt76_connac_mcu_chip_config(struct mt76_dev *dev); 1092 int mt76_connac_mcu_set_deep_sleep(struct mt76_dev *dev, bool enable); 1093 void mt76_connac_mcu_coredump_event(struct mt76_dev *dev, struct sk_buff *skb, 1094 struct mt76_connac_coredump *coredump); 1095 int mt76_connac_mcu_set_rate_txpower(struct mt76_phy *phy); 1096 #endif /* __MT76_CONNAC_MCU_H */ 1097