1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT76_CONNAC_MCU_H 5 #define __MT76_CONNAC_MCU_H 6 7 #include "mt76_connac.h" 8 9 struct tlv { 10 __le16 tag; 11 __le16 len; 12 } __packed; 13 14 /* sta_rec */ 15 16 struct sta_ntlv_hdr { 17 u8 rsv[2]; 18 __le16 tlv_num; 19 } __packed; 20 21 struct sta_req_hdr { 22 u8 bss_idx; 23 u8 wlan_idx_lo; 24 __le16 tlv_num; 25 u8 is_tlv_append; 26 u8 muar_idx; 27 u8 wlan_idx_hi; 28 u8 rsv; 29 } __packed; 30 31 struct sta_rec_basic { 32 __le16 tag; 33 __le16 len; 34 __le32 conn_type; 35 u8 conn_state; 36 u8 qos; 37 __le16 aid; 38 u8 peer_addr[ETH_ALEN]; 39 #define EXTRA_INFO_VER BIT(0) 40 #define EXTRA_INFO_NEW BIT(1) 41 __le16 extra_info; 42 } __packed; 43 44 struct sta_rec_ht { 45 __le16 tag; 46 __le16 len; 47 __le16 ht_cap; 48 u16 rsv; 49 } __packed; 50 51 struct sta_rec_vht { 52 __le16 tag; 53 __le16 len; 54 __le32 vht_cap; 55 __le16 vht_rx_mcs_map; 56 __le16 vht_tx_mcs_map; 57 /* mt7921 */ 58 u8 rts_bw_sig; 59 u8 rsv[3]; 60 } __packed; 61 62 struct sta_rec_uapsd { 63 __le16 tag; 64 __le16 len; 65 u8 dac_map; 66 u8 tac_map; 67 u8 max_sp; 68 u8 rsv0; 69 __le16 listen_interval; 70 u8 rsv1[2]; 71 } __packed; 72 73 struct sta_rec_ba { 74 __le16 tag; 75 __le16 len; 76 u8 tid; 77 u8 ba_type; 78 u8 amsdu; 79 u8 ba_en; 80 __le16 ssn; 81 __le16 winsize; 82 } __packed; 83 84 struct sta_rec_he { 85 __le16 tag; 86 __le16 len; 87 88 __le32 he_cap; 89 90 u8 t_frame_dur; 91 u8 max_ampdu_exp; 92 u8 bw_set; 93 u8 device_class; 94 u8 dcm_tx_mode; 95 u8 dcm_tx_max_nss; 96 u8 dcm_rx_mode; 97 u8 dcm_rx_max_nss; 98 u8 dcm_max_ru; 99 u8 punc_pream_rx; 100 u8 pkt_ext; 101 u8 rsv1; 102 103 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 104 105 u8 rsv2[2]; 106 } __packed; 107 108 struct sta_rec_amsdu { 109 __le16 tag; 110 __le16 len; 111 u8 max_amsdu_num; 112 u8 max_mpdu_size; 113 u8 amsdu_en; 114 u8 rsv; 115 } __packed; 116 117 struct sta_rec_state { 118 __le16 tag; 119 __le16 len; 120 __le32 flags; 121 u8 state; 122 u8 vht_opmode; 123 u8 action; 124 u8 rsv[1]; 125 } __packed; 126 127 #define RA_LEGACY_OFDM GENMASK(13, 6) 128 #define RA_LEGACY_CCK GENMASK(3, 0) 129 #define HT_MCS_MASK_NUM 10 130 struct sta_rec_ra_info { 131 __le16 tag; 132 __le16 len; 133 __le16 legacy; 134 u8 rx_mcs_bitmask[HT_MCS_MASK_NUM]; 135 } __packed; 136 137 struct sta_rec_phy { 138 __le16 tag; 139 __le16 len; 140 __le16 basic_rate; 141 u8 phy_type; 142 u8 ampdu; 143 u8 rts_policy; 144 u8 rcpi; 145 u8 rsv[2]; 146 } __packed; 147 148 struct sta_rec_he_6g_capa { 149 __le16 tag; 150 __le16 len; 151 __le16 capa; 152 u8 rsv[2]; 153 } __packed; 154 155 /* wtbl_rec */ 156 157 struct wtbl_req_hdr { 158 u8 wlan_idx_lo; 159 u8 operation; 160 __le16 tlv_num; 161 u8 wlan_idx_hi; 162 u8 rsv[3]; 163 } __packed; 164 165 struct wtbl_generic { 166 __le16 tag; 167 __le16 len; 168 u8 peer_addr[ETH_ALEN]; 169 u8 muar_idx; 170 u8 skip_tx; 171 u8 cf_ack; 172 u8 qos; 173 u8 mesh; 174 u8 adm; 175 __le16 partial_aid; 176 u8 baf_en; 177 u8 aad_om; 178 } __packed; 179 180 struct wtbl_rx { 181 __le16 tag; 182 __le16 len; 183 u8 rcid; 184 u8 rca1; 185 u8 rca2; 186 u8 rv; 187 u8 rsv[4]; 188 } __packed; 189 190 struct wtbl_ht { 191 __le16 tag; 192 __le16 len; 193 u8 ht; 194 u8 ldpc; 195 u8 af; 196 u8 mm; 197 u8 rsv[4]; 198 } __packed; 199 200 struct wtbl_vht { 201 __le16 tag; 202 __le16 len; 203 u8 ldpc; 204 u8 dyn_bw; 205 u8 vht; 206 u8 txop_ps; 207 u8 rsv[4]; 208 } __packed; 209 210 struct wtbl_tx_ps { 211 __le16 tag; 212 __le16 len; 213 u8 txps; 214 u8 rsv[3]; 215 } __packed; 216 217 struct wtbl_hdr_trans { 218 __le16 tag; 219 __le16 len; 220 u8 to_ds; 221 u8 from_ds; 222 u8 no_rx_trans; 223 u8 rsv; 224 } __packed; 225 226 struct wtbl_ba { 227 __le16 tag; 228 __le16 len; 229 /* common */ 230 u8 tid; 231 u8 ba_type; 232 u8 rsv0[2]; 233 /* originator only */ 234 __le16 sn; 235 u8 ba_en; 236 u8 ba_winsize_idx; 237 __le16 ba_winsize; 238 /* recipient only */ 239 u8 peer_addr[ETH_ALEN]; 240 u8 rst_ba_tid; 241 u8 rst_ba_sel; 242 u8 rst_ba_sb; 243 u8 band_idx; 244 u8 rsv1[4]; 245 } __packed; 246 247 struct wtbl_smps { 248 __le16 tag; 249 __le16 len; 250 u8 smps; 251 u8 rsv[3]; 252 } __packed; 253 254 /* mt7615 only */ 255 256 struct wtbl_bf { 257 __le16 tag; 258 __le16 len; 259 u8 ibf; 260 u8 ebf; 261 u8 ibf_vht; 262 u8 ebf_vht; 263 u8 gid; 264 u8 pfmu_idx; 265 u8 rsv[2]; 266 } __packed; 267 268 struct wtbl_pn { 269 __le16 tag; 270 __le16 len; 271 u8 pn[6]; 272 u8 rsv[2]; 273 } __packed; 274 275 struct wtbl_spe { 276 __le16 tag; 277 __le16 len; 278 u8 spe_idx; 279 u8 rsv[3]; 280 } __packed; 281 282 struct wtbl_raw { 283 __le16 tag; 284 __le16 len; 285 u8 wtbl_idx; 286 u8 dw; 287 u8 rsv[2]; 288 __le32 msk; 289 __le32 val; 290 } __packed; 291 292 #define MT76_CONNAC_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \ 293 sizeof(struct wtbl_generic) + \ 294 sizeof(struct wtbl_rx) + \ 295 sizeof(struct wtbl_ht) + \ 296 sizeof(struct wtbl_vht) + \ 297 sizeof(struct wtbl_tx_ps) + \ 298 sizeof(struct wtbl_hdr_trans) +\ 299 sizeof(struct wtbl_ba) + \ 300 sizeof(struct wtbl_bf) + \ 301 sizeof(struct wtbl_smps) + \ 302 sizeof(struct wtbl_pn) + \ 303 sizeof(struct wtbl_spe)) 304 305 #define MT76_CONNAC_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 306 sizeof(struct sta_rec_basic) + \ 307 sizeof(struct sta_rec_ht) + \ 308 sizeof(struct sta_rec_he) + \ 309 sizeof(struct sta_rec_ba) + \ 310 sizeof(struct sta_rec_vht) + \ 311 sizeof(struct sta_rec_uapsd) + \ 312 sizeof(struct sta_rec_amsdu) + \ 313 sizeof(struct sta_rec_he_6g_capa) + \ 314 sizeof(struct tlv) + \ 315 MT76_CONNAC_WTBL_UPDATE_MAX_SIZE) 316 317 enum { 318 STA_REC_BASIC, 319 STA_REC_RA, 320 STA_REC_RA_CMM_INFO, 321 STA_REC_RA_UPDATE, 322 STA_REC_BF, 323 STA_REC_AMSDU, 324 STA_REC_BA, 325 STA_REC_STATE, 326 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */ 327 STA_REC_HT, 328 STA_REC_VHT, 329 STA_REC_APPS, 330 STA_REC_KEY, 331 STA_REC_WTBL, 332 STA_REC_HE, 333 STA_REC_HW_AMSDU, 334 STA_REC_WTBL_AADOM, 335 STA_REC_KEY_V2, 336 STA_REC_MURU, 337 STA_REC_MUEDCA, 338 STA_REC_BFEE, 339 STA_REC_PHY = 0x15, 340 STA_REC_HE_6G = 0x17, 341 STA_REC_MAX_NUM 342 }; 343 344 enum { 345 WTBL_GENERIC, 346 WTBL_RX, 347 WTBL_HT, 348 WTBL_VHT, 349 WTBL_PEER_PS, /* not used */ 350 WTBL_TX_PS, 351 WTBL_HDR_TRANS, 352 WTBL_SEC_KEY, 353 WTBL_BA, 354 WTBL_RDG, /* obsoleted */ 355 WTBL_PROTECT, /* not used */ 356 WTBL_CLEAR, /* not used */ 357 WTBL_BF, 358 WTBL_SMPS, 359 WTBL_RAW_DATA, /* debug only */ 360 WTBL_PN, 361 WTBL_SPE, 362 WTBL_MAX_NUM 363 }; 364 365 #define STA_TYPE_STA BIT(0) 366 #define STA_TYPE_AP BIT(1) 367 #define STA_TYPE_ADHOC BIT(2) 368 #define STA_TYPE_WDS BIT(4) 369 #define STA_TYPE_BC BIT(5) 370 371 #define NETWORK_INFRA BIT(16) 372 #define NETWORK_P2P BIT(17) 373 #define NETWORK_IBSS BIT(18) 374 #define NETWORK_WDS BIT(21) 375 376 #define SCAN_FUNC_RANDOM_MAC BIT(0) 377 #define SCAN_FUNC_SPLIT_SCAN BIT(5) 378 379 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA) 380 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA) 381 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P) 382 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P) 383 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS) 384 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS) 385 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA) 386 387 #define CONN_STATE_DISCONNECT 0 388 #define CONN_STATE_CONNECT 1 389 #define CONN_STATE_PORT_SECURE 2 390 391 /* HE MAC */ 392 #define STA_REC_HE_CAP_HTC BIT(0) 393 #define STA_REC_HE_CAP_BQR BIT(1) 394 #define STA_REC_HE_CAP_BSR BIT(2) 395 #define STA_REC_HE_CAP_OM BIT(3) 396 #define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4) 397 /* HE PHY */ 398 #define STA_REC_HE_CAP_DUAL_BAND BIT(5) 399 #define STA_REC_HE_CAP_LDPC BIT(6) 400 #define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7) 401 #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8) 402 /* STBC */ 403 #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9) 404 #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10) 405 #define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11) 406 #define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12) 407 /* GI */ 408 #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13) 409 #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14) 410 #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15) 411 #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16) 412 #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17) 413 /* 242 TONE */ 414 #define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18) 415 #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19) 416 #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20) 417 418 #define PHY_MODE_A BIT(0) 419 #define PHY_MODE_B BIT(1) 420 #define PHY_MODE_G BIT(2) 421 #define PHY_MODE_GN BIT(3) 422 #define PHY_MODE_AN BIT(4) 423 #define PHY_MODE_AC BIT(5) 424 #define PHY_MODE_AX_24G BIT(6) 425 #define PHY_MODE_AX_5G BIT(7) 426 427 #define PHY_MODE_AX_6G BIT(0) /* phymode_ext */ 428 429 #define MODE_CCK BIT(0) 430 #define MODE_OFDM BIT(1) 431 #define MODE_HT BIT(2) 432 #define MODE_VHT BIT(3) 433 #define MODE_HE BIT(4) 434 435 enum { 436 PHY_TYPE_HR_DSSS_INDEX = 0, 437 PHY_TYPE_ERP_INDEX, 438 PHY_TYPE_ERP_P2P_INDEX, 439 PHY_TYPE_OFDM_INDEX, 440 PHY_TYPE_HT_INDEX, 441 PHY_TYPE_VHT_INDEX, 442 PHY_TYPE_HE_INDEX, 443 PHY_TYPE_INDEX_NUM 444 }; 445 446 #define PHY_TYPE_BIT_HR_DSSS BIT(PHY_TYPE_HR_DSSS_INDEX) 447 #define PHY_TYPE_BIT_ERP BIT(PHY_TYPE_ERP_INDEX) 448 #define PHY_TYPE_BIT_OFDM BIT(PHY_TYPE_OFDM_INDEX) 449 #define PHY_TYPE_BIT_HT BIT(PHY_TYPE_HT_INDEX) 450 #define PHY_TYPE_BIT_VHT BIT(PHY_TYPE_VHT_INDEX) 451 #define PHY_TYPE_BIT_HE BIT(PHY_TYPE_HE_INDEX) 452 453 #define MT_WTBL_RATE_TX_MODE GENMASK(9, 6) 454 #define MT_WTBL_RATE_MCS GENMASK(5, 0) 455 #define MT_WTBL_RATE_NSS GENMASK(12, 10) 456 #define MT_WTBL_RATE_HE_GI GENMASK(7, 4) 457 #define MT_WTBL_RATE_GI GENMASK(3, 0) 458 459 #define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5) 460 #define MT_WTBL_W5_SHORT_GI_20 BIT(8) 461 #define MT_WTBL_W5_SHORT_GI_40 BIT(9) 462 #define MT_WTBL_W5_SHORT_GI_80 BIT(10) 463 #define MT_WTBL_W5_SHORT_GI_160 BIT(11) 464 #define MT_WTBL_W5_BW_CAP GENMASK(13, 12) 465 #define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23) 466 #define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26) 467 #define MT_WTBL_W5_RATE_IDX GENMASK(31, 29) 468 469 enum { 470 WTBL_RESET_AND_SET = 1, 471 WTBL_SET, 472 WTBL_QUERY, 473 WTBL_RESET_ALL 474 }; 475 476 enum { 477 MT_BA_TYPE_INVALID, 478 MT_BA_TYPE_ORIGINATOR, 479 MT_BA_TYPE_RECIPIENT 480 }; 481 482 enum { 483 RST_BA_MAC_TID_MATCH, 484 RST_BA_MAC_MATCH, 485 RST_BA_NO_MATCH 486 }; 487 488 enum { 489 DEV_INFO_ACTIVE, 490 DEV_INFO_MAX_NUM 491 }; 492 493 #define MCU_CMD_ACK BIT(0) 494 #define MCU_CMD_UNI BIT(1) 495 #define MCU_CMD_QUERY BIT(2) 496 497 #define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | \ 498 MCU_CMD_QUERY) 499 500 #define MCU_CE_PREFIX BIT(29) 501 #define MCU_CMD_MASK ~(MCU_CE_PREFIX) 502 503 #define __MCU_CMD_FIELD_ID GENMASK(7, 0) 504 #define __MCU_CMD_FIELD_EXT_ID GENMASK(15, 8) 505 #define __MCU_CMD_FIELD_QUERY BIT(16) 506 #define __MCU_CMD_FIELD_UNI BIT(17) 507 508 #define MCU_CMD(_t) FIELD_PREP(__MCU_CMD_FIELD_ID, \ 509 MCU_CMD_##_t) 510 #define MCU_EXT_CMD(_t) (MCU_CMD(EXT_CID) | \ 511 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ 512 MCU_EXT_CMD_##_t)) 513 #define MCU_EXT_QUERY(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_QUERY) 514 #define MCU_UNI_CMD(_t) (__MCU_CMD_FIELD_UNI | \ 515 FIELD_PREP(__MCU_CMD_FIELD_ID, \ 516 MCU_UNI_CMD_##_t)) 517 518 enum { 519 MCU_EXT_CMD_EFUSE_ACCESS = 0x01, 520 MCU_EXT_CMD_RF_REG_ACCESS = 0x02, 521 MCU_EXT_CMD_RF_TEST = 0x04, 522 MCU_EXT_CMD_PM_STATE_CTRL = 0x07, 523 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08, 524 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11, 525 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13, 526 MCU_EXT_CMD_TXBF_ACTION = 0x1e, 527 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21, 528 MCU_EXT_CMD_THERMAL_PROT = 0x23, 529 MCU_EXT_CMD_STA_REC_UPDATE = 0x25, 530 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26, 531 MCU_EXT_CMD_EDCA_UPDATE = 0x27, 532 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A, 533 MCU_EXT_CMD_THERMAL_CTRL = 0x2c, 534 MCU_EXT_CMD_WTBL_UPDATE = 0x32, 535 MCU_EXT_CMD_SET_DRR_CTRL = 0x36, 536 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a, 537 MCU_EXT_CMD_ATE_CTRL = 0x3d, 538 MCU_EXT_CMD_PROTECT_CTRL = 0x3e, 539 MCU_EXT_CMD_DBDC_CTRL = 0x45, 540 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46, 541 MCU_EXT_CMD_RX_HDR_TRANS = 0x47, 542 MCU_EXT_CMD_MUAR_UPDATE = 0x48, 543 MCU_EXT_CMD_BCN_OFFLOAD = 0x49, 544 MCU_EXT_CMD_RX_AIRTIME_CTRL = 0x4a, 545 MCU_EXT_CMD_SET_RX_PATH = 0x4e, 546 MCU_EXT_CMD_EFUSE_FREE_BLOCK = 0x4f, 547 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58, 548 MCU_EXT_CMD_RXDCOC_CAL = 0x59, 549 MCU_EXT_CMD_GET_MIB_INFO = 0x5a, 550 MCU_EXT_CMD_TXDPD_CAL = 0x60, 551 MCU_EXT_CMD_CAL_CACHE = 0x67, 552 MCU_EXT_CMD_SET_RADAR_TH = 0x7c, 553 MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d, 554 MCU_EXT_CMD_MWDS_SUPPORT = 0x80, 555 MCU_EXT_CMD_SET_SER_TRIGGER = 0x81, 556 MCU_EXT_CMD_SCS_CTRL = 0x82, 557 MCU_EXT_CMD_TWT_AGRT_UPDATE = 0x94, 558 MCU_EXT_CMD_FW_DBG_CTRL = 0x95, 559 MCU_EXT_CMD_OFFCH_SCAN_CTRL = 0x9a, 560 MCU_EXT_CMD_SET_RDD_TH = 0x9d, 561 MCU_EXT_CMD_MURU_CTRL = 0x9f, 562 MCU_EXT_CMD_SET_SPR = 0xa8, 563 MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab, 564 MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac, 565 MCU_EXT_CMD_PHY_STAT_INFO = 0xad, 566 }; 567 568 enum { 569 MCU_UNI_CMD_DEV_INFO_UPDATE = 0x01, 570 MCU_UNI_CMD_BSS_INFO_UPDATE = 0x02, 571 MCU_UNI_CMD_STA_REC_UPDATE = 0x03, 572 MCU_UNI_CMD_SUSPEND = 0x05, 573 MCU_UNI_CMD_OFFLOAD = 0x06, 574 MCU_UNI_CMD_HIF_CTRL = 0x07, 575 }; 576 577 enum { 578 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01, 579 MCU_CMD_FW_START_REQ = 0x02, 580 MCU_CMD_INIT_ACCESS_REG = 0x3, 581 MCU_CMD_NIC_POWER_CTRL = 0x4, 582 MCU_CMD_PATCH_START_REQ = 0x05, 583 MCU_CMD_PATCH_FINISH_REQ = 0x07, 584 MCU_CMD_PATCH_SEM_CONTROL = 0x10, 585 MCU_CMD_WA_PARAM = 0xc4, 586 MCU_CMD_EXT_CID = 0xed, 587 MCU_CMD_FW_SCATTER = 0xee, 588 MCU_CMD_RESTART_DL_REQ = 0xef, 589 }; 590 591 /* offload mcu commands */ 592 enum { 593 MCU_CMD_TEST_CTRL = MCU_CE_PREFIX | 0x01, 594 MCU_CMD_START_HW_SCAN = MCU_CE_PREFIX | 0x03, 595 MCU_CMD_SET_PS_PROFILE = MCU_CE_PREFIX | 0x05, 596 MCU_CMD_SET_CHAN_DOMAIN = MCU_CE_PREFIX | 0x0f, 597 MCU_CMD_SET_BSS_CONNECTED = MCU_CE_PREFIX | 0x16, 598 MCU_CMD_SET_BSS_ABORT = MCU_CE_PREFIX | 0x17, 599 MCU_CMD_CANCEL_HW_SCAN = MCU_CE_PREFIX | 0x1b, 600 MCU_CMD_SET_ROC = MCU_CE_PREFIX | 0x1d, 601 MCU_CMD_SET_P2P_OPPPS = MCU_CE_PREFIX | 0x33, 602 MCU_CMD_SET_RATE_TX_POWER = MCU_CE_PREFIX | 0x5d, 603 MCU_CMD_SCHED_SCAN_ENABLE = MCU_CE_PREFIX | 0x61, 604 MCU_CMD_SCHED_SCAN_REQ = MCU_CE_PREFIX | 0x62, 605 MCU_CMD_GET_NIC_CAPAB = MCU_CE_PREFIX | 0x8a, 606 MCU_CMD_SET_MU_EDCA_PARMS = MCU_CE_PREFIX | 0xb0, 607 MCU_CMD_REG_WRITE = MCU_CE_PREFIX | 0xc0, 608 MCU_CMD_REG_READ = MCU_CE_PREFIX | __MCU_CMD_FIELD_QUERY | 0xc0, 609 MCU_CMD_CHIP_CONFIG = MCU_CE_PREFIX | 0xca, 610 MCU_CMD_FWLOG_2_HOST = MCU_CE_PREFIX | 0xc5, 611 MCU_CMD_GET_WTBL = MCU_CE_PREFIX | 0xcd, 612 MCU_CMD_GET_TXPWR = MCU_CE_PREFIX | 0xd0, 613 }; 614 615 enum { 616 PATCH_SEM_RELEASE, 617 PATCH_SEM_GET 618 }; 619 620 enum { 621 UNI_BSS_INFO_BASIC = 0, 622 UNI_BSS_INFO_RLM = 2, 623 UNI_BSS_INFO_BSS_COLOR = 4, 624 UNI_BSS_INFO_HE_BASIC = 5, 625 UNI_BSS_INFO_BCN_CONTENT = 7, 626 UNI_BSS_INFO_QBSS = 15, 627 UNI_BSS_INFO_UAPSD = 19, 628 UNI_BSS_INFO_PS = 21, 629 UNI_BSS_INFO_BCNFT = 22, 630 }; 631 632 enum { 633 UNI_OFFLOAD_OFFLOAD_ARP, 634 UNI_OFFLOAD_OFFLOAD_ND, 635 UNI_OFFLOAD_OFFLOAD_GTK_REKEY, 636 UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT, 637 }; 638 639 enum { 640 MT_NIC_CAP_TX_RESOURCE, 641 MT_NIC_CAP_TX_EFUSE_ADDR, 642 MT_NIC_CAP_COEX, 643 MT_NIC_CAP_SINGLE_SKU, 644 MT_NIC_CAP_CSUM_OFFLOAD, 645 MT_NIC_CAP_HW_VER, 646 MT_NIC_CAP_SW_VER, 647 MT_NIC_CAP_MAC_ADDR, 648 MT_NIC_CAP_PHY, 649 MT_NIC_CAP_MAC, 650 MT_NIC_CAP_FRAME_BUF, 651 MT_NIC_CAP_BEAM_FORM, 652 MT_NIC_CAP_LOCATION, 653 MT_NIC_CAP_MUMIMO, 654 MT_NIC_CAP_BUFFER_MODE_INFO, 655 MT_NIC_CAP_HW_ADIE_VERSION = 0x14, 656 MT_NIC_CAP_ANTSWP = 0x16, 657 MT_NIC_CAP_WFDMA_REALLOC, 658 MT_NIC_CAP_6G, 659 }; 660 661 #define UNI_WOW_DETECT_TYPE_MAGIC BIT(0) 662 #define UNI_WOW_DETECT_TYPE_ANY BIT(1) 663 #define UNI_WOW_DETECT_TYPE_DISCONNECT BIT(2) 664 #define UNI_WOW_DETECT_TYPE_GTK_REKEY_FAIL BIT(3) 665 #define UNI_WOW_DETECT_TYPE_BCN_LOST BIT(4) 666 #define UNI_WOW_DETECT_TYPE_SCH_SCAN_HIT BIT(5) 667 #define UNI_WOW_DETECT_TYPE_BITMAP BIT(6) 668 669 enum { 670 UNI_SUSPEND_MODE_SETTING, 671 UNI_SUSPEND_WOW_CTRL, 672 UNI_SUSPEND_WOW_GPIO_PARAM, 673 UNI_SUSPEND_WOW_WAKEUP_PORT, 674 UNI_SUSPEND_WOW_PATTERN, 675 }; 676 677 enum { 678 WOW_USB = 1, 679 WOW_PCIE = 2, 680 WOW_GPIO = 3, 681 }; 682 683 struct mt76_connac_bss_basic_tlv { 684 __le16 tag; 685 __le16 len; 686 u8 active; 687 u8 omac_idx; 688 u8 hw_bss_idx; 689 u8 band_idx; 690 __le32 conn_type; 691 u8 conn_state; 692 u8 wmm_idx; 693 u8 bssid[ETH_ALEN]; 694 __le16 bmc_tx_wlan_idx; 695 __le16 bcn_interval; 696 u8 dtim_period; 697 u8 phymode; /* bit(0): A 698 * bit(1): B 699 * bit(2): G 700 * bit(3): GN 701 * bit(4): AN 702 * bit(5): AC 703 * bit(6): AX2 704 * bit(7): AX5 705 * bit(8): AX6 706 */ 707 __le16 sta_idx; 708 __le16 nonht_basic_phy; 709 u8 phymode_ext; /* bit(0) AX_6G */ 710 u8 pad[1]; 711 } __packed; 712 713 struct mt76_connac_bss_qos_tlv { 714 __le16 tag; 715 __le16 len; 716 u8 qos; 717 u8 pad[3]; 718 } __packed; 719 720 struct mt76_connac_beacon_loss_event { 721 u8 bss_idx; 722 u8 reason; 723 u8 pad[2]; 724 } __packed; 725 726 struct mt76_connac_mcu_bss_event { 727 u8 bss_idx; 728 u8 is_absent; 729 u8 free_quota; 730 u8 pad; 731 } __packed; 732 733 struct mt76_connac_mcu_scan_ssid { 734 __le32 ssid_len; 735 u8 ssid[IEEE80211_MAX_SSID_LEN]; 736 } __packed; 737 738 struct mt76_connac_mcu_scan_channel { 739 u8 band; /* 1: 2.4GHz 740 * 2: 5.0GHz 741 * Others: Reserved 742 */ 743 u8 channel_num; 744 } __packed; 745 746 struct mt76_connac_mcu_scan_match { 747 __le32 rssi_th; 748 u8 ssid[IEEE80211_MAX_SSID_LEN]; 749 u8 ssid_len; 750 u8 rsv[3]; 751 } __packed; 752 753 struct mt76_connac_hw_scan_req { 754 u8 seq_num; 755 u8 bss_idx; 756 u8 scan_type; /* 0: PASSIVE SCAN 757 * 1: ACTIVE SCAN 758 */ 759 u8 ssid_type; /* BIT(0) wildcard SSID 760 * BIT(1) P2P wildcard SSID 761 * BIT(2) specified SSID + wildcard SSID 762 * BIT(2) + ssid_type_ext BIT(0) specified SSID only 763 */ 764 u8 ssids_num; 765 u8 probe_req_num; /* Number of probe request for each SSID */ 766 u8 scan_func; /* BIT(0) Enable random MAC scan 767 * BIT(1) Disable DBDC scan type 1~3. 768 * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan). 769 */ 770 u8 version; /* 0: Not support fields after ies. 771 * 1: Support fields after ies. 772 */ 773 struct mt76_connac_mcu_scan_ssid ssids[4]; 774 __le16 probe_delay_time; 775 __le16 channel_dwell_time; /* channel Dwell interval */ 776 __le16 timeout_value; 777 u8 channel_type; /* 0: Full channels 778 * 1: Only 2.4GHz channels 779 * 2: Only 5GHz channels 780 * 3: P2P social channel only (channel #1, #6 and #11) 781 * 4: Specified channels 782 * Others: Reserved 783 */ 784 u8 channels_num; /* valid when channel_type is 4 */ 785 /* valid when channels_num is set */ 786 struct mt76_connac_mcu_scan_channel channels[32]; 787 __le16 ies_len; 788 u8 ies[MT76_CONNAC_SCAN_IE_LEN]; 789 /* following fields are valid if version > 0 */ 790 u8 ext_channels_num; 791 u8 ext_ssids_num; 792 __le16 channel_min_dwell_time; 793 struct mt76_connac_mcu_scan_channel ext_channels[32]; 794 struct mt76_connac_mcu_scan_ssid ext_ssids[6]; 795 u8 bssid[ETH_ALEN]; 796 u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */ 797 u8 pad[63]; 798 u8 ssid_type_ext; 799 } __packed; 800 801 #define MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM 64 802 803 struct mt76_connac_hw_scan_done { 804 u8 seq_num; 805 u8 sparse_channel_num; 806 struct mt76_connac_mcu_scan_channel sparse_channel; 807 u8 complete_channel_num; 808 u8 current_state; 809 u8 version; 810 u8 pad; 811 __le32 beacon_scan_num; 812 u8 pno_enabled; 813 u8 pad2[3]; 814 u8 sparse_channel_valid_num; 815 u8 pad3[3]; 816 u8 channel_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 817 /* idle format for channel_idle_time 818 * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms) 819 * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms) 820 * 2: dwell time (16us) 821 */ 822 __le16 channel_idle_time[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 823 /* beacon and probe response count */ 824 u8 beacon_probe_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 825 u8 mdrdy_count[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 826 __le32 beacon_2g_num; 827 __le32 beacon_5g_num; 828 } __packed; 829 830 struct mt76_connac_sched_scan_req { 831 u8 version; 832 u8 seq_num; 833 u8 stop_on_match; 834 u8 ssids_num; 835 u8 match_num; 836 u8 pad; 837 __le16 ie_len; 838 struct mt76_connac_mcu_scan_ssid ssids[MT76_CONNAC_MAX_SCHED_SCAN_SSID]; 839 struct mt76_connac_mcu_scan_match match[MT76_CONNAC_MAX_SCAN_MATCH]; 840 u8 channel_type; 841 u8 channels_num; 842 u8 intervals_num; 843 u8 scan_func; /* MT7663: BIT(0) eable random mac address */ 844 struct mt76_connac_mcu_scan_channel channels[64]; 845 __le16 intervals[MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL]; 846 union { 847 struct { 848 u8 random_mac[ETH_ALEN]; 849 u8 pad2[58]; 850 } mt7663; 851 struct { 852 u8 bss_idx; 853 u8 pad1[3]; 854 __le32 delay; 855 u8 pad2[12]; 856 u8 random_mac[ETH_ALEN]; 857 u8 pad3[38]; 858 } mt7921; 859 }; 860 } __packed; 861 862 struct mt76_connac_sched_scan_done { 863 u8 seq_num; 864 u8 status; /* 0: ssid found */ 865 __le16 pad; 866 } __packed; 867 868 struct bss_info_uni_bss_color { 869 __le16 tag; 870 __le16 len; 871 u8 enable; 872 u8 bss_color; 873 u8 rsv[2]; 874 } __packed; 875 876 struct bss_info_uni_he { 877 __le16 tag; 878 __le16 len; 879 __le16 he_rts_thres; 880 u8 he_pe_duration; 881 u8 su_disable; 882 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 883 u8 rsv[2]; 884 } __packed; 885 886 struct mt76_connac_gtk_rekey_tlv { 887 __le16 tag; 888 __le16 len; 889 u8 kek[NL80211_KEK_LEN]; 890 u8 kck[NL80211_KCK_LEN]; 891 u8 replay_ctr[NL80211_REPLAY_CTR_LEN]; 892 u8 rekey_mode; /* 0: rekey offload enable 893 * 1: rekey offload disable 894 * 2: rekey update 895 */ 896 u8 keyid; 897 u8 option; /* 1: rekey data update without enabling offload */ 898 u8 pad[1]; 899 __le32 proto; /* WPA-RSN-WAPI-OPSN */ 900 __le32 pairwise_cipher; 901 __le32 group_cipher; 902 __le32 key_mgmt; /* NONE-PSK-IEEE802.1X */ 903 __le32 mgmt_group_cipher; 904 u8 reserverd[4]; 905 } __packed; 906 907 #define MT76_CONNAC_WOW_MASK_MAX_LEN 16 908 #define MT76_CONNAC_WOW_PATTEN_MAX_LEN 128 909 910 struct mt76_connac_wow_pattern_tlv { 911 __le16 tag; 912 __le16 len; 913 u8 index; /* pattern index */ 914 u8 enable; /* 0: disable 915 * 1: enable 916 */ 917 u8 data_len; /* pattern length */ 918 u8 pad; 919 u8 mask[MT76_CONNAC_WOW_MASK_MAX_LEN]; 920 u8 pattern[MT76_CONNAC_WOW_PATTEN_MAX_LEN]; 921 u8 rsv[4]; 922 } __packed; 923 924 struct mt76_connac_wow_ctrl_tlv { 925 __le16 tag; 926 __le16 len; 927 u8 cmd; /* 0x1: PM_WOWLAN_REQ_START 928 * 0x2: PM_WOWLAN_REQ_STOP 929 * 0x3: PM_WOWLAN_PARAM_CLEAR 930 */ 931 u8 trigger; /* 0: NONE 932 * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT 933 * BIT(1): NL80211_WOWLAN_TRIG_ANY 934 * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT 935 * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE 936 * BIT(4): BEACON_LOST 937 * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT 938 */ 939 u8 wakeup_hif; /* 0x0: HIF_SDIO 940 * 0x1: HIF_USB 941 * 0x2: HIF_PCIE 942 * 0x3: HIF_GPIO 943 */ 944 u8 pad; 945 u8 rsv[4]; 946 } __packed; 947 948 struct mt76_connac_wow_gpio_param_tlv { 949 __le16 tag; 950 __le16 len; 951 u8 gpio_pin; 952 u8 trigger_lvl; 953 u8 pad[2]; 954 __le32 gpio_interval; 955 u8 rsv[4]; 956 } __packed; 957 958 struct mt76_connac_arpns_tlv { 959 __le16 tag; 960 __le16 len; 961 u8 mode; 962 u8 ips_num; 963 u8 option; 964 u8 pad[1]; 965 } __packed; 966 967 struct mt76_connac_suspend_tlv { 968 __le16 tag; 969 __le16 len; 970 u8 enable; /* 0: suspend mode disabled 971 * 1: suspend mode enabled 972 */ 973 u8 mdtim; /* LP parameter */ 974 u8 wow_suspend; /* 0: update by origin policy 975 * 1: update by wow dtim 976 */ 977 u8 pad[5]; 978 } __packed; 979 980 enum mt76_sta_info_state { 981 MT76_STA_INFO_STATE_NONE, 982 MT76_STA_INFO_STATE_AUTH, 983 MT76_STA_INFO_STATE_ASSOC 984 }; 985 986 struct mt76_sta_cmd_info { 987 struct ieee80211_sta *sta; 988 struct mt76_wcid *wcid; 989 990 struct ieee80211_vif *vif; 991 992 bool offload_fw; 993 bool enable; 994 bool newly; 995 int cmd; 996 u8 rcpi; 997 u8 state; 998 }; 999 1000 #define MT_SKU_POWER_LIMIT 161 1001 1002 struct mt76_connac_sku_tlv { 1003 u8 channel; 1004 s8 pwr_limit[MT_SKU_POWER_LIMIT]; 1005 } __packed; 1006 1007 struct mt76_connac_tx_power_limit_tlv { 1008 /* DW0 - common info*/ 1009 u8 ver; 1010 u8 pad0; 1011 __le16 len; 1012 /* DW1 - cmd hint */ 1013 u8 n_chan; /* # channel */ 1014 u8 band; /* 2.4GHz - 5GHz - 6GHz */ 1015 u8 last_msg; 1016 u8 pad1; 1017 /* DW3 */ 1018 u8 alpha2[4]; /* regulatory_request.alpha2 */ 1019 u8 pad2[32]; 1020 } __packed; 1021 1022 struct mt76_connac_config { 1023 __le16 id; 1024 u8 type; 1025 u8 resp_type; 1026 __le16 data_size; 1027 __le16 resv; 1028 u8 data[320]; 1029 } __packed; 1030 1031 #define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id) 1032 #define to_wcid_hi(id) FIELD_GET(GENMASK(9, 8), (u16)id) 1033 1034 static inline void 1035 mt76_connac_mcu_get_wlan_idx(struct mt76_dev *dev, struct mt76_wcid *wcid, 1036 u8 *wlan_idx_lo, u8 *wlan_idx_hi) 1037 { 1038 *wlan_idx_hi = 0; 1039 1040 if (is_mt7921(dev)) { 1041 *wlan_idx_lo = wcid ? to_wcid_lo(wcid->idx) : 0; 1042 *wlan_idx_hi = wcid ? to_wcid_hi(wcid->idx) : 0; 1043 } else { 1044 *wlan_idx_lo = wcid ? wcid->idx : 0; 1045 } 1046 } 1047 1048 struct sk_buff * 1049 mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif, 1050 struct mt76_wcid *wcid); 1051 struct wtbl_req_hdr * 1052 mt76_connac_mcu_alloc_wtbl_req(struct mt76_dev *dev, struct mt76_wcid *wcid, 1053 int cmd, void *sta_wtbl, struct sk_buff **skb); 1054 struct tlv *mt76_connac_mcu_add_nested_tlv(struct sk_buff *skb, int tag, 1055 int len, void *sta_ntlv, 1056 void *sta_wtbl); 1057 static inline struct tlv * 1058 mt76_connac_mcu_add_tlv(struct sk_buff *skb, int tag, int len) 1059 { 1060 return mt76_connac_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL); 1061 } 1062 1063 int mt76_connac_mcu_set_channel_domain(struct mt76_phy *phy); 1064 int mt76_connac_mcu_set_vif_ps(struct mt76_dev *dev, struct ieee80211_vif *vif); 1065 void mt76_connac_mcu_sta_basic_tlv(struct sk_buff *skb, 1066 struct ieee80211_vif *vif, 1067 struct ieee80211_sta *sta, bool enable, 1068 bool newly); 1069 void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1070 struct ieee80211_vif *vif, 1071 struct ieee80211_sta *sta, void *sta_wtbl, 1072 void *wtbl_tlv); 1073 void mt76_connac_mcu_wtbl_hdr_trans_tlv(struct sk_buff *skb, 1074 struct ieee80211_vif *vif, 1075 struct mt76_wcid *wcid, 1076 void *sta_wtbl, void *wtbl_tlv); 1077 int mt76_connac_mcu_sta_update_hdr_trans(struct mt76_dev *dev, 1078 struct ieee80211_vif *vif, 1079 struct mt76_wcid *wcid, int cmd); 1080 void mt76_connac_mcu_sta_tlv(struct mt76_phy *mphy, struct sk_buff *skb, 1081 struct ieee80211_sta *sta, 1082 struct ieee80211_vif *vif, 1083 u8 rcpi, u8 state); 1084 void mt76_connac_mcu_wtbl_ht_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1085 struct ieee80211_sta *sta, void *sta_wtbl, 1086 void *wtbl_tlv); 1087 void mt76_connac_mcu_wtbl_ba_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1088 struct ieee80211_ampdu_params *params, 1089 bool enable, bool tx, void *sta_wtbl, 1090 void *wtbl_tlv); 1091 void mt76_connac_mcu_sta_ba_tlv(struct sk_buff *skb, 1092 struct ieee80211_ampdu_params *params, 1093 bool enable, bool tx); 1094 int mt76_connac_mcu_uni_add_dev(struct mt76_phy *phy, 1095 struct ieee80211_vif *vif, 1096 struct mt76_wcid *wcid, 1097 bool enable); 1098 int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif, 1099 struct ieee80211_ampdu_params *params, 1100 bool enable, bool tx); 1101 int mt76_connac_mcu_uni_add_bss(struct mt76_phy *phy, 1102 struct ieee80211_vif *vif, 1103 struct mt76_wcid *wcid, 1104 bool enable); 1105 int mt76_connac_mcu_sta_cmd(struct mt76_phy *phy, 1106 struct mt76_sta_cmd_info *info); 1107 void mt76_connac_mcu_beacon_loss_iter(void *priv, u8 *mac, 1108 struct ieee80211_vif *vif); 1109 int mt76_connac_mcu_set_rts_thresh(struct mt76_dev *dev, u32 val, u8 band); 1110 int mt76_connac_mcu_set_mac_enable(struct mt76_dev *dev, int band, bool enable, 1111 bool hdr_trans); 1112 int mt76_connac_mcu_init_download(struct mt76_dev *dev, u32 addr, u32 len, 1113 u32 mode); 1114 int mt76_connac_mcu_start_patch(struct mt76_dev *dev); 1115 int mt76_connac_mcu_patch_sem_ctrl(struct mt76_dev *dev, bool get); 1116 int mt76_connac_mcu_start_firmware(struct mt76_dev *dev, u32 addr, u32 option); 1117 int mt76_connac_mcu_get_nic_capability(struct mt76_phy *phy); 1118 1119 int mt76_connac_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif, 1120 struct ieee80211_scan_request *scan_req); 1121 int mt76_connac_mcu_cancel_hw_scan(struct mt76_phy *phy, 1122 struct ieee80211_vif *vif); 1123 int mt76_connac_mcu_sched_scan_req(struct mt76_phy *phy, 1124 struct ieee80211_vif *vif, 1125 struct cfg80211_sched_scan_request *sreq); 1126 int mt76_connac_mcu_sched_scan_enable(struct mt76_phy *phy, 1127 struct ieee80211_vif *vif, 1128 bool enable); 1129 int mt76_connac_mcu_update_arp_filter(struct mt76_dev *dev, 1130 struct mt76_vif *vif, 1131 struct ieee80211_bss_conf *info); 1132 int mt76_connac_mcu_update_gtk_rekey(struct ieee80211_hw *hw, 1133 struct ieee80211_vif *vif, 1134 struct cfg80211_gtk_rekey_data *key); 1135 int mt76_connac_mcu_set_hif_suspend(struct mt76_dev *dev, bool suspend); 1136 void mt76_connac_mcu_set_suspend_iter(void *priv, u8 *mac, 1137 struct ieee80211_vif *vif); 1138 int mt76_connac_sta_state_dp(struct mt76_dev *dev, 1139 enum ieee80211_sta_state old_state, 1140 enum ieee80211_sta_state new_state); 1141 int mt76_connac_mcu_chip_config(struct mt76_dev *dev); 1142 int mt76_connac_mcu_set_deep_sleep(struct mt76_dev *dev, bool enable); 1143 void mt76_connac_mcu_coredump_event(struct mt76_dev *dev, struct sk_buff *skb, 1144 struct mt76_connac_coredump *coredump); 1145 int mt76_connac_mcu_set_rate_txpower(struct mt76_phy *phy); 1146 int mt76_connac_mcu_set_p2p_oppps(struct ieee80211_hw *hw, 1147 struct ieee80211_vif *vif); 1148 u32 mt76_connac_mcu_reg_rr(struct mt76_dev *dev, u32 offset); 1149 void mt76_connac_mcu_reg_wr(struct mt76_dev *dev, u32 offset, u32 val); 1150 #endif /* __MT76_CONNAC_MCU_H */ 1151