1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT76_CONNAC_MCU_H 5 #define __MT76_CONNAC_MCU_H 6 7 #include "mt76_connac.h" 8 9 #define FW_FEATURE_SET_ENCRYPT BIT(0) 10 #define FW_FEATURE_SET_KEY_IDX GENMASK(2, 1) 11 #define FW_FEATURE_ENCRY_MODE BIT(4) 12 #define FW_FEATURE_OVERRIDE_ADDR BIT(5) 13 14 #define DL_MODE_ENCRYPT BIT(0) 15 #define DL_MODE_KEY_IDX GENMASK(2, 1) 16 #define DL_MODE_RESET_SEC_IV BIT(3) 17 #define DL_MODE_WORKING_PDA_CR4 BIT(4) 18 #define DL_MODE_VALID_RAM_ENTRY BIT(5) 19 #define DL_CONFIG_ENCRY_MODE_SEL BIT(6) 20 #define DL_MODE_NEED_RSP BIT(31) 21 22 #define FW_START_OVERRIDE BIT(0) 23 #define FW_START_WORKING_PDA_CR4 BIT(2) 24 25 #define PATCH_SEC_NOT_SUPPORT GENMASK(31, 0) 26 #define PATCH_SEC_TYPE_MASK GENMASK(15, 0) 27 #define PATCH_SEC_TYPE_INFO 0x2 28 29 #define PATCH_SEC_ENC_TYPE_MASK GENMASK(31, 24) 30 #define PATCH_SEC_ENC_TYPE_PLAIN 0x00 31 #define PATCH_SEC_ENC_TYPE_AES 0x01 32 #define PATCH_SEC_ENC_TYPE_SCRAMBLE 0x02 33 #define PATCH_SEC_ENC_SCRAMBLE_INFO_MASK GENMASK(15, 0) 34 #define PATCH_SEC_ENC_AES_KEY_MASK GENMASK(7, 0) 35 36 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10)) 37 #define MCU_PKT_ID 0xa0 38 39 struct mt76_connac2_mcu_txd { 40 __le32 txd[8]; 41 42 __le16 len; 43 __le16 pq_id; 44 45 u8 cid; 46 u8 pkt_type; 47 u8 set_query; /* FW don't care */ 48 u8 seq; 49 50 u8 uc_d2b0_rev; 51 u8 ext_cid; 52 u8 s2d_index; 53 u8 ext_cid_ack; 54 55 u32 rsv[5]; 56 } __packed __aligned(4); 57 58 /** 59 * struct mt76_connac2_mcu_uni_txd - mcu command descriptor for firmware v3 60 * @txd: hardware descriptor 61 * @len: total length not including txd 62 * @cid: command identifier 63 * @pkt_type: must be 0xa0 (cmd packet by long format) 64 * @frag_n: fragment number 65 * @seq: sequence number 66 * @checksum: 0 mean there is no checksum 67 * @s2d_index: index for command source and destination 68 * Definition | value | note 69 * CMD_S2D_IDX_H2N | 0x00 | command from HOST to WM 70 * CMD_S2D_IDX_C2N | 0x01 | command from WA to WM 71 * CMD_S2D_IDX_H2C | 0x02 | command from HOST to WA 72 * CMD_S2D_IDX_H2N_AND_H2C | 0x03 | command from HOST to WA and WM 73 * 74 * @option: command option 75 * BIT[0]: UNI_CMD_OPT_BIT_ACK 76 * set to 1 to request a fw reply 77 * if UNI_CMD_OPT_BIT_0_ACK is set and UNI_CMD_OPT_BIT_2_SET_QUERY 78 * is set, mcu firmware will send response event EID = 0x01 79 * (UNI_EVENT_ID_CMD_RESULT) to the host. 80 * BIT[1]: UNI_CMD_OPT_BIT_UNI_CMD 81 * 0: original command 82 * 1: unified command 83 * BIT[2]: UNI_CMD_OPT_BIT_SET_QUERY 84 * 0: QUERY command 85 * 1: SET command 86 */ 87 struct mt76_connac2_mcu_uni_txd { 88 __le32 txd[8]; 89 90 /* DW1 */ 91 __le16 len; 92 __le16 cid; 93 94 /* DW2 */ 95 u8 rsv; 96 u8 pkt_type; 97 u8 frag_n; 98 u8 seq; 99 100 /* DW3 */ 101 __le16 checksum; 102 u8 s2d_index; 103 u8 option; 104 105 /* DW4 */ 106 u8 rsv1[4]; 107 } __packed __aligned(4); 108 109 struct mt76_connac2_mcu_rxd { 110 __le32 rxd[6]; 111 112 __le16 len; 113 __le16 pkt_type_id; 114 115 u8 eid; 116 u8 seq; 117 u8 rsv[2]; 118 119 u8 ext_eid; 120 u8 rsv1[2]; 121 u8 s2d_index; 122 }; 123 124 struct mt76_connac2_patch_hdr { 125 char build_date[16]; 126 char platform[4]; 127 __be32 hw_sw_ver; 128 __be32 patch_ver; 129 __be16 checksum; 130 u16 rsv; 131 struct { 132 __be32 patch_ver; 133 __be32 subsys; 134 __be32 feature; 135 __be32 n_region; 136 __be32 crc; 137 u32 rsv[11]; 138 } desc; 139 } __packed; 140 141 struct mt76_connac2_patch_sec { 142 __be32 type; 143 __be32 offs; 144 __be32 size; 145 union { 146 __be32 spec[13]; 147 struct { 148 __be32 addr; 149 __be32 len; 150 __be32 sec_key_idx; 151 __be32 align_len; 152 u32 rsv[9]; 153 } info; 154 }; 155 } __packed; 156 157 struct mt76_connac2_fw_trailer { 158 u8 chip_id; 159 u8 eco_code; 160 u8 n_region; 161 u8 format_ver; 162 u8 format_flag; 163 u8 rsv[2]; 164 char fw_ver[10]; 165 char build_date[15]; 166 __le32 crc; 167 } __packed; 168 169 struct mt76_connac2_fw_region { 170 __le32 decomp_crc; 171 __le32 decomp_len; 172 __le32 decomp_blk_sz; 173 u8 rsv[4]; 174 __le32 addr; 175 __le32 len; 176 u8 feature_set; 177 u8 rsv1[15]; 178 } __packed; 179 180 struct tlv { 181 __le16 tag; 182 __le16 len; 183 } __packed; 184 185 struct bss_info_omac { 186 __le16 tag; 187 __le16 len; 188 u8 hw_bss_idx; 189 u8 omac_idx; 190 u8 band_idx; 191 u8 rsv0; 192 __le32 conn_type; 193 u32 rsv1; 194 } __packed; 195 196 struct bss_info_basic { 197 __le16 tag; 198 __le16 len; 199 __le32 network_type; 200 u8 active; 201 u8 rsv0; 202 __le16 bcn_interval; 203 u8 bssid[ETH_ALEN]; 204 u8 wmm_idx; 205 u8 dtim_period; 206 u8 bmc_wcid_lo; 207 u8 cipher; 208 u8 phy_mode; 209 u8 max_bssid; /* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */ 210 u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */ 211 u8 bmc_wcid_hi; /* high Byte and version */ 212 u8 rsv[2]; 213 } __packed; 214 215 struct bss_info_rf_ch { 216 __le16 tag; 217 __le16 len; 218 u8 pri_ch; 219 u8 center_ch0; 220 u8 center_ch1; 221 u8 bw; 222 u8 he_ru26_block; /* 1: don't send HETB in RU26, 0: allow */ 223 u8 he_all_disable; /* 1: disallow all HETB, 0: allow */ 224 u8 rsv[2]; 225 } __packed; 226 227 struct bss_info_ext_bss { 228 __le16 tag; 229 __le16 len; 230 __le32 mbss_tsf_offset; /* in unit of us */ 231 u8 rsv[8]; 232 } __packed; 233 234 enum { 235 BSS_INFO_OMAC, 236 BSS_INFO_BASIC, 237 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */ 238 BSS_INFO_PM, /* sta only */ 239 BSS_INFO_UAPSD, /* sta only */ 240 BSS_INFO_ROAM_DETECT, /* obsoleted */ 241 BSS_INFO_LQ_RM, /* obsoleted */ 242 BSS_INFO_EXT_BSS, 243 BSS_INFO_BMC_RATE, /* for bmc rate control in CR4 */ 244 BSS_INFO_SYNC_MODE, /* obsoleted */ 245 BSS_INFO_RA, 246 BSS_INFO_HW_AMSDU, 247 BSS_INFO_BSS_COLOR, 248 BSS_INFO_HE_BASIC, 249 BSS_INFO_PROTECT_INFO, 250 BSS_INFO_OFFLOAD, 251 BSS_INFO_11V_MBSSID, 252 BSS_INFO_MAX_NUM 253 }; 254 255 /* sta_rec */ 256 257 struct sta_ntlv_hdr { 258 u8 rsv[2]; 259 __le16 tlv_num; 260 } __packed; 261 262 struct sta_req_hdr { 263 u8 bss_idx; 264 u8 wlan_idx_lo; 265 __le16 tlv_num; 266 u8 is_tlv_append; 267 u8 muar_idx; 268 u8 wlan_idx_hi; 269 u8 rsv; 270 } __packed; 271 272 struct sta_rec_basic { 273 __le16 tag; 274 __le16 len; 275 __le32 conn_type; 276 u8 conn_state; 277 u8 qos; 278 __le16 aid; 279 u8 peer_addr[ETH_ALEN]; 280 #define EXTRA_INFO_VER BIT(0) 281 #define EXTRA_INFO_NEW BIT(1) 282 __le16 extra_info; 283 } __packed; 284 285 struct sta_rec_ht { 286 __le16 tag; 287 __le16 len; 288 __le16 ht_cap; 289 u16 rsv; 290 } __packed; 291 292 struct sta_rec_vht { 293 __le16 tag; 294 __le16 len; 295 __le32 vht_cap; 296 __le16 vht_rx_mcs_map; 297 __le16 vht_tx_mcs_map; 298 /* mt7915 - mt7921 */ 299 u8 rts_bw_sig; 300 u8 rsv[3]; 301 } __packed; 302 303 struct sta_rec_uapsd { 304 __le16 tag; 305 __le16 len; 306 u8 dac_map; 307 u8 tac_map; 308 u8 max_sp; 309 u8 rsv0; 310 __le16 listen_interval; 311 u8 rsv1[2]; 312 } __packed; 313 314 struct sta_rec_ba { 315 __le16 tag; 316 __le16 len; 317 u8 tid; 318 u8 ba_type; 319 u8 amsdu; 320 u8 ba_en; 321 __le16 ssn; 322 __le16 winsize; 323 } __packed; 324 325 struct sta_rec_he { 326 __le16 tag; 327 __le16 len; 328 329 __le32 he_cap; 330 331 u8 t_frame_dur; 332 u8 max_ampdu_exp; 333 u8 bw_set; 334 u8 device_class; 335 u8 dcm_tx_mode; 336 u8 dcm_tx_max_nss; 337 u8 dcm_rx_mode; 338 u8 dcm_rx_max_nss; 339 u8 dcm_max_ru; 340 u8 punc_pream_rx; 341 u8 pkt_ext; 342 u8 rsv1; 343 344 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 345 346 u8 rsv2[2]; 347 } __packed; 348 349 struct sta_rec_amsdu { 350 __le16 tag; 351 __le16 len; 352 u8 max_amsdu_num; 353 u8 max_mpdu_size; 354 u8 amsdu_en; 355 u8 rsv; 356 } __packed; 357 358 struct sta_rec_state { 359 __le16 tag; 360 __le16 len; 361 __le32 flags; 362 u8 state; 363 u8 vht_opmode; 364 u8 action; 365 u8 rsv[1]; 366 } __packed; 367 368 #define RA_LEGACY_OFDM GENMASK(13, 6) 369 #define RA_LEGACY_CCK GENMASK(3, 0) 370 #define HT_MCS_MASK_NUM 10 371 struct sta_rec_ra_info { 372 __le16 tag; 373 __le16 len; 374 __le16 legacy; 375 u8 rx_mcs_bitmask[HT_MCS_MASK_NUM]; 376 } __packed; 377 378 struct sta_rec_phy { 379 __le16 tag; 380 __le16 len; 381 __le16 basic_rate; 382 u8 phy_type; 383 u8 ampdu; 384 u8 rts_policy; 385 u8 rcpi; 386 u8 rsv[2]; 387 } __packed; 388 389 struct sta_rec_he_6g_capa { 390 __le16 tag; 391 __le16 len; 392 __le16 capa; 393 u8 rsv[2]; 394 } __packed; 395 396 struct sec_key { 397 u8 cipher_id; 398 u8 cipher_len; 399 u8 key_id; 400 u8 key_len; 401 u8 key[32]; 402 } __packed; 403 404 struct sta_rec_sec { 405 __le16 tag; 406 __le16 len; 407 u8 add; 408 u8 n_cipher; 409 u8 rsv[2]; 410 411 struct sec_key key[2]; 412 } __packed; 413 414 struct sta_rec_bf { 415 __le16 tag; 416 __le16 len; 417 418 __le16 pfmu; /* 0xffff: no access right for PFMU */ 419 bool su_mu; /* 0: SU, 1: MU */ 420 u8 bf_cap; /* 0: iBF, 1: eBF */ 421 u8 sounding_phy; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT */ 422 u8 ndpa_rate; 423 u8 ndp_rate; 424 u8 rept_poll_rate; 425 u8 tx_mode; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */ 426 u8 ncol; 427 u8 nrow; 428 u8 bw; /* 0: 20M, 1: 40M, 2: 80M, 3: 160M */ 429 430 u8 mem_total; 431 u8 mem_20m; 432 struct { 433 u8 row; 434 u8 col: 6, row_msb: 2; 435 } mem[4]; 436 437 __le16 smart_ant; 438 u8 se_idx; 439 u8 auto_sounding; /* b7: low traffic indicator 440 * b6: Stop sounding for this entry 441 * b5 ~ b0: postpone sounding 442 */ 443 u8 ibf_timeout; 444 u8 ibf_dbw; 445 u8 ibf_ncol; 446 u8 ibf_nrow; 447 u8 nrow_bw160; 448 u8 ncol_bw160; 449 u8 ru_start_idx; 450 u8 ru_end_idx; 451 452 bool trigger_su; 453 bool trigger_mu; 454 bool ng16_su; 455 bool ng16_mu; 456 bool codebook42_su; 457 bool codebook75_mu; 458 459 u8 he_ltf; 460 u8 rsv[3]; 461 } __packed; 462 463 struct sta_rec_bfee { 464 __le16 tag; 465 __le16 len; 466 bool fb_identity_matrix; /* 1: feedback identity matrix */ 467 bool ignore_feedback; /* 1: ignore */ 468 u8 rsv[2]; 469 } __packed; 470 471 struct sta_rec_muru { 472 __le16 tag; 473 __le16 len; 474 475 struct { 476 bool ofdma_dl_en; 477 bool ofdma_ul_en; 478 bool mimo_dl_en; 479 bool mimo_ul_en; 480 u8 rsv[4]; 481 } cfg; 482 483 struct { 484 u8 punc_pream_rx; 485 bool he_20m_in_40m_2g; 486 bool he_20m_in_160m; 487 bool he_80m_in_160m; 488 bool lt16_sigb; 489 bool rx_su_comp_sigb; 490 bool rx_su_non_comp_sigb; 491 u8 rsv; 492 } ofdma_dl; 493 494 struct { 495 u8 t_frame_dur; 496 u8 mu_cascading; 497 u8 uo_ra; 498 u8 he_2x996_tone; 499 u8 rx_t_frame_11ac; 500 u8 rsv[3]; 501 } ofdma_ul; 502 503 struct { 504 bool vht_mu_bfee; 505 bool partial_bw_dl_mimo; 506 u8 rsv[2]; 507 } mimo_dl; 508 509 struct { 510 bool full_ul_mimo; 511 bool partial_ul_mimo; 512 u8 rsv[2]; 513 } mimo_ul; 514 } __packed; 515 516 struct sta_phy { 517 u8 type; 518 u8 flag; 519 u8 stbc; 520 u8 sgi; 521 u8 bw; 522 u8 ldpc; 523 u8 mcs; 524 u8 nss; 525 u8 he_ltf; 526 }; 527 528 struct sta_rec_ra { 529 __le16 tag; 530 __le16 len; 531 532 u8 valid; 533 u8 auto_rate; 534 u8 phy_mode; 535 u8 channel; 536 u8 bw; 537 u8 disable_cck; 538 u8 ht_mcs32; 539 u8 ht_gf; 540 u8 ht_mcs[4]; 541 u8 mmps_mode; 542 u8 gband_256; 543 u8 af; 544 u8 auth_wapi_mode; 545 u8 rate_len; 546 547 u8 supp_mode; 548 u8 supp_cck_rate; 549 u8 supp_ofdm_rate; 550 __le32 supp_ht_mcs; 551 __le16 supp_vht_mcs[4]; 552 553 u8 op_mode; 554 u8 op_vht_chan_width; 555 u8 op_vht_rx_nss; 556 u8 op_vht_rx_nss_type; 557 558 __le32 sta_cap; 559 560 struct sta_phy phy; 561 } __packed; 562 563 struct sta_rec_ra_fixed { 564 __le16 tag; 565 __le16 len; 566 567 __le32 field; 568 u8 op_mode; 569 u8 op_vht_chan_width; 570 u8 op_vht_rx_nss; 571 u8 op_vht_rx_nss_type; 572 573 struct sta_phy phy; 574 575 u8 spe_en; 576 u8 short_preamble; 577 u8 is_5g; 578 u8 mmps_mode; 579 } __packed; 580 581 /* wtbl_rec */ 582 583 struct wtbl_req_hdr { 584 u8 wlan_idx_lo; 585 u8 operation; 586 __le16 tlv_num; 587 u8 wlan_idx_hi; 588 u8 rsv[3]; 589 } __packed; 590 591 struct wtbl_generic { 592 __le16 tag; 593 __le16 len; 594 u8 peer_addr[ETH_ALEN]; 595 u8 muar_idx; 596 u8 skip_tx; 597 u8 cf_ack; 598 u8 qos; 599 u8 mesh; 600 u8 adm; 601 __le16 partial_aid; 602 u8 baf_en; 603 u8 aad_om; 604 } __packed; 605 606 struct wtbl_rx { 607 __le16 tag; 608 __le16 len; 609 u8 rcid; 610 u8 rca1; 611 u8 rca2; 612 u8 rv; 613 u8 rsv[4]; 614 } __packed; 615 616 struct wtbl_ht { 617 __le16 tag; 618 __le16 len; 619 u8 ht; 620 u8 ldpc; 621 u8 af; 622 u8 mm; 623 u8 rsv[4]; 624 } __packed; 625 626 struct wtbl_vht { 627 __le16 tag; 628 __le16 len; 629 u8 ldpc; 630 u8 dyn_bw; 631 u8 vht; 632 u8 txop_ps; 633 u8 rsv[4]; 634 } __packed; 635 636 struct wtbl_tx_ps { 637 __le16 tag; 638 __le16 len; 639 u8 txps; 640 u8 rsv[3]; 641 } __packed; 642 643 struct wtbl_hdr_trans { 644 __le16 tag; 645 __le16 len; 646 u8 to_ds; 647 u8 from_ds; 648 u8 no_rx_trans; 649 u8 rsv; 650 } __packed; 651 652 struct wtbl_ba { 653 __le16 tag; 654 __le16 len; 655 /* common */ 656 u8 tid; 657 u8 ba_type; 658 u8 rsv0[2]; 659 /* originator only */ 660 __le16 sn; 661 u8 ba_en; 662 u8 ba_winsize_idx; 663 /* originator & recipient */ 664 __le16 ba_winsize; 665 /* recipient only */ 666 u8 peer_addr[ETH_ALEN]; 667 u8 rst_ba_tid; 668 u8 rst_ba_sel; 669 u8 rst_ba_sb; 670 u8 band_idx; 671 u8 rsv1[4]; 672 } __packed; 673 674 struct wtbl_smps { 675 __le16 tag; 676 __le16 len; 677 u8 smps; 678 u8 rsv[3]; 679 } __packed; 680 681 /* mt7615 only */ 682 683 struct wtbl_bf { 684 __le16 tag; 685 __le16 len; 686 u8 ibf; 687 u8 ebf; 688 u8 ibf_vht; 689 u8 ebf_vht; 690 u8 gid; 691 u8 pfmu_idx; 692 u8 rsv[2]; 693 } __packed; 694 695 struct wtbl_pn { 696 __le16 tag; 697 __le16 len; 698 u8 pn[6]; 699 u8 rsv[2]; 700 } __packed; 701 702 struct wtbl_spe { 703 __le16 tag; 704 __le16 len; 705 u8 spe_idx; 706 u8 rsv[3]; 707 } __packed; 708 709 struct wtbl_raw { 710 __le16 tag; 711 __le16 len; 712 u8 wtbl_idx; 713 u8 dw; 714 u8 rsv[2]; 715 __le32 msk; 716 __le32 val; 717 } __packed; 718 719 #define MT76_CONNAC_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \ 720 sizeof(struct wtbl_generic) + \ 721 sizeof(struct wtbl_rx) + \ 722 sizeof(struct wtbl_ht) + \ 723 sizeof(struct wtbl_vht) + \ 724 sizeof(struct wtbl_tx_ps) + \ 725 sizeof(struct wtbl_hdr_trans) +\ 726 sizeof(struct wtbl_ba) + \ 727 sizeof(struct wtbl_bf) + \ 728 sizeof(struct wtbl_smps) + \ 729 sizeof(struct wtbl_pn) + \ 730 sizeof(struct wtbl_spe)) 731 732 #define MT76_CONNAC_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 733 sizeof(struct sta_rec_basic) + \ 734 sizeof(struct sta_rec_bf) + \ 735 sizeof(struct sta_rec_ht) + \ 736 sizeof(struct sta_rec_he) + \ 737 sizeof(struct sta_rec_ba) + \ 738 sizeof(struct sta_rec_vht) + \ 739 sizeof(struct sta_rec_uapsd) + \ 740 sizeof(struct sta_rec_amsdu) + \ 741 sizeof(struct sta_rec_muru) + \ 742 sizeof(struct sta_rec_bfee) + \ 743 sizeof(struct sta_rec_ra) + \ 744 sizeof(struct sta_rec_sec) + \ 745 sizeof(struct sta_rec_ra_fixed) + \ 746 sizeof(struct sta_rec_he_6g_capa) + \ 747 sizeof(struct tlv) + \ 748 MT76_CONNAC_WTBL_UPDATE_MAX_SIZE) 749 750 enum { 751 STA_REC_BASIC, 752 STA_REC_RA, 753 STA_REC_RA_CMM_INFO, 754 STA_REC_RA_UPDATE, 755 STA_REC_BF, 756 STA_REC_AMSDU, 757 STA_REC_BA, 758 STA_REC_STATE, 759 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */ 760 STA_REC_HT, 761 STA_REC_VHT, 762 STA_REC_APPS, 763 STA_REC_KEY, 764 STA_REC_WTBL, 765 STA_REC_HE, 766 STA_REC_HW_AMSDU, 767 STA_REC_WTBL_AADOM, 768 STA_REC_KEY_V2, 769 STA_REC_MURU, 770 STA_REC_MUEDCA, 771 STA_REC_BFEE, 772 STA_REC_PHY = 0x15, 773 STA_REC_HE_6G = 0x17, 774 STA_REC_MAX_NUM 775 }; 776 777 enum { 778 WTBL_GENERIC, 779 WTBL_RX, 780 WTBL_HT, 781 WTBL_VHT, 782 WTBL_PEER_PS, /* not used */ 783 WTBL_TX_PS, 784 WTBL_HDR_TRANS, 785 WTBL_SEC_KEY, 786 WTBL_BA, 787 WTBL_RDG, /* obsoleted */ 788 WTBL_PROTECT, /* not used */ 789 WTBL_CLEAR, /* not used */ 790 WTBL_BF, 791 WTBL_SMPS, 792 WTBL_RAW_DATA, /* debug only */ 793 WTBL_PN, 794 WTBL_SPE, 795 WTBL_MAX_NUM 796 }; 797 798 #define STA_TYPE_STA BIT(0) 799 #define STA_TYPE_AP BIT(1) 800 #define STA_TYPE_ADHOC BIT(2) 801 #define STA_TYPE_WDS BIT(4) 802 #define STA_TYPE_BC BIT(5) 803 804 #define NETWORK_INFRA BIT(16) 805 #define NETWORK_P2P BIT(17) 806 #define NETWORK_IBSS BIT(18) 807 #define NETWORK_WDS BIT(21) 808 809 #define SCAN_FUNC_RANDOM_MAC BIT(0) 810 #define SCAN_FUNC_SPLIT_SCAN BIT(5) 811 812 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA) 813 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA) 814 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P) 815 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P) 816 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS) 817 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS) 818 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA) 819 820 #define CONN_STATE_DISCONNECT 0 821 #define CONN_STATE_CONNECT 1 822 #define CONN_STATE_PORT_SECURE 2 823 824 /* HE MAC */ 825 #define STA_REC_HE_CAP_HTC BIT(0) 826 #define STA_REC_HE_CAP_BQR BIT(1) 827 #define STA_REC_HE_CAP_BSR BIT(2) 828 #define STA_REC_HE_CAP_OM BIT(3) 829 #define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4) 830 /* HE PHY */ 831 #define STA_REC_HE_CAP_DUAL_BAND BIT(5) 832 #define STA_REC_HE_CAP_LDPC BIT(6) 833 #define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7) 834 #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8) 835 /* STBC */ 836 #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9) 837 #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10) 838 #define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11) 839 #define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12) 840 /* GI */ 841 #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13) 842 #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14) 843 #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15) 844 #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16) 845 #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17) 846 /* 242 TONE */ 847 #define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18) 848 #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19) 849 #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20) 850 851 #define PHY_MODE_A BIT(0) 852 #define PHY_MODE_B BIT(1) 853 #define PHY_MODE_G BIT(2) 854 #define PHY_MODE_GN BIT(3) 855 #define PHY_MODE_AN BIT(4) 856 #define PHY_MODE_AC BIT(5) 857 #define PHY_MODE_AX_24G BIT(6) 858 #define PHY_MODE_AX_5G BIT(7) 859 860 #define PHY_MODE_AX_6G BIT(0) /* phymode_ext */ 861 862 #define MODE_CCK BIT(0) 863 #define MODE_OFDM BIT(1) 864 #define MODE_HT BIT(2) 865 #define MODE_VHT BIT(3) 866 #define MODE_HE BIT(4) 867 868 #define STA_CAP_WMM BIT(0) 869 #define STA_CAP_SGI_20 BIT(4) 870 #define STA_CAP_SGI_40 BIT(5) 871 #define STA_CAP_TX_STBC BIT(6) 872 #define STA_CAP_RX_STBC BIT(7) 873 #define STA_CAP_VHT_SGI_80 BIT(16) 874 #define STA_CAP_VHT_SGI_160 BIT(17) 875 #define STA_CAP_VHT_TX_STBC BIT(18) 876 #define STA_CAP_VHT_RX_STBC BIT(19) 877 #define STA_CAP_VHT_LDPC BIT(23) 878 #define STA_CAP_LDPC BIT(24) 879 #define STA_CAP_HT BIT(26) 880 #define STA_CAP_VHT BIT(27) 881 #define STA_CAP_HE BIT(28) 882 883 enum { 884 PHY_TYPE_HR_DSSS_INDEX = 0, 885 PHY_TYPE_ERP_INDEX, 886 PHY_TYPE_ERP_P2P_INDEX, 887 PHY_TYPE_OFDM_INDEX, 888 PHY_TYPE_HT_INDEX, 889 PHY_TYPE_VHT_INDEX, 890 PHY_TYPE_HE_INDEX, 891 PHY_TYPE_INDEX_NUM 892 }; 893 894 #define PHY_TYPE_BIT_HR_DSSS BIT(PHY_TYPE_HR_DSSS_INDEX) 895 #define PHY_TYPE_BIT_ERP BIT(PHY_TYPE_ERP_INDEX) 896 #define PHY_TYPE_BIT_OFDM BIT(PHY_TYPE_OFDM_INDEX) 897 #define PHY_TYPE_BIT_HT BIT(PHY_TYPE_HT_INDEX) 898 #define PHY_TYPE_BIT_VHT BIT(PHY_TYPE_VHT_INDEX) 899 #define PHY_TYPE_BIT_HE BIT(PHY_TYPE_HE_INDEX) 900 901 #define MT_WTBL_RATE_TX_MODE GENMASK(9, 6) 902 #define MT_WTBL_RATE_MCS GENMASK(5, 0) 903 #define MT_WTBL_RATE_NSS GENMASK(12, 10) 904 #define MT_WTBL_RATE_HE_GI GENMASK(7, 4) 905 #define MT_WTBL_RATE_GI GENMASK(3, 0) 906 907 #define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5) 908 #define MT_WTBL_W5_SHORT_GI_20 BIT(8) 909 #define MT_WTBL_W5_SHORT_GI_40 BIT(9) 910 #define MT_WTBL_W5_SHORT_GI_80 BIT(10) 911 #define MT_WTBL_W5_SHORT_GI_160 BIT(11) 912 #define MT_WTBL_W5_BW_CAP GENMASK(13, 12) 913 #define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23) 914 #define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26) 915 #define MT_WTBL_W5_RATE_IDX GENMASK(31, 29) 916 917 enum { 918 WTBL_RESET_AND_SET = 1, 919 WTBL_SET, 920 WTBL_QUERY, 921 WTBL_RESET_ALL 922 }; 923 924 enum { 925 MT_BA_TYPE_INVALID, 926 MT_BA_TYPE_ORIGINATOR, 927 MT_BA_TYPE_RECIPIENT 928 }; 929 930 enum { 931 RST_BA_MAC_TID_MATCH, 932 RST_BA_MAC_MATCH, 933 RST_BA_NO_MATCH 934 }; 935 936 enum { 937 DEV_INFO_ACTIVE, 938 DEV_INFO_MAX_NUM 939 }; 940 941 /* event table */ 942 enum { 943 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01, 944 MCU_EVENT_FW_START = 0x01, 945 MCU_EVENT_GENERIC = 0x01, 946 MCU_EVENT_ACCESS_REG = 0x02, 947 MCU_EVENT_MT_PATCH_SEM = 0x04, 948 MCU_EVENT_REG_ACCESS = 0x05, 949 MCU_EVENT_LP_INFO = 0x07, 950 MCU_EVENT_SCAN_DONE = 0x0d, 951 MCU_EVENT_TX_DONE = 0x0f, 952 MCU_EVENT_ROC = 0x10, 953 MCU_EVENT_BSS_ABSENCE = 0x11, 954 MCU_EVENT_BSS_BEACON_LOSS = 0x13, 955 MCU_EVENT_CH_PRIVILEGE = 0x18, 956 MCU_EVENT_SCHED_SCAN_DONE = 0x23, 957 MCU_EVENT_DBG_MSG = 0x27, 958 MCU_EVENT_TXPWR = 0xd0, 959 MCU_EVENT_EXT = 0xed, 960 MCU_EVENT_RESTART_DL = 0xef, 961 MCU_EVENT_COREDUMP = 0xf0, 962 }; 963 964 /* ext event table */ 965 enum { 966 MCU_EXT_EVENT_PS_SYNC = 0x5, 967 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13, 968 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22, 969 MCU_EXT_EVENT_ASSERT_DUMP = 0x23, 970 MCU_EXT_EVENT_RDD_REPORT = 0x3a, 971 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f, 972 MCU_EXT_EVENT_BCC_NOTIFY = 0x75, 973 MCU_EXT_EVENT_MURU_CTRL = 0x9f, 974 }; 975 976 enum { 977 MCU_Q_QUERY, 978 MCU_Q_SET, 979 MCU_Q_RESERVED, 980 MCU_Q_NA 981 }; 982 983 enum { 984 MCU_S2D_H2N, 985 MCU_S2D_C2N, 986 MCU_S2D_H2C, 987 MCU_S2D_H2CN 988 }; 989 990 enum { 991 PATCH_NOT_DL_SEM_FAIL, 992 PATCH_IS_DL, 993 PATCH_NOT_DL_SEM_SUCCESS, 994 PATCH_REL_SEM_SUCCESS 995 }; 996 997 enum { 998 FW_STATE_INITIAL, 999 FW_STATE_FW_DOWNLOAD, 1000 FW_STATE_NORMAL_OPERATION, 1001 FW_STATE_NORMAL_TRX, 1002 FW_STATE_RDY = 7 1003 }; 1004 1005 enum { 1006 CH_SWITCH_NORMAL = 0, 1007 CH_SWITCH_SCAN = 3, 1008 CH_SWITCH_MCC = 4, 1009 CH_SWITCH_DFS = 5, 1010 CH_SWITCH_BACKGROUND_SCAN_START = 6, 1011 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7, 1012 CH_SWITCH_BACKGROUND_SCAN_STOP = 8, 1013 CH_SWITCH_SCAN_BYPASS_DPD = 9 1014 }; 1015 1016 enum { 1017 THERMAL_SENSOR_TEMP_QUERY, 1018 THERMAL_SENSOR_MANUAL_CTRL, 1019 THERMAL_SENSOR_INFO_QUERY, 1020 THERMAL_SENSOR_TASK_CTRL, 1021 }; 1022 1023 enum mcu_cipher_type { 1024 MCU_CIPHER_NONE = 0, 1025 MCU_CIPHER_WEP40, 1026 MCU_CIPHER_WEP104, 1027 MCU_CIPHER_WEP128, 1028 MCU_CIPHER_TKIP, 1029 MCU_CIPHER_AES_CCMP, 1030 MCU_CIPHER_CCMP_256, 1031 MCU_CIPHER_GCMP, 1032 MCU_CIPHER_GCMP_256, 1033 MCU_CIPHER_WAPI, 1034 MCU_CIPHER_BIP_CMAC_128, 1035 }; 1036 1037 enum { 1038 EE_MODE_EFUSE, 1039 EE_MODE_BUFFER, 1040 }; 1041 1042 enum { 1043 EE_FORMAT_BIN, 1044 EE_FORMAT_WHOLE, 1045 EE_FORMAT_MULTIPLE, 1046 }; 1047 1048 enum { 1049 MCU_PHY_STATE_TX_RATE, 1050 MCU_PHY_STATE_RX_RATE, 1051 MCU_PHY_STATE_RSSI, 1052 MCU_PHY_STATE_CONTENTION_RX_RATE, 1053 MCU_PHY_STATE_OFDMLQ_CNINFO, 1054 }; 1055 1056 #define MCU_CMD_ACK BIT(0) 1057 #define MCU_CMD_UNI BIT(1) 1058 #define MCU_CMD_QUERY BIT(2) 1059 1060 #define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | \ 1061 MCU_CMD_QUERY) 1062 1063 #define __MCU_CMD_FIELD_ID GENMASK(7, 0) 1064 #define __MCU_CMD_FIELD_EXT_ID GENMASK(15, 8) 1065 #define __MCU_CMD_FIELD_QUERY BIT(16) 1066 #define __MCU_CMD_FIELD_UNI BIT(17) 1067 #define __MCU_CMD_FIELD_CE BIT(18) 1068 #define __MCU_CMD_FIELD_WA BIT(19) 1069 1070 #define MCU_CMD(_t) FIELD_PREP(__MCU_CMD_FIELD_ID, \ 1071 MCU_CMD_##_t) 1072 #define MCU_EXT_CMD(_t) (MCU_CMD(EXT_CID) | \ 1073 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ 1074 MCU_EXT_CMD_##_t)) 1075 #define MCU_EXT_QUERY(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_QUERY) 1076 #define MCU_UNI_CMD(_t) (__MCU_CMD_FIELD_UNI | \ 1077 FIELD_PREP(__MCU_CMD_FIELD_ID, \ 1078 MCU_UNI_CMD_##_t)) 1079 #define MCU_CE_CMD(_t) (__MCU_CMD_FIELD_CE | \ 1080 FIELD_PREP(__MCU_CMD_FIELD_ID, \ 1081 MCU_CE_CMD_##_t)) 1082 #define MCU_CE_QUERY(_t) (MCU_CE_CMD(_t) | __MCU_CMD_FIELD_QUERY) 1083 1084 #define MCU_WA_CMD(_t) (MCU_CMD(_t) | __MCU_CMD_FIELD_WA) 1085 #define MCU_WA_EXT_CMD(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_WA) 1086 #define MCU_WA_PARAM_CMD(_t) (MCU_WA_CMD(WA_PARAM) | \ 1087 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ 1088 MCU_WA_PARAM_CMD_##_t)) 1089 1090 enum { 1091 MCU_EXT_CMD_EFUSE_ACCESS = 0x01, 1092 MCU_EXT_CMD_RF_REG_ACCESS = 0x02, 1093 MCU_EXT_CMD_RF_TEST = 0x04, 1094 MCU_EXT_CMD_PM_STATE_CTRL = 0x07, 1095 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08, 1096 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11, 1097 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13, 1098 MCU_EXT_CMD_TXBF_ACTION = 0x1e, 1099 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21, 1100 MCU_EXT_CMD_THERMAL_PROT = 0x23, 1101 MCU_EXT_CMD_STA_REC_UPDATE = 0x25, 1102 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26, 1103 MCU_EXT_CMD_EDCA_UPDATE = 0x27, 1104 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A, 1105 MCU_EXT_CMD_THERMAL_CTRL = 0x2c, 1106 MCU_EXT_CMD_WTBL_UPDATE = 0x32, 1107 MCU_EXT_CMD_SET_DRR_CTRL = 0x36, 1108 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a, 1109 MCU_EXT_CMD_ATE_CTRL = 0x3d, 1110 MCU_EXT_CMD_PROTECT_CTRL = 0x3e, 1111 MCU_EXT_CMD_DBDC_CTRL = 0x45, 1112 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46, 1113 MCU_EXT_CMD_RX_HDR_TRANS = 0x47, 1114 MCU_EXT_CMD_MUAR_UPDATE = 0x48, 1115 MCU_EXT_CMD_BCN_OFFLOAD = 0x49, 1116 MCU_EXT_CMD_RX_AIRTIME_CTRL = 0x4a, 1117 MCU_EXT_CMD_SET_RX_PATH = 0x4e, 1118 MCU_EXT_CMD_EFUSE_FREE_BLOCK = 0x4f, 1119 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58, 1120 MCU_EXT_CMD_RXDCOC_CAL = 0x59, 1121 MCU_EXT_CMD_GET_MIB_INFO = 0x5a, 1122 MCU_EXT_CMD_TXDPD_CAL = 0x60, 1123 MCU_EXT_CMD_CAL_CACHE = 0x67, 1124 MCU_EXT_CMD_SET_RADAR_TH = 0x7c, 1125 MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d, 1126 MCU_EXT_CMD_MWDS_SUPPORT = 0x80, 1127 MCU_EXT_CMD_SET_SER_TRIGGER = 0x81, 1128 MCU_EXT_CMD_TWT_AGRT_UPDATE = 0x94, 1129 MCU_EXT_CMD_FW_DBG_CTRL = 0x95, 1130 MCU_EXT_CMD_OFFCH_SCAN_CTRL = 0x9a, 1131 MCU_EXT_CMD_SET_RDD_TH = 0x9d, 1132 MCU_EXT_CMD_MURU_CTRL = 0x9f, 1133 MCU_EXT_CMD_SET_SPR = 0xa8, 1134 MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab, 1135 MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac, 1136 MCU_EXT_CMD_PHY_STAT_INFO = 0xad, 1137 }; 1138 1139 enum { 1140 MCU_UNI_CMD_DEV_INFO_UPDATE = 0x01, 1141 MCU_UNI_CMD_BSS_INFO_UPDATE = 0x02, 1142 MCU_UNI_CMD_STA_REC_UPDATE = 0x03, 1143 MCU_UNI_CMD_SUSPEND = 0x05, 1144 MCU_UNI_CMD_OFFLOAD = 0x06, 1145 MCU_UNI_CMD_HIF_CTRL = 0x07, 1146 MCU_UNI_CMD_SNIFFER = 0x24, 1147 }; 1148 1149 enum { 1150 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01, 1151 MCU_CMD_FW_START_REQ = 0x02, 1152 MCU_CMD_INIT_ACCESS_REG = 0x3, 1153 MCU_CMD_NIC_POWER_CTRL = 0x4, 1154 MCU_CMD_PATCH_START_REQ = 0x05, 1155 MCU_CMD_PATCH_FINISH_REQ = 0x07, 1156 MCU_CMD_PATCH_SEM_CONTROL = 0x10, 1157 MCU_CMD_WA_PARAM = 0xc4, 1158 MCU_CMD_EXT_CID = 0xed, 1159 MCU_CMD_FW_SCATTER = 0xee, 1160 MCU_CMD_RESTART_DL_REQ = 0xef, 1161 }; 1162 1163 /* offload mcu commands */ 1164 enum { 1165 MCU_CE_CMD_TEST_CTRL = 0x01, 1166 MCU_CE_CMD_START_HW_SCAN = 0x03, 1167 MCU_CE_CMD_SET_PS_PROFILE = 0x05, 1168 MCU_CE_CMD_SET_CHAN_DOMAIN = 0x0f, 1169 MCU_CE_CMD_SET_BSS_CONNECTED = 0x16, 1170 MCU_CE_CMD_SET_BSS_ABORT = 0x17, 1171 MCU_CE_CMD_CANCEL_HW_SCAN = 0x1b, 1172 MCU_CE_CMD_SET_ROC = 0x1c, 1173 MCU_CE_CMD_SET_EDCA_PARMS = 0x1d, 1174 MCU_CE_CMD_SET_P2P_OPPPS = 0x33, 1175 MCU_CE_CMD_SET_RATE_TX_POWER = 0x5d, 1176 MCU_CE_CMD_SCHED_SCAN_ENABLE = 0x61, 1177 MCU_CE_CMD_SCHED_SCAN_REQ = 0x62, 1178 MCU_CE_CMD_GET_NIC_CAPAB = 0x8a, 1179 MCU_CE_CMD_SET_MU_EDCA_PARMS = 0xb0, 1180 MCU_CE_CMD_REG_WRITE = 0xc0, 1181 MCU_CE_CMD_REG_READ = 0xc0, 1182 MCU_CE_CMD_CHIP_CONFIG = 0xca, 1183 MCU_CE_CMD_FWLOG_2_HOST = 0xc5, 1184 MCU_CE_CMD_GET_WTBL = 0xcd, 1185 MCU_CE_CMD_GET_TXPWR = 0xd0, 1186 }; 1187 1188 enum { 1189 PATCH_SEM_RELEASE, 1190 PATCH_SEM_GET 1191 }; 1192 1193 enum { 1194 UNI_BSS_INFO_BASIC = 0, 1195 UNI_BSS_INFO_RLM = 2, 1196 UNI_BSS_INFO_BSS_COLOR = 4, 1197 UNI_BSS_INFO_HE_BASIC = 5, 1198 UNI_BSS_INFO_BCN_CONTENT = 7, 1199 UNI_BSS_INFO_QBSS = 15, 1200 UNI_BSS_INFO_UAPSD = 19, 1201 UNI_BSS_INFO_PS = 21, 1202 UNI_BSS_INFO_BCNFT = 22, 1203 }; 1204 1205 enum { 1206 UNI_OFFLOAD_OFFLOAD_ARP, 1207 UNI_OFFLOAD_OFFLOAD_ND, 1208 UNI_OFFLOAD_OFFLOAD_GTK_REKEY, 1209 UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT, 1210 }; 1211 1212 enum { 1213 MT_NIC_CAP_TX_RESOURCE, 1214 MT_NIC_CAP_TX_EFUSE_ADDR, 1215 MT_NIC_CAP_COEX, 1216 MT_NIC_CAP_SINGLE_SKU, 1217 MT_NIC_CAP_CSUM_OFFLOAD, 1218 MT_NIC_CAP_HW_VER, 1219 MT_NIC_CAP_SW_VER, 1220 MT_NIC_CAP_MAC_ADDR, 1221 MT_NIC_CAP_PHY, 1222 MT_NIC_CAP_MAC, 1223 MT_NIC_CAP_FRAME_BUF, 1224 MT_NIC_CAP_BEAM_FORM, 1225 MT_NIC_CAP_LOCATION, 1226 MT_NIC_CAP_MUMIMO, 1227 MT_NIC_CAP_BUFFER_MODE_INFO, 1228 MT_NIC_CAP_HW_ADIE_VERSION = 0x14, 1229 MT_NIC_CAP_ANTSWP = 0x16, 1230 MT_NIC_CAP_WFDMA_REALLOC, 1231 MT_NIC_CAP_6G, 1232 }; 1233 1234 #define UNI_WOW_DETECT_TYPE_MAGIC BIT(0) 1235 #define UNI_WOW_DETECT_TYPE_ANY BIT(1) 1236 #define UNI_WOW_DETECT_TYPE_DISCONNECT BIT(2) 1237 #define UNI_WOW_DETECT_TYPE_GTK_REKEY_FAIL BIT(3) 1238 #define UNI_WOW_DETECT_TYPE_BCN_LOST BIT(4) 1239 #define UNI_WOW_DETECT_TYPE_SCH_SCAN_HIT BIT(5) 1240 #define UNI_WOW_DETECT_TYPE_BITMAP BIT(6) 1241 1242 enum { 1243 UNI_SUSPEND_MODE_SETTING, 1244 UNI_SUSPEND_WOW_CTRL, 1245 UNI_SUSPEND_WOW_GPIO_PARAM, 1246 UNI_SUSPEND_WOW_WAKEUP_PORT, 1247 UNI_SUSPEND_WOW_PATTERN, 1248 }; 1249 1250 enum { 1251 WOW_USB = 1, 1252 WOW_PCIE = 2, 1253 WOW_GPIO = 3, 1254 }; 1255 1256 struct mt76_connac_bss_basic_tlv { 1257 __le16 tag; 1258 __le16 len; 1259 u8 active; 1260 u8 omac_idx; 1261 u8 hw_bss_idx; 1262 u8 band_idx; 1263 __le32 conn_type; 1264 u8 conn_state; 1265 u8 wmm_idx; 1266 u8 bssid[ETH_ALEN]; 1267 __le16 bmc_tx_wlan_idx; 1268 __le16 bcn_interval; 1269 u8 dtim_period; 1270 u8 phymode; /* bit(0): A 1271 * bit(1): B 1272 * bit(2): G 1273 * bit(3): GN 1274 * bit(4): AN 1275 * bit(5): AC 1276 * bit(6): AX2 1277 * bit(7): AX5 1278 * bit(8): AX6 1279 */ 1280 __le16 sta_idx; 1281 __le16 nonht_basic_phy; 1282 u8 phymode_ext; /* bit(0) AX_6G */ 1283 u8 pad[1]; 1284 } __packed; 1285 1286 struct mt76_connac_bss_qos_tlv { 1287 __le16 tag; 1288 __le16 len; 1289 u8 qos; 1290 u8 pad[3]; 1291 } __packed; 1292 1293 struct mt76_connac_beacon_loss_event { 1294 u8 bss_idx; 1295 u8 reason; 1296 u8 pad[2]; 1297 } __packed; 1298 1299 struct mt76_connac_mcu_bss_event { 1300 u8 bss_idx; 1301 u8 is_absent; 1302 u8 free_quota; 1303 u8 pad; 1304 } __packed; 1305 1306 struct mt76_connac_mcu_scan_ssid { 1307 __le32 ssid_len; 1308 u8 ssid[IEEE80211_MAX_SSID_LEN]; 1309 } __packed; 1310 1311 struct mt76_connac_mcu_scan_channel { 1312 u8 band; /* 1: 2.4GHz 1313 * 2: 5.0GHz 1314 * Others: Reserved 1315 */ 1316 u8 channel_num; 1317 } __packed; 1318 1319 struct mt76_connac_mcu_scan_match { 1320 __le32 rssi_th; 1321 u8 ssid[IEEE80211_MAX_SSID_LEN]; 1322 u8 ssid_len; 1323 u8 rsv[3]; 1324 } __packed; 1325 1326 struct mt76_connac_hw_scan_req { 1327 u8 seq_num; 1328 u8 bss_idx; 1329 u8 scan_type; /* 0: PASSIVE SCAN 1330 * 1: ACTIVE SCAN 1331 */ 1332 u8 ssid_type; /* BIT(0) wildcard SSID 1333 * BIT(1) P2P wildcard SSID 1334 * BIT(2) specified SSID + wildcard SSID 1335 * BIT(2) + ssid_type_ext BIT(0) specified SSID only 1336 */ 1337 u8 ssids_num; 1338 u8 probe_req_num; /* Number of probe request for each SSID */ 1339 u8 scan_func; /* BIT(0) Enable random MAC scan 1340 * BIT(1) Disable DBDC scan type 1~3. 1341 * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan). 1342 */ 1343 u8 version; /* 0: Not support fields after ies. 1344 * 1: Support fields after ies. 1345 */ 1346 struct mt76_connac_mcu_scan_ssid ssids[4]; 1347 __le16 probe_delay_time; 1348 __le16 channel_dwell_time; /* channel Dwell interval */ 1349 __le16 timeout_value; 1350 u8 channel_type; /* 0: Full channels 1351 * 1: Only 2.4GHz channels 1352 * 2: Only 5GHz channels 1353 * 3: P2P social channel only (channel #1, #6 and #11) 1354 * 4: Specified channels 1355 * Others: Reserved 1356 */ 1357 u8 channels_num; /* valid when channel_type is 4 */ 1358 /* valid when channels_num is set */ 1359 struct mt76_connac_mcu_scan_channel channels[32]; 1360 __le16 ies_len; 1361 u8 ies[MT76_CONNAC_SCAN_IE_LEN]; 1362 /* following fields are valid if version > 0 */ 1363 u8 ext_channels_num; 1364 u8 ext_ssids_num; 1365 __le16 channel_min_dwell_time; 1366 struct mt76_connac_mcu_scan_channel ext_channels[32]; 1367 struct mt76_connac_mcu_scan_ssid ext_ssids[6]; 1368 u8 bssid[ETH_ALEN]; 1369 u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */ 1370 u8 pad[63]; 1371 u8 ssid_type_ext; 1372 } __packed; 1373 1374 #define MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM 64 1375 1376 struct mt76_connac_hw_scan_done { 1377 u8 seq_num; 1378 u8 sparse_channel_num; 1379 struct mt76_connac_mcu_scan_channel sparse_channel; 1380 u8 complete_channel_num; 1381 u8 current_state; 1382 u8 version; 1383 u8 pad; 1384 __le32 beacon_scan_num; 1385 u8 pno_enabled; 1386 u8 pad2[3]; 1387 u8 sparse_channel_valid_num; 1388 u8 pad3[3]; 1389 u8 channel_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1390 /* idle format for channel_idle_time 1391 * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms) 1392 * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms) 1393 * 2: dwell time (16us) 1394 */ 1395 __le16 channel_idle_time[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1396 /* beacon and probe response count */ 1397 u8 beacon_probe_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1398 u8 mdrdy_count[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1399 __le32 beacon_2g_num; 1400 __le32 beacon_5g_num; 1401 } __packed; 1402 1403 struct mt76_connac_sched_scan_req { 1404 u8 version; 1405 u8 seq_num; 1406 u8 stop_on_match; 1407 u8 ssids_num; 1408 u8 match_num; 1409 u8 pad; 1410 __le16 ie_len; 1411 struct mt76_connac_mcu_scan_ssid ssids[MT76_CONNAC_MAX_SCHED_SCAN_SSID]; 1412 struct mt76_connac_mcu_scan_match match[MT76_CONNAC_MAX_SCAN_MATCH]; 1413 u8 channel_type; 1414 u8 channels_num; 1415 u8 intervals_num; 1416 u8 scan_func; /* MT7663: BIT(0) eable random mac address */ 1417 struct mt76_connac_mcu_scan_channel channels[64]; 1418 __le16 intervals[MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL]; 1419 union { 1420 struct { 1421 u8 random_mac[ETH_ALEN]; 1422 u8 pad2[58]; 1423 } mt7663; 1424 struct { 1425 u8 bss_idx; 1426 u8 pad1[3]; 1427 __le32 delay; 1428 u8 pad2[12]; 1429 u8 random_mac[ETH_ALEN]; 1430 u8 pad3[38]; 1431 } mt7921; 1432 }; 1433 } __packed; 1434 1435 struct mt76_connac_sched_scan_done { 1436 u8 seq_num; 1437 u8 status; /* 0: ssid found */ 1438 __le16 pad; 1439 } __packed; 1440 1441 struct bss_info_uni_bss_color { 1442 __le16 tag; 1443 __le16 len; 1444 u8 enable; 1445 u8 bss_color; 1446 u8 rsv[2]; 1447 } __packed; 1448 1449 struct bss_info_uni_he { 1450 __le16 tag; 1451 __le16 len; 1452 __le16 he_rts_thres; 1453 u8 he_pe_duration; 1454 u8 su_disable; 1455 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 1456 u8 rsv[2]; 1457 } __packed; 1458 1459 struct mt76_connac_gtk_rekey_tlv { 1460 __le16 tag; 1461 __le16 len; 1462 u8 kek[NL80211_KEK_LEN]; 1463 u8 kck[NL80211_KCK_LEN]; 1464 u8 replay_ctr[NL80211_REPLAY_CTR_LEN]; 1465 u8 rekey_mode; /* 0: rekey offload enable 1466 * 1: rekey offload disable 1467 * 2: rekey update 1468 */ 1469 u8 keyid; 1470 u8 option; /* 1: rekey data update without enabling offload */ 1471 u8 pad[1]; 1472 __le32 proto; /* WPA-RSN-WAPI-OPSN */ 1473 __le32 pairwise_cipher; 1474 __le32 group_cipher; 1475 __le32 key_mgmt; /* NONE-PSK-IEEE802.1X */ 1476 __le32 mgmt_group_cipher; 1477 u8 reserverd[4]; 1478 } __packed; 1479 1480 #define MT76_CONNAC_WOW_MASK_MAX_LEN 16 1481 #define MT76_CONNAC_WOW_PATTEN_MAX_LEN 128 1482 1483 struct mt76_connac_wow_pattern_tlv { 1484 __le16 tag; 1485 __le16 len; 1486 u8 index; /* pattern index */ 1487 u8 enable; /* 0: disable 1488 * 1: enable 1489 */ 1490 u8 data_len; /* pattern length */ 1491 u8 pad; 1492 u8 mask[MT76_CONNAC_WOW_MASK_MAX_LEN]; 1493 u8 pattern[MT76_CONNAC_WOW_PATTEN_MAX_LEN]; 1494 u8 rsv[4]; 1495 } __packed; 1496 1497 struct mt76_connac_wow_ctrl_tlv { 1498 __le16 tag; 1499 __le16 len; 1500 u8 cmd; /* 0x1: PM_WOWLAN_REQ_START 1501 * 0x2: PM_WOWLAN_REQ_STOP 1502 * 0x3: PM_WOWLAN_PARAM_CLEAR 1503 */ 1504 u8 trigger; /* 0: NONE 1505 * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT 1506 * BIT(1): NL80211_WOWLAN_TRIG_ANY 1507 * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT 1508 * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE 1509 * BIT(4): BEACON_LOST 1510 * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT 1511 */ 1512 u8 wakeup_hif; /* 0x0: HIF_SDIO 1513 * 0x1: HIF_USB 1514 * 0x2: HIF_PCIE 1515 * 0x3: HIF_GPIO 1516 */ 1517 u8 pad; 1518 u8 rsv[4]; 1519 } __packed; 1520 1521 struct mt76_connac_wow_gpio_param_tlv { 1522 __le16 tag; 1523 __le16 len; 1524 u8 gpio_pin; 1525 u8 trigger_lvl; 1526 u8 pad[2]; 1527 __le32 gpio_interval; 1528 u8 rsv[4]; 1529 } __packed; 1530 1531 struct mt76_connac_arpns_tlv { 1532 __le16 tag; 1533 __le16 len; 1534 u8 mode; 1535 u8 ips_num; 1536 u8 option; 1537 u8 pad[1]; 1538 } __packed; 1539 1540 struct mt76_connac_suspend_tlv { 1541 __le16 tag; 1542 __le16 len; 1543 u8 enable; /* 0: suspend mode disabled 1544 * 1: suspend mode enabled 1545 */ 1546 u8 mdtim; /* LP parameter */ 1547 u8 wow_suspend; /* 0: update by origin policy 1548 * 1: update by wow dtim 1549 */ 1550 u8 pad[5]; 1551 } __packed; 1552 1553 enum mt76_sta_info_state { 1554 MT76_STA_INFO_STATE_NONE, 1555 MT76_STA_INFO_STATE_AUTH, 1556 MT76_STA_INFO_STATE_ASSOC 1557 }; 1558 1559 struct mt76_sta_cmd_info { 1560 struct ieee80211_sta *sta; 1561 struct mt76_wcid *wcid; 1562 1563 struct ieee80211_vif *vif; 1564 1565 bool offload_fw; 1566 bool enable; 1567 bool newly; 1568 int cmd; 1569 u8 rcpi; 1570 u8 state; 1571 }; 1572 1573 #define MT_SKU_POWER_LIMIT 161 1574 1575 struct mt76_connac_sku_tlv { 1576 u8 channel; 1577 s8 pwr_limit[MT_SKU_POWER_LIMIT]; 1578 } __packed; 1579 1580 struct mt76_connac_tx_power_limit_tlv { 1581 /* DW0 - common info*/ 1582 u8 ver; 1583 u8 pad0; 1584 __le16 len; 1585 /* DW1 - cmd hint */ 1586 u8 n_chan; /* # channel */ 1587 u8 band; /* 2.4GHz - 5GHz - 6GHz */ 1588 u8 last_msg; 1589 u8 pad1; 1590 /* DW3 */ 1591 u8 alpha2[4]; /* regulatory_request.alpha2 */ 1592 u8 pad2[32]; 1593 } __packed; 1594 1595 struct mt76_connac_config { 1596 __le16 id; 1597 u8 type; 1598 u8 resp_type; 1599 __le16 data_size; 1600 __le16 resv; 1601 u8 data[320]; 1602 } __packed; 1603 1604 static inline enum mcu_cipher_type 1605 mt76_connac_mcu_get_cipher(int cipher) 1606 { 1607 switch (cipher) { 1608 case WLAN_CIPHER_SUITE_WEP40: 1609 return MCU_CIPHER_WEP40; 1610 case WLAN_CIPHER_SUITE_WEP104: 1611 return MCU_CIPHER_WEP104; 1612 case WLAN_CIPHER_SUITE_TKIP: 1613 return MCU_CIPHER_TKIP; 1614 case WLAN_CIPHER_SUITE_AES_CMAC: 1615 return MCU_CIPHER_BIP_CMAC_128; 1616 case WLAN_CIPHER_SUITE_CCMP: 1617 return MCU_CIPHER_AES_CCMP; 1618 case WLAN_CIPHER_SUITE_CCMP_256: 1619 return MCU_CIPHER_CCMP_256; 1620 case WLAN_CIPHER_SUITE_GCMP: 1621 return MCU_CIPHER_GCMP; 1622 case WLAN_CIPHER_SUITE_GCMP_256: 1623 return MCU_CIPHER_GCMP_256; 1624 case WLAN_CIPHER_SUITE_SMS4: 1625 return MCU_CIPHER_WAPI; 1626 default: 1627 return MCU_CIPHER_NONE; 1628 } 1629 } 1630 1631 static inline u32 1632 mt76_connac_mcu_gen_dl_mode(struct mt76_dev *dev, u8 feature_set, bool is_wa) 1633 { 1634 u32 ret = 0; 1635 1636 ret |= feature_set & FW_FEATURE_SET_ENCRYPT ? 1637 DL_MODE_ENCRYPT | DL_MODE_RESET_SEC_IV : 0; 1638 if (is_mt7921(dev)) 1639 ret |= feature_set & FW_FEATURE_ENCRY_MODE ? 1640 DL_CONFIG_ENCRY_MODE_SEL : 0; 1641 ret |= FIELD_PREP(DL_MODE_KEY_IDX, 1642 FIELD_GET(FW_FEATURE_SET_KEY_IDX, feature_set)); 1643 ret |= DL_MODE_NEED_RSP; 1644 ret |= is_wa ? DL_MODE_WORKING_PDA_CR4 : 0; 1645 1646 return ret; 1647 } 1648 1649 #define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id) 1650 #define to_wcid_hi(id) FIELD_GET(GENMASK(9, 8), (u16)id) 1651 1652 static inline void 1653 mt76_connac_mcu_get_wlan_idx(struct mt76_dev *dev, struct mt76_wcid *wcid, 1654 u8 *wlan_idx_lo, u8 *wlan_idx_hi) 1655 { 1656 *wlan_idx_hi = 0; 1657 1658 if (!is_connac_v1(dev)) { 1659 *wlan_idx_lo = wcid ? to_wcid_lo(wcid->idx) : 0; 1660 *wlan_idx_hi = wcid ? to_wcid_hi(wcid->idx) : 0; 1661 } else { 1662 *wlan_idx_lo = wcid ? wcid->idx : 0; 1663 } 1664 } 1665 1666 struct sk_buff * 1667 __mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif, 1668 struct mt76_wcid *wcid, int len); 1669 static inline struct sk_buff * 1670 mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif, 1671 struct mt76_wcid *wcid) 1672 { 1673 return __mt76_connac_mcu_alloc_sta_req(dev, mvif, wcid, 1674 MT76_CONNAC_STA_UPDATE_MAX_SIZE); 1675 } 1676 1677 struct wtbl_req_hdr * 1678 mt76_connac_mcu_alloc_wtbl_req(struct mt76_dev *dev, struct mt76_wcid *wcid, 1679 int cmd, void *sta_wtbl, struct sk_buff **skb); 1680 struct tlv *mt76_connac_mcu_add_nested_tlv(struct sk_buff *skb, int tag, 1681 int len, void *sta_ntlv, 1682 void *sta_wtbl); 1683 static inline struct tlv * 1684 mt76_connac_mcu_add_tlv(struct sk_buff *skb, int tag, int len) 1685 { 1686 return mt76_connac_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL); 1687 } 1688 1689 int mt76_connac_mcu_set_channel_domain(struct mt76_phy *phy); 1690 int mt76_connac_mcu_set_vif_ps(struct mt76_dev *dev, struct ieee80211_vif *vif); 1691 void mt76_connac_mcu_sta_basic_tlv(struct sk_buff *skb, 1692 struct ieee80211_vif *vif, 1693 struct ieee80211_sta *sta, bool enable, 1694 bool newly); 1695 void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1696 struct ieee80211_vif *vif, 1697 struct ieee80211_sta *sta, void *sta_wtbl, 1698 void *wtbl_tlv); 1699 void mt76_connac_mcu_wtbl_hdr_trans_tlv(struct sk_buff *skb, 1700 struct ieee80211_vif *vif, 1701 struct mt76_wcid *wcid, 1702 void *sta_wtbl, void *wtbl_tlv); 1703 int mt76_connac_mcu_sta_update_hdr_trans(struct mt76_dev *dev, 1704 struct ieee80211_vif *vif, 1705 struct mt76_wcid *wcid, int cmd); 1706 int mt76_connac_mcu_wtbl_update_hdr_trans(struct mt76_dev *dev, 1707 struct ieee80211_vif *vif, 1708 struct ieee80211_sta *sta); 1709 void mt76_connac_mcu_sta_tlv(struct mt76_phy *mphy, struct sk_buff *skb, 1710 struct ieee80211_sta *sta, 1711 struct ieee80211_vif *vif, 1712 u8 rcpi, u8 state); 1713 void mt76_connac_mcu_wtbl_ht_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1714 struct ieee80211_sta *sta, void *sta_wtbl, 1715 void *wtbl_tlv, bool ht_ldpc, bool vht_ldpc); 1716 void mt76_connac_mcu_wtbl_ba_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1717 struct ieee80211_ampdu_params *params, 1718 bool enable, bool tx, void *sta_wtbl, 1719 void *wtbl_tlv); 1720 void mt76_connac_mcu_sta_ba_tlv(struct sk_buff *skb, 1721 struct ieee80211_ampdu_params *params, 1722 bool enable, bool tx); 1723 int mt76_connac_mcu_uni_add_dev(struct mt76_phy *phy, 1724 struct ieee80211_vif *vif, 1725 struct mt76_wcid *wcid, 1726 bool enable); 1727 int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif, 1728 struct ieee80211_ampdu_params *params, 1729 int cmd, bool enable, bool tx); 1730 int mt76_connac_mcu_uni_add_bss(struct mt76_phy *phy, 1731 struct ieee80211_vif *vif, 1732 struct mt76_wcid *wcid, 1733 bool enable); 1734 int mt76_connac_mcu_sta_cmd(struct mt76_phy *phy, 1735 struct mt76_sta_cmd_info *info); 1736 void mt76_connac_mcu_beacon_loss_iter(void *priv, u8 *mac, 1737 struct ieee80211_vif *vif); 1738 int mt76_connac_mcu_set_rts_thresh(struct mt76_dev *dev, u32 val, u8 band); 1739 int mt76_connac_mcu_set_mac_enable(struct mt76_dev *dev, int band, bool enable, 1740 bool hdr_trans); 1741 int mt76_connac_mcu_init_download(struct mt76_dev *dev, u32 addr, u32 len, 1742 u32 mode); 1743 int mt76_connac_mcu_start_patch(struct mt76_dev *dev); 1744 int mt76_connac_mcu_patch_sem_ctrl(struct mt76_dev *dev, bool get); 1745 int mt76_connac_mcu_start_firmware(struct mt76_dev *dev, u32 addr, u32 option); 1746 int mt76_connac_mcu_get_nic_capability(struct mt76_phy *phy); 1747 1748 int mt76_connac_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif, 1749 struct ieee80211_scan_request *scan_req); 1750 int mt76_connac_mcu_cancel_hw_scan(struct mt76_phy *phy, 1751 struct ieee80211_vif *vif); 1752 int mt76_connac_mcu_sched_scan_req(struct mt76_phy *phy, 1753 struct ieee80211_vif *vif, 1754 struct cfg80211_sched_scan_request *sreq); 1755 int mt76_connac_mcu_sched_scan_enable(struct mt76_phy *phy, 1756 struct ieee80211_vif *vif, 1757 bool enable); 1758 int mt76_connac_mcu_update_arp_filter(struct mt76_dev *dev, 1759 struct mt76_vif *vif, 1760 struct ieee80211_bss_conf *info); 1761 int mt76_connac_mcu_update_gtk_rekey(struct ieee80211_hw *hw, 1762 struct ieee80211_vif *vif, 1763 struct cfg80211_gtk_rekey_data *key); 1764 int mt76_connac_mcu_set_hif_suspend(struct mt76_dev *dev, bool suspend); 1765 void mt76_connac_mcu_set_suspend_iter(void *priv, u8 *mac, 1766 struct ieee80211_vif *vif); 1767 int mt76_connac_sta_state_dp(struct mt76_dev *dev, 1768 enum ieee80211_sta_state old_state, 1769 enum ieee80211_sta_state new_state); 1770 int mt76_connac_mcu_chip_config(struct mt76_dev *dev); 1771 int mt76_connac_mcu_set_deep_sleep(struct mt76_dev *dev, bool enable); 1772 void mt76_connac_mcu_coredump_event(struct mt76_dev *dev, struct sk_buff *skb, 1773 struct mt76_connac_coredump *coredump); 1774 int mt76_connac_mcu_set_rate_txpower(struct mt76_phy *phy); 1775 int mt76_connac_mcu_set_p2p_oppps(struct ieee80211_hw *hw, 1776 struct ieee80211_vif *vif); 1777 u32 mt76_connac_mcu_reg_rr(struct mt76_dev *dev, u32 offset); 1778 void mt76_connac_mcu_reg_wr(struct mt76_dev *dev, u32 offset, u32 val); 1779 1780 const struct ieee80211_sta_he_cap * 1781 mt76_connac_get_he_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif); 1782 u8 mt76_connac_get_phy_mode(struct mt76_phy *phy, struct ieee80211_vif *vif, 1783 enum nl80211_band band, struct ieee80211_sta *sta); 1784 1785 int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif, 1786 struct mt76_connac_sta_key_conf *sta_key_conf, 1787 struct ieee80211_key_conf *key, int mcu_cmd, 1788 struct mt76_wcid *wcid, enum set_key_cmd cmd); 1789 1790 void mt76_connac_mcu_bss_ext_tlv(struct sk_buff *skb, struct mt76_vif *mvif); 1791 void mt76_connac_mcu_bss_omac_tlv(struct sk_buff *skb, 1792 struct ieee80211_vif *vif); 1793 int mt76_connac_mcu_bss_basic_tlv(struct sk_buff *skb, 1794 struct ieee80211_vif *vif, 1795 struct ieee80211_sta *sta, 1796 struct mt76_phy *phy, u16 wlan_idx, 1797 bool enable); 1798 void mt76_connac_mcu_sta_uapsd(struct sk_buff *skb, struct ieee80211_vif *vif, 1799 struct ieee80211_sta *sta); 1800 void mt76_connac_mcu_wtbl_smps_tlv(struct sk_buff *skb, 1801 struct ieee80211_sta *sta, 1802 void *sta_wtbl, void *wtbl_tlv); 1803 int mt76_connac_mcu_set_pm(struct mt76_dev *dev, int band, int enter); 1804 int mt76_connac_mcu_restart(struct mt76_dev *dev); 1805 int mt76_connac_mcu_rdd_cmd(struct mt76_dev *dev, int cmd, u8 index, 1806 u8 rx_sel, u8 val); 1807 int mt76_connac2_load_ram(struct mt76_dev *dev, const char *fw_wm, 1808 const char *fw_wa); 1809 int mt76_connac2_load_patch(struct mt76_dev *dev, const char *fw_name); 1810 int mt76_connac2_mcu_fill_message(struct mt76_dev *mdev, struct sk_buff *skb, 1811 int cmd, int *wait_seq); 1812 #endif /* __MT76_CONNAC_MCU_H */ 1813