1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT76_CONNAC_MCU_H 5 #define __MT76_CONNAC_MCU_H 6 7 #include "mt76_connac.h" 8 9 struct tlv { 10 __le16 tag; 11 __le16 len; 12 } __packed; 13 14 /* sta_rec */ 15 16 struct sta_ntlv_hdr { 17 u8 rsv[2]; 18 __le16 tlv_num; 19 } __packed; 20 21 struct sta_req_hdr { 22 u8 bss_idx; 23 u8 wlan_idx_lo; 24 __le16 tlv_num; 25 u8 is_tlv_append; 26 u8 muar_idx; 27 u8 wlan_idx_hi; 28 u8 rsv; 29 } __packed; 30 31 struct sta_rec_basic { 32 __le16 tag; 33 __le16 len; 34 __le32 conn_type; 35 u8 conn_state; 36 u8 qos; 37 __le16 aid; 38 u8 peer_addr[ETH_ALEN]; 39 #define EXTRA_INFO_VER BIT(0) 40 #define EXTRA_INFO_NEW BIT(1) 41 __le16 extra_info; 42 } __packed; 43 44 struct sta_rec_ht { 45 __le16 tag; 46 __le16 len; 47 __le16 ht_cap; 48 u16 rsv; 49 } __packed; 50 51 struct sta_rec_vht { 52 __le16 tag; 53 __le16 len; 54 __le32 vht_cap; 55 __le16 vht_rx_mcs_map; 56 __le16 vht_tx_mcs_map; 57 /* mt7921 */ 58 u8 rts_bw_sig; 59 u8 rsv[3]; 60 } __packed; 61 62 struct sta_rec_uapsd { 63 __le16 tag; 64 __le16 len; 65 u8 dac_map; 66 u8 tac_map; 67 u8 max_sp; 68 u8 rsv0; 69 __le16 listen_interval; 70 u8 rsv1[2]; 71 } __packed; 72 73 struct sta_rec_ba { 74 __le16 tag; 75 __le16 len; 76 u8 tid; 77 u8 ba_type; 78 u8 amsdu; 79 u8 ba_en; 80 __le16 ssn; 81 __le16 winsize; 82 } __packed; 83 84 struct sta_rec_he { 85 __le16 tag; 86 __le16 len; 87 88 __le32 he_cap; 89 90 u8 t_frame_dur; 91 u8 max_ampdu_exp; 92 u8 bw_set; 93 u8 device_class; 94 u8 dcm_tx_mode; 95 u8 dcm_tx_max_nss; 96 u8 dcm_rx_mode; 97 u8 dcm_rx_max_nss; 98 u8 dcm_max_ru; 99 u8 punc_pream_rx; 100 u8 pkt_ext; 101 u8 rsv1; 102 103 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 104 105 u8 rsv2[2]; 106 } __packed; 107 108 struct sta_rec_amsdu { 109 __le16 tag; 110 __le16 len; 111 u8 max_amsdu_num; 112 u8 max_mpdu_size; 113 u8 amsdu_en; 114 u8 rsv; 115 } __packed; 116 117 struct sta_rec_state { 118 __le16 tag; 119 __le16 len; 120 __le32 flags; 121 u8 state; 122 u8 vht_opmode; 123 u8 action; 124 u8 rsv[1]; 125 } __packed; 126 127 #define HT_MCS_MASK_NUM 10 128 struct sta_rec_ra_info { 129 __le16 tag; 130 __le16 len; 131 __le16 legacy; 132 u8 rx_mcs_bitmask[HT_MCS_MASK_NUM]; 133 } __packed; 134 135 struct sta_rec_phy { 136 __le16 tag; 137 __le16 len; 138 __le16 basic_rate; 139 u8 phy_type; 140 u8 ampdu; 141 u8 rts_policy; 142 u8 rcpi; 143 u8 rsv[2]; 144 } __packed; 145 146 /* wtbl_rec */ 147 148 struct wtbl_req_hdr { 149 u8 wlan_idx_lo; 150 u8 operation; 151 __le16 tlv_num; 152 u8 wlan_idx_hi; 153 u8 rsv[3]; 154 } __packed; 155 156 struct wtbl_generic { 157 __le16 tag; 158 __le16 len; 159 u8 peer_addr[ETH_ALEN]; 160 u8 muar_idx; 161 u8 skip_tx; 162 u8 cf_ack; 163 u8 qos; 164 u8 mesh; 165 u8 adm; 166 __le16 partial_aid; 167 u8 baf_en; 168 u8 aad_om; 169 } __packed; 170 171 struct wtbl_rx { 172 __le16 tag; 173 __le16 len; 174 u8 rcid; 175 u8 rca1; 176 u8 rca2; 177 u8 rv; 178 u8 rsv[4]; 179 } __packed; 180 181 struct wtbl_ht { 182 __le16 tag; 183 __le16 len; 184 u8 ht; 185 u8 ldpc; 186 u8 af; 187 u8 mm; 188 u8 rsv[4]; 189 } __packed; 190 191 struct wtbl_vht { 192 __le16 tag; 193 __le16 len; 194 u8 ldpc; 195 u8 dyn_bw; 196 u8 vht; 197 u8 txop_ps; 198 u8 rsv[4]; 199 } __packed; 200 201 struct wtbl_tx_ps { 202 __le16 tag; 203 __le16 len; 204 u8 txps; 205 u8 rsv[3]; 206 } __packed; 207 208 struct wtbl_hdr_trans { 209 __le16 tag; 210 __le16 len; 211 u8 to_ds; 212 u8 from_ds; 213 u8 no_rx_trans; 214 u8 rsv; 215 } __packed; 216 217 struct wtbl_ba { 218 __le16 tag; 219 __le16 len; 220 /* common */ 221 u8 tid; 222 u8 ba_type; 223 u8 rsv0[2]; 224 /* originator only */ 225 __le16 sn; 226 u8 ba_en; 227 u8 ba_winsize_idx; 228 __le16 ba_winsize; 229 /* recipient only */ 230 u8 peer_addr[ETH_ALEN]; 231 u8 rst_ba_tid; 232 u8 rst_ba_sel; 233 u8 rst_ba_sb; 234 u8 band_idx; 235 u8 rsv1[4]; 236 } __packed; 237 238 struct wtbl_smps { 239 __le16 tag; 240 __le16 len; 241 u8 smps; 242 u8 rsv[3]; 243 } __packed; 244 245 /* mt7615 only */ 246 247 struct wtbl_bf { 248 __le16 tag; 249 __le16 len; 250 u8 ibf; 251 u8 ebf; 252 u8 ibf_vht; 253 u8 ebf_vht; 254 u8 gid; 255 u8 pfmu_idx; 256 u8 rsv[2]; 257 } __packed; 258 259 struct wtbl_pn { 260 __le16 tag; 261 __le16 len; 262 u8 pn[6]; 263 u8 rsv[2]; 264 } __packed; 265 266 struct wtbl_spe { 267 __le16 tag; 268 __le16 len; 269 u8 spe_idx; 270 u8 rsv[3]; 271 } __packed; 272 273 struct wtbl_raw { 274 __le16 tag; 275 __le16 len; 276 u8 wtbl_idx; 277 u8 dw; 278 u8 rsv[2]; 279 __le32 msk; 280 __le32 val; 281 } __packed; 282 283 #define MT76_CONNAC_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \ 284 sizeof(struct wtbl_generic) + \ 285 sizeof(struct wtbl_rx) + \ 286 sizeof(struct wtbl_ht) + \ 287 sizeof(struct wtbl_vht) + \ 288 sizeof(struct wtbl_tx_ps) + \ 289 sizeof(struct wtbl_hdr_trans) +\ 290 sizeof(struct wtbl_ba) + \ 291 sizeof(struct wtbl_bf) + \ 292 sizeof(struct wtbl_smps) + \ 293 sizeof(struct wtbl_pn) + \ 294 sizeof(struct wtbl_spe)) 295 296 #define MT76_CONNAC_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 297 sizeof(struct sta_rec_basic) + \ 298 sizeof(struct sta_rec_ht) + \ 299 sizeof(struct sta_rec_he) + \ 300 sizeof(struct sta_rec_ba) + \ 301 sizeof(struct sta_rec_vht) + \ 302 sizeof(struct sta_rec_uapsd) + \ 303 sizeof(struct sta_rec_amsdu) + \ 304 sizeof(struct tlv) + \ 305 MT76_CONNAC_WTBL_UPDATE_MAX_SIZE) 306 307 enum { 308 STA_REC_BASIC, 309 STA_REC_RA, 310 STA_REC_RA_CMM_INFO, 311 STA_REC_RA_UPDATE, 312 STA_REC_BF, 313 STA_REC_AMSDU, 314 STA_REC_BA, 315 STA_REC_STATE, 316 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */ 317 STA_REC_HT, 318 STA_REC_VHT, 319 STA_REC_APPS, 320 STA_REC_KEY, 321 STA_REC_WTBL, 322 STA_REC_HE, 323 STA_REC_HW_AMSDU, 324 STA_REC_WTBL_AADOM, 325 STA_REC_KEY_V2, 326 STA_REC_MURU, 327 STA_REC_MUEDCA, 328 STA_REC_BFEE, 329 STA_REC_PHY = 0x15, 330 STA_REC_MAX_NUM 331 }; 332 333 enum { 334 WTBL_GENERIC, 335 WTBL_RX, 336 WTBL_HT, 337 WTBL_VHT, 338 WTBL_PEER_PS, /* not used */ 339 WTBL_TX_PS, 340 WTBL_HDR_TRANS, 341 WTBL_SEC_KEY, 342 WTBL_BA, 343 WTBL_RDG, /* obsoleted */ 344 WTBL_PROTECT, /* not used */ 345 WTBL_CLEAR, /* not used */ 346 WTBL_BF, 347 WTBL_SMPS, 348 WTBL_RAW_DATA, /* debug only */ 349 WTBL_PN, 350 WTBL_SPE, 351 WTBL_MAX_NUM 352 }; 353 354 #define STA_TYPE_STA BIT(0) 355 #define STA_TYPE_AP BIT(1) 356 #define STA_TYPE_ADHOC BIT(2) 357 #define STA_TYPE_WDS BIT(4) 358 #define STA_TYPE_BC BIT(5) 359 360 #define NETWORK_INFRA BIT(16) 361 #define NETWORK_P2P BIT(17) 362 #define NETWORK_IBSS BIT(18) 363 #define NETWORK_WDS BIT(21) 364 365 #define SCAN_FUNC_RANDOM_MAC BIT(0) 366 #define SCAN_FUNC_SPLIT_SCAN BIT(5) 367 368 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA) 369 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA) 370 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P) 371 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P) 372 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS) 373 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS) 374 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA) 375 376 #define CONN_STATE_DISCONNECT 0 377 #define CONN_STATE_CONNECT 1 378 #define CONN_STATE_PORT_SECURE 2 379 380 /* HE MAC */ 381 #define STA_REC_HE_CAP_HTC BIT(0) 382 #define STA_REC_HE_CAP_BQR BIT(1) 383 #define STA_REC_HE_CAP_BSR BIT(2) 384 #define STA_REC_HE_CAP_OM BIT(3) 385 #define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4) 386 /* HE PHY */ 387 #define STA_REC_HE_CAP_DUAL_BAND BIT(5) 388 #define STA_REC_HE_CAP_LDPC BIT(6) 389 #define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7) 390 #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8) 391 /* STBC */ 392 #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9) 393 #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10) 394 #define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11) 395 #define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12) 396 /* GI */ 397 #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13) 398 #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14) 399 #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15) 400 #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16) 401 #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17) 402 /* 242 TONE */ 403 #define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18) 404 #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19) 405 #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20) 406 407 #define PHY_MODE_A BIT(0) 408 #define PHY_MODE_B BIT(1) 409 #define PHY_MODE_G BIT(2) 410 #define PHY_MODE_GN BIT(3) 411 #define PHY_MODE_AN BIT(4) 412 #define PHY_MODE_AC BIT(5) 413 #define PHY_MODE_AX_24G BIT(6) 414 #define PHY_MODE_AX_5G BIT(7) 415 #define PHY_MODE_AX_6G BIT(8) 416 417 #define MODE_CCK BIT(0) 418 #define MODE_OFDM BIT(1) 419 #define MODE_HT BIT(2) 420 #define MODE_VHT BIT(3) 421 #define MODE_HE BIT(4) 422 423 enum { 424 PHY_TYPE_HR_DSSS_INDEX = 0, 425 PHY_TYPE_ERP_INDEX, 426 PHY_TYPE_ERP_P2P_INDEX, 427 PHY_TYPE_OFDM_INDEX, 428 PHY_TYPE_HT_INDEX, 429 PHY_TYPE_VHT_INDEX, 430 PHY_TYPE_HE_INDEX, 431 PHY_TYPE_INDEX_NUM 432 }; 433 434 #define PHY_TYPE_BIT_HR_DSSS BIT(PHY_TYPE_HR_DSSS_INDEX) 435 #define PHY_TYPE_BIT_ERP BIT(PHY_TYPE_ERP_INDEX) 436 #define PHY_TYPE_BIT_OFDM BIT(PHY_TYPE_OFDM_INDEX) 437 #define PHY_TYPE_BIT_HT BIT(PHY_TYPE_HT_INDEX) 438 #define PHY_TYPE_BIT_VHT BIT(PHY_TYPE_VHT_INDEX) 439 #define PHY_TYPE_BIT_HE BIT(PHY_TYPE_HE_INDEX) 440 441 #define MT_WTBL_RATE_TX_MODE GENMASK(9, 6) 442 #define MT_WTBL_RATE_MCS GENMASK(5, 0) 443 #define MT_WTBL_RATE_NSS GENMASK(12, 10) 444 #define MT_WTBL_RATE_HE_GI GENMASK(7, 4) 445 #define MT_WTBL_RATE_GI GENMASK(3, 0) 446 447 #define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5) 448 #define MT_WTBL_W5_SHORT_GI_20 BIT(8) 449 #define MT_WTBL_W5_SHORT_GI_40 BIT(9) 450 #define MT_WTBL_W5_SHORT_GI_80 BIT(10) 451 #define MT_WTBL_W5_SHORT_GI_160 BIT(11) 452 #define MT_WTBL_W5_BW_CAP GENMASK(13, 12) 453 #define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23) 454 #define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26) 455 #define MT_WTBL_W5_RATE_IDX GENMASK(31, 29) 456 457 enum { 458 WTBL_RESET_AND_SET = 1, 459 WTBL_SET, 460 WTBL_QUERY, 461 WTBL_RESET_ALL 462 }; 463 464 enum { 465 MT_BA_TYPE_INVALID, 466 MT_BA_TYPE_ORIGINATOR, 467 MT_BA_TYPE_RECIPIENT 468 }; 469 470 enum { 471 RST_BA_MAC_TID_MATCH, 472 RST_BA_MAC_MATCH, 473 RST_BA_NO_MATCH 474 }; 475 476 enum { 477 DEV_INFO_ACTIVE, 478 DEV_INFO_MAX_NUM 479 }; 480 481 #define MCU_CMD_ACK BIT(0) 482 #define MCU_CMD_UNI BIT(1) 483 #define MCU_CMD_QUERY BIT(2) 484 485 #define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | \ 486 MCU_CMD_QUERY) 487 488 #define MCU_FW_PREFIX BIT(31) 489 #define MCU_UNI_PREFIX BIT(30) 490 #define MCU_CE_PREFIX BIT(29) 491 #define MCU_QUERY_PREFIX BIT(28) 492 #define MCU_CMD_MASK ~(MCU_FW_PREFIX | MCU_UNI_PREFIX | \ 493 MCU_CE_PREFIX | MCU_QUERY_PREFIX) 494 495 #define MCU_QUERY_MASK BIT(16) 496 497 enum { 498 MCU_EXT_CMD_EFUSE_ACCESS = 0x01, 499 MCU_EXT_CMD_RF_REG_ACCESS = 0x02, 500 MCU_EXT_CMD_PM_STATE_CTRL = 0x07, 501 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08, 502 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11, 503 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13, 504 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21, 505 MCU_EXT_CMD_STA_REC_UPDATE = 0x25, 506 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26, 507 MCU_EXT_CMD_EDCA_UPDATE = 0x27, 508 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A, 509 MCU_EXT_CMD_GET_TEMP = 0x2c, 510 MCU_EXT_CMD_WTBL_UPDATE = 0x32, 511 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a, 512 MCU_EXT_CMD_ATE_CTRL = 0x3d, 513 MCU_EXT_CMD_PROTECT_CTRL = 0x3e, 514 MCU_EXT_CMD_DBDC_CTRL = 0x45, 515 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46, 516 MCU_EXT_CMD_RX_HDR_TRANS = 0x47, 517 MCU_EXT_CMD_MUAR_UPDATE = 0x48, 518 MCU_EXT_CMD_BCN_OFFLOAD = 0x49, 519 MCU_EXT_CMD_SET_RX_PATH = 0x4e, 520 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58, 521 MCU_EXT_CMD_RXDCOC_CAL = 0x59, 522 MCU_EXT_CMD_TXDPD_CAL = 0x60, 523 MCU_EXT_CMD_SET_RDD_TH = 0x7c, 524 MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d, 525 }; 526 527 enum { 528 MCU_UNI_CMD_DEV_INFO_UPDATE = MCU_UNI_PREFIX | 0x01, 529 MCU_UNI_CMD_BSS_INFO_UPDATE = MCU_UNI_PREFIX | 0x02, 530 MCU_UNI_CMD_STA_REC_UPDATE = MCU_UNI_PREFIX | 0x03, 531 MCU_UNI_CMD_SUSPEND = MCU_UNI_PREFIX | 0x05, 532 MCU_UNI_CMD_OFFLOAD = MCU_UNI_PREFIX | 0x06, 533 MCU_UNI_CMD_HIF_CTRL = MCU_UNI_PREFIX | 0x07, 534 }; 535 536 enum { 537 MCU_CMD_TARGET_ADDRESS_LEN_REQ = MCU_FW_PREFIX | 0x01, 538 MCU_CMD_FW_START_REQ = MCU_FW_PREFIX | 0x02, 539 MCU_CMD_INIT_ACCESS_REG = 0x3, 540 MCU_CMD_NIC_POWER_CTRL = MCU_FW_PREFIX | 0x4, 541 MCU_CMD_PATCH_START_REQ = MCU_FW_PREFIX | 0x05, 542 MCU_CMD_PATCH_FINISH_REQ = MCU_FW_PREFIX | 0x07, 543 MCU_CMD_PATCH_SEM_CONTROL = MCU_FW_PREFIX | 0x10, 544 MCU_CMD_EXT_CID = 0xed, 545 MCU_CMD_FW_SCATTER = MCU_FW_PREFIX | 0xee, 546 MCU_CMD_RESTART_DL_REQ = MCU_FW_PREFIX | 0xef, 547 }; 548 549 /* offload mcu commands */ 550 enum { 551 MCU_CMD_START_HW_SCAN = MCU_CE_PREFIX | 0x03, 552 MCU_CMD_SET_PS_PROFILE = MCU_CE_PREFIX | 0x05, 553 MCU_CMD_SET_CHAN_DOMAIN = MCU_CE_PREFIX | 0x0f, 554 MCU_CMD_SET_BSS_CONNECTED = MCU_CE_PREFIX | 0x16, 555 MCU_CMD_SET_BSS_ABORT = MCU_CE_PREFIX | 0x17, 556 MCU_CMD_CANCEL_HW_SCAN = MCU_CE_PREFIX | 0x1b, 557 MCU_CMD_SET_ROC = MCU_CE_PREFIX | 0x1d, 558 MCU_CMD_SET_P2P_OPPPS = MCU_CE_PREFIX | 0x33, 559 MCU_CMD_SET_RATE_TX_POWER = MCU_CE_PREFIX | 0x5d, 560 MCU_CMD_SCHED_SCAN_ENABLE = MCU_CE_PREFIX | 0x61, 561 MCU_CMD_SCHED_SCAN_REQ = MCU_CE_PREFIX | 0x62, 562 MCU_CMD_REG_WRITE = MCU_CE_PREFIX | 0xc0, 563 MCU_CMD_REG_READ = MCU_CE_PREFIX | MCU_QUERY_MASK | 0xc0, 564 MCU_CMD_CHIP_CONFIG = MCU_CE_PREFIX | 0xca, 565 MCU_CMD_FWLOG_2_HOST = MCU_CE_PREFIX | 0xc5, 566 MCU_CMD_GET_WTBL = MCU_CE_PREFIX | 0xcd, 567 MCU_CMD_GET_TXPWR = MCU_CE_PREFIX | 0xd0, 568 }; 569 570 enum { 571 PATCH_SEM_RELEASE, 572 PATCH_SEM_GET 573 }; 574 575 enum { 576 UNI_BSS_INFO_BASIC = 0, 577 UNI_BSS_INFO_RLM = 2, 578 UNI_BSS_INFO_HE_BASIC = 5, 579 UNI_BSS_INFO_BCN_CONTENT = 7, 580 UNI_BSS_INFO_QBSS = 15, 581 UNI_BSS_INFO_UAPSD = 19, 582 UNI_BSS_INFO_PS = 21, 583 UNI_BSS_INFO_BCNFT = 22, 584 }; 585 586 enum { 587 UNI_OFFLOAD_OFFLOAD_ARP, 588 UNI_OFFLOAD_OFFLOAD_ND, 589 UNI_OFFLOAD_OFFLOAD_GTK_REKEY, 590 UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT, 591 }; 592 593 enum { 594 UNI_SUSPEND_MODE_SETTING, 595 UNI_SUSPEND_WOW_CTRL, 596 UNI_SUSPEND_WOW_GPIO_PARAM, 597 UNI_SUSPEND_WOW_WAKEUP_PORT, 598 UNI_SUSPEND_WOW_PATTERN, 599 }; 600 601 enum { 602 WOW_USB = 1, 603 WOW_PCIE = 2, 604 WOW_GPIO = 3, 605 }; 606 607 struct mt76_connac_bss_basic_tlv { 608 __le16 tag; 609 __le16 len; 610 u8 active; 611 u8 omac_idx; 612 u8 hw_bss_idx; 613 u8 band_idx; 614 __le32 conn_type; 615 u8 conn_state; 616 u8 wmm_idx; 617 u8 bssid[ETH_ALEN]; 618 __le16 bmc_tx_wlan_idx; 619 __le16 bcn_interval; 620 u8 dtim_period; 621 u8 phymode; /* bit(0): A 622 * bit(1): B 623 * bit(2): G 624 * bit(3): GN 625 * bit(4): AN 626 * bit(5): AC 627 */ 628 __le16 sta_idx; 629 u8 nonht_basic_phy; 630 u8 pad[3]; 631 } __packed; 632 633 struct mt76_connac_bss_qos_tlv { 634 __le16 tag; 635 __le16 len; 636 u8 qos; 637 u8 pad[3]; 638 } __packed; 639 640 struct mt76_connac_beacon_loss_event { 641 u8 bss_idx; 642 u8 reason; 643 u8 pad[2]; 644 } __packed; 645 646 struct mt76_connac_mcu_bss_event { 647 u8 bss_idx; 648 u8 is_absent; 649 u8 free_quota; 650 u8 pad; 651 } __packed; 652 653 struct mt76_connac_mcu_scan_ssid { 654 __le32 ssid_len; 655 u8 ssid[IEEE80211_MAX_SSID_LEN]; 656 } __packed; 657 658 struct mt76_connac_mcu_scan_channel { 659 u8 band; /* 1: 2.4GHz 660 * 2: 5.0GHz 661 * Others: Reserved 662 */ 663 u8 channel_num; 664 } __packed; 665 666 struct mt76_connac_mcu_scan_match { 667 __le32 rssi_th; 668 u8 ssid[IEEE80211_MAX_SSID_LEN]; 669 u8 ssid_len; 670 u8 rsv[3]; 671 } __packed; 672 673 struct mt76_connac_hw_scan_req { 674 u8 seq_num; 675 u8 bss_idx; 676 u8 scan_type; /* 0: PASSIVE SCAN 677 * 1: ACTIVE SCAN 678 */ 679 u8 ssid_type; /* BIT(0) wildcard SSID 680 * BIT(1) P2P wildcard SSID 681 * BIT(2) specified SSID + wildcard SSID 682 * BIT(2) + ssid_type_ext BIT(0) specified SSID only 683 */ 684 u8 ssids_num; 685 u8 probe_req_num; /* Number of probe request for each SSID */ 686 u8 scan_func; /* BIT(0) Enable random MAC scan 687 * BIT(1) Disable DBDC scan type 1~3. 688 * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan). 689 */ 690 u8 version; /* 0: Not support fields after ies. 691 * 1: Support fields after ies. 692 */ 693 struct mt76_connac_mcu_scan_ssid ssids[4]; 694 __le16 probe_delay_time; 695 __le16 channel_dwell_time; /* channel Dwell interval */ 696 __le16 timeout_value; 697 u8 channel_type; /* 0: Full channels 698 * 1: Only 2.4GHz channels 699 * 2: Only 5GHz channels 700 * 3: P2P social channel only (channel #1, #6 and #11) 701 * 4: Specified channels 702 * Others: Reserved 703 */ 704 u8 channels_num; /* valid when channel_type is 4 */ 705 /* valid when channels_num is set */ 706 struct mt76_connac_mcu_scan_channel channels[32]; 707 __le16 ies_len; 708 u8 ies[MT76_CONNAC_SCAN_IE_LEN]; 709 /* following fields are valid if version > 0 */ 710 u8 ext_channels_num; 711 u8 ext_ssids_num; 712 __le16 channel_min_dwell_time; 713 struct mt76_connac_mcu_scan_channel ext_channels[32]; 714 struct mt76_connac_mcu_scan_ssid ext_ssids[6]; 715 u8 bssid[ETH_ALEN]; 716 u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */ 717 u8 pad[63]; 718 u8 ssid_type_ext; 719 } __packed; 720 721 #define MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM 64 722 723 struct mt76_connac_hw_scan_done { 724 u8 seq_num; 725 u8 sparse_channel_num; 726 struct mt76_connac_mcu_scan_channel sparse_channel; 727 u8 complete_channel_num; 728 u8 current_state; 729 u8 version; 730 u8 pad; 731 __le32 beacon_scan_num; 732 u8 pno_enabled; 733 u8 pad2[3]; 734 u8 sparse_channel_valid_num; 735 u8 pad3[3]; 736 u8 channel_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 737 /* idle format for channel_idle_time 738 * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms) 739 * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms) 740 * 2: dwell time (16us) 741 */ 742 __le16 channel_idle_time[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 743 /* beacon and probe response count */ 744 u8 beacon_probe_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 745 u8 mdrdy_count[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 746 __le32 beacon_2g_num; 747 __le32 beacon_5g_num; 748 } __packed; 749 750 struct mt76_connac_sched_scan_req { 751 u8 version; 752 u8 seq_num; 753 u8 stop_on_match; 754 u8 ssids_num; 755 u8 match_num; 756 u8 pad; 757 __le16 ie_len; 758 struct mt76_connac_mcu_scan_ssid ssids[MT76_CONNAC_MAX_SCHED_SCAN_SSID]; 759 struct mt76_connac_mcu_scan_match match[MT76_CONNAC_MAX_SCAN_MATCH]; 760 u8 channel_type; 761 u8 channels_num; 762 u8 intervals_num; 763 u8 scan_func; /* MT7663: BIT(0) eable random mac address */ 764 struct mt76_connac_mcu_scan_channel channels[64]; 765 __le16 intervals[MT76_CONNAC_MAX_SCHED_SCAN_INTERVAL]; 766 union { 767 struct { 768 u8 random_mac[ETH_ALEN]; 769 u8 pad2[58]; 770 } mt7663; 771 struct { 772 u8 bss_idx; 773 u8 pad2[63]; 774 } mt7921; 775 }; 776 } __packed; 777 778 struct mt76_connac_sched_scan_done { 779 u8 seq_num; 780 u8 status; /* 0: ssid found */ 781 __le16 pad; 782 } __packed; 783 784 struct bss_info_uni_he { 785 __le16 tag; 786 __le16 len; 787 __le16 he_rts_thres; 788 u8 he_pe_duration; 789 u8 su_disable; 790 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 791 u8 rsv[2]; 792 } __packed; 793 794 struct mt76_connac_gtk_rekey_tlv { 795 __le16 tag; 796 __le16 len; 797 u8 kek[NL80211_KEK_LEN]; 798 u8 kck[NL80211_KCK_LEN]; 799 u8 replay_ctr[NL80211_REPLAY_CTR_LEN]; 800 u8 rekey_mode; /* 0: rekey offload enable 801 * 1: rekey offload disable 802 * 2: rekey update 803 */ 804 u8 keyid; 805 u8 pad[2]; 806 __le32 proto; /* WPA-RSN-WAPI-OPSN */ 807 __le32 pairwise_cipher; 808 __le32 group_cipher; 809 __le32 key_mgmt; /* NONE-PSK-IEEE802.1X */ 810 __le32 mgmt_group_cipher; 811 u8 option; /* 1: rekey data update without enabling offload */ 812 u8 reserverd[3]; 813 } __packed; 814 815 #define MT76_CONNAC_WOW_MASK_MAX_LEN 16 816 #define MT76_CONNAC_WOW_PATTEN_MAX_LEN 128 817 818 struct mt76_connac_wow_pattern_tlv { 819 __le16 tag; 820 __le16 len; 821 u8 index; /* pattern index */ 822 u8 enable; /* 0: disable 823 * 1: enable 824 */ 825 u8 data_len; /* pattern length */ 826 u8 pad; 827 u8 mask[MT76_CONNAC_WOW_MASK_MAX_LEN]; 828 u8 pattern[MT76_CONNAC_WOW_PATTEN_MAX_LEN]; 829 u8 rsv[4]; 830 } __packed; 831 832 struct mt76_connac_wow_ctrl_tlv { 833 __le16 tag; 834 __le16 len; 835 u8 cmd; /* 0x1: PM_WOWLAN_REQ_START 836 * 0x2: PM_WOWLAN_REQ_STOP 837 * 0x3: PM_WOWLAN_PARAM_CLEAR 838 */ 839 u8 trigger; /* 0: NONE 840 * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT 841 * BIT(1): NL80211_WOWLAN_TRIG_ANY 842 * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT 843 * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE 844 * BIT(4): BEACON_LOST 845 * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT 846 */ 847 u8 wakeup_hif; /* 0x0: HIF_SDIO 848 * 0x1: HIF_USB 849 * 0x2: HIF_PCIE 850 * 0x3: HIF_GPIO 851 */ 852 u8 pad; 853 u8 rsv[4]; 854 } __packed; 855 856 struct mt76_connac_wow_gpio_param_tlv { 857 __le16 tag; 858 __le16 len; 859 u8 gpio_pin; 860 u8 trigger_lvl; 861 u8 pad[2]; 862 __le32 gpio_interval; 863 u8 rsv[4]; 864 } __packed; 865 866 struct mt76_connac_arpns_tlv { 867 __le16 tag; 868 __le16 len; 869 u8 mode; 870 u8 ips_num; 871 u8 option; 872 u8 pad[1]; 873 } __packed; 874 875 struct mt76_connac_suspend_tlv { 876 __le16 tag; 877 __le16 len; 878 u8 enable; /* 0: suspend mode disabled 879 * 1: suspend mode enabled 880 */ 881 u8 mdtim; /* LP parameter */ 882 u8 wow_suspend; /* 0: update by origin policy 883 * 1: update by wow dtim 884 */ 885 u8 pad[5]; 886 } __packed; 887 888 struct mt76_sta_cmd_info { 889 struct ieee80211_sta *sta; 890 struct mt76_wcid *wcid; 891 892 struct ieee80211_vif *vif; 893 894 bool enable; 895 int cmd; 896 u8 rcpi; 897 }; 898 899 #define MT_SKU_POWER_LIMIT 161 900 901 struct mt76_connac_sku_tlv { 902 u8 channel; 903 s8 pwr_limit[MT_SKU_POWER_LIMIT]; 904 } __packed; 905 906 struct mt76_connac_tx_power_limit_tlv { 907 /* DW0 - common info*/ 908 u8 ver; 909 u8 pad0; 910 __le16 len; 911 /* DW1 - cmd hint */ 912 u8 n_chan; /* # channel */ 913 u8 band; /* 2.4GHz - 5GHz */ 914 u8 last_msg; 915 u8 pad1; 916 /* DW3 */ 917 u8 alpha2[4]; /* regulatory_request.alpha2 */ 918 u8 pad2[32]; 919 } __packed; 920 921 struct mt76_connac_config { 922 __le16 id; 923 u8 type; 924 u8 resp_type; 925 __le16 data_size; 926 __le16 resv; 927 u8 data[320]; 928 } __packed; 929 930 #define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id) 931 #define to_wcid_hi(id) FIELD_GET(GENMASK(9, 8), (u16)id) 932 933 static inline void 934 mt76_connac_mcu_get_wlan_idx(struct mt76_dev *dev, struct mt76_wcid *wcid, 935 u8 *wlan_idx_lo, u8 *wlan_idx_hi) 936 { 937 *wlan_idx_hi = 0; 938 939 if (is_mt7921(dev)) { 940 *wlan_idx_lo = wcid ? to_wcid_lo(wcid->idx) : 0; 941 *wlan_idx_hi = wcid ? to_wcid_hi(wcid->idx) : 0; 942 } else { 943 *wlan_idx_lo = wcid ? wcid->idx : 0; 944 } 945 } 946 947 struct sk_buff * 948 mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif, 949 struct mt76_wcid *wcid); 950 struct wtbl_req_hdr * 951 mt76_connac_mcu_alloc_wtbl_req(struct mt76_dev *dev, struct mt76_wcid *wcid, 952 int cmd, void *sta_wtbl, struct sk_buff **skb); 953 struct tlv *mt76_connac_mcu_add_nested_tlv(struct sk_buff *skb, int tag, 954 int len, void *sta_ntlv, 955 void *sta_wtbl); 956 static inline struct tlv * 957 mt76_connac_mcu_add_tlv(struct sk_buff *skb, int tag, int len) 958 { 959 return mt76_connac_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL); 960 } 961 962 int mt76_connac_mcu_set_channel_domain(struct mt76_phy *phy); 963 int mt76_connac_mcu_set_vif_ps(struct mt76_dev *dev, struct ieee80211_vif *vif); 964 void mt76_connac_mcu_sta_basic_tlv(struct sk_buff *skb, 965 struct ieee80211_vif *vif, 966 struct ieee80211_sta *sta, bool enable); 967 void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev, struct sk_buff *skb, 968 struct ieee80211_vif *vif, 969 struct ieee80211_sta *sta, void *sta_wtbl, 970 void *wtbl_tlv); 971 void mt76_connac_mcu_wtbl_hdr_trans_tlv(struct sk_buff *skb, 972 struct mt76_wcid *wcid, 973 void *sta_wtbl, void *wtbl_tlv); 974 void mt76_connac_mcu_sta_tlv(struct mt76_phy *mphy, struct sk_buff *skb, 975 struct ieee80211_sta *sta, 976 struct ieee80211_vif *vif, 977 u8 rcpi); 978 void mt76_connac_mcu_wtbl_ht_tlv(struct mt76_dev *dev, struct sk_buff *skb, 979 struct ieee80211_sta *sta, void *sta_wtbl, 980 void *wtbl_tlv); 981 void mt76_connac_mcu_wtbl_ba_tlv(struct mt76_dev *dev, struct sk_buff *skb, 982 struct ieee80211_ampdu_params *params, 983 bool enable, bool tx, void *sta_wtbl, 984 void *wtbl_tlv); 985 void mt76_connac_mcu_sta_ba_tlv(struct sk_buff *skb, 986 struct ieee80211_ampdu_params *params, 987 bool enable, bool tx); 988 int mt76_connac_mcu_uni_add_dev(struct mt76_phy *phy, 989 struct ieee80211_vif *vif, 990 struct mt76_wcid *wcid, 991 bool enable); 992 int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif, 993 struct ieee80211_ampdu_params *params, 994 bool enable, bool tx); 995 int mt76_connac_mcu_uni_add_bss(struct mt76_phy *phy, 996 struct ieee80211_vif *vif, 997 struct mt76_wcid *wcid, 998 bool enable); 999 int mt76_connac_mcu_add_sta_cmd(struct mt76_phy *phy, 1000 struct mt76_sta_cmd_info *info); 1001 void mt76_connac_mcu_beacon_loss_iter(void *priv, u8 *mac, 1002 struct ieee80211_vif *vif); 1003 int mt76_connac_mcu_set_rts_thresh(struct mt76_dev *dev, u32 val, u8 band); 1004 int mt76_connac_mcu_set_mac_enable(struct mt76_dev *dev, int band, bool enable, 1005 bool hdr_trans); 1006 int mt76_connac_mcu_init_download(struct mt76_dev *dev, u32 addr, u32 len, 1007 u32 mode); 1008 int mt76_connac_mcu_start_patch(struct mt76_dev *dev); 1009 int mt76_connac_mcu_patch_sem_ctrl(struct mt76_dev *dev, bool get); 1010 int mt76_connac_mcu_start_firmware(struct mt76_dev *dev, u32 addr, u32 option); 1011 1012 int mt76_connac_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif, 1013 struct ieee80211_scan_request *scan_req); 1014 int mt76_connac_mcu_cancel_hw_scan(struct mt76_phy *phy, 1015 struct ieee80211_vif *vif); 1016 int mt76_connac_mcu_sched_scan_req(struct mt76_phy *phy, 1017 struct ieee80211_vif *vif, 1018 struct cfg80211_sched_scan_request *sreq); 1019 int mt76_connac_mcu_sched_scan_enable(struct mt76_phy *phy, 1020 struct ieee80211_vif *vif, 1021 bool enable); 1022 int mt76_connac_mcu_update_arp_filter(struct mt76_dev *dev, 1023 struct mt76_vif *vif, 1024 struct ieee80211_bss_conf *info); 1025 int mt76_connac_mcu_update_gtk_rekey(struct ieee80211_hw *hw, 1026 struct ieee80211_vif *vif, 1027 struct cfg80211_gtk_rekey_data *key); 1028 int mt76_connac_mcu_set_hif_suspend(struct mt76_dev *dev, bool suspend); 1029 void mt76_connac_mcu_set_suspend_iter(void *priv, u8 *mac, 1030 struct ieee80211_vif *vif); 1031 int mt76_connac_mcu_chip_config(struct mt76_dev *dev); 1032 int mt76_connac_mcu_set_deep_sleep(struct mt76_dev *dev, bool enable); 1033 void mt76_connac_mcu_coredump_event(struct mt76_dev *dev, struct sk_buff *skb, 1034 struct mt76_connac_coredump *coredump); 1035 int mt76_connac_mcu_set_rate_txpower(struct mt76_phy *phy); 1036 #endif /* __MT76_CONNAC_MCU_H */ 1037