1 /* SPDX-License-Identifier: ISC */ 2 3 #ifndef __MT7603_H 4 #define __MT7603_H 5 6 #include <linux/interrupt.h> 7 #include <linux/ktime.h> 8 #include "../mt76.h" 9 #include "regs.h" 10 11 #define MT7603_MAX_INTERFACES 4 12 #define MT7603_WTBL_SIZE 128 13 #define MT7603_WTBL_RESERVED (MT7603_WTBL_SIZE - 1) 14 #define MT7603_WTBL_STA (MT7603_WTBL_RESERVED - MT7603_MAX_INTERFACES) 15 16 #define MT7603_RATE_RETRY 2 17 18 #define MT7603_RX_RING_SIZE 128 19 20 #define MT7603_FIRMWARE_E1 "mt7603_e1.bin" 21 #define MT7603_FIRMWARE_E2 "mt7603_e2.bin" 22 #define MT7628_FIRMWARE_E1 "mt7628_e1.bin" 23 #define MT7628_FIRMWARE_E2 "mt7628_e2.bin" 24 25 #define MT7603_EEPROM_SIZE 1024 26 27 #define MT_AGG_SIZE_LIMIT(_n) (((_n) + 1) * 4) 28 29 #define MT7603_PRE_TBTT_TIME 5000 /* ms */ 30 31 #define MT7603_WATCHDOG_TIME 100 /* ms */ 32 #define MT7603_WATCHDOG_TIMEOUT 10 /* number of checks */ 33 34 #define MT7603_EDCCA_BLOCK_TH 10 35 36 #define MT7603_CFEND_RATE_DEFAULT 0x69 /* chip default (24M) */ 37 #define MT7603_CFEND_RATE_11B 0x03 /* 11B LP, 11M */ 38 39 struct mt7603_vif; 40 struct mt7603_sta; 41 42 enum { 43 MT7603_REV_E1 = 0x00, 44 MT7603_REV_E2 = 0x10, 45 MT7628_REV_E1 = 0x8a00, 46 }; 47 48 enum mt7603_bw { 49 MT_BW_20, 50 MT_BW_40, 51 MT_BW_80, 52 }; 53 54 struct mt7603_sta { 55 struct mt76_wcid wcid; /* must be first */ 56 57 struct mt7603_vif *vif; 58 59 struct sk_buff_head psq; 60 61 struct ieee80211_tx_rate rates[8]; 62 u8 rate_count; 63 u8 n_rates; 64 65 u8 rate_probe; 66 u8 smps; 67 68 u8 ps; 69 }; 70 71 struct mt7603_vif { 72 struct mt7603_sta sta; /* must be first */ 73 74 u8 idx; 75 }; 76 77 enum mt7603_reset_cause { 78 RESET_CAUSE_TX_HANG, 79 RESET_CAUSE_TX_BUSY, 80 RESET_CAUSE_RX_BUSY, 81 RESET_CAUSE_BEACON_STUCK, 82 RESET_CAUSE_RX_PSE_BUSY, 83 RESET_CAUSE_MCU_HANG, 84 RESET_CAUSE_RESET_FAILED, 85 __RESET_CAUSE_MAX 86 }; 87 88 struct mt7603_dev { 89 struct mt76_dev mt76; /* must be first */ 90 91 const struct mt76_bus_ops *bus_ops; 92 93 u32 rxfilter; 94 95 u8 vif_mask; 96 97 struct mt7603_sta global_sta; 98 99 u32 agc0, agc3; 100 u32 false_cca_ofdm, false_cca_cck; 101 unsigned long last_cca_adj; 102 103 u8 rssi_offset[3]; 104 105 u8 slottime; 106 s16 coverage_class; 107 108 s8 tx_power_limit; 109 110 ktime_t survey_time; 111 ktime_t ed_time; 112 int beacon_int; 113 114 struct mt76_queue q_rx; 115 116 spinlock_t ps_lock; 117 118 u8 mac_work_count; 119 120 u8 mcu_running; 121 u8 ed_monitor; 122 123 s8 ed_trigger; 124 u8 ed_strict_mode; 125 u8 ed_strong_signal; 126 127 s8 sensitivity; 128 129 u8 beacon_mask; 130 131 u8 beacon_check; 132 u8 tx_hang_check; 133 u8 tx_dma_check; 134 u8 rx_dma_check; 135 u8 rx_pse_check; 136 u8 mcu_hang; 137 138 enum mt7603_reset_cause cur_reset_cause; 139 140 u16 tx_dma_idx[4]; 141 u16 rx_dma_idx; 142 143 u32 reset_test; 144 145 unsigned int reset_cause[__RESET_CAUSE_MAX]; 146 147 struct delayed_work mac_work; 148 struct tasklet_struct tx_tasklet; 149 struct tasklet_struct pre_tbtt_tasklet; 150 }; 151 152 extern const struct mt76_driver_ops mt7603_drv_ops; 153 extern const struct ieee80211_ops mt7603_ops; 154 extern struct pci_driver mt7603_pci_driver; 155 extern struct platform_driver mt76_wmac_driver; 156 157 static inline bool is_mt7603(struct mt7603_dev *dev) 158 { 159 return mt76xx_chip(dev) == 0x7603; 160 } 161 162 static inline bool is_mt7628(struct mt7603_dev *dev) 163 { 164 return mt76xx_chip(dev) == 0x7628; 165 } 166 167 /* need offset to prevent conflict with ampdu_ack_len */ 168 #define MT_RATE_DRIVER_DATA_OFFSET 4 169 170 u32 mt7603_reg_map(struct mt7603_dev *dev, u32 addr); 171 172 irqreturn_t mt7603_irq_handler(int irq, void *dev_instance); 173 174 int mt7603_register_device(struct mt7603_dev *dev); 175 void mt7603_unregister_device(struct mt7603_dev *dev); 176 int mt7603_eeprom_init(struct mt7603_dev *dev); 177 int mt7603_dma_init(struct mt7603_dev *dev); 178 void mt7603_dma_cleanup(struct mt7603_dev *dev); 179 int mt7603_mcu_init(struct mt7603_dev *dev); 180 void mt7603_init_debugfs(struct mt7603_dev *dev); 181 182 void mt7603_set_irq_mask(struct mt7603_dev *dev, u32 clear, u32 set); 183 184 static inline void mt7603_irq_enable(struct mt7603_dev *dev, u32 mask) 185 { 186 mt7603_set_irq_mask(dev, 0, mask); 187 } 188 189 static inline void mt7603_irq_disable(struct mt7603_dev *dev, u32 mask) 190 { 191 mt7603_set_irq_mask(dev, mask, 0); 192 } 193 194 void mt7603_mac_dma_start(struct mt7603_dev *dev); 195 void mt7603_mac_start(struct mt7603_dev *dev); 196 void mt7603_mac_stop(struct mt7603_dev *dev); 197 void mt7603_mac_work(struct work_struct *work); 198 void mt7603_mac_set_timing(struct mt7603_dev *dev); 199 void mt7603_beacon_set_timer(struct mt7603_dev *dev, int idx, int intval); 200 int mt7603_mac_fill_rx(struct mt7603_dev *dev, struct sk_buff *skb); 201 void mt7603_mac_add_txs(struct mt7603_dev *dev, void *data); 202 void mt7603_mac_rx_ba_reset(struct mt7603_dev *dev, void *addr, u8 tid); 203 void mt7603_mac_tx_ba_reset(struct mt7603_dev *dev, int wcid, int tid, int ssn, 204 int ba_size); 205 206 void mt7603_pse_client_reset(struct mt7603_dev *dev); 207 208 int mt7603_mcu_set_channel(struct mt7603_dev *dev); 209 int mt7603_mcu_set_eeprom(struct mt7603_dev *dev); 210 void mt7603_mcu_exit(struct mt7603_dev *dev); 211 212 void mt7603_wtbl_init(struct mt7603_dev *dev, int idx, int vif, 213 const u8 *mac_addr); 214 void mt7603_wtbl_clear(struct mt7603_dev *dev, int idx); 215 void mt7603_wtbl_update_cap(struct mt7603_dev *dev, struct ieee80211_sta *sta); 216 void mt7603_wtbl_set_rates(struct mt7603_dev *dev, struct mt7603_sta *sta, 217 struct ieee80211_tx_rate *probe_rate, 218 struct ieee80211_tx_rate *rates); 219 int mt7603_wtbl_set_key(struct mt7603_dev *dev, int wcid, 220 struct ieee80211_key_conf *key); 221 void mt7603_wtbl_set_ps(struct mt7603_dev *dev, struct mt7603_sta *sta, 222 bool enabled); 223 void mt7603_wtbl_set_smps(struct mt7603_dev *dev, struct mt7603_sta *sta, 224 bool enabled); 225 void mt7603_filter_tx(struct mt7603_dev *dev, int idx, bool abort); 226 227 int mt7603_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 228 struct sk_buff *skb, struct mt76_queue *q, 229 struct mt76_wcid *wcid, struct ieee80211_sta *sta, 230 u32 *tx_info); 231 232 void mt7603_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue *q, 233 struct mt76_queue_entry *e, bool flush); 234 235 void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 236 struct sk_buff *skb); 237 void mt7603_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q); 238 void mt7603_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps); 239 int mt7603_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif, 240 struct ieee80211_sta *sta); 241 void mt7603_sta_assoc(struct mt76_dev *mdev, struct ieee80211_vif *vif, 242 struct ieee80211_sta *sta); 243 void mt7603_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif, 244 struct ieee80211_sta *sta); 245 246 void mt7603_pre_tbtt_tasklet(unsigned long arg); 247 248 void mt7603_update_channel(struct mt76_dev *mdev); 249 250 void mt7603_edcca_set_strict(struct mt7603_dev *dev, bool val); 251 void mt7603_cca_stats_reset(struct mt7603_dev *dev); 252 253 #endif 254