1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #ifndef __MT76_H 7 #define __MT76_H 8 9 #include <linux/kernel.h> 10 #include <linux/io.h> 11 #include <linux/spinlock.h> 12 #include <linux/skbuff.h> 13 #include <linux/leds.h> 14 #include <linux/usb.h> 15 #include <linux/average.h> 16 #include <linux/soc/mediatek/mtk_wed.h> 17 #include <net/mac80211.h> 18 #include "util.h" 19 #include "testmode.h" 20 21 #define MT_MCU_RING_SIZE 32 22 #define MT_RX_BUF_SIZE 2048 23 #define MT_SKB_HEAD_LEN 256 24 25 #define MT_MAX_NON_AQL_PKT 16 26 #define MT_TXQ_FREE_THR 32 27 28 #define MT76_TOKEN_FREE_THR 64 29 30 #define MT_QFLAG_WED_RING GENMASK(1, 0) 31 #define MT_QFLAG_WED_TYPE GENMASK(3, 2) 32 #define MT_QFLAG_WED BIT(4) 33 34 #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \ 35 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ 36 FIELD_PREP(MT_QFLAG_WED_RING, _n)) 37 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n) 38 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0) 39 40 struct mt76_dev; 41 struct mt76_phy; 42 struct mt76_wcid; 43 struct mt76s_intr; 44 45 struct mt76_reg_pair { 46 u32 reg; 47 u32 value; 48 }; 49 50 enum mt76_bus_type { 51 MT76_BUS_MMIO, 52 MT76_BUS_USB, 53 MT76_BUS_SDIO, 54 }; 55 56 enum mt76_wed_type { 57 MT76_WED_Q_TX, 58 MT76_WED_Q_TXFREE, 59 }; 60 61 struct mt76_bus_ops { 62 u32 (*rr)(struct mt76_dev *dev, u32 offset); 63 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 64 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 65 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, 66 int len); 67 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, 68 int len); 69 int (*wr_rp)(struct mt76_dev *dev, u32 base, 70 const struct mt76_reg_pair *rp, int len); 71 int (*rd_rp)(struct mt76_dev *dev, u32 base, 72 struct mt76_reg_pair *rp, int len); 73 enum mt76_bus_type type; 74 }; 75 76 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) 77 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) 78 #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO) 79 80 enum mt76_txq_id { 81 MT_TXQ_VO = IEEE80211_AC_VO, 82 MT_TXQ_VI = IEEE80211_AC_VI, 83 MT_TXQ_BE = IEEE80211_AC_BE, 84 MT_TXQ_BK = IEEE80211_AC_BK, 85 MT_TXQ_PSD, 86 MT_TXQ_BEACON, 87 MT_TXQ_CAB, 88 __MT_TXQ_MAX 89 }; 90 91 enum mt76_mcuq_id { 92 MT_MCUQ_WM, 93 MT_MCUQ_WA, 94 MT_MCUQ_FWDL, 95 __MT_MCUQ_MAX 96 }; 97 98 enum mt76_rxq_id { 99 MT_RXQ_MAIN, 100 MT_RXQ_MCU, 101 MT_RXQ_MCU_WA, 102 MT_RXQ_BAND1, 103 MT_RXQ_BAND1_WA, 104 MT_RXQ_MAIN_WA, 105 MT_RXQ_BAND2, 106 MT_RXQ_BAND2_WA, 107 __MT_RXQ_MAX 108 }; 109 110 enum mt76_band_id { 111 MT_BAND0, 112 MT_BAND1, 113 MT_BAND2, 114 __MT_MAX_BAND 115 }; 116 117 enum mt76_cipher_type { 118 MT_CIPHER_NONE, 119 MT_CIPHER_WEP40, 120 MT_CIPHER_TKIP, 121 MT_CIPHER_TKIP_NO_MIC, 122 MT_CIPHER_AES_CCMP, 123 MT_CIPHER_WEP104, 124 MT_CIPHER_BIP_CMAC_128, 125 MT_CIPHER_WEP128, 126 MT_CIPHER_WAPI, 127 MT_CIPHER_CCMP_CCX, 128 MT_CIPHER_CCMP_256, 129 MT_CIPHER_GCMP, 130 MT_CIPHER_GCMP_256, 131 }; 132 133 enum mt76_dfs_state { 134 MT_DFS_STATE_UNKNOWN, 135 MT_DFS_STATE_DISABLED, 136 MT_DFS_STATE_CAC, 137 MT_DFS_STATE_ACTIVE, 138 }; 139 140 struct mt76_queue_buf { 141 dma_addr_t addr; 142 u16 len; 143 bool skip_unmap; 144 }; 145 146 struct mt76_tx_info { 147 struct mt76_queue_buf buf[32]; 148 struct sk_buff *skb; 149 int nbuf; 150 u32 info; 151 }; 152 153 struct mt76_queue_entry { 154 union { 155 void *buf; 156 struct sk_buff *skb; 157 }; 158 union { 159 struct mt76_txwi_cache *txwi; 160 struct urb *urb; 161 int buf_sz; 162 }; 163 u32 dma_addr[2]; 164 u16 dma_len[2]; 165 u16 wcid; 166 bool skip_buf0:1; 167 bool skip_buf1:1; 168 bool done:1; 169 }; 170 171 struct mt76_queue_regs { 172 u32 desc_base; 173 u32 ring_size; 174 u32 cpu_idx; 175 u32 dma_idx; 176 } __packed __aligned(4); 177 178 struct mt76_queue { 179 struct mt76_queue_regs __iomem *regs; 180 181 spinlock_t lock; 182 spinlock_t cleanup_lock; 183 struct mt76_queue_entry *entry; 184 struct mt76_desc *desc; 185 186 u16 first; 187 u16 head; 188 u16 tail; 189 int ndesc; 190 int queued; 191 int buf_size; 192 bool stopped; 193 bool blocked; 194 195 u8 buf_offset; 196 u8 hw_idx; 197 u8 flags; 198 199 u32 wed_regs; 200 201 dma_addr_t desc_dma; 202 struct sk_buff *rx_head; 203 struct page_frag_cache rx_page; 204 }; 205 206 struct mt76_mcu_ops { 207 u32 headroom; 208 u32 tailroom; 209 210 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, 211 int len, bool wait_resp); 212 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, 213 int cmd, int *seq); 214 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd, 215 struct sk_buff *skb, int seq); 216 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset); 217 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val); 218 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, 219 const struct mt76_reg_pair *rp, int len); 220 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, 221 struct mt76_reg_pair *rp, int len); 222 int (*mcu_restart)(struct mt76_dev *dev); 223 }; 224 225 struct mt76_queue_ops { 226 int (*init)(struct mt76_dev *dev, 227 int (*poll)(struct napi_struct *napi, int budget)); 228 229 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, 230 int idx, int n_desc, int bufsize, 231 u32 ring_base); 232 233 int (*tx_queue_skb)(struct mt76_dev *dev, struct mt76_queue *q, 234 enum mt76_txq_id qid, struct sk_buff *skb, 235 struct mt76_wcid *wcid, struct ieee80211_sta *sta); 236 237 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q, 238 struct sk_buff *skb, u32 tx_info); 239 240 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 241 int *len, u32 *info, bool *more); 242 243 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); 244 245 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q, 246 bool flush); 247 248 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q); 249 250 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 251 252 void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q); 253 }; 254 255 enum mt76_phy_type { 256 MT_PHY_TYPE_CCK, 257 MT_PHY_TYPE_OFDM, 258 MT_PHY_TYPE_HT, 259 MT_PHY_TYPE_HT_GF, 260 MT_PHY_TYPE_VHT, 261 MT_PHY_TYPE_HE_SU = 8, 262 MT_PHY_TYPE_HE_EXT_SU, 263 MT_PHY_TYPE_HE_TB, 264 MT_PHY_TYPE_HE_MU, 265 __MT_PHY_TYPE_HE_MAX, 266 }; 267 268 struct mt76_sta_stats { 269 u64 tx_mode[__MT_PHY_TYPE_HE_MAX]; 270 u64 tx_bw[4]; /* 20, 40, 80, 160 */ 271 u64 tx_nss[4]; /* 1, 2, 3, 4 */ 272 u64 tx_mcs[16]; /* mcs idx */ 273 u64 tx_bytes; 274 u32 tx_packets; 275 u32 tx_retries; 276 u32 tx_failed; 277 }; 278 279 enum mt76_wcid_flags { 280 MT_WCID_FLAG_CHECK_PS, 281 MT_WCID_FLAG_PS, 282 MT_WCID_FLAG_4ADDR, 283 MT_WCID_FLAG_HDR_TRANS, 284 }; 285 286 #define MT76_N_WCIDS 544 287 288 /* stored in ieee80211_tx_info::hw_queue */ 289 #define MT_TX_HW_QUEUE_PHY GENMASK(3, 2) 290 291 DECLARE_EWMA(signal, 10, 8); 292 293 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) 294 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) 295 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) 296 #define MT_WCID_TX_INFO_SET BIT(31) 297 298 struct mt76_wcid { 299 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; 300 301 atomic_t non_aql_packets; 302 unsigned long flags; 303 304 struct ewma_signal rssi; 305 int inactive_count; 306 307 struct rate_info rate; 308 309 u16 idx; 310 u8 hw_key_idx; 311 u8 hw_key_idx2; 312 313 u8 sta:1; 314 u8 amsdu:1; 315 u8 phy_idx:2; 316 317 u8 rx_check_pn; 318 u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6]; 319 u16 cipher; 320 321 u32 tx_info; 322 bool sw_iv; 323 324 struct list_head list; 325 struct idr pktid; 326 327 struct mt76_sta_stats stats; 328 }; 329 330 struct mt76_txq { 331 u16 wcid; 332 333 u16 agg_ssn; 334 bool send_bar; 335 bool aggr; 336 }; 337 338 struct mt76_txwi_cache { 339 struct list_head list; 340 dma_addr_t dma_addr; 341 342 struct sk_buff *skb; 343 }; 344 345 struct mt76_rx_tid { 346 struct rcu_head rcu_head; 347 348 struct mt76_dev *dev; 349 350 spinlock_t lock; 351 struct delayed_work reorder_work; 352 353 u16 head; 354 u16 size; 355 u16 nframes; 356 357 u8 num; 358 359 u8 started:1, stopped:1, timer_pending:1; 360 361 struct sk_buff *reorder_buf[]; 362 }; 363 364 #define MT_TX_CB_DMA_DONE BIT(0) 365 #define MT_TX_CB_TXS_DONE BIT(1) 366 #define MT_TX_CB_TXS_FAILED BIT(2) 367 368 #define MT_PACKET_ID_MASK GENMASK(6, 0) 369 #define MT_PACKET_ID_NO_ACK 0 370 #define MT_PACKET_ID_NO_SKB 1 371 #define MT_PACKET_ID_WED 2 372 #define MT_PACKET_ID_FIRST 3 373 #define MT_PACKET_ID_HAS_RATE BIT(7) 374 /* This is timer for when to give up when waiting for TXS callback, 375 * with starting time being the time at which the DMA_DONE callback 376 * was seen (so, we know packet was processed then, it should not take 377 * long after that for firmware to send the TXS callback if it is going 378 * to do so.) 379 */ 380 #define MT_TX_STATUS_SKB_TIMEOUT (HZ / 4) 381 382 struct mt76_tx_cb { 383 unsigned long jiffies; 384 u16 wcid; 385 u8 pktid; 386 u8 flags; 387 }; 388 389 enum { 390 MT76_STATE_INITIALIZED, 391 MT76_STATE_RUNNING, 392 MT76_STATE_MCU_RUNNING, 393 MT76_SCANNING, 394 MT76_HW_SCANNING, 395 MT76_HW_SCHED_SCANNING, 396 MT76_RESTART, 397 MT76_RESET, 398 MT76_MCU_RESET, 399 MT76_REMOVED, 400 MT76_READING_STATS, 401 MT76_STATE_POWER_OFF, 402 MT76_STATE_SUSPEND, 403 MT76_STATE_ROC, 404 MT76_STATE_PM, 405 }; 406 407 struct mt76_hw_cap { 408 bool has_2ghz; 409 bool has_5ghz; 410 bool has_6ghz; 411 }; 412 413 #define MT_DRV_TXWI_NO_FREE BIT(0) 414 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) 415 #define MT_DRV_SW_RX_AIRTIME BIT(2) 416 #define MT_DRV_RX_DMA_HDR BIT(3) 417 #define MT_DRV_HW_MGMT_TXQ BIT(4) 418 419 struct mt76_driver_ops { 420 u32 drv_flags; 421 u32 survey_flags; 422 u16 txwi_size; 423 u16 token_size; 424 u8 mcs_rates; 425 426 void (*update_survey)(struct mt76_phy *phy); 427 428 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, 429 enum mt76_txq_id qid, struct mt76_wcid *wcid, 430 struct ieee80211_sta *sta, 431 struct mt76_tx_info *tx_info); 432 433 void (*tx_complete_skb)(struct mt76_dev *dev, 434 struct mt76_queue_entry *e); 435 436 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); 437 438 bool (*rx_check)(struct mt76_dev *dev, void *data, int len); 439 440 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, 441 struct sk_buff *skb); 442 443 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 444 445 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 446 bool ps); 447 448 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, 449 struct ieee80211_sta *sta); 450 451 void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif, 452 struct ieee80211_sta *sta); 453 454 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, 455 struct ieee80211_sta *sta); 456 }; 457 458 struct mt76_channel_state { 459 u64 cc_active; 460 u64 cc_busy; 461 u64 cc_rx; 462 u64 cc_bss_rx; 463 u64 cc_tx; 464 465 s8 noise; 466 }; 467 468 struct mt76_sband { 469 struct ieee80211_supported_band sband; 470 struct mt76_channel_state *chan; 471 }; 472 473 /* addr req mask */ 474 #define MT_VEND_TYPE_EEPROM BIT(31) 475 #define MT_VEND_TYPE_CFG BIT(30) 476 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 477 478 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 479 enum mt_vendor_req { 480 MT_VEND_DEV_MODE = 0x1, 481 MT_VEND_WRITE = 0x2, 482 MT_VEND_POWER_ON = 0x4, 483 MT_VEND_MULTI_WRITE = 0x6, 484 MT_VEND_MULTI_READ = 0x7, 485 MT_VEND_READ_EEPROM = 0x9, 486 MT_VEND_WRITE_FCE = 0x42, 487 MT_VEND_WRITE_CFG = 0x46, 488 MT_VEND_READ_CFG = 0x47, 489 MT_VEND_READ_EXT = 0x63, 490 MT_VEND_WRITE_EXT = 0x66, 491 MT_VEND_FEATURE_SET = 0x91, 492 }; 493 494 enum mt76u_in_ep { 495 MT_EP_IN_PKT_RX, 496 MT_EP_IN_CMD_RESP, 497 __MT_EP_IN_MAX, 498 }; 499 500 enum mt76u_out_ep { 501 MT_EP_OUT_INBAND_CMD, 502 MT_EP_OUT_AC_BE, 503 MT_EP_OUT_AC_BK, 504 MT_EP_OUT_AC_VI, 505 MT_EP_OUT_AC_VO, 506 MT_EP_OUT_HCCA, 507 __MT_EP_OUT_MAX, 508 }; 509 510 struct mt76_mcu { 511 struct mutex mutex; 512 u32 msg_seq; 513 int timeout; 514 515 struct sk_buff_head res_q; 516 wait_queue_head_t wait; 517 }; 518 519 #define MT_TX_SG_MAX_SIZE 8 520 #define MT_RX_SG_MAX_SIZE 4 521 #define MT_NUM_TX_ENTRIES 256 522 #define MT_NUM_RX_ENTRIES 128 523 #define MCU_RESP_URB_SIZE 1024 524 struct mt76_usb { 525 struct mutex usb_ctrl_mtx; 526 u8 *data; 527 u16 data_len; 528 529 struct mt76_worker status_worker; 530 struct mt76_worker rx_worker; 531 532 struct work_struct stat_work; 533 534 u8 out_ep[__MT_EP_OUT_MAX]; 535 u8 in_ep[__MT_EP_IN_MAX]; 536 bool sg_en; 537 538 struct mt76u_mcu { 539 u8 *data; 540 /* multiple reads */ 541 struct mt76_reg_pair *rp; 542 int rp_len; 543 u32 base; 544 } mcu; 545 }; 546 547 #define MT76S_XMIT_BUF_SZ 0x3fe00 548 #define MT76S_NUM_TX_ENTRIES 256 549 #define MT76S_NUM_RX_ENTRIES 512 550 struct mt76_sdio { 551 struct mt76_worker txrx_worker; 552 struct mt76_worker status_worker; 553 struct mt76_worker net_worker; 554 555 struct work_struct stat_work; 556 557 u8 *xmit_buf; 558 u32 xmit_buf_sz; 559 560 struct sdio_func *func; 561 void *intr_data; 562 u8 hw_ver; 563 wait_queue_head_t wait; 564 565 struct { 566 int pse_data_quota; 567 int ple_data_quota; 568 int pse_mcu_quota; 569 int pse_page_size; 570 int deficit; 571 } sched; 572 573 int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr); 574 }; 575 576 struct mt76_mmio { 577 void __iomem *regs; 578 spinlock_t irq_lock; 579 u32 irqmask; 580 581 struct mtk_wed_device wed; 582 }; 583 584 struct mt76_rx_status { 585 union { 586 struct mt76_wcid *wcid; 587 u16 wcid_idx; 588 }; 589 590 u32 reorder_time; 591 592 u32 ampdu_ref; 593 u32 timestamp; 594 595 u8 iv[6]; 596 597 u8 phy_idx:2; 598 u8 aggr:1; 599 u8 qos_ctl; 600 u16 seqno; 601 602 u16 freq; 603 u32 flag; 604 u8 enc_flags; 605 u8 encoding:2, bw:3, he_ru:3; 606 u8 he_gi:2, he_dcm:1; 607 u8 amsdu:1, first_amsdu:1, last_amsdu:1; 608 u8 rate_idx; 609 u8 nss; 610 u8 band; 611 s8 signal; 612 u8 chains; 613 s8 chain_signal[IEEE80211_MAX_CHAINS]; 614 }; 615 616 struct mt76_freq_range_power { 617 const struct cfg80211_sar_freq_ranges *range; 618 s8 power; 619 }; 620 621 struct mt76_testmode_ops { 622 int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state); 623 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb, 624 enum mt76_testmode_state new_state); 625 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg); 626 }; 627 628 struct mt76_testmode_data { 629 enum mt76_testmode_state state; 630 631 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)]; 632 struct sk_buff *tx_skb; 633 634 u32 tx_count; 635 u16 tx_mpdu_len; 636 637 u8 tx_rate_mode; 638 u8 tx_rate_idx; 639 u8 tx_rate_nss; 640 u8 tx_rate_sgi; 641 u8 tx_rate_ldpc; 642 u8 tx_rate_stbc; 643 u8 tx_ltf; 644 645 u8 tx_antenna_mask; 646 u8 tx_spe_idx; 647 648 u8 tx_duty_cycle; 649 u32 tx_time; 650 u32 tx_ipg; 651 652 u32 freq_offset; 653 654 u8 tx_power[4]; 655 u8 tx_power_control; 656 657 u8 addr[3][ETH_ALEN]; 658 659 u32 tx_pending; 660 u32 tx_queued; 661 u16 tx_queued_limit; 662 u32 tx_done; 663 struct { 664 u64 packets[__MT_RXQ_MAX]; 665 u64 fcs_error[__MT_RXQ_MAX]; 666 } rx_stats; 667 }; 668 669 struct mt76_vif { 670 u8 idx; 671 u8 omac_idx; 672 u8 band_idx; 673 u8 wmm_idx; 674 u8 scan_seq_num; 675 u8 cipher; 676 }; 677 678 struct mt76_phy { 679 struct ieee80211_hw *hw; 680 struct mt76_dev *dev; 681 void *priv; 682 683 unsigned long state; 684 u8 band_idx; 685 686 struct mt76_queue *q_tx[__MT_TXQ_MAX]; 687 688 struct cfg80211_chan_def chandef; 689 struct ieee80211_channel *main_chan; 690 691 struct mt76_channel_state *chan_state; 692 enum mt76_dfs_state dfs_state; 693 ktime_t survey_time; 694 695 struct mt76_hw_cap cap; 696 struct mt76_sband sband_2g; 697 struct mt76_sband sband_5g; 698 struct mt76_sband sband_6g; 699 700 u8 macaddr[ETH_ALEN]; 701 702 int txpower_cur; 703 u8 antenna_mask; 704 u16 chainmask; 705 706 #ifdef CONFIG_NL80211_TESTMODE 707 struct mt76_testmode_data test; 708 #endif 709 710 struct delayed_work mac_work; 711 u8 mac_work_count; 712 713 struct { 714 struct sk_buff *head; 715 struct sk_buff **tail; 716 u16 seqno; 717 } rx_amsdu[__MT_RXQ_MAX]; 718 719 struct mt76_freq_range_power *frp; 720 }; 721 722 struct mt76_dev { 723 struct mt76_phy phy; /* must be first */ 724 struct mt76_phy *phys[__MT_MAX_BAND]; 725 726 struct ieee80211_hw *hw; 727 728 spinlock_t lock; 729 spinlock_t cc_lock; 730 731 u32 cur_cc_bss_rx; 732 733 struct mt76_rx_status rx_ampdu_status; 734 u32 rx_ampdu_len; 735 u32 rx_ampdu_ref; 736 737 struct mutex mutex; 738 739 const struct mt76_bus_ops *bus; 740 const struct mt76_driver_ops *drv; 741 const struct mt76_mcu_ops *mcu_ops; 742 struct device *dev; 743 struct device *dma_dev; 744 745 struct mt76_mcu mcu; 746 747 struct net_device napi_dev; 748 struct net_device tx_napi_dev; 749 spinlock_t rx_lock; 750 struct napi_struct napi[__MT_RXQ_MAX]; 751 struct sk_buff_head rx_skb[__MT_RXQ_MAX]; 752 753 struct list_head txwi_cache; 754 struct mt76_queue *q_mcu[__MT_MCUQ_MAX]; 755 struct mt76_queue q_rx[__MT_RXQ_MAX]; 756 const struct mt76_queue_ops *queue_ops; 757 int tx_dma_idx[4]; 758 759 struct mt76_worker tx_worker; 760 struct napi_struct tx_napi; 761 762 spinlock_t token_lock; 763 struct idr token; 764 u16 wed_token_count; 765 u16 token_count; 766 u16 token_size; 767 768 wait_queue_head_t tx_wait; 769 /* spinclock used to protect wcid pktid linked list */ 770 spinlock_t status_lock; 771 772 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 773 u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 774 775 u64 vif_mask; 776 777 struct mt76_wcid global_wcid; 778 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; 779 struct list_head wcid_list; 780 781 u32 rev; 782 783 u32 aggr_stats[32]; 784 785 struct tasklet_struct pre_tbtt_tasklet; 786 int beacon_int; 787 u8 beacon_mask; 788 789 struct debugfs_blob_wrapper eeprom; 790 struct debugfs_blob_wrapper otp; 791 792 char alpha2[3]; 793 enum nl80211_dfs_regions region; 794 795 u32 debugfs_reg; 796 797 struct led_classdev led_cdev; 798 char led_name[32]; 799 bool led_al; 800 u8 led_pin; 801 802 u8 csa_complete; 803 804 u32 rxfilter; 805 806 #ifdef CONFIG_NL80211_TESTMODE 807 const struct mt76_testmode_ops *test_ops; 808 struct { 809 const char *name; 810 u32 offset; 811 } test_mtd; 812 #endif 813 struct workqueue_struct *wq; 814 815 union { 816 struct mt76_mmio mmio; 817 struct mt76_usb usb; 818 struct mt76_sdio sdio; 819 }; 820 }; 821 822 struct mt76_power_limits { 823 s8 cck[4]; 824 s8 ofdm[8]; 825 s8 mcs[4][10]; 826 s8 ru[7][12]; 827 }; 828 829 struct mt76_ethtool_worker_info { 830 u64 *data; 831 int idx; 832 int initial_stat_idx; 833 int worker_stat_count; 834 int sta_count; 835 }; 836 837 #define CCK_RATE(_idx, _rate) { \ 838 .bitrate = _rate, \ 839 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ 840 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \ 841 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \ 842 } 843 844 #define OFDM_RATE(_idx, _rate) { \ 845 .bitrate = _rate, \ 846 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 847 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 848 } 849 850 extern struct ieee80211_rate mt76_rates[12]; 851 852 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) 853 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) 854 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) 855 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) 856 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) 857 858 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) 859 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) 860 861 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) 862 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) 863 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) 864 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) 865 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) 866 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) 867 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) 868 869 870 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) 871 #define __mt76_mcu_restart(dev, ...) (dev)->mcu_ops->mcu_restart((dev)) 872 873 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) 874 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) 875 876 #define mt76_get_field(_dev, _reg, _field) \ 877 FIELD_GET(_field, mt76_rr(dev, _reg)) 878 879 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 880 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 881 882 #define __mt76_rmw_field(_dev, _reg, _field, _val) \ 883 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 884 885 #define mt76_hw(dev) (dev)->mphy.hw 886 887 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 888 int timeout); 889 890 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) 891 892 bool __mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 893 int timeout); 894 895 #define mt76_poll_msec(dev, ...) __mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) 896 897 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); 898 void mt76_pci_disable_aspm(struct pci_dev *pdev); 899 900 static inline u16 mt76_chip(struct mt76_dev *dev) 901 { 902 return dev->rev >> 16; 903 } 904 905 static inline u16 mt76_rev(struct mt76_dev *dev) 906 { 907 return dev->rev & 0xffff; 908 } 909 910 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) 911 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) 912 913 #define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__) 914 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) 915 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) 916 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__) 917 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 918 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 919 #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__) 920 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 921 #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__) 922 923 #define mt76_for_each_q_rx(dev, i) \ 924 for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++) \ 925 if ((dev)->q_rx[i].ndesc) 926 927 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, 928 const struct ieee80211_ops *ops, 929 const struct mt76_driver_ops *drv_ops); 930 int mt76_register_device(struct mt76_dev *dev, bool vht, 931 struct ieee80211_rate *rates, int n_rates); 932 void mt76_unregister_device(struct mt76_dev *dev); 933 void mt76_free_device(struct mt76_dev *dev); 934 void mt76_unregister_phy(struct mt76_phy *phy); 935 936 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size, 937 const struct ieee80211_ops *ops, 938 u8 band_idx); 939 int mt76_register_phy(struct mt76_phy *phy, bool vht, 940 struct ieee80211_rate *rates, int n_rates); 941 942 struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy, 943 const struct file_operations *ops); 944 static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev) 945 { 946 return mt76_register_debugfs_fops(&dev->phy, NULL); 947 } 948 949 int mt76_queues_read(struct seq_file *s, void *data); 950 void mt76_seq_puts_array(struct seq_file *file, const char *str, 951 s8 *val, int len); 952 953 int mt76_eeprom_init(struct mt76_dev *dev, int len); 954 void mt76_eeprom_override(struct mt76_phy *phy); 955 int mt76_get_of_eeprom(struct mt76_dev *dev, void *data, int offset, int len); 956 957 struct mt76_queue * 958 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, 959 int ring_base, u32 flags); 960 u16 mt76_calculate_default_rate(struct mt76_phy *phy, int rateidx); 961 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx, 962 int n_desc, int ring_base, u32 flags) 963 { 964 struct mt76_queue *q; 965 966 q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base, flags); 967 if (IS_ERR(q)) 968 return PTR_ERR(q); 969 970 phy->q_tx[qid] = q; 971 972 return 0; 973 } 974 975 static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx, 976 int n_desc, int ring_base) 977 { 978 struct mt76_queue *q; 979 980 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base, 0); 981 if (IS_ERR(q)) 982 return PTR_ERR(q); 983 984 dev->q_mcu[qid] = q; 985 986 return 0; 987 } 988 989 static inline struct mt76_phy * 990 mt76_dev_phy(struct mt76_dev *dev, u8 phy_idx) 991 { 992 if ((phy_idx == MT_BAND1 && dev->phys[phy_idx]) || 993 (phy_idx == MT_BAND2 && dev->phys[phy_idx])) 994 return dev->phys[phy_idx]; 995 996 return &dev->phy; 997 } 998 999 static inline struct ieee80211_hw * 1000 mt76_phy_hw(struct mt76_dev *dev, u8 phy_idx) 1001 { 1002 return mt76_dev_phy(dev, phy_idx)->hw; 1003 } 1004 1005 static inline u8 * 1006 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) 1007 { 1008 return (u8 *)t - dev->drv->txwi_size; 1009 } 1010 1011 /* increment with wrap-around */ 1012 static inline int mt76_incr(int val, int size) 1013 { 1014 return (val + 1) & (size - 1); 1015 } 1016 1017 /* decrement with wrap-around */ 1018 static inline int mt76_decr(int val, int size) 1019 { 1020 return (val - 1) & (size - 1); 1021 } 1022 1023 u8 mt76_ac_to_hwq(u8 ac); 1024 1025 static inline struct ieee80211_txq * 1026 mtxq_to_txq(struct mt76_txq *mtxq) 1027 { 1028 void *ptr = mtxq; 1029 1030 return container_of(ptr, struct ieee80211_txq, drv_priv); 1031 } 1032 1033 static inline struct ieee80211_sta * 1034 wcid_to_sta(struct mt76_wcid *wcid) 1035 { 1036 void *ptr = wcid; 1037 1038 if (!wcid || !wcid->sta) 1039 return NULL; 1040 1041 return container_of(ptr, struct ieee80211_sta, drv_priv); 1042 } 1043 1044 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) 1045 { 1046 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > 1047 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); 1048 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); 1049 } 1050 1051 static inline void *mt76_skb_get_hdr(struct sk_buff *skb) 1052 { 1053 struct mt76_rx_status mstat; 1054 u8 *data = skb->data; 1055 1056 /* Alignment concerns */ 1057 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4); 1058 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4); 1059 1060 mstat = *((struct mt76_rx_status *)skb->cb); 1061 1062 if (mstat.flag & RX_FLAG_RADIOTAP_HE) 1063 data += sizeof(struct ieee80211_radiotap_he); 1064 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU) 1065 data += sizeof(struct ieee80211_radiotap_he_mu); 1066 1067 return data; 1068 } 1069 1070 static inline void mt76_insert_hdr_pad(struct sk_buff *skb) 1071 { 1072 int len = ieee80211_get_hdrlen_from_skb(skb); 1073 1074 if (len % 4 == 0) 1075 return; 1076 1077 skb_push(skb, 2); 1078 memmove(skb->data, skb->data + 2, len); 1079 1080 skb->data[len] = 0; 1081 skb->data[len + 1] = 0; 1082 } 1083 1084 static inline bool mt76_is_skb_pktid(u8 pktid) 1085 { 1086 if (pktid & MT_PACKET_ID_HAS_RATE) 1087 return false; 1088 1089 return pktid >= MT_PACKET_ID_FIRST; 1090 } 1091 1092 static inline u8 mt76_tx_power_nss_delta(u8 nss) 1093 { 1094 static const u8 nss_delta[4] = { 0, 6, 9, 12 }; 1095 1096 return nss_delta[nss - 1]; 1097 } 1098 1099 static inline bool mt76_testmode_enabled(struct mt76_phy *phy) 1100 { 1101 #ifdef CONFIG_NL80211_TESTMODE 1102 return phy->test.state != MT76_TM_STATE_OFF; 1103 #else 1104 return false; 1105 #endif 1106 } 1107 1108 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev, 1109 struct sk_buff *skb, 1110 struct ieee80211_hw **hw) 1111 { 1112 #ifdef CONFIG_NL80211_TESTMODE 1113 int i; 1114 1115 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) { 1116 struct mt76_phy *phy = dev->phys[i]; 1117 1118 if (phy && skb == phy->test.tx_skb) { 1119 *hw = dev->phys[i]->hw; 1120 return true; 1121 } 1122 } 1123 return false; 1124 #else 1125 return false; 1126 #endif 1127 } 1128 1129 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); 1130 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, 1131 struct mt76_wcid *wcid, struct sk_buff *skb); 1132 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); 1133 void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta, 1134 bool send_bar); 1135 void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb); 1136 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); 1137 void mt76_txq_schedule_all(struct mt76_phy *phy); 1138 void mt76_tx_worker_run(struct mt76_dev *dev); 1139 void mt76_tx_worker(struct mt76_worker *w); 1140 void mt76_release_buffered_frames(struct ieee80211_hw *hw, 1141 struct ieee80211_sta *sta, 1142 u16 tids, int nframes, 1143 enum ieee80211_frame_release_type reason, 1144 bool more_data); 1145 bool mt76_has_tx_pending(struct mt76_phy *phy); 1146 void mt76_set_channel(struct mt76_phy *phy); 1147 void mt76_update_survey(struct mt76_phy *phy); 1148 void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time); 1149 int mt76_get_survey(struct ieee80211_hw *hw, int idx, 1150 struct survey_info *survey); 1151 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht); 1152 1153 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, 1154 u16 ssn, u16 size); 1155 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); 1156 1157 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, 1158 struct ieee80211_key_conf *key); 1159 1160 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) 1161 __acquires(&dev->status_lock); 1162 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) 1163 __releases(&dev->status_lock); 1164 1165 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, 1166 struct sk_buff *skb); 1167 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, 1168 struct mt76_wcid *wcid, int pktid, 1169 struct sk_buff_head *list); 1170 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, 1171 struct sk_buff_head *list); 1172 void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb, 1173 struct list_head *free_list); 1174 static inline void 1175 mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb) 1176 { 1177 __mt76_tx_complete_skb(dev, wcid, skb, NULL); 1178 } 1179 1180 void mt76_tx_status_check(struct mt76_dev *dev, bool flush); 1181 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1182 struct ieee80211_sta *sta, 1183 enum ieee80211_sta_state old_state, 1184 enum ieee80211_sta_state new_state); 1185 void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif, 1186 struct ieee80211_sta *sta); 1187 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1188 struct ieee80211_sta *sta); 1189 1190 int mt76_get_min_avg_rssi(struct mt76_dev *dev, bool ext_phy); 1191 1192 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1193 int *dbm); 1194 int mt76_init_sar_power(struct ieee80211_hw *hw, 1195 const struct cfg80211_sar_specs *sar); 1196 int mt76_get_sar_power(struct mt76_phy *phy, 1197 struct ieee80211_channel *chan, 1198 int power); 1199 1200 void mt76_csa_check(struct mt76_dev *dev); 1201 void mt76_csa_finish(struct mt76_dev *dev); 1202 1203 int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); 1204 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); 1205 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); 1206 int mt76_get_rate(struct mt76_dev *dev, 1207 struct ieee80211_supported_band *sband, 1208 int idx, bool cck); 1209 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1210 const u8 *mac); 1211 void mt76_sw_scan_complete(struct ieee80211_hw *hw, 1212 struct ieee80211_vif *vif); 1213 enum mt76_dfs_state mt76_phy_dfs_state(struct mt76_phy *phy); 1214 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1215 void *data, int len); 1216 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb, 1217 struct netlink_callback *cb, void *data, int len); 1218 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state); 1219 int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len); 1220 1221 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable) 1222 { 1223 #ifdef CONFIG_NL80211_TESTMODE 1224 enum mt76_testmode_state state = MT76_TM_STATE_IDLE; 1225 1226 if (disable || phy->test.state == MT76_TM_STATE_OFF) 1227 state = MT76_TM_STATE_OFF; 1228 1229 mt76_testmode_set_state(phy, state); 1230 #endif 1231 } 1232 1233 1234 /* internal */ 1235 static inline struct ieee80211_hw * 1236 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) 1237 { 1238 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1239 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 1240 struct ieee80211_hw *hw = mt76_phy_hw(dev, phy_idx); 1241 1242 info->hw_queue &= ~MT_TX_HW_QUEUE_PHY; 1243 1244 return hw; 1245 } 1246 1247 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1248 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, 1249 struct napi_struct *napi); 1250 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, 1251 struct napi_struct *napi); 1252 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); 1253 void mt76_testmode_tx_pending(struct mt76_phy *phy); 1254 void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q, 1255 struct mt76_queue_entry *e); 1256 1257 /* usb */ 1258 static inline bool mt76u_urb_error(struct urb *urb) 1259 { 1260 return urb->status && 1261 urb->status != -ECONNRESET && 1262 urb->status != -ESHUTDOWN && 1263 urb->status != -ENOENT; 1264 } 1265 1266 /* Map hardware queues to usb endpoints */ 1267 static inline u8 q2ep(u8 qid) 1268 { 1269 /* TODO: take management packets to queue 5 */ 1270 return qid + 1; 1271 } 1272 1273 static inline int 1274 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, 1275 int timeout, int ep) 1276 { 1277 struct usb_interface *uintf = to_usb_interface(dev->dev); 1278 struct usb_device *udev = interface_to_usbdev(uintf); 1279 struct mt76_usb *usb = &dev->usb; 1280 unsigned int pipe; 1281 1282 if (actual_len) 1283 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]); 1284 else 1285 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]); 1286 1287 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); 1288 } 1289 1290 void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi, 1291 struct mt76_sta_stats *stats); 1292 int mt76_skb_adjust_pad(struct sk_buff *skb, int pad); 1293 int __mt76u_vendor_request(struct mt76_dev *dev, u8 req, u8 req_type, 1294 u16 val, u16 offset, void *buf, size_t len); 1295 int mt76u_vendor_request(struct mt76_dev *dev, u8 req, 1296 u8 req_type, u16 val, u16 offset, 1297 void *buf, size_t len); 1298 void mt76u_single_wr(struct mt76_dev *dev, const u8 req, 1299 const u16 offset, const u32 val); 1300 void mt76u_read_copy(struct mt76_dev *dev, u32 offset, 1301 void *data, int len); 1302 u32 ___mt76u_rr(struct mt76_dev *dev, u8 req, u8 req_type, u32 addr); 1303 void ___mt76u_wr(struct mt76_dev *dev, u8 req, u8 req_type, 1304 u32 addr, u32 val); 1305 int __mt76u_init(struct mt76_dev *dev, struct usb_interface *intf, 1306 struct mt76_bus_ops *ops); 1307 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf); 1308 int mt76u_alloc_mcu_queue(struct mt76_dev *dev); 1309 int mt76u_alloc_queues(struct mt76_dev *dev); 1310 void mt76u_stop_tx(struct mt76_dev *dev); 1311 void mt76u_stop_rx(struct mt76_dev *dev); 1312 int mt76u_resume_rx(struct mt76_dev *dev); 1313 void mt76u_queues_deinit(struct mt76_dev *dev); 1314 1315 int mt76s_init(struct mt76_dev *dev, struct sdio_func *func, 1316 const struct mt76_bus_ops *bus_ops); 1317 int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid); 1318 int mt76s_alloc_tx(struct mt76_dev *dev); 1319 void mt76s_deinit(struct mt76_dev *dev); 1320 void mt76s_sdio_irq(struct sdio_func *func); 1321 void mt76s_txrx_worker(struct mt76_sdio *sdio); 1322 bool mt76s_txqs_empty(struct mt76_dev *dev); 1323 int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func, 1324 int hw_ver); 1325 u32 mt76s_rr(struct mt76_dev *dev, u32 offset); 1326 void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val); 1327 u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 1328 u32 mt76s_read_pcr(struct mt76_dev *dev); 1329 void mt76s_write_copy(struct mt76_dev *dev, u32 offset, 1330 const void *data, int len); 1331 void mt76s_read_copy(struct mt76_dev *dev, u32 offset, 1332 void *data, int len); 1333 int mt76s_wr_rp(struct mt76_dev *dev, u32 base, 1334 const struct mt76_reg_pair *data, 1335 int len); 1336 int mt76s_rd_rp(struct mt76_dev *dev, u32 base, 1337 struct mt76_reg_pair *data, int len); 1338 1339 struct sk_buff * 1340 __mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1341 int len, int data_len, gfp_t gfp); 1342 static inline struct sk_buff * 1343 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1344 int data_len) 1345 { 1346 return __mt76_mcu_msg_alloc(dev, data, data_len, data_len, GFP_KERNEL); 1347 } 1348 1349 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); 1350 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, 1351 unsigned long expires); 1352 int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data, 1353 int len, bool wait_resp, struct sk_buff **ret); 1354 int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb, 1355 int cmd, bool wait_resp, struct sk_buff **ret); 1356 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1357 int len, int max_len); 1358 static inline int 1359 mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1360 int len) 1361 { 1362 int max_len = 4096 - dev->mcu_ops->headroom; 1363 1364 return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len); 1365 } 1366 1367 static inline int 1368 mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len, 1369 bool wait_resp) 1370 { 1371 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL); 1372 } 1373 1374 static inline int 1375 mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd, 1376 bool wait_resp) 1377 { 1378 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL); 1379 } 1380 1381 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); 1382 1383 s8 mt76_get_rate_power_limits(struct mt76_phy *phy, 1384 struct ieee80211_channel *chan, 1385 struct mt76_power_limits *dest, 1386 s8 target_power); 1387 1388 struct mt76_txwi_cache * 1389 mt76_token_release(struct mt76_dev *dev, int token, bool *wake); 1390 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi); 1391 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked); 1392 1393 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked) 1394 { 1395 spin_lock_bh(&dev->token_lock); 1396 __mt76_set_tx_blocked(dev, blocked); 1397 spin_unlock_bh(&dev->token_lock); 1398 } 1399 1400 static inline int 1401 mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi) 1402 { 1403 int token; 1404 1405 spin_lock_bh(&dev->token_lock); 1406 token = idr_alloc(&dev->token, *ptxwi, 0, dev->token_size, GFP_ATOMIC); 1407 spin_unlock_bh(&dev->token_lock); 1408 1409 return token; 1410 } 1411 1412 static inline struct mt76_txwi_cache * 1413 mt76_token_put(struct mt76_dev *dev, int token) 1414 { 1415 struct mt76_txwi_cache *txwi; 1416 1417 spin_lock_bh(&dev->token_lock); 1418 txwi = idr_remove(&dev->token, token); 1419 spin_unlock_bh(&dev->token_lock); 1420 1421 return txwi; 1422 } 1423 1424 static inline void mt76_packet_id_init(struct mt76_wcid *wcid) 1425 { 1426 INIT_LIST_HEAD(&wcid->list); 1427 idr_init(&wcid->pktid); 1428 } 1429 1430 static inline void 1431 mt76_packet_id_flush(struct mt76_dev *dev, struct mt76_wcid *wcid) 1432 { 1433 struct sk_buff_head list; 1434 1435 mt76_tx_status_lock(dev, &list); 1436 mt76_tx_status_skb_get(dev, wcid, -1, &list); 1437 mt76_tx_status_unlock(dev, &list); 1438 1439 idr_destroy(&wcid->pktid); 1440 } 1441 1442 #endif 1443