1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2008 Christian Lamparter <chunkeey@web.de>
4  *
5  * This driver is a port from stlc45xx:
6  *	Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
7  */
8 
9 #ifndef P54SPI_H
10 #define P54SPI_H
11 
12 #include <linux/mutex.h>
13 #include <linux/list.h>
14 #include <net/mac80211.h>
15 
16 #include "p54.h"
17 
18 /* Bit 15 is read/write bit; ON = READ, OFF = WRITE */
19 #define SPI_ADRS_READ_BIT_15		0x8000
20 
21 #define SPI_ADRS_ARM_INTERRUPTS		0x00
22 #define SPI_ADRS_ARM_INT_EN		0x04
23 
24 #define SPI_ADRS_HOST_INTERRUPTS	0x08
25 #define SPI_ADRS_HOST_INT_EN		0x0c
26 #define SPI_ADRS_HOST_INT_ACK		0x10
27 
28 #define SPI_ADRS_GEN_PURP_1		0x14
29 #define SPI_ADRS_GEN_PURP_2		0x18
30 
31 #define SPI_ADRS_DEV_CTRL_STAT		0x26    /* high word */
32 
33 #define SPI_ADRS_DMA_DATA		0x28
34 
35 #define SPI_ADRS_DMA_WRITE_CTRL		0x2c
36 #define SPI_ADRS_DMA_WRITE_LEN		0x2e
37 #define SPI_ADRS_DMA_WRITE_BASE		0x30
38 
39 #define SPI_ADRS_DMA_READ_CTRL		0x34
40 #define SPI_ADRS_DMA_READ_LEN		0x36
41 #define SPI_ADRS_DMA_READ_BASE		0x38
42 
43 #define SPI_CTRL_STAT_HOST_OVERRIDE	0x8000
44 #define SPI_CTRL_STAT_START_HALTED	0x4000
45 #define SPI_CTRL_STAT_RAM_BOOT		0x2000
46 #define SPI_CTRL_STAT_HOST_RESET	0x1000
47 #define SPI_CTRL_STAT_HOST_CPU_EN	0x0800
48 
49 #define SPI_DMA_WRITE_CTRL_ENABLE	0x0001
50 #define SPI_DMA_READ_CTRL_ENABLE	0x0001
51 #define HOST_ALLOWED			(1 << 7)
52 
53 #define SPI_TIMEOUT			100         /* msec */
54 
55 #define SPI_MAX_TX_PACKETS		32
56 
57 #define SPI_MAX_PACKET_SIZE		32767
58 
59 #define SPI_TARGET_INT_WAKEUP		0x00000001
60 #define SPI_TARGET_INT_SLEEP		0x00000002
61 #define SPI_TARGET_INT_RDDONE		0x00000004
62 
63 #define SPI_TARGET_INT_CTS		0x00004000
64 #define SPI_TARGET_INT_DR		0x00008000
65 
66 #define SPI_HOST_INT_READY		0x00000001
67 #define SPI_HOST_INT_WR_READY		0x00000002
68 #define SPI_HOST_INT_SW_UPDATE		0x00000004
69 #define SPI_HOST_INT_UPDATE		0x10000000
70 
71 /* clear to send */
72 #define SPI_HOST_INT_CR			0x00004000
73 
74 /* data ready */
75 #define SPI_HOST_INT_DR			0x00008000
76 
77 #define SPI_HOST_INTS_DEFAULT 						    \
78 	(SPI_HOST_INT_READY | SPI_HOST_INT_UPDATE | SPI_HOST_INT_SW_UPDATE)
79 
80 #define TARGET_BOOT_SLEEP 50
81 
82 struct p54s_dma_regs {
83 	__le16 cmd;
84 	__le16 len;
85 	__le32 addr;
86 } __packed;
87 
88 struct p54s_tx_info {
89 	struct list_head tx_list;
90 };
91 
92 struct p54s_priv {
93 	/* p54_common has to be the first entry */
94 	struct p54_common common;
95 	struct ieee80211_hw *hw;
96 	struct spi_device *spi;
97 
98 	struct work_struct work;
99 
100 	struct mutex mutex;
101 	struct completion fw_comp;
102 
103 	spinlock_t tx_lock;
104 
105 	/* protected by tx_lock */
106 	struct list_head tx_pending;
107 
108 	enum fw_state fw_state;
109 	const struct firmware *firmware;
110 };
111 
112 #endif /* P54SPI_H */
113