1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* Copyright (c) 2020 The Linux Foundation. All rights reserved. */ 3 4 #include <linux/msi.h> 5 #include <linux/pci.h> 6 #include <linux/of.h> 7 #include <linux/of_address.h> 8 #include <linux/ioport.h> 9 10 #include "core.h" 11 #include "debug.h" 12 #include "mhi.h" 13 #include "pci.h" 14 15 #define MHI_TIMEOUT_DEFAULT_MS 90000 16 17 static struct mhi_channel_config ath11k_mhi_channels_qca6390[] = { 18 { 19 .num = 0, 20 .name = "LOOPBACK", 21 .num_elements = 32, 22 .event_ring = 0, 23 .dir = DMA_TO_DEVICE, 24 .ee_mask = 0x4, 25 .pollcfg = 0, 26 .doorbell = MHI_DB_BRST_DISABLE, 27 .lpm_notify = false, 28 .offload_channel = false, 29 .doorbell_mode_switch = false, 30 .auto_queue = false, 31 }, 32 { 33 .num = 1, 34 .name = "LOOPBACK", 35 .num_elements = 32, 36 .event_ring = 0, 37 .dir = DMA_FROM_DEVICE, 38 .ee_mask = 0x4, 39 .pollcfg = 0, 40 .doorbell = MHI_DB_BRST_DISABLE, 41 .lpm_notify = false, 42 .offload_channel = false, 43 .doorbell_mode_switch = false, 44 .auto_queue = false, 45 }, 46 { 47 .num = 20, 48 .name = "IPCR", 49 .num_elements = 64, 50 .event_ring = 1, 51 .dir = DMA_TO_DEVICE, 52 .ee_mask = 0x4, 53 .pollcfg = 0, 54 .doorbell = MHI_DB_BRST_DISABLE, 55 .lpm_notify = false, 56 .offload_channel = false, 57 .doorbell_mode_switch = false, 58 .auto_queue = false, 59 }, 60 { 61 .num = 21, 62 .name = "IPCR", 63 .num_elements = 64, 64 .event_ring = 1, 65 .dir = DMA_FROM_DEVICE, 66 .ee_mask = 0x4, 67 .pollcfg = 0, 68 .doorbell = MHI_DB_BRST_DISABLE, 69 .lpm_notify = false, 70 .offload_channel = false, 71 .doorbell_mode_switch = false, 72 .auto_queue = true, 73 }, 74 }; 75 76 static struct mhi_event_config ath11k_mhi_events_qca6390[] = { 77 { 78 .num_elements = 32, 79 .irq_moderation_ms = 0, 80 .irq = 1, 81 .mode = MHI_DB_BRST_DISABLE, 82 .data_type = MHI_ER_CTRL, 83 .hardware_event = false, 84 .client_managed = false, 85 .offload_channel = false, 86 }, 87 { 88 .num_elements = 256, 89 .irq_moderation_ms = 1, 90 .irq = 2, 91 .mode = MHI_DB_BRST_DISABLE, 92 .priority = 1, 93 .hardware_event = false, 94 .client_managed = false, 95 .offload_channel = false, 96 }, 97 }; 98 99 static struct mhi_controller_config ath11k_mhi_config_qca6390 = { 100 .max_channels = 128, 101 .timeout_ms = 2000, 102 .use_bounce_buf = false, 103 .buf_len = 0, 104 .num_channels = ARRAY_SIZE(ath11k_mhi_channels_qca6390), 105 .ch_cfg = ath11k_mhi_channels_qca6390, 106 .num_events = ARRAY_SIZE(ath11k_mhi_events_qca6390), 107 .event_cfg = ath11k_mhi_events_qca6390, 108 }; 109 110 static struct mhi_channel_config ath11k_mhi_channels_qcn9074[] = { 111 { 112 .num = 0, 113 .name = "LOOPBACK", 114 .num_elements = 32, 115 .event_ring = 1, 116 .dir = DMA_TO_DEVICE, 117 .ee_mask = 0x14, 118 .pollcfg = 0, 119 .doorbell = MHI_DB_BRST_DISABLE, 120 .lpm_notify = false, 121 .offload_channel = false, 122 .doorbell_mode_switch = false, 123 .auto_queue = false, 124 }, 125 { 126 .num = 1, 127 .name = "LOOPBACK", 128 .num_elements = 32, 129 .event_ring = 1, 130 .dir = DMA_FROM_DEVICE, 131 .ee_mask = 0x14, 132 .pollcfg = 0, 133 .doorbell = MHI_DB_BRST_DISABLE, 134 .lpm_notify = false, 135 .offload_channel = false, 136 .doorbell_mode_switch = false, 137 .auto_queue = false, 138 }, 139 { 140 .num = 20, 141 .name = "IPCR", 142 .num_elements = 32, 143 .event_ring = 1, 144 .dir = DMA_TO_DEVICE, 145 .ee_mask = 0x14, 146 .pollcfg = 0, 147 .doorbell = MHI_DB_BRST_DISABLE, 148 .lpm_notify = false, 149 .offload_channel = false, 150 .doorbell_mode_switch = false, 151 .auto_queue = false, 152 }, 153 { 154 .num = 21, 155 .name = "IPCR", 156 .num_elements = 32, 157 .event_ring = 1, 158 .dir = DMA_FROM_DEVICE, 159 .ee_mask = 0x14, 160 .pollcfg = 0, 161 .doorbell = MHI_DB_BRST_DISABLE, 162 .lpm_notify = false, 163 .offload_channel = false, 164 .doorbell_mode_switch = false, 165 .auto_queue = true, 166 }, 167 }; 168 169 static struct mhi_event_config ath11k_mhi_events_qcn9074[] = { 170 { 171 .num_elements = 32, 172 .irq_moderation_ms = 0, 173 .irq = 1, 174 .data_type = MHI_ER_CTRL, 175 .mode = MHI_DB_BRST_DISABLE, 176 .hardware_event = false, 177 .client_managed = false, 178 .offload_channel = false, 179 }, 180 { 181 .num_elements = 256, 182 .irq_moderation_ms = 1, 183 .irq = 2, 184 .mode = MHI_DB_BRST_DISABLE, 185 .priority = 1, 186 .hardware_event = false, 187 .client_managed = false, 188 .offload_channel = false, 189 }, 190 }; 191 192 static struct mhi_controller_config ath11k_mhi_config_qcn9074 = { 193 .max_channels = 30, 194 .timeout_ms = 10000, 195 .use_bounce_buf = false, 196 .buf_len = 0, 197 .num_channels = ARRAY_SIZE(ath11k_mhi_channels_qcn9074), 198 .ch_cfg = ath11k_mhi_channels_qcn9074, 199 .num_events = ARRAY_SIZE(ath11k_mhi_events_qcn9074), 200 .event_cfg = ath11k_mhi_events_qcn9074, 201 }; 202 203 void ath11k_mhi_set_mhictrl_reset(struct ath11k_base *ab) 204 { 205 u32 val; 206 207 val = ath11k_pci_read32(ab, MHISTATUS); 208 209 ath11k_dbg(ab, ATH11K_DBG_PCI, "MHISTATUS 0x%x\n", val); 210 211 /* Observed on QCA6390 that after SOC_GLOBAL_RESET, MHISTATUS 212 * has SYSERR bit set and thus need to set MHICTRL_RESET 213 * to clear SYSERR. 214 */ 215 ath11k_pci_write32(ab, MHICTRL, MHICTRL_RESET_MASK); 216 217 mdelay(10); 218 } 219 220 static void ath11k_mhi_reset_txvecdb(struct ath11k_base *ab) 221 { 222 ath11k_pci_write32(ab, PCIE_TXVECDB, 0); 223 } 224 225 static void ath11k_mhi_reset_txvecstatus(struct ath11k_base *ab) 226 { 227 ath11k_pci_write32(ab, PCIE_TXVECSTATUS, 0); 228 } 229 230 static void ath11k_mhi_reset_rxvecdb(struct ath11k_base *ab) 231 { 232 ath11k_pci_write32(ab, PCIE_RXVECDB, 0); 233 } 234 235 static void ath11k_mhi_reset_rxvecstatus(struct ath11k_base *ab) 236 { 237 ath11k_pci_write32(ab, PCIE_RXVECSTATUS, 0); 238 } 239 240 void ath11k_mhi_clear_vector(struct ath11k_base *ab) 241 { 242 ath11k_mhi_reset_txvecdb(ab); 243 ath11k_mhi_reset_txvecstatus(ab); 244 ath11k_mhi_reset_rxvecdb(ab); 245 ath11k_mhi_reset_rxvecstatus(ab); 246 } 247 248 static int ath11k_mhi_get_msi(struct ath11k_pci *ab_pci) 249 { 250 struct ath11k_base *ab = ab_pci->ab; 251 u32 user_base_data, base_vector; 252 int ret, num_vectors, i; 253 int *irq; 254 unsigned int msi_data; 255 256 ret = ath11k_pci_get_user_msi_assignment(ab_pci, 257 "MHI", &num_vectors, 258 &user_base_data, &base_vector); 259 if (ret) 260 return ret; 261 262 ath11k_dbg(ab, ATH11K_DBG_PCI, "Number of assigned MSI for MHI is %d, base vector is %d\n", 263 num_vectors, base_vector); 264 265 irq = kcalloc(num_vectors, sizeof(int), GFP_KERNEL); 266 if (!irq) 267 return -ENOMEM; 268 269 for (i = 0; i < num_vectors; i++) { 270 msi_data = base_vector; 271 272 if (test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 273 msi_data += i; 274 275 irq[i] = ath11k_pci_get_msi_irq(ab->dev, 276 msi_data); 277 } 278 279 ab_pci->mhi_ctrl->irq = irq; 280 ab_pci->mhi_ctrl->nr_irqs = num_vectors; 281 282 return 0; 283 } 284 285 static int ath11k_mhi_op_runtime_get(struct mhi_controller *mhi_cntrl) 286 { 287 return 0; 288 } 289 290 static void ath11k_mhi_op_runtime_put(struct mhi_controller *mhi_cntrl) 291 { 292 } 293 294 static void ath11k_mhi_op_status_cb(struct mhi_controller *mhi_cntrl, 295 enum mhi_callback cb) 296 { 297 struct ath11k_base *ab = dev_get_drvdata(mhi_cntrl->cntrl_dev); 298 299 switch (cb) { 300 case MHI_CB_SYS_ERROR: 301 ath11k_warn(ab, "firmware crashed: MHI_CB_SYS_ERROR\n"); 302 break; 303 default: 304 break; 305 } 306 } 307 308 static int ath11k_mhi_op_read_reg(struct mhi_controller *mhi_cntrl, 309 void __iomem *addr, 310 u32 *out) 311 { 312 *out = readl(addr); 313 314 return 0; 315 } 316 317 static void ath11k_mhi_op_write_reg(struct mhi_controller *mhi_cntrl, 318 void __iomem *addr, 319 u32 val) 320 { 321 writel(val, addr); 322 } 323 324 static int ath11k_mhi_read_addr_from_dt(struct mhi_controller *mhi_ctrl) 325 { 326 struct device_node *np; 327 struct resource res; 328 int ret; 329 330 np = of_find_node_by_type(NULL, "memory"); 331 if (!np) 332 return -ENOENT; 333 334 ret = of_address_to_resource(np, 0, &res); 335 if (ret) 336 return ret; 337 338 mhi_ctrl->iova_start = res.start + 0x1000000; 339 mhi_ctrl->iova_stop = res.end; 340 341 return 0; 342 } 343 344 int ath11k_mhi_register(struct ath11k_pci *ab_pci) 345 { 346 struct ath11k_base *ab = ab_pci->ab; 347 struct mhi_controller *mhi_ctrl; 348 struct mhi_controller_config *ath11k_mhi_config; 349 int ret; 350 351 mhi_ctrl = mhi_alloc_controller(); 352 if (!mhi_ctrl) 353 return -ENOMEM; 354 355 ath11k_core_create_firmware_path(ab, ATH11K_AMSS_FILE, 356 ab_pci->amss_path, 357 sizeof(ab_pci->amss_path)); 358 359 ab_pci->mhi_ctrl = mhi_ctrl; 360 mhi_ctrl->cntrl_dev = ab->dev; 361 mhi_ctrl->fw_image = ab_pci->amss_path; 362 mhi_ctrl->regs = ab->mem; 363 mhi_ctrl->reg_len = ab->mem_len; 364 365 ret = ath11k_mhi_get_msi(ab_pci); 366 if (ret) { 367 ath11k_err(ab, "failed to get msi for mhi\n"); 368 mhi_free_controller(mhi_ctrl); 369 return ret; 370 } 371 372 if (!test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 373 mhi_ctrl->irq_flags = IRQF_SHARED | IRQF_NOBALANCING; 374 375 if (test_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags)) { 376 ret = ath11k_mhi_read_addr_from_dt(mhi_ctrl); 377 if (ret < 0) 378 return ret; 379 } else { 380 mhi_ctrl->iova_start = 0; 381 mhi_ctrl->iova_stop = 0xFFFFFFFF; 382 } 383 384 mhi_ctrl->sbl_size = SZ_512K; 385 mhi_ctrl->seg_len = SZ_512K; 386 mhi_ctrl->fbc_download = true; 387 mhi_ctrl->runtime_get = ath11k_mhi_op_runtime_get; 388 mhi_ctrl->runtime_put = ath11k_mhi_op_runtime_put; 389 mhi_ctrl->status_cb = ath11k_mhi_op_status_cb; 390 mhi_ctrl->read_reg = ath11k_mhi_op_read_reg; 391 mhi_ctrl->write_reg = ath11k_mhi_op_write_reg; 392 393 switch (ab->hw_rev) { 394 case ATH11K_HW_QCN9074_HW10: 395 ath11k_mhi_config = &ath11k_mhi_config_qcn9074; 396 break; 397 case ATH11K_HW_QCA6390_HW20: 398 case ATH11K_HW_WCN6855_HW20: 399 case ATH11K_HW_WCN6855_HW21: 400 ath11k_mhi_config = &ath11k_mhi_config_qca6390; 401 break; 402 default: 403 ath11k_err(ab, "failed assign mhi_config for unknown hw rev %d\n", 404 ab->hw_rev); 405 mhi_free_controller(mhi_ctrl); 406 return -EINVAL; 407 } 408 409 ret = mhi_register_controller(mhi_ctrl, ath11k_mhi_config); 410 if (ret) { 411 ath11k_err(ab, "failed to register to mhi bus, err = %d\n", ret); 412 mhi_free_controller(mhi_ctrl); 413 return ret; 414 } 415 416 return 0; 417 } 418 419 void ath11k_mhi_unregister(struct ath11k_pci *ab_pci) 420 { 421 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl; 422 423 mhi_unregister_controller(mhi_ctrl); 424 kfree(mhi_ctrl->irq); 425 mhi_free_controller(mhi_ctrl); 426 } 427 428 static char *ath11k_mhi_state_to_str(enum ath11k_mhi_state mhi_state) 429 { 430 switch (mhi_state) { 431 case ATH11K_MHI_INIT: 432 return "INIT"; 433 case ATH11K_MHI_DEINIT: 434 return "DEINIT"; 435 case ATH11K_MHI_POWER_ON: 436 return "POWER_ON"; 437 case ATH11K_MHI_POWER_OFF: 438 return "POWER_OFF"; 439 case ATH11K_MHI_FORCE_POWER_OFF: 440 return "FORCE_POWER_OFF"; 441 case ATH11K_MHI_SUSPEND: 442 return "SUSPEND"; 443 case ATH11K_MHI_RESUME: 444 return "RESUME"; 445 case ATH11K_MHI_TRIGGER_RDDM: 446 return "TRIGGER_RDDM"; 447 case ATH11K_MHI_RDDM_DONE: 448 return "RDDM_DONE"; 449 default: 450 return "UNKNOWN"; 451 } 452 }; 453 454 static void ath11k_mhi_set_state_bit(struct ath11k_pci *ab_pci, 455 enum ath11k_mhi_state mhi_state) 456 { 457 struct ath11k_base *ab = ab_pci->ab; 458 459 switch (mhi_state) { 460 case ATH11K_MHI_INIT: 461 set_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state); 462 break; 463 case ATH11K_MHI_DEINIT: 464 clear_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state); 465 break; 466 case ATH11K_MHI_POWER_ON: 467 set_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state); 468 break; 469 case ATH11K_MHI_POWER_OFF: 470 case ATH11K_MHI_FORCE_POWER_OFF: 471 clear_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state); 472 clear_bit(ATH11K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state); 473 clear_bit(ATH11K_MHI_RDDM_DONE, &ab_pci->mhi_state); 474 break; 475 case ATH11K_MHI_SUSPEND: 476 set_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state); 477 break; 478 case ATH11K_MHI_RESUME: 479 clear_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state); 480 break; 481 case ATH11K_MHI_TRIGGER_RDDM: 482 set_bit(ATH11K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state); 483 break; 484 case ATH11K_MHI_RDDM_DONE: 485 set_bit(ATH11K_MHI_RDDM_DONE, &ab_pci->mhi_state); 486 break; 487 default: 488 ath11k_err(ab, "unhandled mhi state (%d)\n", mhi_state); 489 } 490 } 491 492 static int ath11k_mhi_check_state_bit(struct ath11k_pci *ab_pci, 493 enum ath11k_mhi_state mhi_state) 494 { 495 struct ath11k_base *ab = ab_pci->ab; 496 497 switch (mhi_state) { 498 case ATH11K_MHI_INIT: 499 if (!test_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state)) 500 return 0; 501 break; 502 case ATH11K_MHI_DEINIT: 503 case ATH11K_MHI_POWER_ON: 504 if (test_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state) && 505 !test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state)) 506 return 0; 507 break; 508 case ATH11K_MHI_FORCE_POWER_OFF: 509 if (test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state)) 510 return 0; 511 break; 512 case ATH11K_MHI_POWER_OFF: 513 case ATH11K_MHI_SUSPEND: 514 if (test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state) && 515 !test_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state)) 516 return 0; 517 break; 518 case ATH11K_MHI_RESUME: 519 if (test_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state)) 520 return 0; 521 break; 522 case ATH11K_MHI_TRIGGER_RDDM: 523 if (test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state) && 524 !test_bit(ATH11K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state)) 525 return 0; 526 break; 527 case ATH11K_MHI_RDDM_DONE: 528 return 0; 529 default: 530 ath11k_err(ab, "unhandled mhi state: %s(%d)\n", 531 ath11k_mhi_state_to_str(mhi_state), mhi_state); 532 } 533 534 ath11k_err(ab, "failed to set mhi state %s(%d) in current mhi state (0x%lx)\n", 535 ath11k_mhi_state_to_str(mhi_state), mhi_state, 536 ab_pci->mhi_state); 537 538 return -EINVAL; 539 } 540 541 static int ath11k_mhi_set_state(struct ath11k_pci *ab_pci, 542 enum ath11k_mhi_state mhi_state) 543 { 544 struct ath11k_base *ab = ab_pci->ab; 545 int ret; 546 547 ret = ath11k_mhi_check_state_bit(ab_pci, mhi_state); 548 if (ret) 549 goto out; 550 551 ath11k_dbg(ab, ATH11K_DBG_PCI, "setting mhi state: %s(%d)\n", 552 ath11k_mhi_state_to_str(mhi_state), mhi_state); 553 554 switch (mhi_state) { 555 case ATH11K_MHI_INIT: 556 ret = mhi_prepare_for_power_up(ab_pci->mhi_ctrl); 557 break; 558 case ATH11K_MHI_DEINIT: 559 mhi_unprepare_after_power_down(ab_pci->mhi_ctrl); 560 ret = 0; 561 break; 562 case ATH11K_MHI_POWER_ON: 563 ret = mhi_async_power_up(ab_pci->mhi_ctrl); 564 break; 565 case ATH11K_MHI_POWER_OFF: 566 mhi_power_down(ab_pci->mhi_ctrl, true); 567 ret = 0; 568 break; 569 case ATH11K_MHI_FORCE_POWER_OFF: 570 mhi_power_down(ab_pci->mhi_ctrl, false); 571 ret = 0; 572 break; 573 case ATH11K_MHI_SUSPEND: 574 ret = mhi_pm_suspend(ab_pci->mhi_ctrl); 575 break; 576 case ATH11K_MHI_RESUME: 577 /* Do force MHI resume as some devices like QCA6390, WCN6855 578 * are not in M3 state but they are functional. So just ignore 579 * the MHI state while resuming. 580 */ 581 ret = mhi_pm_resume_force(ab_pci->mhi_ctrl); 582 break; 583 case ATH11K_MHI_TRIGGER_RDDM: 584 ret = mhi_force_rddm_mode(ab_pci->mhi_ctrl); 585 break; 586 case ATH11K_MHI_RDDM_DONE: 587 break; 588 default: 589 ath11k_err(ab, "unhandled MHI state (%d)\n", mhi_state); 590 ret = -EINVAL; 591 } 592 593 if (ret) 594 goto out; 595 596 ath11k_mhi_set_state_bit(ab_pci, mhi_state); 597 598 return 0; 599 600 out: 601 ath11k_err(ab, "failed to set mhi state: %s(%d)\n", 602 ath11k_mhi_state_to_str(mhi_state), mhi_state); 603 return ret; 604 } 605 606 int ath11k_mhi_start(struct ath11k_pci *ab_pci) 607 { 608 int ret; 609 610 ab_pci->mhi_ctrl->timeout_ms = MHI_TIMEOUT_DEFAULT_MS; 611 612 ret = ath11k_mhi_set_state(ab_pci, ATH11K_MHI_INIT); 613 if (ret) 614 goto out; 615 616 ret = ath11k_mhi_set_state(ab_pci, ATH11K_MHI_POWER_ON); 617 if (ret) 618 goto out; 619 620 return 0; 621 622 out: 623 return ret; 624 } 625 626 void ath11k_mhi_stop(struct ath11k_pci *ab_pci) 627 { 628 ath11k_mhi_set_state(ab_pci, ATH11K_MHI_POWER_OFF); 629 ath11k_mhi_set_state(ab_pci, ATH11K_MHI_DEINIT); 630 } 631 632 void ath11k_mhi_suspend(struct ath11k_pci *ab_pci) 633 { 634 ath11k_mhi_set_state(ab_pci, ATH11K_MHI_SUSPEND); 635 } 636 637 void ath11k_mhi_resume(struct ath11k_pci *ab_pci) 638 { 639 ath11k_mhi_set_state(ab_pci, ATH11K_MHI_RESUME); 640 } 641