1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* Copyright (c) 2020 The Linux Foundation. All rights reserved. */ 3 4 #include <linux/msi.h> 5 #include <linux/pci.h> 6 7 #include "core.h" 8 #include "debug.h" 9 #include "mhi.h" 10 11 #define MHI_TIMEOUT_DEFAULT_MS 90000 12 13 static struct mhi_channel_config ath11k_mhi_channels[] = { 14 { 15 .num = 0, 16 .name = "LOOPBACK", 17 .num_elements = 32, 18 .event_ring = 0, 19 .dir = DMA_TO_DEVICE, 20 .ee_mask = 0x4, 21 .pollcfg = 0, 22 .doorbell = MHI_DB_BRST_DISABLE, 23 .lpm_notify = false, 24 .offload_channel = false, 25 .doorbell_mode_switch = false, 26 .auto_queue = false, 27 }, 28 { 29 .num = 1, 30 .name = "LOOPBACK", 31 .num_elements = 32, 32 .event_ring = 0, 33 .dir = DMA_FROM_DEVICE, 34 .ee_mask = 0x4, 35 .pollcfg = 0, 36 .doorbell = MHI_DB_BRST_DISABLE, 37 .lpm_notify = false, 38 .offload_channel = false, 39 .doorbell_mode_switch = false, 40 .auto_queue = false, 41 }, 42 { 43 .num = 20, 44 .name = "IPCR", 45 .num_elements = 64, 46 .event_ring = 1, 47 .dir = DMA_TO_DEVICE, 48 .ee_mask = 0x4, 49 .pollcfg = 0, 50 .doorbell = MHI_DB_BRST_DISABLE, 51 .lpm_notify = false, 52 .offload_channel = false, 53 .doorbell_mode_switch = false, 54 .auto_queue = false, 55 }, 56 { 57 .num = 21, 58 .name = "IPCR", 59 .num_elements = 64, 60 .event_ring = 1, 61 .dir = DMA_FROM_DEVICE, 62 .ee_mask = 0x4, 63 .pollcfg = 0, 64 .doorbell = MHI_DB_BRST_DISABLE, 65 .lpm_notify = false, 66 .offload_channel = false, 67 .doorbell_mode_switch = false, 68 .auto_queue = true, 69 }, 70 }; 71 72 static struct mhi_event_config ath11k_mhi_events[] = { 73 { 74 .num_elements = 32, 75 .irq_moderation_ms = 0, 76 .irq = 1, 77 .mode = MHI_DB_BRST_DISABLE, 78 .data_type = MHI_ER_CTRL, 79 .hardware_event = false, 80 .client_managed = false, 81 .offload_channel = false, 82 }, 83 { 84 .num_elements = 256, 85 .irq_moderation_ms = 1, 86 .irq = 2, 87 .mode = MHI_DB_BRST_DISABLE, 88 .priority = 1, 89 .hardware_event = false, 90 .client_managed = false, 91 .offload_channel = false, 92 }, 93 }; 94 95 static struct mhi_controller_config ath11k_mhi_config = { 96 .max_channels = 128, 97 .timeout_ms = 2000, 98 .use_bounce_buf = false, 99 .buf_len = 0, 100 .num_channels = ARRAY_SIZE(ath11k_mhi_channels), 101 .ch_cfg = ath11k_mhi_channels, 102 .num_events = ARRAY_SIZE(ath11k_mhi_events), 103 .event_cfg = ath11k_mhi_events, 104 }; 105 106 void ath11k_mhi_set_mhictrl_reset(struct ath11k_base *ab) 107 { 108 u32 val; 109 110 val = ath11k_pci_read32(ab, MHISTATUS); 111 112 ath11k_dbg(ab, ATH11K_DBG_PCI, "MHISTATUS 0x%x\n", val); 113 114 /* Observed on QCA6390 that after SOC_GLOBAL_RESET, MHISTATUS 115 * has SYSERR bit set and thus need to set MHICTRL_RESET 116 * to clear SYSERR. 117 */ 118 ath11k_pci_write32(ab, MHICTRL, MHICTRL_RESET_MASK); 119 120 mdelay(10); 121 } 122 123 static void ath11k_mhi_reset_txvecdb(struct ath11k_base *ab) 124 { 125 ath11k_pci_write32(ab, PCIE_TXVECDB, 0); 126 } 127 128 static void ath11k_mhi_reset_txvecstatus(struct ath11k_base *ab) 129 { 130 ath11k_pci_write32(ab, PCIE_TXVECSTATUS, 0); 131 } 132 133 static void ath11k_mhi_reset_rxvecdb(struct ath11k_base *ab) 134 { 135 ath11k_pci_write32(ab, PCIE_RXVECDB, 0); 136 } 137 138 static void ath11k_mhi_reset_rxvecstatus(struct ath11k_base *ab) 139 { 140 ath11k_pci_write32(ab, PCIE_RXVECSTATUS, 0); 141 } 142 143 void ath11k_mhi_clear_vector(struct ath11k_base *ab) 144 { 145 ath11k_mhi_reset_txvecdb(ab); 146 ath11k_mhi_reset_txvecstatus(ab); 147 ath11k_mhi_reset_rxvecdb(ab); 148 ath11k_mhi_reset_rxvecstatus(ab); 149 } 150 151 static int ath11k_mhi_get_msi(struct ath11k_pci *ab_pci) 152 { 153 struct ath11k_base *ab = ab_pci->ab; 154 u32 user_base_data, base_vector; 155 int ret, num_vectors, i; 156 int *irq; 157 158 ret = ath11k_pci_get_user_msi_assignment(ab_pci, 159 "MHI", &num_vectors, 160 &user_base_data, &base_vector); 161 if (ret) 162 return ret; 163 164 ath11k_dbg(ab, ATH11K_DBG_PCI, "Number of assigned MSI for MHI is %d, base vector is %d\n", 165 num_vectors, base_vector); 166 167 irq = kcalloc(num_vectors, sizeof(int), GFP_KERNEL); 168 if (!irq) 169 return -ENOMEM; 170 171 for (i = 0; i < num_vectors; i++) 172 irq[i] = ath11k_pci_get_msi_irq(ab->dev, 173 base_vector + i); 174 175 ab_pci->mhi_ctrl->irq = irq; 176 ab_pci->mhi_ctrl->nr_irqs = num_vectors; 177 178 return 0; 179 } 180 181 static int ath11k_mhi_op_runtime_get(struct mhi_controller *mhi_cntrl) 182 { 183 return 0; 184 } 185 186 static void ath11k_mhi_op_runtime_put(struct mhi_controller *mhi_cntrl) 187 { 188 } 189 190 static void ath11k_mhi_op_status_cb(struct mhi_controller *mhi_cntrl, 191 enum mhi_callback cb) 192 { 193 } 194 195 static int ath11k_mhi_op_read_reg(struct mhi_controller *mhi_cntrl, 196 void __iomem *addr, 197 u32 *out) 198 { 199 *out = readl(addr); 200 201 return 0; 202 } 203 204 static void ath11k_mhi_op_write_reg(struct mhi_controller *mhi_cntrl, 205 void __iomem *addr, 206 u32 val) 207 { 208 writel(val, addr); 209 } 210 211 int ath11k_mhi_register(struct ath11k_pci *ab_pci) 212 { 213 struct ath11k_base *ab = ab_pci->ab; 214 struct mhi_controller *mhi_ctrl; 215 int ret; 216 217 mhi_ctrl = kzalloc(sizeof(*mhi_ctrl), GFP_KERNEL); 218 if (!mhi_ctrl) 219 return -ENOMEM; 220 221 ath11k_core_create_firmware_path(ab, ATH11K_AMSS_FILE, 222 ab_pci->amss_path, 223 sizeof(ab_pci->amss_path)); 224 225 ab_pci->mhi_ctrl = mhi_ctrl; 226 mhi_ctrl->cntrl_dev = ab->dev; 227 mhi_ctrl->fw_image = ab_pci->amss_path; 228 mhi_ctrl->regs = ab->mem; 229 230 ret = ath11k_mhi_get_msi(ab_pci); 231 if (ret) { 232 ath11k_err(ab, "failed to get msi for mhi\n"); 233 kfree(mhi_ctrl); 234 return ret; 235 } 236 237 mhi_ctrl->iova_start = 0; 238 mhi_ctrl->iova_stop = 0xffffffff; 239 mhi_ctrl->sbl_size = SZ_512K; 240 mhi_ctrl->seg_len = SZ_512K; 241 mhi_ctrl->fbc_download = true; 242 mhi_ctrl->runtime_get = ath11k_mhi_op_runtime_get; 243 mhi_ctrl->runtime_put = ath11k_mhi_op_runtime_put; 244 mhi_ctrl->status_cb = ath11k_mhi_op_status_cb; 245 mhi_ctrl->read_reg = ath11k_mhi_op_read_reg; 246 mhi_ctrl->write_reg = ath11k_mhi_op_write_reg; 247 248 ret = mhi_register_controller(mhi_ctrl, &ath11k_mhi_config); 249 if (ret) { 250 ath11k_err(ab, "failed to register to mhi bus, err = %d\n", ret); 251 kfree(mhi_ctrl); 252 return ret; 253 } 254 255 return 0; 256 } 257 258 void ath11k_mhi_unregister(struct ath11k_pci *ab_pci) 259 { 260 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl; 261 262 mhi_unregister_controller(mhi_ctrl); 263 kfree(mhi_ctrl->irq); 264 } 265 266 static char *ath11k_mhi_state_to_str(enum ath11k_mhi_state mhi_state) 267 { 268 switch (mhi_state) { 269 case ATH11K_MHI_INIT: 270 return "INIT"; 271 case ATH11K_MHI_DEINIT: 272 return "DEINIT"; 273 case ATH11K_MHI_POWER_ON: 274 return "POWER_ON"; 275 case ATH11K_MHI_POWER_OFF: 276 return "POWER_OFF"; 277 case ATH11K_MHI_FORCE_POWER_OFF: 278 return "FORCE_POWER_OFF"; 279 case ATH11K_MHI_SUSPEND: 280 return "SUSPEND"; 281 case ATH11K_MHI_RESUME: 282 return "RESUME"; 283 case ATH11K_MHI_TRIGGER_RDDM: 284 return "TRIGGER_RDDM"; 285 case ATH11K_MHI_RDDM_DONE: 286 return "RDDM_DONE"; 287 default: 288 return "UNKNOWN"; 289 } 290 }; 291 292 static void ath11k_mhi_set_state_bit(struct ath11k_pci *ab_pci, 293 enum ath11k_mhi_state mhi_state) 294 { 295 struct ath11k_base *ab = ab_pci->ab; 296 297 switch (mhi_state) { 298 case ATH11K_MHI_INIT: 299 set_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state); 300 break; 301 case ATH11K_MHI_DEINIT: 302 clear_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state); 303 break; 304 case ATH11K_MHI_POWER_ON: 305 set_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state); 306 break; 307 case ATH11K_MHI_POWER_OFF: 308 case ATH11K_MHI_FORCE_POWER_OFF: 309 clear_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state); 310 clear_bit(ATH11K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state); 311 clear_bit(ATH11K_MHI_RDDM_DONE, &ab_pci->mhi_state); 312 break; 313 case ATH11K_MHI_SUSPEND: 314 set_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state); 315 break; 316 case ATH11K_MHI_RESUME: 317 clear_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state); 318 break; 319 case ATH11K_MHI_TRIGGER_RDDM: 320 set_bit(ATH11K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state); 321 break; 322 case ATH11K_MHI_RDDM_DONE: 323 set_bit(ATH11K_MHI_RDDM_DONE, &ab_pci->mhi_state); 324 break; 325 default: 326 ath11k_err(ab, "unhandled mhi state (%d)\n", mhi_state); 327 } 328 } 329 330 static int ath11k_mhi_check_state_bit(struct ath11k_pci *ab_pci, 331 enum ath11k_mhi_state mhi_state) 332 { 333 struct ath11k_base *ab = ab_pci->ab; 334 335 switch (mhi_state) { 336 case ATH11K_MHI_INIT: 337 if (!test_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state)) 338 return 0; 339 break; 340 case ATH11K_MHI_DEINIT: 341 case ATH11K_MHI_POWER_ON: 342 if (test_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state) && 343 !test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state)) 344 return 0; 345 break; 346 case ATH11K_MHI_FORCE_POWER_OFF: 347 if (test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state)) 348 return 0; 349 break; 350 case ATH11K_MHI_POWER_OFF: 351 case ATH11K_MHI_SUSPEND: 352 if (test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state) && 353 !test_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state)) 354 return 0; 355 break; 356 case ATH11K_MHI_RESUME: 357 if (test_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state)) 358 return 0; 359 break; 360 case ATH11K_MHI_TRIGGER_RDDM: 361 if (test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state) && 362 !test_bit(ATH11K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state)) 363 return 0; 364 break; 365 case ATH11K_MHI_RDDM_DONE: 366 return 0; 367 default: 368 ath11k_err(ab, "unhandled mhi state: %s(%d)\n", 369 ath11k_mhi_state_to_str(mhi_state), mhi_state); 370 } 371 372 ath11k_err(ab, "failed to set mhi state %s(%d) in current mhi state (0x%lx)\n", 373 ath11k_mhi_state_to_str(mhi_state), mhi_state, 374 ab_pci->mhi_state); 375 376 return -EINVAL; 377 } 378 379 static int ath11k_mhi_set_state(struct ath11k_pci *ab_pci, 380 enum ath11k_mhi_state mhi_state) 381 { 382 struct ath11k_base *ab = ab_pci->ab; 383 int ret; 384 385 ret = ath11k_mhi_check_state_bit(ab_pci, mhi_state); 386 if (ret) 387 goto out; 388 389 ath11k_dbg(ab, ATH11K_DBG_PCI, "setting mhi state: %s(%d)\n", 390 ath11k_mhi_state_to_str(mhi_state), mhi_state); 391 392 switch (mhi_state) { 393 case ATH11K_MHI_INIT: 394 ret = mhi_prepare_for_power_up(ab_pci->mhi_ctrl); 395 break; 396 case ATH11K_MHI_DEINIT: 397 mhi_unprepare_after_power_down(ab_pci->mhi_ctrl); 398 ret = 0; 399 break; 400 case ATH11K_MHI_POWER_ON: 401 ret = mhi_async_power_up(ab_pci->mhi_ctrl); 402 break; 403 case ATH11K_MHI_POWER_OFF: 404 mhi_power_down(ab_pci->mhi_ctrl, true); 405 ret = 0; 406 break; 407 case ATH11K_MHI_FORCE_POWER_OFF: 408 mhi_power_down(ab_pci->mhi_ctrl, false); 409 ret = 0; 410 break; 411 case ATH11K_MHI_SUSPEND: 412 break; 413 case ATH11K_MHI_RESUME: 414 break; 415 case ATH11K_MHI_TRIGGER_RDDM: 416 ret = mhi_force_rddm_mode(ab_pci->mhi_ctrl); 417 break; 418 case ATH11K_MHI_RDDM_DONE: 419 break; 420 default: 421 ath11k_err(ab, "unhandled MHI state (%d)\n", mhi_state); 422 ret = -EINVAL; 423 } 424 425 if (ret) 426 goto out; 427 428 ath11k_mhi_set_state_bit(ab_pci, mhi_state); 429 430 return 0; 431 432 out: 433 ath11k_err(ab, "failed to set mhi state: %s(%d)\n", 434 ath11k_mhi_state_to_str(mhi_state), mhi_state); 435 return ret; 436 } 437 438 int ath11k_mhi_start(struct ath11k_pci *ab_pci) 439 { 440 int ret; 441 442 ab_pci->mhi_ctrl->timeout_ms = MHI_TIMEOUT_DEFAULT_MS; 443 444 ret = ath11k_mhi_set_state(ab_pci, ATH11K_MHI_INIT); 445 if (ret) 446 goto out; 447 448 ret = ath11k_mhi_set_state(ab_pci, ATH11K_MHI_POWER_ON); 449 if (ret) 450 goto out; 451 452 return 0; 453 454 out: 455 return ret; 456 } 457 458 void ath11k_mhi_stop(struct ath11k_pci *ab_pci) 459 { 460 ath11k_mhi_set_state(ab_pci, ATH11K_MHI_POWER_OFF); 461 ath11k_mhi_set_state(ab_pci, ATH11K_MHI_DEINIT); 462 } 463 464