1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* Copyright (c) 2020 The Linux Foundation. All rights reserved. */ 3 4 #include <linux/msi.h> 5 #include <linux/pci.h> 6 7 #include "core.h" 8 #include "debug.h" 9 #include "mhi.h" 10 11 #define MHI_TIMEOUT_DEFAULT_MS 90000 12 13 static struct mhi_channel_config ath11k_mhi_channels[] = { 14 { 15 .num = 0, 16 .name = "LOOPBACK", 17 .num_elements = 32, 18 .event_ring = 0, 19 .dir = DMA_TO_DEVICE, 20 .ee_mask = 0x4, 21 .pollcfg = 0, 22 .doorbell = MHI_DB_BRST_DISABLE, 23 .lpm_notify = false, 24 .offload_channel = false, 25 .doorbell_mode_switch = false, 26 .auto_queue = false, 27 }, 28 { 29 .num = 1, 30 .name = "LOOPBACK", 31 .num_elements = 32, 32 .event_ring = 0, 33 .dir = DMA_FROM_DEVICE, 34 .ee_mask = 0x4, 35 .pollcfg = 0, 36 .doorbell = MHI_DB_BRST_DISABLE, 37 .lpm_notify = false, 38 .offload_channel = false, 39 .doorbell_mode_switch = false, 40 .auto_queue = false, 41 }, 42 { 43 .num = 20, 44 .name = "IPCR", 45 .num_elements = 64, 46 .event_ring = 1, 47 .dir = DMA_TO_DEVICE, 48 .ee_mask = 0x4, 49 .pollcfg = 0, 50 .doorbell = MHI_DB_BRST_DISABLE, 51 .lpm_notify = false, 52 .offload_channel = false, 53 .doorbell_mode_switch = false, 54 .auto_queue = false, 55 }, 56 { 57 .num = 21, 58 .name = "IPCR", 59 .num_elements = 64, 60 .event_ring = 1, 61 .dir = DMA_FROM_DEVICE, 62 .ee_mask = 0x4, 63 .pollcfg = 0, 64 .doorbell = MHI_DB_BRST_DISABLE, 65 .lpm_notify = false, 66 .offload_channel = false, 67 .doorbell_mode_switch = false, 68 .auto_queue = true, 69 }, 70 }; 71 72 static struct mhi_event_config ath11k_mhi_events[] = { 73 { 74 .num_elements = 32, 75 .irq_moderation_ms = 0, 76 .irq = 1, 77 .mode = MHI_DB_BRST_DISABLE, 78 .data_type = MHI_ER_CTRL, 79 .hardware_event = false, 80 .client_managed = false, 81 .offload_channel = false, 82 }, 83 { 84 .num_elements = 256, 85 .irq_moderation_ms = 1, 86 .irq = 2, 87 .mode = MHI_DB_BRST_DISABLE, 88 .priority = 1, 89 .hardware_event = false, 90 .client_managed = false, 91 .offload_channel = false, 92 }, 93 }; 94 95 static struct mhi_controller_config ath11k_mhi_config = { 96 .max_channels = 128, 97 .timeout_ms = 2000, 98 .use_bounce_buf = false, 99 .buf_len = 0, 100 .num_channels = ARRAY_SIZE(ath11k_mhi_channels), 101 .ch_cfg = ath11k_mhi_channels, 102 .num_events = ARRAY_SIZE(ath11k_mhi_events), 103 .event_cfg = ath11k_mhi_events, 104 }; 105 106 void ath11k_mhi_set_mhictrl_reset(struct ath11k_base *ab) 107 { 108 u32 val; 109 110 val = ath11k_pci_read32(ab, MHISTATUS); 111 112 ath11k_dbg(ab, ATH11K_DBG_PCI, "MHISTATUS 0x%x\n", val); 113 114 /* Observed on QCA6390 that after SOC_GLOBAL_RESET, MHISTATUS 115 * has SYSERR bit set and thus need to set MHICTRL_RESET 116 * to clear SYSERR. 117 */ 118 ath11k_pci_write32(ab, MHICTRL, MHICTRL_RESET_MASK); 119 120 mdelay(10); 121 } 122 123 static void ath11k_mhi_reset_txvecdb(struct ath11k_base *ab) 124 { 125 ath11k_pci_write32(ab, PCIE_TXVECDB, 0); 126 } 127 128 static void ath11k_mhi_reset_txvecstatus(struct ath11k_base *ab) 129 { 130 ath11k_pci_write32(ab, PCIE_TXVECSTATUS, 0); 131 } 132 133 static void ath11k_mhi_reset_rxvecdb(struct ath11k_base *ab) 134 { 135 ath11k_pci_write32(ab, PCIE_RXVECDB, 0); 136 } 137 138 static void ath11k_mhi_reset_rxvecstatus(struct ath11k_base *ab) 139 { 140 ath11k_pci_write32(ab, PCIE_RXVECSTATUS, 0); 141 } 142 143 void ath11k_mhi_clear_vector(struct ath11k_base *ab) 144 { 145 ath11k_mhi_reset_txvecdb(ab); 146 ath11k_mhi_reset_txvecstatus(ab); 147 ath11k_mhi_reset_rxvecdb(ab); 148 ath11k_mhi_reset_rxvecstatus(ab); 149 } 150 151 static int ath11k_mhi_get_msi(struct ath11k_pci *ab_pci) 152 { 153 struct ath11k_base *ab = ab_pci->ab; 154 u32 user_base_data, base_vector; 155 int ret, num_vectors, i; 156 int *irq; 157 158 ret = ath11k_pci_get_user_msi_assignment(ab_pci, 159 "MHI", &num_vectors, 160 &user_base_data, &base_vector); 161 if (ret) 162 return ret; 163 164 ath11k_dbg(ab, ATH11K_DBG_PCI, "Number of assigned MSI for MHI is %d, base vector is %d\n", 165 num_vectors, base_vector); 166 167 irq = kcalloc(num_vectors, sizeof(int), GFP_KERNEL); 168 if (!irq) 169 return -ENOMEM; 170 171 for (i = 0; i < num_vectors; i++) 172 irq[i] = ath11k_pci_get_msi_irq(ab->dev, 173 base_vector + i); 174 175 ab_pci->mhi_ctrl->irq = irq; 176 ab_pci->mhi_ctrl->nr_irqs = num_vectors; 177 178 return 0; 179 } 180 181 static int ath11k_mhi_op_runtime_get(struct mhi_controller *mhi_cntrl) 182 { 183 return 0; 184 } 185 186 static void ath11k_mhi_op_runtime_put(struct mhi_controller *mhi_cntrl) 187 { 188 } 189 190 static void ath11k_mhi_op_status_cb(struct mhi_controller *mhi_cntrl, 191 enum mhi_callback cb) 192 { 193 struct ath11k_base *ab = dev_get_drvdata(mhi_cntrl->cntrl_dev); 194 195 switch (cb) { 196 case MHI_CB_SYS_ERROR: 197 ath11k_warn(ab, "firmware crashed: MHI_CB_SYS_ERROR\n"); 198 break; 199 default: 200 break; 201 } 202 } 203 204 static int ath11k_mhi_op_read_reg(struct mhi_controller *mhi_cntrl, 205 void __iomem *addr, 206 u32 *out) 207 { 208 *out = readl(addr); 209 210 return 0; 211 } 212 213 static void ath11k_mhi_op_write_reg(struct mhi_controller *mhi_cntrl, 214 void __iomem *addr, 215 u32 val) 216 { 217 writel(val, addr); 218 } 219 220 int ath11k_mhi_register(struct ath11k_pci *ab_pci) 221 { 222 struct ath11k_base *ab = ab_pci->ab; 223 struct mhi_controller *mhi_ctrl; 224 int ret; 225 226 mhi_ctrl = mhi_alloc_controller(); 227 if (!mhi_ctrl) 228 return -ENOMEM; 229 230 ath11k_core_create_firmware_path(ab, ATH11K_AMSS_FILE, 231 ab_pci->amss_path, 232 sizeof(ab_pci->amss_path)); 233 234 ab_pci->mhi_ctrl = mhi_ctrl; 235 mhi_ctrl->cntrl_dev = ab->dev; 236 mhi_ctrl->fw_image = ab_pci->amss_path; 237 mhi_ctrl->regs = ab->mem; 238 239 ret = ath11k_mhi_get_msi(ab_pci); 240 if (ret) { 241 ath11k_err(ab, "failed to get msi for mhi\n"); 242 mhi_free_controller(mhi_ctrl); 243 return ret; 244 } 245 246 mhi_ctrl->iova_start = 0; 247 mhi_ctrl->iova_stop = 0xffffffff; 248 mhi_ctrl->sbl_size = SZ_512K; 249 mhi_ctrl->seg_len = SZ_512K; 250 mhi_ctrl->fbc_download = true; 251 mhi_ctrl->runtime_get = ath11k_mhi_op_runtime_get; 252 mhi_ctrl->runtime_put = ath11k_mhi_op_runtime_put; 253 mhi_ctrl->status_cb = ath11k_mhi_op_status_cb; 254 mhi_ctrl->read_reg = ath11k_mhi_op_read_reg; 255 mhi_ctrl->write_reg = ath11k_mhi_op_write_reg; 256 257 ret = mhi_register_controller(mhi_ctrl, &ath11k_mhi_config); 258 if (ret) { 259 ath11k_err(ab, "failed to register to mhi bus, err = %d\n", ret); 260 mhi_free_controller(mhi_ctrl); 261 return ret; 262 } 263 264 return 0; 265 } 266 267 void ath11k_mhi_unregister(struct ath11k_pci *ab_pci) 268 { 269 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl; 270 271 mhi_unregister_controller(mhi_ctrl); 272 kfree(mhi_ctrl->irq); 273 mhi_free_controller(mhi_ctrl); 274 } 275 276 static char *ath11k_mhi_state_to_str(enum ath11k_mhi_state mhi_state) 277 { 278 switch (mhi_state) { 279 case ATH11K_MHI_INIT: 280 return "INIT"; 281 case ATH11K_MHI_DEINIT: 282 return "DEINIT"; 283 case ATH11K_MHI_POWER_ON: 284 return "POWER_ON"; 285 case ATH11K_MHI_POWER_OFF: 286 return "POWER_OFF"; 287 case ATH11K_MHI_FORCE_POWER_OFF: 288 return "FORCE_POWER_OFF"; 289 case ATH11K_MHI_SUSPEND: 290 return "SUSPEND"; 291 case ATH11K_MHI_RESUME: 292 return "RESUME"; 293 case ATH11K_MHI_TRIGGER_RDDM: 294 return "TRIGGER_RDDM"; 295 case ATH11K_MHI_RDDM_DONE: 296 return "RDDM_DONE"; 297 default: 298 return "UNKNOWN"; 299 } 300 }; 301 302 static void ath11k_mhi_set_state_bit(struct ath11k_pci *ab_pci, 303 enum ath11k_mhi_state mhi_state) 304 { 305 struct ath11k_base *ab = ab_pci->ab; 306 307 switch (mhi_state) { 308 case ATH11K_MHI_INIT: 309 set_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state); 310 break; 311 case ATH11K_MHI_DEINIT: 312 clear_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state); 313 break; 314 case ATH11K_MHI_POWER_ON: 315 set_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state); 316 break; 317 case ATH11K_MHI_POWER_OFF: 318 case ATH11K_MHI_FORCE_POWER_OFF: 319 clear_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state); 320 clear_bit(ATH11K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state); 321 clear_bit(ATH11K_MHI_RDDM_DONE, &ab_pci->mhi_state); 322 break; 323 case ATH11K_MHI_SUSPEND: 324 set_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state); 325 break; 326 case ATH11K_MHI_RESUME: 327 clear_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state); 328 break; 329 case ATH11K_MHI_TRIGGER_RDDM: 330 set_bit(ATH11K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state); 331 break; 332 case ATH11K_MHI_RDDM_DONE: 333 set_bit(ATH11K_MHI_RDDM_DONE, &ab_pci->mhi_state); 334 break; 335 default: 336 ath11k_err(ab, "unhandled mhi state (%d)\n", mhi_state); 337 } 338 } 339 340 static int ath11k_mhi_check_state_bit(struct ath11k_pci *ab_pci, 341 enum ath11k_mhi_state mhi_state) 342 { 343 struct ath11k_base *ab = ab_pci->ab; 344 345 switch (mhi_state) { 346 case ATH11K_MHI_INIT: 347 if (!test_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state)) 348 return 0; 349 break; 350 case ATH11K_MHI_DEINIT: 351 case ATH11K_MHI_POWER_ON: 352 if (test_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state) && 353 !test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state)) 354 return 0; 355 break; 356 case ATH11K_MHI_FORCE_POWER_OFF: 357 if (test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state)) 358 return 0; 359 break; 360 case ATH11K_MHI_POWER_OFF: 361 case ATH11K_MHI_SUSPEND: 362 if (test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state) && 363 !test_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state)) 364 return 0; 365 break; 366 case ATH11K_MHI_RESUME: 367 if (test_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state)) 368 return 0; 369 break; 370 case ATH11K_MHI_TRIGGER_RDDM: 371 if (test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state) && 372 !test_bit(ATH11K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state)) 373 return 0; 374 break; 375 case ATH11K_MHI_RDDM_DONE: 376 return 0; 377 default: 378 ath11k_err(ab, "unhandled mhi state: %s(%d)\n", 379 ath11k_mhi_state_to_str(mhi_state), mhi_state); 380 } 381 382 ath11k_err(ab, "failed to set mhi state %s(%d) in current mhi state (0x%lx)\n", 383 ath11k_mhi_state_to_str(mhi_state), mhi_state, 384 ab_pci->mhi_state); 385 386 return -EINVAL; 387 } 388 389 static int ath11k_mhi_set_state(struct ath11k_pci *ab_pci, 390 enum ath11k_mhi_state mhi_state) 391 { 392 struct ath11k_base *ab = ab_pci->ab; 393 int ret; 394 395 ret = ath11k_mhi_check_state_bit(ab_pci, mhi_state); 396 if (ret) 397 goto out; 398 399 ath11k_dbg(ab, ATH11K_DBG_PCI, "setting mhi state: %s(%d)\n", 400 ath11k_mhi_state_to_str(mhi_state), mhi_state); 401 402 switch (mhi_state) { 403 case ATH11K_MHI_INIT: 404 ret = mhi_prepare_for_power_up(ab_pci->mhi_ctrl); 405 break; 406 case ATH11K_MHI_DEINIT: 407 mhi_unprepare_after_power_down(ab_pci->mhi_ctrl); 408 ret = 0; 409 break; 410 case ATH11K_MHI_POWER_ON: 411 ret = mhi_async_power_up(ab_pci->mhi_ctrl); 412 break; 413 case ATH11K_MHI_POWER_OFF: 414 mhi_power_down(ab_pci->mhi_ctrl, true); 415 ret = 0; 416 break; 417 case ATH11K_MHI_FORCE_POWER_OFF: 418 mhi_power_down(ab_pci->mhi_ctrl, false); 419 ret = 0; 420 break; 421 case ATH11K_MHI_SUSPEND: 422 ret = mhi_pm_suspend(ab_pci->mhi_ctrl); 423 break; 424 case ATH11K_MHI_RESUME: 425 ret = mhi_pm_resume(ab_pci->mhi_ctrl); 426 break; 427 case ATH11K_MHI_TRIGGER_RDDM: 428 ret = mhi_force_rddm_mode(ab_pci->mhi_ctrl); 429 break; 430 case ATH11K_MHI_RDDM_DONE: 431 break; 432 default: 433 ath11k_err(ab, "unhandled MHI state (%d)\n", mhi_state); 434 ret = -EINVAL; 435 } 436 437 if (ret) 438 goto out; 439 440 ath11k_mhi_set_state_bit(ab_pci, mhi_state); 441 442 return 0; 443 444 out: 445 ath11k_err(ab, "failed to set mhi state: %s(%d)\n", 446 ath11k_mhi_state_to_str(mhi_state), mhi_state); 447 return ret; 448 } 449 450 int ath11k_mhi_start(struct ath11k_pci *ab_pci) 451 { 452 int ret; 453 454 ab_pci->mhi_ctrl->timeout_ms = MHI_TIMEOUT_DEFAULT_MS; 455 456 ret = ath11k_mhi_set_state(ab_pci, ATH11K_MHI_INIT); 457 if (ret) 458 goto out; 459 460 ret = ath11k_mhi_set_state(ab_pci, ATH11K_MHI_POWER_ON); 461 if (ret) 462 goto out; 463 464 return 0; 465 466 out: 467 return ret; 468 } 469 470 void ath11k_mhi_stop(struct ath11k_pci *ab_pci) 471 { 472 ath11k_mhi_set_state(ab_pci, ATH11K_MHI_POWER_OFF); 473 ath11k_mhi_set_state(ab_pci, ATH11K_MHI_DEINIT); 474 } 475 476 void ath11k_mhi_suspend(struct ath11k_pci *ab_pci) 477 { 478 ath11k_mhi_set_state(ab_pci, ATH11K_MHI_SUSPEND); 479 } 480 481 void ath11k_mhi_resume(struct ath11k_pci *ab_pci) 482 { 483 ath11k_mhi_set_state(ab_pci, ATH11K_MHI_RESUME); 484 } 485