1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef ATH_H 18 #define ATH_H 19 20 #include <linux/etherdevice.h> 21 #include <linux/skbuff.h> 22 #include <linux/if_ether.h> 23 #include <linux/spinlock.h> 24 #include <net/mac80211.h> 25 26 /* 27 * The key cache is used for h/w cipher state and also for 28 * tracking station state such as the current tx antenna. 29 * We also setup a mapping table between key cache slot indices 30 * and station state to short-circuit node lookups on rx. 31 * Different parts have different size key caches. We handle 32 * up to ATH_KEYMAX entries (could dynamically allocate state). 33 */ 34 #define ATH_KEYMAX 128 /* max key cache size we handle */ 35 36 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 37 38 struct ath_ani { 39 bool caldone; 40 unsigned int longcal_timer; 41 unsigned int shortcal_timer; 42 unsigned int resetcal_timer; 43 unsigned int checkani_timer; 44 struct timer_list timer; 45 }; 46 47 struct ath_cycle_counters { 48 u32 cycles; 49 u32 rx_busy; 50 u32 rx_frame; 51 u32 tx_frame; 52 }; 53 54 enum ath_device_state { 55 ATH_HW_UNAVAILABLE, 56 ATH_HW_INITIALIZED, 57 }; 58 59 enum ath_op_flags { 60 ATH_OP_INVALID, 61 ATH_OP_BEACONS, 62 ATH_OP_ANI_RUN, 63 ATH_OP_PRIM_STA_VIF, 64 ATH_OP_HW_RESET, 65 ATH_OP_SCANNING, 66 ATH_OP_MULTI_CHANNEL, 67 ATH_OP_WOW_ENABLED, 68 }; 69 70 enum ath_bus_type { 71 ATH_PCI, 72 ATH_AHB, 73 ATH_USB, 74 }; 75 76 struct reg_dmn_pair_mapping { 77 u16 reg_domain; 78 u16 reg_5ghz_ctl; 79 u16 reg_2ghz_ctl; 80 }; 81 82 struct ath_regulatory { 83 char alpha2[2]; 84 enum nl80211_dfs_regions region; 85 u16 country_code; 86 u16 max_power_level; 87 u16 current_rd; 88 int16_t power_limit; 89 struct reg_dmn_pair_mapping *regpair; 90 }; 91 92 enum ath_crypt_caps { 93 ATH_CRYPT_CAP_CIPHER_AESCCM = BIT(0), 94 ATH_CRYPT_CAP_MIC_COMBINED = BIT(1), 95 }; 96 97 struct ath_keyval { 98 u8 kv_type; 99 u8 kv_pad; 100 u16 kv_len; 101 u8 kv_val[16]; /* TK */ 102 u8 kv_mic[8]; /* Michael MIC key */ 103 u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware 104 * supports both MIC keys in the same key cache entry; 105 * in that case, kv_mic is the RX key) */ 106 }; 107 108 enum ath_cipher { 109 ATH_CIPHER_WEP = 0, 110 ATH_CIPHER_AES_OCB = 1, 111 ATH_CIPHER_AES_CCM = 2, 112 ATH_CIPHER_CKIP = 3, 113 ATH_CIPHER_TKIP = 4, 114 ATH_CIPHER_CLR = 5, 115 ATH_CIPHER_MIC = 127 116 }; 117 118 /** 119 * struct ath_ops - Register read/write operations 120 * 121 * @read: Register read 122 * @multi_read: Multiple register read 123 * @write: Register write 124 * @enable_write_buffer: Enable multiple register writes 125 * @write_flush: flush buffered register writes and disable buffering 126 */ 127 struct ath_ops { 128 unsigned int (*read)(void *, u32 reg_offset); 129 void (*multi_read)(void *, u32 *addr, u32 *val, u16 count); 130 void (*write)(void *, u32 val, u32 reg_offset); 131 void (*enable_write_buffer)(void *); 132 void (*write_flush) (void *); 133 u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr); 134 }; 135 136 struct ath_common; 137 struct ath_bus_ops; 138 139 struct ath_ps_ops { 140 void (*wakeup)(struct ath_common *common); 141 void (*restore)(struct ath_common *common); 142 }; 143 144 struct ath_common { 145 void *ah; 146 void *priv; 147 struct ieee80211_hw *hw; 148 int debug_mask; 149 enum ath_device_state state; 150 unsigned long op_flags; 151 152 struct ath_ani ani; 153 154 u16 cachelsz; 155 u16 curaid; 156 u8 macaddr[ETH_ALEN]; 157 u8 curbssid[ETH_ALEN] __aligned(2); 158 u8 bssidmask[ETH_ALEN]; 159 160 u32 rx_bufsize; 161 162 u32 keymax; 163 DECLARE_BITMAP(keymap, ATH_KEYMAX); 164 DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX); 165 DECLARE_BITMAP(ccmp_keymap, ATH_KEYMAX); 166 enum ath_crypt_caps crypt_caps; 167 168 unsigned int clockrate; 169 170 spinlock_t cc_lock; 171 struct ath_cycle_counters cc_ani; 172 struct ath_cycle_counters cc_survey; 173 174 struct ath_regulatory regulatory; 175 struct ath_regulatory reg_world_copy; 176 const struct ath_ops *ops; 177 const struct ath_bus_ops *bus_ops; 178 const struct ath_ps_ops *ps_ops; 179 180 bool btcoex_enabled; 181 bool disable_ani; 182 bool bt_ant_diversity; 183 184 int last_rssi; 185 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; 186 }; 187 188 static inline const struct ath_ps_ops *ath_ps_ops(struct ath_common *common) 189 { 190 return common->ps_ops; 191 } 192 193 struct sk_buff *ath_rxbuf_alloc(struct ath_common *common, 194 u32 len, 195 gfp_t gfp_mask); 196 bool ath_is_mybeacon(struct ath_common *common, struct ieee80211_hdr *hdr); 197 198 void ath_hw_setbssidmask(struct ath_common *common); 199 void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key); 200 int ath_key_config(struct ath_common *common, 201 struct ieee80211_vif *vif, 202 struct ieee80211_sta *sta, 203 struct ieee80211_key_conf *key); 204 bool ath_hw_keyreset(struct ath_common *common, u16 entry); 205 void ath_hw_cycle_counters_update(struct ath_common *common); 206 int32_t ath_hw_get_listen_time(struct ath_common *common); 207 208 __printf(3, 4) 209 void ath_printk(const char *level, const struct ath_common *common, 210 const char *fmt, ...); 211 212 #define ath_emerg(common, fmt, ...) \ 213 ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__) 214 #define ath_alert(common, fmt, ...) \ 215 ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__) 216 #define ath_crit(common, fmt, ...) \ 217 ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__) 218 #define ath_err(common, fmt, ...) \ 219 ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__) 220 #define ath_warn(common, fmt, ...) \ 221 ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__) 222 #define ath_notice(common, fmt, ...) \ 223 ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__) 224 #define ath_info(common, fmt, ...) \ 225 ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__) 226 227 /** 228 * enum ath_debug_level - atheros wireless debug level 229 * 230 * @ATH_DBG_RESET: reset processing 231 * @ATH_DBG_QUEUE: hardware queue management 232 * @ATH_DBG_EEPROM: eeprom processing 233 * @ATH_DBG_CALIBRATE: periodic calibration 234 * @ATH_DBG_INTERRUPT: interrupt processing 235 * @ATH_DBG_REGULATORY: regulatory processing 236 * @ATH_DBG_ANI: adaptive noise immunitive processing 237 * @ATH_DBG_XMIT: basic xmit operation 238 * @ATH_DBG_BEACON: beacon handling 239 * @ATH_DBG_CONFIG: configuration of the hardware 240 * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT 241 * @ATH_DBG_PS: power save processing 242 * @ATH_DBG_HWTIMER: hardware timer handling 243 * @ATH_DBG_BTCOEX: bluetooth coexistance 244 * @ATH_DBG_BSTUCK: stuck beacons 245 * @ATH_DBG_MCI: Message Coexistence Interface, a private protocol 246 * used exclusively for WLAN-BT coexistence starting from 247 * AR9462. 248 * @ATH_DBG_DFS: radar datection 249 * @ATH_DBG_WOW: Wake on Wireless 250 * @ATH_DBG_DYNACK: dynack handling 251 * @ATH_DBG_ANY: enable all debugging 252 * 253 * The debug level is used to control the amount and type of debugging output 254 * we want to see. Each driver has its own method for enabling debugging and 255 * modifying debug level states -- but this is typically done through a 256 * module parameter 'debug' along with a respective 'debug' debugfs file 257 * entry. 258 */ 259 enum ATH_DEBUG { 260 ATH_DBG_RESET = 0x00000001, 261 ATH_DBG_QUEUE = 0x00000002, 262 ATH_DBG_EEPROM = 0x00000004, 263 ATH_DBG_CALIBRATE = 0x00000008, 264 ATH_DBG_INTERRUPT = 0x00000010, 265 ATH_DBG_REGULATORY = 0x00000020, 266 ATH_DBG_ANI = 0x00000040, 267 ATH_DBG_XMIT = 0x00000080, 268 ATH_DBG_BEACON = 0x00000100, 269 ATH_DBG_CONFIG = 0x00000200, 270 ATH_DBG_FATAL = 0x00000400, 271 ATH_DBG_PS = 0x00000800, 272 ATH_DBG_BTCOEX = 0x00001000, 273 ATH_DBG_WMI = 0x00002000, 274 ATH_DBG_BSTUCK = 0x00004000, 275 ATH_DBG_MCI = 0x00008000, 276 ATH_DBG_DFS = 0x00010000, 277 ATH_DBG_WOW = 0x00020000, 278 ATH_DBG_CHAN_CTX = 0x00040000, 279 ATH_DBG_DYNACK = 0x00080000, 280 ATH_DBG_ANY = 0xffffffff 281 }; 282 283 #define ATH_DBG_DEFAULT (ATH_DBG_FATAL) 284 #define ATH_DBG_MAX_LEN 512 285 286 #ifdef CONFIG_ATH_DEBUG 287 288 #define ath_dbg(common, dbg_mask, fmt, ...) \ 289 do { \ 290 if ((common)->debug_mask & ATH_DBG_##dbg_mask) \ 291 ath_printk(KERN_DEBUG, common, fmt, ##__VA_ARGS__); \ 292 } while (0) 293 294 #define ATH_DBG_WARN(foo, arg...) WARN(foo, arg) 295 #define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo) 296 297 #else 298 299 static inline __attribute__ ((format (printf, 3, 4))) 300 void _ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask, 301 const char *fmt, ...) 302 { 303 } 304 #define ath_dbg(common, dbg_mask, fmt, ...) \ 305 _ath_dbg(common, ATH_DBG_##dbg_mask, fmt, ##__VA_ARGS__) 306 307 #define ATH_DBG_WARN(foo, arg...) do {} while (0) 308 #define ATH_DBG_WARN_ON_ONCE(foo) ({ \ 309 int __ret_warn_once = !!(foo); \ 310 unlikely(__ret_warn_once); \ 311 }) 312 313 #endif /* CONFIG_ATH_DEBUG */ 314 315 /** Returns string describing opmode, or NULL if unknown mode. */ 316 #ifdef CONFIG_ATH_DEBUG 317 const char *ath_opmode_to_string(enum nl80211_iftype opmode); 318 #else 319 static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode) 320 { 321 return "UNKNOWN"; 322 } 323 #endif 324 325 #endif /* ATH_H */ 326