1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef ATH_H 18 #define ATH_H 19 20 #include <linux/etherdevice.h> 21 #include <linux/skbuff.h> 22 #include <linux/if_ether.h> 23 #include <linux/spinlock.h> 24 #include <net/mac80211.h> 25 26 /* 27 * The key cache is used for h/w cipher state and also for 28 * tracking station state such as the current tx antenna. 29 * We also setup a mapping table between key cache slot indices 30 * and station state to short-circuit node lookups on rx. 31 * Different parts have different size key caches. We handle 32 * up to ATH_KEYMAX entries (could dynamically allocate state). 33 */ 34 #define ATH_KEYMAX 128 /* max key cache size we handle */ 35 36 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 37 38 struct ath_ani { 39 bool caldone; 40 unsigned int longcal_timer; 41 unsigned int shortcal_timer; 42 unsigned int resetcal_timer; 43 unsigned int checkani_timer; 44 struct timer_list timer; 45 }; 46 47 struct ath_cycle_counters { 48 u32 cycles; 49 u32 rx_busy; 50 u32 rx_frame; 51 u32 tx_frame; 52 }; 53 54 enum ath_device_state { 55 ATH_HW_UNAVAILABLE, 56 ATH_HW_INITIALIZED, 57 }; 58 59 enum ath_op_flags { 60 ATH_OP_INVALID, 61 ATH_OP_BEACONS, 62 ATH_OP_ANI_RUN, 63 ATH_OP_PRIM_STA_VIF, 64 ATH_OP_HW_RESET, 65 ATH_OP_SCANNING, 66 ATH_OP_MULTI_CHANNEL, 67 }; 68 69 enum ath_bus_type { 70 ATH_PCI, 71 ATH_AHB, 72 ATH_USB, 73 }; 74 75 struct reg_dmn_pair_mapping { 76 u16 reg_domain; 77 u16 reg_5ghz_ctl; 78 u16 reg_2ghz_ctl; 79 }; 80 81 struct ath_regulatory { 82 char alpha2[2]; 83 enum nl80211_dfs_regions region; 84 u16 country_code; 85 u16 max_power_level; 86 u16 current_rd; 87 int16_t power_limit; 88 struct reg_dmn_pair_mapping *regpair; 89 }; 90 91 enum ath_crypt_caps { 92 ATH_CRYPT_CAP_CIPHER_AESCCM = BIT(0), 93 ATH_CRYPT_CAP_MIC_COMBINED = BIT(1), 94 }; 95 96 struct ath_keyval { 97 u8 kv_type; 98 u8 kv_pad; 99 u16 kv_len; 100 u8 kv_val[16]; /* TK */ 101 u8 kv_mic[8]; /* Michael MIC key */ 102 u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware 103 * supports both MIC keys in the same key cache entry; 104 * in that case, kv_mic is the RX key) */ 105 }; 106 107 enum ath_cipher { 108 ATH_CIPHER_WEP = 0, 109 ATH_CIPHER_AES_OCB = 1, 110 ATH_CIPHER_AES_CCM = 2, 111 ATH_CIPHER_CKIP = 3, 112 ATH_CIPHER_TKIP = 4, 113 ATH_CIPHER_CLR = 5, 114 ATH_CIPHER_MIC = 127 115 }; 116 117 /** 118 * struct ath_ops - Register read/write operations 119 * 120 * @read: Register read 121 * @multi_read: Multiple register read 122 * @write: Register write 123 * @enable_write_buffer: Enable multiple register writes 124 * @write_flush: flush buffered register writes and disable buffering 125 */ 126 struct ath_ops { 127 unsigned int (*read)(void *, u32 reg_offset); 128 void (*multi_read)(void *, u32 *addr, u32 *val, u16 count); 129 void (*write)(void *, u32 val, u32 reg_offset); 130 void (*enable_write_buffer)(void *); 131 void (*write_flush) (void *); 132 u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr); 133 }; 134 135 struct ath_common; 136 struct ath_bus_ops; 137 138 struct ath_ps_ops { 139 void (*wakeup)(struct ath_common *common); 140 void (*restore)(struct ath_common *common); 141 }; 142 143 struct ath_common { 144 void *ah; 145 void *priv; 146 struct ieee80211_hw *hw; 147 int debug_mask; 148 enum ath_device_state state; 149 unsigned long op_flags; 150 151 struct ath_ani ani; 152 153 u16 cachelsz; 154 u16 curaid; 155 u8 macaddr[ETH_ALEN]; 156 u8 curbssid[ETH_ALEN] __aligned(2); 157 u8 bssidmask[ETH_ALEN]; 158 159 u32 rx_bufsize; 160 161 u32 keymax; 162 DECLARE_BITMAP(keymap, ATH_KEYMAX); 163 DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX); 164 DECLARE_BITMAP(ccmp_keymap, ATH_KEYMAX); 165 enum ath_crypt_caps crypt_caps; 166 167 unsigned int clockrate; 168 169 spinlock_t cc_lock; 170 struct ath_cycle_counters cc_ani; 171 struct ath_cycle_counters cc_survey; 172 173 struct ath_regulatory regulatory; 174 struct ath_regulatory reg_world_copy; 175 const struct ath_ops *ops; 176 const struct ath_bus_ops *bus_ops; 177 const struct ath_ps_ops *ps_ops; 178 179 bool btcoex_enabled; 180 bool disable_ani; 181 bool bt_ant_diversity; 182 183 int last_rssi; 184 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; 185 }; 186 187 static inline const struct ath_ps_ops *ath_ps_ops(struct ath_common *common) 188 { 189 return common->ps_ops; 190 } 191 192 struct sk_buff *ath_rxbuf_alloc(struct ath_common *common, 193 u32 len, 194 gfp_t gfp_mask); 195 bool ath_is_mybeacon(struct ath_common *common, struct ieee80211_hdr *hdr); 196 197 void ath_hw_setbssidmask(struct ath_common *common); 198 void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key); 199 int ath_key_config(struct ath_common *common, 200 struct ieee80211_vif *vif, 201 struct ieee80211_sta *sta, 202 struct ieee80211_key_conf *key); 203 bool ath_hw_keyreset(struct ath_common *common, u16 entry); 204 void ath_hw_cycle_counters_update(struct ath_common *common); 205 int32_t ath_hw_get_listen_time(struct ath_common *common); 206 207 __printf(3, 4) 208 void ath_printk(const char *level, const struct ath_common *common, 209 const char *fmt, ...); 210 211 #define ath_emerg(common, fmt, ...) \ 212 ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__) 213 #define ath_alert(common, fmt, ...) \ 214 ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__) 215 #define ath_crit(common, fmt, ...) \ 216 ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__) 217 #define ath_err(common, fmt, ...) \ 218 ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__) 219 #define ath_warn(common, fmt, ...) \ 220 ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__) 221 #define ath_notice(common, fmt, ...) \ 222 ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__) 223 #define ath_info(common, fmt, ...) \ 224 ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__) 225 226 /** 227 * enum ath_debug_level - atheros wireless debug level 228 * 229 * @ATH_DBG_RESET: reset processing 230 * @ATH_DBG_QUEUE: hardware queue management 231 * @ATH_DBG_EEPROM: eeprom processing 232 * @ATH_DBG_CALIBRATE: periodic calibration 233 * @ATH_DBG_INTERRUPT: interrupt processing 234 * @ATH_DBG_REGULATORY: regulatory processing 235 * @ATH_DBG_ANI: adaptive noise immunitive processing 236 * @ATH_DBG_XMIT: basic xmit operation 237 * @ATH_DBG_BEACON: beacon handling 238 * @ATH_DBG_CONFIG: configuration of the hardware 239 * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT 240 * @ATH_DBG_PS: power save processing 241 * @ATH_DBG_HWTIMER: hardware timer handling 242 * @ATH_DBG_BTCOEX: bluetooth coexistance 243 * @ATH_DBG_BSTUCK: stuck beacons 244 * @ATH_DBG_MCI: Message Coexistence Interface, a private protocol 245 * used exclusively for WLAN-BT coexistence starting from 246 * AR9462. 247 * @ATH_DBG_DFS: radar datection 248 * @ATH_DBG_WOW: Wake on Wireless 249 * @ATH_DBG_DYNACK: dynack handling 250 * @ATH_DBG_ANY: enable all debugging 251 * 252 * The debug level is used to control the amount and type of debugging output 253 * we want to see. Each driver has its own method for enabling debugging and 254 * modifying debug level states -- but this is typically done through a 255 * module parameter 'debug' along with a respective 'debug' debugfs file 256 * entry. 257 */ 258 enum ATH_DEBUG { 259 ATH_DBG_RESET = 0x00000001, 260 ATH_DBG_QUEUE = 0x00000002, 261 ATH_DBG_EEPROM = 0x00000004, 262 ATH_DBG_CALIBRATE = 0x00000008, 263 ATH_DBG_INTERRUPT = 0x00000010, 264 ATH_DBG_REGULATORY = 0x00000020, 265 ATH_DBG_ANI = 0x00000040, 266 ATH_DBG_XMIT = 0x00000080, 267 ATH_DBG_BEACON = 0x00000100, 268 ATH_DBG_CONFIG = 0x00000200, 269 ATH_DBG_FATAL = 0x00000400, 270 ATH_DBG_PS = 0x00000800, 271 ATH_DBG_BTCOEX = 0x00001000, 272 ATH_DBG_WMI = 0x00002000, 273 ATH_DBG_BSTUCK = 0x00004000, 274 ATH_DBG_MCI = 0x00008000, 275 ATH_DBG_DFS = 0x00010000, 276 ATH_DBG_WOW = 0x00020000, 277 ATH_DBG_CHAN_CTX = 0x00040000, 278 ATH_DBG_DYNACK = 0x00080000, 279 ATH_DBG_ANY = 0xffffffff 280 }; 281 282 #define ATH_DBG_DEFAULT (ATH_DBG_FATAL) 283 #define ATH_DBG_MAX_LEN 512 284 285 #ifdef CONFIG_ATH_DEBUG 286 287 #define ath_dbg(common, dbg_mask, fmt, ...) \ 288 do { \ 289 if ((common)->debug_mask & ATH_DBG_##dbg_mask) \ 290 ath_printk(KERN_DEBUG, common, fmt, ##__VA_ARGS__); \ 291 } while (0) 292 293 #define ATH_DBG_WARN(foo, arg...) WARN(foo, arg) 294 #define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo) 295 296 #else 297 298 static inline __attribute__ ((format (printf, 3, 4))) 299 void _ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask, 300 const char *fmt, ...) 301 { 302 } 303 #define ath_dbg(common, dbg_mask, fmt, ...) \ 304 _ath_dbg(common, ATH_DBG_##dbg_mask, fmt, ##__VA_ARGS__) 305 306 #define ATH_DBG_WARN(foo, arg...) do {} while (0) 307 #define ATH_DBG_WARN_ON_ONCE(foo) ({ \ 308 int __ret_warn_once = !!(foo); \ 309 unlikely(__ret_warn_once); \ 310 }) 311 312 #endif /* CONFIG_ATH_DEBUG */ 313 314 /** Returns string describing opmode, or NULL if unknown mode. */ 315 #ifdef CONFIG_ATH_DEBUG 316 const char *ath_opmode_to_string(enum nl80211_iftype opmode); 317 #else 318 static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode) 319 { 320 return "UNKNOWN"; 321 } 322 #endif 323 324 #endif /* ATH_H */ 325