1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef ATH_H 18 #define ATH_H 19 20 #include <linux/etherdevice.h> 21 #include <linux/skbuff.h> 22 #include <linux/if_ether.h> 23 #include <linux/spinlock.h> 24 #include <net/mac80211.h> 25 26 /* 27 * The key cache is used for h/w cipher state and also for 28 * tracking station state such as the current tx antenna. 29 * We also setup a mapping table between key cache slot indices 30 * and station state to short-circuit node lookups on rx. 31 * Different parts have different size key caches. We handle 32 * up to ATH_KEYMAX entries (could dynamically allocate state). 33 */ 34 #define ATH_KEYMAX 128 /* max key cache size we handle */ 35 36 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 37 38 struct ath_ani { 39 bool caldone; 40 unsigned int longcal_timer; 41 unsigned int shortcal_timer; 42 unsigned int resetcal_timer; 43 unsigned int checkani_timer; 44 struct timer_list timer; 45 }; 46 47 struct ath_cycle_counters { 48 u32 cycles; 49 u32 rx_busy; 50 u32 rx_frame; 51 u32 tx_frame; 52 }; 53 54 enum ath_device_state { 55 ATH_HW_UNAVAILABLE, 56 ATH_HW_INITIALIZED, 57 }; 58 59 enum ath_bus_type { 60 ATH_PCI, 61 ATH_AHB, 62 ATH_USB, 63 }; 64 65 struct reg_dmn_pair_mapping { 66 u16 regDmnEnum; 67 u16 reg_5ghz_ctl; 68 u16 reg_2ghz_ctl; 69 }; 70 71 struct ath_regulatory { 72 char alpha2[2]; 73 u16 country_code; 74 u16 max_power_level; 75 u16 current_rd; 76 int16_t power_limit; 77 struct reg_dmn_pair_mapping *regpair; 78 }; 79 80 enum ath_crypt_caps { 81 ATH_CRYPT_CAP_CIPHER_AESCCM = BIT(0), 82 ATH_CRYPT_CAP_MIC_COMBINED = BIT(1), 83 }; 84 85 struct ath_keyval { 86 u8 kv_type; 87 u8 kv_pad; 88 u16 kv_len; 89 u8 kv_val[16]; /* TK */ 90 u8 kv_mic[8]; /* Michael MIC key */ 91 u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware 92 * supports both MIC keys in the same key cache entry; 93 * in that case, kv_mic is the RX key) */ 94 }; 95 96 enum ath_cipher { 97 ATH_CIPHER_WEP = 0, 98 ATH_CIPHER_AES_OCB = 1, 99 ATH_CIPHER_AES_CCM = 2, 100 ATH_CIPHER_CKIP = 3, 101 ATH_CIPHER_TKIP = 4, 102 ATH_CIPHER_CLR = 5, 103 ATH_CIPHER_MIC = 127 104 }; 105 106 /** 107 * struct ath_ops - Register read/write operations 108 * 109 * @read: Register read 110 * @multi_read: Multiple register read 111 * @write: Register write 112 * @enable_write_buffer: Enable multiple register writes 113 * @write_flush: flush buffered register writes and disable buffering 114 */ 115 struct ath_ops { 116 unsigned int (*read)(void *, u32 reg_offset); 117 void (*multi_read)(void *, u32 *addr, u32 *val, u16 count); 118 void (*write)(void *, u32 val, u32 reg_offset); 119 void (*enable_write_buffer)(void *); 120 void (*write_flush) (void *); 121 u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr); 122 }; 123 124 struct ath_common; 125 struct ath_bus_ops; 126 127 struct ath_common { 128 void *ah; 129 void *priv; 130 struct ieee80211_hw *hw; 131 int debug_mask; 132 enum ath_device_state state; 133 134 struct ath_ani ani; 135 136 u16 cachelsz; 137 u16 curaid; 138 u8 macaddr[ETH_ALEN]; 139 u8 curbssid[ETH_ALEN]; 140 u8 bssidmask[ETH_ALEN]; 141 142 u32 rx_bufsize; 143 144 u32 keymax; 145 DECLARE_BITMAP(keymap, ATH_KEYMAX); 146 DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX); 147 DECLARE_BITMAP(ccmp_keymap, ATH_KEYMAX); 148 enum ath_crypt_caps crypt_caps; 149 150 unsigned int clockrate; 151 152 spinlock_t cc_lock; 153 struct ath_cycle_counters cc_ani; 154 struct ath_cycle_counters cc_survey; 155 156 struct ath_regulatory regulatory; 157 struct ath_regulatory reg_world_copy; 158 const struct ath_ops *ops; 159 const struct ath_bus_ops *bus_ops; 160 161 bool btcoex_enabled; 162 bool disable_ani; 163 bool bt_ant_diversity; 164 }; 165 166 struct sk_buff *ath_rxbuf_alloc(struct ath_common *common, 167 u32 len, 168 gfp_t gfp_mask); 169 bool ath_is_mybeacon(struct ath_common *common, struct ieee80211_hdr *hdr); 170 171 void ath_hw_setbssidmask(struct ath_common *common); 172 void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key); 173 int ath_key_config(struct ath_common *common, 174 struct ieee80211_vif *vif, 175 struct ieee80211_sta *sta, 176 struct ieee80211_key_conf *key); 177 bool ath_hw_keyreset(struct ath_common *common, u16 entry); 178 void ath_hw_cycle_counters_update(struct ath_common *common); 179 int32_t ath_hw_get_listen_time(struct ath_common *common); 180 181 __printf(3, 4) 182 void ath_printk(const char *level, const struct ath_common *common, 183 const char *fmt, ...); 184 185 #define ath_emerg(common, fmt, ...) \ 186 ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__) 187 #define ath_alert(common, fmt, ...) \ 188 ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__) 189 #define ath_crit(common, fmt, ...) \ 190 ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__) 191 #define ath_err(common, fmt, ...) \ 192 ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__) 193 #define ath_warn(common, fmt, ...) \ 194 ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__) 195 #define ath_notice(common, fmt, ...) \ 196 ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__) 197 #define ath_info(common, fmt, ...) \ 198 ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__) 199 200 /** 201 * enum ath_debug_level - atheros wireless debug level 202 * 203 * @ATH_DBG_RESET: reset processing 204 * @ATH_DBG_QUEUE: hardware queue management 205 * @ATH_DBG_EEPROM: eeprom processing 206 * @ATH_DBG_CALIBRATE: periodic calibration 207 * @ATH_DBG_INTERRUPT: interrupt processing 208 * @ATH_DBG_REGULATORY: regulatory processing 209 * @ATH_DBG_ANI: adaptive noise immunitive processing 210 * @ATH_DBG_XMIT: basic xmit operation 211 * @ATH_DBG_BEACON: beacon handling 212 * @ATH_DBG_CONFIG: configuration of the hardware 213 * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT 214 * @ATH_DBG_PS: power save processing 215 * @ATH_DBG_HWTIMER: hardware timer handling 216 * @ATH_DBG_BTCOEX: bluetooth coexistance 217 * @ATH_DBG_BSTUCK: stuck beacons 218 * @ATH_DBG_MCI: Message Coexistence Interface, a private protocol 219 * used exclusively for WLAN-BT coexistence starting from 220 * AR9462. 221 * @ATH_DBG_DFS: radar datection 222 * @ATH_DBG_WOW: Wake on Wireless 223 * @ATH_DBG_ANY: enable all debugging 224 * 225 * The debug level is used to control the amount and type of debugging output 226 * we want to see. Each driver has its own method for enabling debugging and 227 * modifying debug level states -- but this is typically done through a 228 * module parameter 'debug' along with a respective 'debug' debugfs file 229 * entry. 230 */ 231 enum ATH_DEBUG { 232 ATH_DBG_RESET = 0x00000001, 233 ATH_DBG_QUEUE = 0x00000002, 234 ATH_DBG_EEPROM = 0x00000004, 235 ATH_DBG_CALIBRATE = 0x00000008, 236 ATH_DBG_INTERRUPT = 0x00000010, 237 ATH_DBG_REGULATORY = 0x00000020, 238 ATH_DBG_ANI = 0x00000040, 239 ATH_DBG_XMIT = 0x00000080, 240 ATH_DBG_BEACON = 0x00000100, 241 ATH_DBG_CONFIG = 0x00000200, 242 ATH_DBG_FATAL = 0x00000400, 243 ATH_DBG_PS = 0x00000800, 244 ATH_DBG_BTCOEX = 0x00001000, 245 ATH_DBG_WMI = 0x00002000, 246 ATH_DBG_BSTUCK = 0x00004000, 247 ATH_DBG_MCI = 0x00008000, 248 ATH_DBG_DFS = 0x00010000, 249 ATH_DBG_WOW = 0x00020000, 250 ATH_DBG_ANY = 0xffffffff 251 }; 252 253 #define ATH_DBG_DEFAULT (ATH_DBG_FATAL) 254 255 #ifdef CONFIG_ATH_DEBUG 256 257 #define ath_dbg(common, dbg_mask, fmt, ...) \ 258 do { \ 259 if ((common)->debug_mask & ATH_DBG_##dbg_mask) \ 260 ath_printk(KERN_DEBUG, common, fmt, ##__VA_ARGS__); \ 261 } while (0) 262 263 #define ATH_DBG_WARN(foo, arg...) WARN(foo, arg) 264 #define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo) 265 266 #else 267 268 static inline __attribute__ ((format (printf, 3, 4))) 269 void _ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask, 270 const char *fmt, ...) 271 { 272 } 273 #define ath_dbg(common, dbg_mask, fmt, ...) \ 274 _ath_dbg(common, ATH_DBG_##dbg_mask, fmt, ##__VA_ARGS__) 275 276 #define ATH_DBG_WARN(foo, arg...) do {} while (0) 277 #define ATH_DBG_WARN_ON_ONCE(foo) ({ \ 278 int __ret_warn_once = !!(foo); \ 279 unlikely(__ret_warn_once); \ 280 }) 281 282 #endif /* CONFIG_ATH_DEBUG */ 283 284 /** Returns string describing opmode, or NULL if unknown mode. */ 285 #ifdef CONFIG_ATH_DEBUG 286 const char *ath_opmode_to_string(enum nl80211_iftype opmode); 287 #else 288 static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode) 289 { 290 return "UNKNOWN"; 291 } 292 #endif 293 294 #endif /* ATH_H */ 295