1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef ATH_H 18 #define ATH_H 19 20 #include <linux/etherdevice.h> 21 #include <linux/skbuff.h> 22 #include <linux/if_ether.h> 23 #include <linux/spinlock.h> 24 #include <net/mac80211.h> 25 26 /* 27 * The key cache is used for h/w cipher state and also for 28 * tracking station state such as the current tx antenna. 29 * We also setup a mapping table between key cache slot indices 30 * and station state to short-circuit node lookups on rx. 31 * Different parts have different size key caches. We handle 32 * up to ATH_KEYMAX entries (could dynamically allocate state). 33 */ 34 #define ATH_KEYMAX 128 /* max key cache size we handle */ 35 36 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 37 38 struct ath_ani { 39 bool caldone; 40 unsigned int longcal_timer; 41 unsigned int shortcal_timer; 42 unsigned int resetcal_timer; 43 unsigned int checkani_timer; 44 struct timer_list timer; 45 }; 46 47 struct ath_cycle_counters { 48 u32 cycles; 49 u32 rx_busy; 50 u32 rx_frame; 51 u32 tx_frame; 52 }; 53 54 enum ath_device_state { 55 ATH_HW_UNAVAILABLE, 56 ATH_HW_INITIALIZED, 57 }; 58 59 enum ath_op_flags { 60 ATH_OP_INVALID, 61 ATH_OP_BEACONS, 62 ATH_OP_ANI_RUN, 63 ATH_OP_PRIM_STA_VIF, 64 ATH_OP_HW_RESET, 65 ATH_OP_SCANNING, 66 }; 67 68 enum ath_bus_type { 69 ATH_PCI, 70 ATH_AHB, 71 ATH_USB, 72 }; 73 74 struct reg_dmn_pair_mapping { 75 u16 reg_domain; 76 u16 reg_5ghz_ctl; 77 u16 reg_2ghz_ctl; 78 }; 79 80 struct ath_regulatory { 81 char alpha2[2]; 82 u16 country_code; 83 u16 max_power_level; 84 u16 current_rd; 85 int16_t power_limit; 86 struct reg_dmn_pair_mapping *regpair; 87 }; 88 89 enum ath_crypt_caps { 90 ATH_CRYPT_CAP_CIPHER_AESCCM = BIT(0), 91 ATH_CRYPT_CAP_MIC_COMBINED = BIT(1), 92 }; 93 94 struct ath_keyval { 95 u8 kv_type; 96 u8 kv_pad; 97 u16 kv_len; 98 u8 kv_val[16]; /* TK */ 99 u8 kv_mic[8]; /* Michael MIC key */ 100 u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware 101 * supports both MIC keys in the same key cache entry; 102 * in that case, kv_mic is the RX key) */ 103 }; 104 105 enum ath_cipher { 106 ATH_CIPHER_WEP = 0, 107 ATH_CIPHER_AES_OCB = 1, 108 ATH_CIPHER_AES_CCM = 2, 109 ATH_CIPHER_CKIP = 3, 110 ATH_CIPHER_TKIP = 4, 111 ATH_CIPHER_CLR = 5, 112 ATH_CIPHER_MIC = 127 113 }; 114 115 /** 116 * struct ath_ops - Register read/write operations 117 * 118 * @read: Register read 119 * @multi_read: Multiple register read 120 * @write: Register write 121 * @enable_write_buffer: Enable multiple register writes 122 * @write_flush: flush buffered register writes and disable buffering 123 */ 124 struct ath_ops { 125 unsigned int (*read)(void *, u32 reg_offset); 126 void (*multi_read)(void *, u32 *addr, u32 *val, u16 count); 127 void (*write)(void *, u32 val, u32 reg_offset); 128 void (*enable_write_buffer)(void *); 129 void (*write_flush) (void *); 130 u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr); 131 }; 132 133 struct ath_common; 134 struct ath_bus_ops; 135 136 struct ath_common { 137 void *ah; 138 void *priv; 139 struct ieee80211_hw *hw; 140 int debug_mask; 141 enum ath_device_state state; 142 unsigned long op_flags; 143 144 struct ath_ani ani; 145 146 u16 cachelsz; 147 u16 curaid; 148 u8 macaddr[ETH_ALEN]; 149 u8 curbssid[ETH_ALEN]; 150 u8 bssidmask[ETH_ALEN]; 151 152 u32 rx_bufsize; 153 154 u32 keymax; 155 DECLARE_BITMAP(keymap, ATH_KEYMAX); 156 DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX); 157 DECLARE_BITMAP(ccmp_keymap, ATH_KEYMAX); 158 enum ath_crypt_caps crypt_caps; 159 160 unsigned int clockrate; 161 162 spinlock_t cc_lock; 163 struct ath_cycle_counters cc_ani; 164 struct ath_cycle_counters cc_survey; 165 166 struct ath_regulatory regulatory; 167 struct ath_regulatory reg_world_copy; 168 const struct ath_ops *ops; 169 const struct ath_bus_ops *bus_ops; 170 171 bool btcoex_enabled; 172 bool disable_ani; 173 bool bt_ant_diversity; 174 175 int last_rssi; 176 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; 177 }; 178 179 struct sk_buff *ath_rxbuf_alloc(struct ath_common *common, 180 u32 len, 181 gfp_t gfp_mask); 182 bool ath_is_mybeacon(struct ath_common *common, struct ieee80211_hdr *hdr); 183 184 void ath_hw_setbssidmask(struct ath_common *common); 185 void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key); 186 int ath_key_config(struct ath_common *common, 187 struct ieee80211_vif *vif, 188 struct ieee80211_sta *sta, 189 struct ieee80211_key_conf *key); 190 bool ath_hw_keyreset(struct ath_common *common, u16 entry); 191 void ath_hw_cycle_counters_update(struct ath_common *common); 192 int32_t ath_hw_get_listen_time(struct ath_common *common); 193 194 __printf(3, 4) 195 void ath_printk(const char *level, const struct ath_common *common, 196 const char *fmt, ...); 197 198 #define ath_emerg(common, fmt, ...) \ 199 ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__) 200 #define ath_alert(common, fmt, ...) \ 201 ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__) 202 #define ath_crit(common, fmt, ...) \ 203 ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__) 204 #define ath_err(common, fmt, ...) \ 205 ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__) 206 #define ath_warn(common, fmt, ...) \ 207 ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__) 208 #define ath_notice(common, fmt, ...) \ 209 ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__) 210 #define ath_info(common, fmt, ...) \ 211 ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__) 212 213 /** 214 * enum ath_debug_level - atheros wireless debug level 215 * 216 * @ATH_DBG_RESET: reset processing 217 * @ATH_DBG_QUEUE: hardware queue management 218 * @ATH_DBG_EEPROM: eeprom processing 219 * @ATH_DBG_CALIBRATE: periodic calibration 220 * @ATH_DBG_INTERRUPT: interrupt processing 221 * @ATH_DBG_REGULATORY: regulatory processing 222 * @ATH_DBG_ANI: adaptive noise immunitive processing 223 * @ATH_DBG_XMIT: basic xmit operation 224 * @ATH_DBG_BEACON: beacon handling 225 * @ATH_DBG_CONFIG: configuration of the hardware 226 * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT 227 * @ATH_DBG_PS: power save processing 228 * @ATH_DBG_HWTIMER: hardware timer handling 229 * @ATH_DBG_BTCOEX: bluetooth coexistance 230 * @ATH_DBG_BSTUCK: stuck beacons 231 * @ATH_DBG_MCI: Message Coexistence Interface, a private protocol 232 * used exclusively for WLAN-BT coexistence starting from 233 * AR9462. 234 * @ATH_DBG_DFS: radar datection 235 * @ATH_DBG_WOW: Wake on Wireless 236 * @ATH_DBG_ANY: enable all debugging 237 * 238 * The debug level is used to control the amount and type of debugging output 239 * we want to see. Each driver has its own method for enabling debugging and 240 * modifying debug level states -- but this is typically done through a 241 * module parameter 'debug' along with a respective 'debug' debugfs file 242 * entry. 243 */ 244 enum ATH_DEBUG { 245 ATH_DBG_RESET = 0x00000001, 246 ATH_DBG_QUEUE = 0x00000002, 247 ATH_DBG_EEPROM = 0x00000004, 248 ATH_DBG_CALIBRATE = 0x00000008, 249 ATH_DBG_INTERRUPT = 0x00000010, 250 ATH_DBG_REGULATORY = 0x00000020, 251 ATH_DBG_ANI = 0x00000040, 252 ATH_DBG_XMIT = 0x00000080, 253 ATH_DBG_BEACON = 0x00000100, 254 ATH_DBG_CONFIG = 0x00000200, 255 ATH_DBG_FATAL = 0x00000400, 256 ATH_DBG_PS = 0x00000800, 257 ATH_DBG_BTCOEX = 0x00001000, 258 ATH_DBG_WMI = 0x00002000, 259 ATH_DBG_BSTUCK = 0x00004000, 260 ATH_DBG_MCI = 0x00008000, 261 ATH_DBG_DFS = 0x00010000, 262 ATH_DBG_WOW = 0x00020000, 263 ATH_DBG_ANY = 0xffffffff 264 }; 265 266 #define ATH_DBG_DEFAULT (ATH_DBG_FATAL) 267 268 #ifdef CONFIG_ATH_DEBUG 269 270 #define ath_dbg(common, dbg_mask, fmt, ...) \ 271 do { \ 272 if ((common)->debug_mask & ATH_DBG_##dbg_mask) \ 273 ath_printk(KERN_DEBUG, common, fmt, ##__VA_ARGS__); \ 274 } while (0) 275 276 #define ATH_DBG_WARN(foo, arg...) WARN(foo, arg) 277 #define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo) 278 279 #else 280 281 static inline __attribute__ ((format (printf, 3, 4))) 282 void _ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask, 283 const char *fmt, ...) 284 { 285 } 286 #define ath_dbg(common, dbg_mask, fmt, ...) \ 287 _ath_dbg(common, ATH_DBG_##dbg_mask, fmt, ##__VA_ARGS__) 288 289 #define ATH_DBG_WARN(foo, arg...) do {} while (0) 290 #define ATH_DBG_WARN_ON_ONCE(foo) ({ \ 291 int __ret_warn_once = !!(foo); \ 292 unlikely(__ret_warn_once); \ 293 }) 294 295 #endif /* CONFIG_ATH_DEBUG */ 296 297 /** Returns string describing opmode, or NULL if unknown mode. */ 298 #ifdef CONFIG_ATH_DEBUG 299 const char *ath_opmode_to_string(enum nl80211_iftype opmode); 300 #else 301 static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode) 302 { 303 return "UNKNOWN"; 304 } 305 #endif 306 307 #endif /* ATH_H */ 308