1d15dd3e5SLuis R. Rodriguez /* 2d15dd3e5SLuis R. Rodriguez * Copyright (c) 2008-2009 Atheros Communications Inc. 3d15dd3e5SLuis R. Rodriguez * 4d15dd3e5SLuis R. Rodriguez * Permission to use, copy, modify, and/or distribute this software for any 5d15dd3e5SLuis R. Rodriguez * purpose with or without fee is hereby granted, provided that the above 6d15dd3e5SLuis R. Rodriguez * copyright notice and this permission notice appear in all copies. 7d15dd3e5SLuis R. Rodriguez * 8d15dd3e5SLuis R. Rodriguez * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9d15dd3e5SLuis R. Rodriguez * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10d15dd3e5SLuis R. Rodriguez * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11d15dd3e5SLuis R. Rodriguez * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12d15dd3e5SLuis R. Rodriguez * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13d15dd3e5SLuis R. Rodriguez * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14d15dd3e5SLuis R. Rodriguez * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15d15dd3e5SLuis R. Rodriguez */ 16d15dd3e5SLuis R. Rodriguez 17d15dd3e5SLuis R. Rodriguez #ifndef ATH_H 18d15dd3e5SLuis R. Rodriguez #define ATH_H 19d15dd3e5SLuis R. Rodriguez 20d15dd3e5SLuis R. Rodriguez #include <linux/skbuff.h> 21bcd8f54aSLuis R. Rodriguez #include <linux/if_ether.h> 22b5bfc568SFelix Fietkau #include <linux/spinlock.h> 23b002a4a9SLuis R. Rodriguez #include <net/mac80211.h> 24d15dd3e5SLuis R. Rodriguez 257e86c104SLuis R. Rodriguez /* 267e86c104SLuis R. Rodriguez * The key cache is used for h/w cipher state and also for 277e86c104SLuis R. Rodriguez * tracking station state such as the current tx antenna. 287e86c104SLuis R. Rodriguez * We also setup a mapping table between key cache slot indices 297e86c104SLuis R. Rodriguez * and station state to short-circuit node lookups on rx. 307e86c104SLuis R. Rodriguez * Different parts have different size key caches. We handle 317e86c104SLuis R. Rodriguez * up to ATH_KEYMAX entries (could dynamically allocate state). 327e86c104SLuis R. Rodriguez */ 337e86c104SLuis R. Rodriguez #define ATH_KEYMAX 128 /* max key cache size we handle */ 347e86c104SLuis R. Rodriguez 3517753748SLuis R. Rodriguez static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 3617753748SLuis R. Rodriguez 373d536acfSLuis R. Rodriguez struct ath_ani { 383d536acfSLuis R. Rodriguez bool caldone; 393d536acfSLuis R. Rodriguez unsigned int longcal_timer; 403d536acfSLuis R. Rodriguez unsigned int shortcal_timer; 413d536acfSLuis R. Rodriguez unsigned int resetcal_timer; 423d536acfSLuis R. Rodriguez unsigned int checkani_timer; 433d536acfSLuis R. Rodriguez struct timer_list timer; 443d536acfSLuis R. Rodriguez }; 453d536acfSLuis R. Rodriguez 46b5bfc568SFelix Fietkau struct ath_cycle_counters { 47b5bfc568SFelix Fietkau u32 cycles; 48b5bfc568SFelix Fietkau u32 rx_busy; 49b5bfc568SFelix Fietkau u32 rx_frame; 50b5bfc568SFelix Fietkau u32 tx_frame; 51b5bfc568SFelix Fietkau }; 52b5bfc568SFelix Fietkau 53211f5859SLuis R. Rodriguez enum ath_device_state { 54211f5859SLuis R. Rodriguez ATH_HW_UNAVAILABLE, 55211f5859SLuis R. Rodriguez ATH_HW_INITIALIZED, 56211f5859SLuis R. Rodriguez }; 57211f5859SLuis R. Rodriguez 58497ad9adSSujith enum ath_bus_type { 59497ad9adSSujith ATH_PCI, 60497ad9adSSujith ATH_AHB, 61497ad9adSSujith ATH_USB, 62497ad9adSSujith }; 63497ad9adSSujith 64608b88cbSLuis R. Rodriguez struct reg_dmn_pair_mapping { 65608b88cbSLuis R. Rodriguez u16 regDmnEnum; 66608b88cbSLuis R. Rodriguez u16 reg_5ghz_ctl; 67608b88cbSLuis R. Rodriguez u16 reg_2ghz_ctl; 68608b88cbSLuis R. Rodriguez }; 69608b88cbSLuis R. Rodriguez 70608b88cbSLuis R. Rodriguez struct ath_regulatory { 71608b88cbSLuis R. Rodriguez char alpha2[2]; 72608b88cbSLuis R. Rodriguez u16 country_code; 73608b88cbSLuis R. Rodriguez u16 max_power_level; 74608b88cbSLuis R. Rodriguez u16 current_rd; 75608b88cbSLuis R. Rodriguez int16_t power_limit; 76608b88cbSLuis R. Rodriguez struct reg_dmn_pair_mapping *regpair; 77608b88cbSLuis R. Rodriguez }; 78608b88cbSLuis R. Rodriguez 7934a13051SBruno Randolf enum ath_crypt_caps { 80ce2220d1SBruno Randolf ATH_CRYPT_CAP_CIPHER_AESCCM = BIT(0), 81ce2220d1SBruno Randolf ATH_CRYPT_CAP_MIC_COMBINED = BIT(1), 8234a13051SBruno Randolf }; 8334a13051SBruno Randolf 841bba5b73SBruno Randolf struct ath_keyval { 851bba5b73SBruno Randolf u8 kv_type; 861bba5b73SBruno Randolf u8 kv_pad; 871bba5b73SBruno Randolf u16 kv_len; 881bba5b73SBruno Randolf u8 kv_val[16]; /* TK */ 891bba5b73SBruno Randolf u8 kv_mic[8]; /* Michael MIC key */ 901bba5b73SBruno Randolf u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware 911bba5b73SBruno Randolf * supports both MIC keys in the same key cache entry; 921bba5b73SBruno Randolf * in that case, kv_mic is the RX key) */ 931bba5b73SBruno Randolf }; 941bba5b73SBruno Randolf 951bba5b73SBruno Randolf enum ath_cipher { 961bba5b73SBruno Randolf ATH_CIPHER_WEP = 0, 971bba5b73SBruno Randolf ATH_CIPHER_AES_OCB = 1, 981bba5b73SBruno Randolf ATH_CIPHER_AES_CCM = 2, 991bba5b73SBruno Randolf ATH_CIPHER_CKIP = 3, 1001bba5b73SBruno Randolf ATH_CIPHER_TKIP = 4, 1011bba5b73SBruno Randolf ATH_CIPHER_CLR = 5, 1021bba5b73SBruno Randolf ATH_CIPHER_MIC = 127 1031bba5b73SBruno Randolf }; 1041bba5b73SBruno Randolf 10550f56316SSujith /** 10650f56316SSujith * struct ath_ops - Register read/write operations 10750f56316SSujith * 10850f56316SSujith * @read: Register read 10909a525d3SSujith Manoharan * @multi_read: Multiple register read 11050f56316SSujith * @write: Register write 11150f56316SSujith * @enable_write_buffer: Enable multiple register writes 112435c1610SFelix Fietkau * @write_flush: flush buffered register writes and disable buffering 11350f56316SSujith */ 1149e4bffd2SLuis R. Rodriguez struct ath_ops { 1159e4bffd2SLuis R. Rodriguez unsigned int (*read)(void *, u32 reg_offset); 11609a525d3SSujith Manoharan void (*multi_read)(void *, u32 *addr, u32 *val, u16 count); 1179e4bffd2SLuis R. Rodriguez void (*write)(void *, u32 val, u32 reg_offset); 11850f56316SSujith void (*enable_write_buffer)(void *); 11950f56316SSujith void (*write_flush) (void *); 120845e03c9SFelix Fietkau u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr); 1219e4bffd2SLuis R. Rodriguez }; 1229e4bffd2SLuis R. Rodriguez 1235bb12791SLuis R. Rodriguez struct ath_common; 1240cb9e06bSFelix Fietkau struct ath_bus_ops; 1255bb12791SLuis R. Rodriguez 126d15dd3e5SLuis R. Rodriguez struct ath_common { 12713b81559SLuis R. Rodriguez void *ah; 128bc974f4aSLuis R. Rodriguez void *priv; 129b002a4a9SLuis R. Rodriguez struct ieee80211_hw *hw; 130c46917bbSLuis R. Rodriguez int debug_mask; 131211f5859SLuis R. Rodriguez enum ath_device_state state; 132c46917bbSLuis R. Rodriguez 1333d536acfSLuis R. Rodriguez struct ath_ani ani; 1343d536acfSLuis R. Rodriguez 135d15dd3e5SLuis R. Rodriguez u16 cachelsz; 1361510718dSLuis R. Rodriguez u16 curaid; 1371510718dSLuis R. Rodriguez u8 macaddr[ETH_ALEN]; 1381510718dSLuis R. Rodriguez u8 curbssid[ETH_ALEN]; 1391510718dSLuis R. Rodriguez u8 bssidmask[ETH_ALEN]; 140c46917bbSLuis R. Rodriguez 141cc861f74SLuis R. Rodriguez u32 rx_bufsize; 142cc861f74SLuis R. Rodriguez 1437e86c104SLuis R. Rodriguez u32 keymax; 1447e86c104SLuis R. Rodriguez DECLARE_BITMAP(keymap, ATH_KEYMAX); 14556363ddeSFelix Fietkau DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX); 146bed3d9c0SFelix Fietkau DECLARE_BITMAP(ccmp_keymap, ATH_KEYMAX); 14734a13051SBruno Randolf enum ath_crypt_caps crypt_caps; 1487e86c104SLuis R. Rodriguez 149dfdac8acSFelix Fietkau unsigned int clockrate; 150dfdac8acSFelix Fietkau 151b5bfc568SFelix Fietkau spinlock_t cc_lock; 152b5bfc568SFelix Fietkau struct ath_cycle_counters cc_ani; 153b5bfc568SFelix Fietkau struct ath_cycle_counters cc_survey; 154b5bfc568SFelix Fietkau 155608b88cbSLuis R. Rodriguez struct ath_regulatory regulatory; 156de1c732bSLuis R. Rodriguez struct ath_regulatory reg_world_copy; 1579adca126SLuis R. Rodriguez const struct ath_ops *ops; 1585bb12791SLuis R. Rodriguez const struct ath_bus_ops *bus_ops; 1598f5dcb1cSVasanthakumar Thiagarajan 1608f5dcb1cSVasanthakumar Thiagarajan bool btcoex_enabled; 16105c0be2fSMohammed Shafi Shajakhan bool disable_ani; 162d15dd3e5SLuis R. Rodriguez }; 163d15dd3e5SLuis R. Rodriguez 164d15dd3e5SLuis R. Rodriguez struct sk_buff *ath_rxbuf_alloc(struct ath_common *common, 165d15dd3e5SLuis R. Rodriguez u32 len, 166d15dd3e5SLuis R. Rodriguez gfp_t gfp_mask); 167d15dd3e5SLuis R. Rodriguez 16813b81559SLuis R. Rodriguez void ath_hw_setbssidmask(struct ath_common *common); 1691bba5b73SBruno Randolf void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key); 1701bba5b73SBruno Randolf int ath_key_config(struct ath_common *common, 1711bba5b73SBruno Randolf struct ieee80211_vif *vif, 1721bba5b73SBruno Randolf struct ieee80211_sta *sta, 1731bba5b73SBruno Randolf struct ieee80211_key_conf *key); 1741bba5b73SBruno Randolf bool ath_hw_keyreset(struct ath_common *common, u16 entry); 175b5bfc568SFelix Fietkau void ath_hw_cycle_counters_update(struct ath_common *common); 176b5bfc568SFelix Fietkau int32_t ath_hw_get_listen_time(struct ath_common *common); 17713b81559SLuis R. Rodriguez 17898b36a02SBen Greear __printf(3, 4) 17998b36a02SBen Greear void ath_printk(const char *level, const struct ath_common *common, 18098b36a02SBen Greear const char *fmt, ...); 18121a99f93SJoe Perches 18221a99f93SJoe Perches #define ath_emerg(common, fmt, ...) \ 18398b36a02SBen Greear ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__) 18421a99f93SJoe Perches #define ath_alert(common, fmt, ...) \ 18598b36a02SBen Greear ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__) 18621a99f93SJoe Perches #define ath_crit(common, fmt, ...) \ 18798b36a02SBen Greear ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__) 18821a99f93SJoe Perches #define ath_err(common, fmt, ...) \ 18998b36a02SBen Greear ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__) 19021a99f93SJoe Perches #define ath_warn(common, fmt, ...) \ 19198b36a02SBen Greear ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__) 19221a99f93SJoe Perches #define ath_notice(common, fmt, ...) \ 19398b36a02SBen Greear ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__) 19421a99f93SJoe Perches #define ath_info(common, fmt, ...) \ 19598b36a02SBen Greear ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__) 19621a99f93SJoe Perches 19721a99f93SJoe Perches /** 19821a99f93SJoe Perches * enum ath_debug_level - atheros wireless debug level 19921a99f93SJoe Perches * 20021a99f93SJoe Perches * @ATH_DBG_RESET: reset processing 20121a99f93SJoe Perches * @ATH_DBG_QUEUE: hardware queue management 20221a99f93SJoe Perches * @ATH_DBG_EEPROM: eeprom processing 20321a99f93SJoe Perches * @ATH_DBG_CALIBRATE: periodic calibration 20421a99f93SJoe Perches * @ATH_DBG_INTERRUPT: interrupt processing 20521a99f93SJoe Perches * @ATH_DBG_REGULATORY: regulatory processing 20621a99f93SJoe Perches * @ATH_DBG_ANI: adaptive noise immunitive processing 20721a99f93SJoe Perches * @ATH_DBG_XMIT: basic xmit operation 20821a99f93SJoe Perches * @ATH_DBG_BEACON: beacon handling 20921a99f93SJoe Perches * @ATH_DBG_CONFIG: configuration of the hardware 21021a99f93SJoe Perches * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT 21121a99f93SJoe Perches * @ATH_DBG_PS: power save processing 21221a99f93SJoe Perches * @ATH_DBG_HWTIMER: hardware timer handling 21321a99f93SJoe Perches * @ATH_DBG_BTCOEX: bluetooth coexistance 21421a99f93SJoe Perches * @ATH_DBG_BSTUCK: stuck beacons 21555e435deSLuis R. Rodriguez * @ATH_DBG_MCI: Message Coexistence Interface, a private protocol 21655e435deSLuis R. Rodriguez * used exclusively for WLAN-BT coexistence starting from 21755e435deSLuis R. Rodriguez * AR9462. 2189b203c8fSZefir Kurtisi * @ATH_DBG_DFS: radar datection 21921a99f93SJoe Perches * @ATH_DBG_ANY: enable all debugging 22021a99f93SJoe Perches * 22121a99f93SJoe Perches * The debug level is used to control the amount and type of debugging output 22221a99f93SJoe Perches * we want to see. Each driver has its own method for enabling debugging and 22321a99f93SJoe Perches * modifying debug level states -- but this is typically done through a 22421a99f93SJoe Perches * module parameter 'debug' along with a respective 'debug' debugfs file 22521a99f93SJoe Perches * entry. 22621a99f93SJoe Perches */ 22721a99f93SJoe Perches enum ATH_DEBUG { 22821a99f93SJoe Perches ATH_DBG_RESET = 0x00000001, 22921a99f93SJoe Perches ATH_DBG_QUEUE = 0x00000002, 23021a99f93SJoe Perches ATH_DBG_EEPROM = 0x00000004, 23121a99f93SJoe Perches ATH_DBG_CALIBRATE = 0x00000008, 23221a99f93SJoe Perches ATH_DBG_INTERRUPT = 0x00000010, 23321a99f93SJoe Perches ATH_DBG_REGULATORY = 0x00000020, 23421a99f93SJoe Perches ATH_DBG_ANI = 0x00000040, 23521a99f93SJoe Perches ATH_DBG_XMIT = 0x00000080, 23621a99f93SJoe Perches ATH_DBG_BEACON = 0x00000100, 23721a99f93SJoe Perches ATH_DBG_CONFIG = 0x00000200, 23821a99f93SJoe Perches ATH_DBG_FATAL = 0x00000400, 23921a99f93SJoe Perches ATH_DBG_PS = 0x00000800, 24021a99f93SJoe Perches ATH_DBG_HWTIMER = 0x00001000, 24121a99f93SJoe Perches ATH_DBG_BTCOEX = 0x00002000, 24221a99f93SJoe Perches ATH_DBG_WMI = 0x00004000, 24321a99f93SJoe Perches ATH_DBG_BSTUCK = 0x00008000, 2447dc181c2SRajkumar Manoharan ATH_DBG_MCI = 0x00010000, 2459b203c8fSZefir Kurtisi ATH_DBG_DFS = 0x00020000, 24621a99f93SJoe Perches ATH_DBG_ANY = 0xffffffff 24721a99f93SJoe Perches }; 24821a99f93SJoe Perches 24921a99f93SJoe Perches #define ATH_DBG_DEFAULT (ATH_DBG_FATAL) 25021a99f93SJoe Perches 25121a99f93SJoe Perches #ifdef CONFIG_ATH_DEBUG 25221a99f93SJoe Perches 25321a99f93SJoe Perches #define ath_dbg(common, dbg_mask, fmt, ...) \ 2547b8112d6SJoe Perches do { \ 255d2182b69SJoe Perches if ((common)->debug_mask & ATH_DBG_##dbg_mask) \ 25698b36a02SBen Greear ath_printk(KERN_DEBUG, common, fmt, ##__VA_ARGS__); \ 2577b8112d6SJoe Perches } while (0) 2587b8112d6SJoe Perches 25921a99f93SJoe Perches #define ATH_DBG_WARN(foo, arg...) WARN(foo, arg) 260d7fd1b50SBen Greear #define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo) 26121a99f93SJoe Perches 26221a99f93SJoe Perches #else 26321a99f93SJoe Perches 2647b8112d6SJoe Perches static inline __attribute__ ((format (printf, 3, 4))) 265d2182b69SJoe Perches void _ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask, 26621a99f93SJoe Perches const char *fmt, ...) 26721a99f93SJoe Perches { 26821a99f93SJoe Perches } 269d2182b69SJoe Perches #define ath_dbg(common, dbg_mask, fmt, ...) \ 270d2182b69SJoe Perches _ath_dbg(common, ATH_DBG_##dbg_mask, fmt, ##__VA_ARGS__) 271d2182b69SJoe Perches 27221a99f93SJoe Perches #define ATH_DBG_WARN(foo, arg...) do {} while (0) 273b7613370SJohn W. Linville #define ATH_DBG_WARN_ON_ONCE(foo) ({ \ 274b7613370SJohn W. Linville int __ret_warn_once = !!(foo); \ 275b7613370SJohn W. Linville unlikely(__ret_warn_once); \ 276b7613370SJohn W. Linville }) 27721a99f93SJoe Perches 27821a99f93SJoe Perches #endif /* CONFIG_ATH_DEBUG */ 27921a99f93SJoe Perches 28021a99f93SJoe Perches /** Returns string describing opmode, or NULL if unknown mode. */ 28121a99f93SJoe Perches #ifdef CONFIG_ATH_DEBUG 28221a99f93SJoe Perches const char *ath_opmode_to_string(enum nl80211_iftype opmode); 28321a99f93SJoe Perches #else 28421a99f93SJoe Perches static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode) 28521a99f93SJoe Perches { 28621a99f93SJoe Perches return "UNKNOWN"; 28721a99f93SJoe Perches } 28821a99f93SJoe Perches #endif 28921a99f93SJoe Perches 290d15dd3e5SLuis R. Rodriguez #endif /* ATH_H */ 291