1 // SPDX-License-Identifier: GPL-2.0 2 /* NXP TJA1100 BroadRReach PHY driver 3 * 4 * Copyright (C) 2018 Marek Vasut <marex@denx.de> 5 */ 6 #include <linux/delay.h> 7 #include <linux/ethtool.h> 8 #include <linux/kernel.h> 9 #include <linux/mii.h> 10 #include <linux/module.h> 11 #include <linux/phy.h> 12 #include <linux/hwmon.h> 13 #include <linux/bitfield.h> 14 15 #define PHY_ID_MASK 0xfffffff0 16 #define PHY_ID_TJA1100 0x0180dc40 17 #define PHY_ID_TJA1101 0x0180dd00 18 19 #define MII_ECTRL 17 20 #define MII_ECTRL_LINK_CONTROL BIT(15) 21 #define MII_ECTRL_POWER_MODE_MASK GENMASK(14, 11) 22 #define MII_ECTRL_POWER_MODE_NO_CHANGE (0x0 << 11) 23 #define MII_ECTRL_POWER_MODE_NORMAL (0x3 << 11) 24 #define MII_ECTRL_POWER_MODE_STANDBY (0xc << 11) 25 #define MII_ECTRL_CONFIG_EN BIT(2) 26 #define MII_ECTRL_WAKE_REQUEST BIT(0) 27 28 #define MII_CFG1 18 29 #define MII_CFG1_AUTO_OP BIT(14) 30 #define MII_CFG1_SLEEP_CONFIRM BIT(6) 31 #define MII_CFG1_LED_MODE_MASK GENMASK(5, 4) 32 #define MII_CFG1_LED_MODE_LINKUP 0 33 #define MII_CFG1_LED_ENABLE BIT(3) 34 35 #define MII_CFG2 19 36 #define MII_CFG2_SLEEP_REQUEST_TO GENMASK(1, 0) 37 #define MII_CFG2_SLEEP_REQUEST_TO_16MS 0x3 38 39 #define MII_INTSRC 21 40 #define MII_INTSRC_TEMP_ERR BIT(1) 41 #define MII_INTSRC_UV_ERR BIT(3) 42 43 #define MII_COMMSTAT 23 44 #define MII_COMMSTAT_LINK_UP BIT(15) 45 46 #define MII_GENSTAT 24 47 #define MII_GENSTAT_PLL_LOCKED BIT(14) 48 49 #define MII_COMMCFG 27 50 #define MII_COMMCFG_AUTO_OP BIT(15) 51 52 struct tja11xx_priv { 53 char *hwmon_name; 54 struct device *hwmon_dev; 55 }; 56 57 struct tja11xx_phy_stats { 58 const char *string; 59 u8 reg; 60 u8 off; 61 u16 mask; 62 }; 63 64 static struct tja11xx_phy_stats tja11xx_hw_stats[] = { 65 { "phy_symbol_error_count", 20, 0, GENMASK(15, 0) }, 66 { "phy_polarity_detect", 25, 6, BIT(6) }, 67 { "phy_open_detect", 25, 7, BIT(7) }, 68 { "phy_short_detect", 25, 8, BIT(8) }, 69 { "phy_rem_rcvr_count", 26, 0, GENMASK(7, 0) }, 70 { "phy_loc_rcvr_count", 26, 8, GENMASK(15, 8) }, 71 }; 72 73 static int tja11xx_check(struct phy_device *phydev, u8 reg, u16 mask, u16 set) 74 { 75 int val; 76 77 return phy_read_poll_timeout(phydev, reg, val, (val & mask) == set, 78 150, 30000, false); 79 } 80 81 static int phy_modify_check(struct phy_device *phydev, u8 reg, 82 u16 mask, u16 set) 83 { 84 int ret; 85 86 ret = phy_modify(phydev, reg, mask, set); 87 if (ret) 88 return ret; 89 90 return tja11xx_check(phydev, reg, mask, set); 91 } 92 93 static int tja11xx_enable_reg_write(struct phy_device *phydev) 94 { 95 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CONFIG_EN); 96 } 97 98 static int tja11xx_enable_link_control(struct phy_device *phydev) 99 { 100 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL); 101 } 102 103 static int tja11xx_wakeup(struct phy_device *phydev) 104 { 105 int ret; 106 107 ret = phy_read(phydev, MII_ECTRL); 108 if (ret < 0) 109 return ret; 110 111 switch (ret & MII_ECTRL_POWER_MODE_MASK) { 112 case MII_ECTRL_POWER_MODE_NO_CHANGE: 113 break; 114 case MII_ECTRL_POWER_MODE_NORMAL: 115 ret = phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST); 116 if (ret) 117 return ret; 118 119 ret = phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST); 120 if (ret) 121 return ret; 122 break; 123 case MII_ECTRL_POWER_MODE_STANDBY: 124 ret = phy_modify_check(phydev, MII_ECTRL, 125 MII_ECTRL_POWER_MODE_MASK, 126 MII_ECTRL_POWER_MODE_STANDBY); 127 if (ret) 128 return ret; 129 130 ret = phy_modify(phydev, MII_ECTRL, MII_ECTRL_POWER_MODE_MASK, 131 MII_ECTRL_POWER_MODE_NORMAL); 132 if (ret) 133 return ret; 134 135 ret = phy_modify_check(phydev, MII_GENSTAT, 136 MII_GENSTAT_PLL_LOCKED, 137 MII_GENSTAT_PLL_LOCKED); 138 if (ret) 139 return ret; 140 141 return tja11xx_enable_link_control(phydev); 142 default: 143 break; 144 } 145 146 return 0; 147 } 148 149 static int tja11xx_soft_reset(struct phy_device *phydev) 150 { 151 int ret; 152 153 ret = tja11xx_enable_reg_write(phydev); 154 if (ret) 155 return ret; 156 157 return genphy_soft_reset(phydev); 158 } 159 160 static int tja11xx_config_init(struct phy_device *phydev) 161 { 162 int ret; 163 164 ret = tja11xx_enable_reg_write(phydev); 165 if (ret) 166 return ret; 167 168 phydev->autoneg = AUTONEG_DISABLE; 169 phydev->speed = SPEED_100; 170 phydev->duplex = DUPLEX_FULL; 171 172 switch (phydev->phy_id & PHY_ID_MASK) { 173 case PHY_ID_TJA1100: 174 ret = phy_modify(phydev, MII_CFG1, 175 MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_MASK | 176 MII_CFG1_LED_ENABLE, 177 MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_LINKUP | 178 MII_CFG1_LED_ENABLE); 179 if (ret) 180 return ret; 181 break; 182 case PHY_ID_TJA1101: 183 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP); 184 if (ret) 185 return ret; 186 break; 187 default: 188 return -EINVAL; 189 } 190 191 ret = phy_clear_bits(phydev, MII_CFG1, MII_CFG1_SLEEP_CONFIRM); 192 if (ret) 193 return ret; 194 195 ret = phy_modify(phydev, MII_CFG2, MII_CFG2_SLEEP_REQUEST_TO, 196 MII_CFG2_SLEEP_REQUEST_TO_16MS); 197 if (ret) 198 return ret; 199 200 ret = tja11xx_wakeup(phydev); 201 if (ret < 0) 202 return ret; 203 204 /* ACK interrupts by reading the status register */ 205 ret = phy_read(phydev, MII_INTSRC); 206 if (ret < 0) 207 return ret; 208 209 return 0; 210 } 211 212 static int tja11xx_read_status(struct phy_device *phydev) 213 { 214 int ret; 215 216 ret = genphy_update_link(phydev); 217 if (ret) 218 return ret; 219 220 if (phydev->link) { 221 ret = phy_read(phydev, MII_COMMSTAT); 222 if (ret < 0) 223 return ret; 224 225 if (!(ret & MII_COMMSTAT_LINK_UP)) 226 phydev->link = 0; 227 } 228 229 return 0; 230 } 231 232 static int tja11xx_get_sset_count(struct phy_device *phydev) 233 { 234 return ARRAY_SIZE(tja11xx_hw_stats); 235 } 236 237 static void tja11xx_get_strings(struct phy_device *phydev, u8 *data) 238 { 239 int i; 240 241 for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) { 242 strncpy(data + i * ETH_GSTRING_LEN, 243 tja11xx_hw_stats[i].string, ETH_GSTRING_LEN); 244 } 245 } 246 247 static void tja11xx_get_stats(struct phy_device *phydev, 248 struct ethtool_stats *stats, u64 *data) 249 { 250 int i, ret; 251 252 for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) { 253 ret = phy_read(phydev, tja11xx_hw_stats[i].reg); 254 if (ret < 0) 255 data[i] = U64_MAX; 256 else { 257 data[i] = ret & tja11xx_hw_stats[i].mask; 258 data[i] >>= tja11xx_hw_stats[i].off; 259 } 260 } 261 } 262 263 static int tja11xx_hwmon_read(struct device *dev, 264 enum hwmon_sensor_types type, 265 u32 attr, int channel, long *value) 266 { 267 struct phy_device *phydev = dev_get_drvdata(dev); 268 int ret; 269 270 if (type == hwmon_in && attr == hwmon_in_lcrit_alarm) { 271 ret = phy_read(phydev, MII_INTSRC); 272 if (ret < 0) 273 return ret; 274 275 *value = !!(ret & MII_INTSRC_TEMP_ERR); 276 return 0; 277 } 278 279 if (type == hwmon_temp && attr == hwmon_temp_crit_alarm) { 280 ret = phy_read(phydev, MII_INTSRC); 281 if (ret < 0) 282 return ret; 283 284 *value = !!(ret & MII_INTSRC_UV_ERR); 285 return 0; 286 } 287 288 return -EOPNOTSUPP; 289 } 290 291 static umode_t tja11xx_hwmon_is_visible(const void *data, 292 enum hwmon_sensor_types type, 293 u32 attr, int channel) 294 { 295 if (type == hwmon_in && attr == hwmon_in_lcrit_alarm) 296 return 0444; 297 298 if (type == hwmon_temp && attr == hwmon_temp_crit_alarm) 299 return 0444; 300 301 return 0; 302 } 303 304 static const struct hwmon_channel_info *tja11xx_hwmon_info[] = { 305 HWMON_CHANNEL_INFO(in, HWMON_I_LCRIT_ALARM), 306 HWMON_CHANNEL_INFO(temp, HWMON_T_CRIT_ALARM), 307 NULL 308 }; 309 310 static const struct hwmon_ops tja11xx_hwmon_hwmon_ops = { 311 .is_visible = tja11xx_hwmon_is_visible, 312 .read = tja11xx_hwmon_read, 313 }; 314 315 static const struct hwmon_chip_info tja11xx_hwmon_chip_info = { 316 .ops = &tja11xx_hwmon_hwmon_ops, 317 .info = tja11xx_hwmon_info, 318 }; 319 320 static int tja11xx_probe(struct phy_device *phydev) 321 { 322 struct device *dev = &phydev->mdio.dev; 323 struct tja11xx_priv *priv; 324 int i; 325 326 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 327 if (!priv) 328 return -ENOMEM; 329 330 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); 331 if (!priv->hwmon_name) 332 return -ENOMEM; 333 334 for (i = 0; priv->hwmon_name[i]; i++) 335 if (hwmon_is_bad_char(priv->hwmon_name[i])) 336 priv->hwmon_name[i] = '_'; 337 338 priv->hwmon_dev = 339 devm_hwmon_device_register_with_info(dev, priv->hwmon_name, 340 phydev, 341 &tja11xx_hwmon_chip_info, 342 NULL); 343 344 return PTR_ERR_OR_ZERO(priv->hwmon_dev); 345 } 346 347 static struct phy_driver tja11xx_driver[] = { 348 { 349 PHY_ID_MATCH_MODEL(PHY_ID_TJA1100), 350 .name = "NXP TJA1100", 351 .features = PHY_BASIC_T1_FEATURES, 352 .probe = tja11xx_probe, 353 .soft_reset = tja11xx_soft_reset, 354 .config_init = tja11xx_config_init, 355 .read_status = tja11xx_read_status, 356 .suspend = genphy_suspend, 357 .resume = genphy_resume, 358 .set_loopback = genphy_loopback, 359 /* Statistics */ 360 .get_sset_count = tja11xx_get_sset_count, 361 .get_strings = tja11xx_get_strings, 362 .get_stats = tja11xx_get_stats, 363 }, { 364 PHY_ID_MATCH_MODEL(PHY_ID_TJA1101), 365 .name = "NXP TJA1101", 366 .features = PHY_BASIC_T1_FEATURES, 367 .probe = tja11xx_probe, 368 .soft_reset = tja11xx_soft_reset, 369 .config_init = tja11xx_config_init, 370 .read_status = tja11xx_read_status, 371 .suspend = genphy_suspend, 372 .resume = genphy_resume, 373 .set_loopback = genphy_loopback, 374 /* Statistics */ 375 .get_sset_count = tja11xx_get_sset_count, 376 .get_strings = tja11xx_get_strings, 377 .get_stats = tja11xx_get_stats, 378 } 379 }; 380 381 module_phy_driver(tja11xx_driver); 382 383 static struct mdio_device_id __maybe_unused tja11xx_tbl[] = { 384 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1100) }, 385 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1101) }, 386 { } 387 }; 388 389 MODULE_DEVICE_TABLE(mdio, tja11xx_tbl); 390 391 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 392 MODULE_DESCRIPTION("NXP TJA11xx BoardR-Reach PHY driver"); 393 MODULE_LICENSE("GPL"); 394