1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2021 Maxlinear Corporation 3 * Copyright (C) 2020 Intel Corporation 4 * 5 * Drivers for Maxlinear Ethernet GPY 6 * 7 */ 8 9 #include <linux/module.h> 10 #include <linux/bitfield.h> 11 #include <linux/hwmon.h> 12 #include <linux/phy.h> 13 #include <linux/polynomial.h> 14 #include <linux/netdevice.h> 15 16 /* PHY ID */ 17 #define PHY_ID_GPYx15B_MASK 0xFFFFFFFC 18 #define PHY_ID_GPY21xB_MASK 0xFFFFFFF9 19 #define PHY_ID_GPY2xx 0x67C9DC00 20 #define PHY_ID_GPY115B 0x67C9DF00 21 #define PHY_ID_GPY115C 0x67C9DF10 22 #define PHY_ID_GPY211B 0x67C9DE08 23 #define PHY_ID_GPY211C 0x67C9DE10 24 #define PHY_ID_GPY212B 0x67C9DE09 25 #define PHY_ID_GPY212C 0x67C9DE20 26 #define PHY_ID_GPY215B 0x67C9DF04 27 #define PHY_ID_GPY215C 0x67C9DF20 28 #define PHY_ID_GPY241B 0x67C9DE40 29 #define PHY_ID_GPY241BM 0x67C9DE80 30 #define PHY_ID_GPY245B 0x67C9DEC0 31 32 #define PHY_CTL1 0x13 33 #define PHY_CTL1_MDICD BIT(3) 34 #define PHY_CTL1_MDIAB BIT(2) 35 #define PHY_CTL1_AMDIX BIT(0) 36 #define PHY_MIISTAT 0x18 /* MII state */ 37 #define PHY_IMASK 0x19 /* interrupt mask */ 38 #define PHY_ISTAT 0x1A /* interrupt status */ 39 #define PHY_FWV 0x1E /* firmware version */ 40 41 #define PHY_MIISTAT_SPD_MASK GENMASK(2, 0) 42 #define PHY_MIISTAT_DPX BIT(3) 43 #define PHY_MIISTAT_LS BIT(10) 44 45 #define PHY_MIISTAT_SPD_10 0 46 #define PHY_MIISTAT_SPD_100 1 47 #define PHY_MIISTAT_SPD_1000 2 48 #define PHY_MIISTAT_SPD_2500 4 49 50 #define PHY_IMASK_WOL BIT(15) /* Wake-on-LAN */ 51 #define PHY_IMASK_ANC BIT(10) /* Auto-Neg complete */ 52 #define PHY_IMASK_ADSC BIT(5) /* Link auto-downspeed detect */ 53 #define PHY_IMASK_DXMC BIT(2) /* Duplex mode change */ 54 #define PHY_IMASK_LSPC BIT(1) /* Link speed change */ 55 #define PHY_IMASK_LSTC BIT(0) /* Link state change */ 56 #define PHY_IMASK_MASK (PHY_IMASK_LSTC | \ 57 PHY_IMASK_LSPC | \ 58 PHY_IMASK_DXMC | \ 59 PHY_IMASK_ADSC | \ 60 PHY_IMASK_ANC) 61 62 #define PHY_FWV_REL_MASK BIT(15) 63 #define PHY_FWV_MAJOR_MASK GENMASK(11, 8) 64 #define PHY_FWV_MINOR_MASK GENMASK(7, 0) 65 66 #define PHY_PMA_MGBT_POLARITY 0x82 67 #define PHY_MDI_MDI_X_MASK GENMASK(1, 0) 68 #define PHY_MDI_MDI_X_NORMAL 0x3 69 #define PHY_MDI_MDI_X_AB 0x2 70 #define PHY_MDI_MDI_X_CD 0x1 71 #define PHY_MDI_MDI_X_CROSS 0x0 72 73 /* SGMII */ 74 #define VSPEC1_SGMII_CTRL 0x08 75 #define VSPEC1_SGMII_CTRL_ANEN BIT(12) /* Aneg enable */ 76 #define VSPEC1_SGMII_CTRL_ANRS BIT(9) /* Restart Aneg */ 77 #define VSPEC1_SGMII_ANEN_ANRS (VSPEC1_SGMII_CTRL_ANEN | \ 78 VSPEC1_SGMII_CTRL_ANRS) 79 80 /* Temperature sensor */ 81 #define VPSPEC1_TEMP_STA 0x0E 82 #define VPSPEC1_TEMP_STA_DATA GENMASK(9, 0) 83 84 /* WoL */ 85 #define VPSPEC2_WOL_CTL 0x0E06 86 #define VPSPEC2_WOL_AD01 0x0E08 87 #define VPSPEC2_WOL_AD23 0x0E09 88 #define VPSPEC2_WOL_AD45 0x0E0A 89 #define WOL_EN BIT(0) 90 91 struct gpy_priv { 92 u8 fw_major; 93 u8 fw_minor; 94 }; 95 96 static const struct { 97 int major; 98 int minor; 99 } ver_need_sgmii_reaneg[] = { 100 {7, 0x6D}, 101 {8, 0x6D}, 102 {9, 0x73}, 103 }; 104 105 #if IS_ENABLED(CONFIG_HWMON) 106 /* The original translation formulae of the temperature (in degrees of Celsius) 107 * are as follows: 108 * 109 * T = -2.5761e-11*(N^4) + 9.7332e-8*(N^3) + -1.9165e-4*(N^2) + 110 * 3.0762e-1*(N^1) + -5.2156e1 111 * 112 * where [-52.156, 137.961]C and N = [0, 1023]. 113 * 114 * They must be accordingly altered to be suitable for the integer arithmetics. 115 * The technique is called 'factor redistribution', which just makes sure the 116 * multiplications and divisions are made so to have a result of the operations 117 * within the integer numbers limit. In addition we need to translate the 118 * formulae to accept millidegrees of Celsius. Here what it looks like after 119 * the alterations: 120 * 121 * T = -25761e-12*(N^4) + 97332e-9*(N^3) + -191650e-6*(N^2) + 122 * 307620e-3*(N^1) + -52156 123 * 124 * where T = [-52156, 137961]mC and N = [0, 1023]. 125 */ 126 static const struct polynomial poly_N_to_temp = { 127 .terms = { 128 {4, -25761, 1000, 1}, 129 {3, 97332, 1000, 1}, 130 {2, -191650, 1000, 1}, 131 {1, 307620, 1000, 1}, 132 {0, -52156, 1, 1} 133 } 134 }; 135 136 static int gpy_hwmon_read(struct device *dev, 137 enum hwmon_sensor_types type, 138 u32 attr, int channel, long *value) 139 { 140 struct phy_device *phydev = dev_get_drvdata(dev); 141 int ret; 142 143 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VPSPEC1_TEMP_STA); 144 if (ret < 0) 145 return ret; 146 if (!ret) 147 return -ENODATA; 148 149 *value = polynomial_calc(&poly_N_to_temp, 150 FIELD_GET(VPSPEC1_TEMP_STA_DATA, ret)); 151 152 return 0; 153 } 154 155 static umode_t gpy_hwmon_is_visible(const void *data, 156 enum hwmon_sensor_types type, 157 u32 attr, int channel) 158 { 159 return 0444; 160 } 161 162 static const struct hwmon_channel_info *gpy_hwmon_info[] = { 163 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT), 164 NULL 165 }; 166 167 static const struct hwmon_ops gpy_hwmon_hwmon_ops = { 168 .is_visible = gpy_hwmon_is_visible, 169 .read = gpy_hwmon_read, 170 }; 171 172 static const struct hwmon_chip_info gpy_hwmon_chip_info = { 173 .ops = &gpy_hwmon_hwmon_ops, 174 .info = gpy_hwmon_info, 175 }; 176 177 static int gpy_hwmon_register(struct phy_device *phydev) 178 { 179 struct device *dev = &phydev->mdio.dev; 180 struct device *hwmon_dev; 181 char *hwmon_name; 182 183 hwmon_name = devm_hwmon_sanitize_name(dev, dev_name(dev)); 184 if (IS_ERR(hwmon_name)) 185 return PTR_ERR(hwmon_name); 186 187 hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name, 188 phydev, 189 &gpy_hwmon_chip_info, 190 NULL); 191 192 return PTR_ERR_OR_ZERO(hwmon_dev); 193 } 194 #else 195 static int gpy_hwmon_register(struct phy_device *phydev) 196 { 197 return 0; 198 } 199 #endif 200 201 static int gpy_config_init(struct phy_device *phydev) 202 { 203 int ret; 204 205 /* Mask all interrupts */ 206 ret = phy_write(phydev, PHY_IMASK, 0); 207 if (ret) 208 return ret; 209 210 /* Clear all pending interrupts */ 211 ret = phy_read(phydev, PHY_ISTAT); 212 return ret < 0 ? ret : 0; 213 } 214 215 static int gpy_probe(struct phy_device *phydev) 216 { 217 struct device *dev = &phydev->mdio.dev; 218 struct gpy_priv *priv; 219 int fw_version; 220 int ret; 221 222 if (!phydev->is_c45) { 223 ret = phy_get_c45_ids(phydev); 224 if (ret < 0) 225 return ret; 226 } 227 228 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 229 if (!priv) 230 return -ENOMEM; 231 phydev->priv = priv; 232 233 fw_version = phy_read(phydev, PHY_FWV); 234 if (fw_version < 0) 235 return fw_version; 236 priv->fw_major = FIELD_GET(PHY_FWV_MAJOR_MASK, fw_version); 237 priv->fw_minor = FIELD_GET(PHY_FWV_MINOR_MASK, fw_version); 238 239 ret = gpy_hwmon_register(phydev); 240 if (ret) 241 return ret; 242 243 /* Show GPY PHY FW version in dmesg */ 244 phydev_info(phydev, "Firmware Version: %d.%d (0x%04X%s)\n", 245 priv->fw_major, priv->fw_minor, fw_version, 246 fw_version & PHY_FWV_REL_MASK ? "" : " test version"); 247 248 return 0; 249 } 250 251 static bool gpy_sgmii_need_reaneg(struct phy_device *phydev) 252 { 253 struct gpy_priv *priv = phydev->priv; 254 size_t i; 255 256 for (i = 0; i < ARRAY_SIZE(ver_need_sgmii_reaneg); i++) { 257 if (priv->fw_major != ver_need_sgmii_reaneg[i].major) 258 continue; 259 if (priv->fw_minor < ver_need_sgmii_reaneg[i].minor) 260 return true; 261 break; 262 } 263 264 return false; 265 } 266 267 static bool gpy_2500basex_chk(struct phy_device *phydev) 268 { 269 int ret; 270 271 ret = phy_read(phydev, PHY_MIISTAT); 272 if (ret < 0) { 273 phydev_err(phydev, "Error: MDIO register access failed: %d\n", 274 ret); 275 return false; 276 } 277 278 if (!(ret & PHY_MIISTAT_LS) || 279 FIELD_GET(PHY_MIISTAT_SPD_MASK, ret) != PHY_MIISTAT_SPD_2500) 280 return false; 281 282 phydev->speed = SPEED_2500; 283 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 284 phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 285 VSPEC1_SGMII_CTRL_ANEN, 0); 286 return true; 287 } 288 289 static bool gpy_sgmii_aneg_en(struct phy_device *phydev) 290 { 291 int ret; 292 293 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL); 294 if (ret < 0) { 295 phydev_err(phydev, "Error: MMD register access failed: %d\n", 296 ret); 297 return true; 298 } 299 300 return (ret & VSPEC1_SGMII_CTRL_ANEN) ? true : false; 301 } 302 303 static int gpy_config_mdix(struct phy_device *phydev, u8 ctrl) 304 { 305 int ret; 306 u16 val; 307 308 switch (ctrl) { 309 case ETH_TP_MDI_AUTO: 310 val = PHY_CTL1_AMDIX; 311 break; 312 case ETH_TP_MDI_X: 313 val = (PHY_CTL1_MDIAB | PHY_CTL1_MDICD); 314 break; 315 case ETH_TP_MDI: 316 val = 0; 317 break; 318 default: 319 return 0; 320 } 321 322 ret = phy_modify(phydev, PHY_CTL1, PHY_CTL1_AMDIX | PHY_CTL1_MDIAB | 323 PHY_CTL1_MDICD, val); 324 if (ret < 0) 325 return ret; 326 327 return genphy_c45_restart_aneg(phydev); 328 } 329 330 static int gpy_config_aneg(struct phy_device *phydev) 331 { 332 bool changed = false; 333 u32 adv; 334 int ret; 335 336 if (phydev->autoneg == AUTONEG_DISABLE) { 337 /* Configure half duplex with genphy_setup_forced, 338 * because genphy_c45_pma_setup_forced does not support. 339 */ 340 return phydev->duplex != DUPLEX_FULL 341 ? genphy_setup_forced(phydev) 342 : genphy_c45_pma_setup_forced(phydev); 343 } 344 345 ret = gpy_config_mdix(phydev, phydev->mdix_ctrl); 346 if (ret < 0) 347 return ret; 348 349 ret = genphy_c45_an_config_aneg(phydev); 350 if (ret < 0) 351 return ret; 352 if (ret > 0) 353 changed = true; 354 355 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 356 ret = phy_modify_changed(phydev, MII_CTRL1000, 357 ADVERTISE_1000FULL | ADVERTISE_1000HALF, 358 adv); 359 if (ret < 0) 360 return ret; 361 if (ret > 0) 362 changed = true; 363 364 ret = genphy_c45_check_and_restart_aneg(phydev, changed); 365 if (ret < 0) 366 return ret; 367 368 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII || 369 phydev->interface == PHY_INTERFACE_MODE_INTERNAL) 370 return 0; 371 372 /* No need to trigger re-ANEG if link speed is 2.5G or SGMII ANEG is 373 * disabled. 374 */ 375 if (!gpy_sgmii_need_reaneg(phydev) || gpy_2500basex_chk(phydev) || 376 !gpy_sgmii_aneg_en(phydev)) 377 return 0; 378 379 /* There is a design constraint in GPY2xx device where SGMII AN is 380 * only triggered when there is change of speed. If, PHY link 381 * partner`s speed is still same even after PHY TPI is down and up 382 * again, SGMII AN is not triggered and hence no new in-band message 383 * from GPY to MAC side SGMII. 384 * This could cause an issue during power up, when PHY is up prior to 385 * MAC. At this condition, once MAC side SGMII is up, MAC side SGMII 386 * wouldn`t receive new in-band message from GPY with correct link 387 * status, speed and duplex info. 388 * 389 * 1) If PHY is already up and TPI link status is still down (such as 390 * hard reboot), TPI link status is polled for 4 seconds before 391 * retriggerring SGMII AN. 392 * 2) If PHY is already up and TPI link status is also up (such as soft 393 * reboot), polling of TPI link status is not needed and SGMII AN is 394 * immediately retriggered. 395 * 3) Other conditions such as PHY is down, speed change etc, skip 396 * retriggering SGMII AN. Note: in case of speed change, GPY FW will 397 * initiate SGMII AN. 398 */ 399 400 if (phydev->state != PHY_UP) 401 return 0; 402 403 ret = phy_read_poll_timeout(phydev, MII_BMSR, ret, ret & BMSR_LSTATUS, 404 20000, 4000000, false); 405 if (ret == -ETIMEDOUT) 406 return 0; 407 else if (ret < 0) 408 return ret; 409 410 /* Trigger SGMII AN. */ 411 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 412 VSPEC1_SGMII_CTRL_ANRS, VSPEC1_SGMII_CTRL_ANRS); 413 } 414 415 static int gpy_update_mdix(struct phy_device *phydev) 416 { 417 int ret; 418 419 ret = phy_read(phydev, PHY_CTL1); 420 if (ret < 0) 421 return ret; 422 423 if (ret & PHY_CTL1_AMDIX) 424 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 425 else 426 if (ret & PHY_CTL1_MDICD || ret & PHY_CTL1_MDIAB) 427 phydev->mdix_ctrl = ETH_TP_MDI_X; 428 else 429 phydev->mdix_ctrl = ETH_TP_MDI; 430 431 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PHY_PMA_MGBT_POLARITY); 432 if (ret < 0) 433 return ret; 434 435 if ((ret & PHY_MDI_MDI_X_MASK) < PHY_MDI_MDI_X_NORMAL) 436 phydev->mdix = ETH_TP_MDI_X; 437 else 438 phydev->mdix = ETH_TP_MDI; 439 440 return 0; 441 } 442 443 static int gpy_update_interface(struct phy_device *phydev) 444 { 445 int ret; 446 447 /* Interface mode is fixed for USXGMII and integrated PHY */ 448 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII || 449 phydev->interface == PHY_INTERFACE_MODE_INTERNAL) 450 return -EINVAL; 451 452 /* Automatically switch SERDES interface between SGMII and 2500-BaseX 453 * according to speed. Disable ANEG in 2500-BaseX mode. 454 */ 455 switch (phydev->speed) { 456 case SPEED_2500: 457 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 458 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 459 VSPEC1_SGMII_CTRL_ANEN, 0); 460 if (ret < 0) { 461 phydev_err(phydev, 462 "Error: Disable of SGMII ANEG failed: %d\n", 463 ret); 464 return ret; 465 } 466 break; 467 case SPEED_1000: 468 case SPEED_100: 469 case SPEED_10: 470 phydev->interface = PHY_INTERFACE_MODE_SGMII; 471 if (gpy_sgmii_aneg_en(phydev)) 472 break; 473 /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed 474 * if ANEG is disabled (in 2500-BaseX mode). 475 */ 476 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 477 VSPEC1_SGMII_ANEN_ANRS, 478 VSPEC1_SGMII_ANEN_ANRS); 479 if (ret < 0) { 480 phydev_err(phydev, 481 "Error: Enable of SGMII ANEG failed: %d\n", 482 ret); 483 return ret; 484 } 485 break; 486 } 487 488 if (phydev->speed == SPEED_2500 || phydev->speed == SPEED_1000) { 489 ret = genphy_read_master_slave(phydev); 490 if (ret < 0) 491 return ret; 492 } 493 494 return gpy_update_mdix(phydev); 495 } 496 497 static int gpy_read_status(struct phy_device *phydev) 498 { 499 int ret; 500 501 ret = genphy_update_link(phydev); 502 if (ret) 503 return ret; 504 505 phydev->speed = SPEED_UNKNOWN; 506 phydev->duplex = DUPLEX_UNKNOWN; 507 phydev->pause = 0; 508 phydev->asym_pause = 0; 509 510 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) { 511 ret = genphy_c45_read_lpa(phydev); 512 if (ret < 0) 513 return ret; 514 515 /* Read the link partner's 1G advertisement */ 516 ret = phy_read(phydev, MII_STAT1000); 517 if (ret < 0) 518 return ret; 519 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret); 520 } else if (phydev->autoneg == AUTONEG_DISABLE) { 521 linkmode_zero(phydev->lp_advertising); 522 } 523 524 ret = phy_read(phydev, PHY_MIISTAT); 525 if (ret < 0) 526 return ret; 527 528 phydev->link = (ret & PHY_MIISTAT_LS) ? 1 : 0; 529 phydev->duplex = (ret & PHY_MIISTAT_DPX) ? DUPLEX_FULL : DUPLEX_HALF; 530 switch (FIELD_GET(PHY_MIISTAT_SPD_MASK, ret)) { 531 case PHY_MIISTAT_SPD_10: 532 phydev->speed = SPEED_10; 533 break; 534 case PHY_MIISTAT_SPD_100: 535 phydev->speed = SPEED_100; 536 break; 537 case PHY_MIISTAT_SPD_1000: 538 phydev->speed = SPEED_1000; 539 break; 540 case PHY_MIISTAT_SPD_2500: 541 phydev->speed = SPEED_2500; 542 break; 543 } 544 545 if (phydev->link) { 546 ret = gpy_update_interface(phydev); 547 if (ret < 0) 548 return ret; 549 } 550 551 return 0; 552 } 553 554 static int gpy_config_intr(struct phy_device *phydev) 555 { 556 u16 mask = 0; 557 558 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 559 mask = PHY_IMASK_MASK; 560 561 return phy_write(phydev, PHY_IMASK, mask); 562 } 563 564 static irqreturn_t gpy_handle_interrupt(struct phy_device *phydev) 565 { 566 int reg; 567 568 reg = phy_read(phydev, PHY_ISTAT); 569 if (reg < 0) { 570 phy_error(phydev); 571 return IRQ_NONE; 572 } 573 574 if (!(reg & PHY_IMASK_MASK)) 575 return IRQ_NONE; 576 577 phy_trigger_machine(phydev); 578 579 return IRQ_HANDLED; 580 } 581 582 static int gpy_set_wol(struct phy_device *phydev, 583 struct ethtool_wolinfo *wol) 584 { 585 struct net_device *attach_dev = phydev->attached_dev; 586 int ret; 587 588 if (wol->wolopts & WAKE_MAGIC) { 589 /* MAC address - Byte0:Byte1:Byte2:Byte3:Byte4:Byte5 590 * VPSPEC2_WOL_AD45 = Byte0:Byte1 591 * VPSPEC2_WOL_AD23 = Byte2:Byte3 592 * VPSPEC2_WOL_AD01 = Byte4:Byte5 593 */ 594 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 595 VPSPEC2_WOL_AD45, 596 ((attach_dev->dev_addr[0] << 8) | 597 attach_dev->dev_addr[1])); 598 if (ret < 0) 599 return ret; 600 601 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 602 VPSPEC2_WOL_AD23, 603 ((attach_dev->dev_addr[2] << 8) | 604 attach_dev->dev_addr[3])); 605 if (ret < 0) 606 return ret; 607 608 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 609 VPSPEC2_WOL_AD01, 610 ((attach_dev->dev_addr[4] << 8) | 611 attach_dev->dev_addr[5])); 612 if (ret < 0) 613 return ret; 614 615 /* Enable the WOL interrupt */ 616 ret = phy_write(phydev, PHY_IMASK, PHY_IMASK_WOL); 617 if (ret < 0) 618 return ret; 619 620 /* Enable magic packet matching */ 621 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 622 VPSPEC2_WOL_CTL, 623 WOL_EN); 624 if (ret < 0) 625 return ret; 626 627 /* Clear the interrupt status register. 628 * Only WoL is enabled so clear all. 629 */ 630 ret = phy_read(phydev, PHY_ISTAT); 631 if (ret < 0) 632 return ret; 633 } else { 634 /* Disable magic packet matching */ 635 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 636 VPSPEC2_WOL_CTL, 637 WOL_EN); 638 if (ret < 0) 639 return ret; 640 } 641 642 if (wol->wolopts & WAKE_PHY) { 643 /* Enable the link state change interrupt */ 644 ret = phy_set_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC); 645 if (ret < 0) 646 return ret; 647 648 /* Clear the interrupt status register */ 649 ret = phy_read(phydev, PHY_ISTAT); 650 if (ret < 0) 651 return ret; 652 653 if (ret & (PHY_IMASK_MASK & ~PHY_IMASK_LSTC)) 654 phy_trigger_machine(phydev); 655 656 return 0; 657 } 658 659 /* Disable the link state change interrupt */ 660 return phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC); 661 } 662 663 static void gpy_get_wol(struct phy_device *phydev, 664 struct ethtool_wolinfo *wol) 665 { 666 int ret; 667 668 wol->supported = WAKE_MAGIC | WAKE_PHY; 669 wol->wolopts = 0; 670 671 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, VPSPEC2_WOL_CTL); 672 if (ret & WOL_EN) 673 wol->wolopts |= WAKE_MAGIC; 674 675 ret = phy_read(phydev, PHY_IMASK); 676 if (ret & PHY_IMASK_LSTC) 677 wol->wolopts |= WAKE_PHY; 678 } 679 680 static int gpy_loopback(struct phy_device *phydev, bool enable) 681 { 682 int ret; 683 684 ret = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, 685 enable ? BMCR_LOOPBACK : 0); 686 if (!ret) { 687 /* It takes some time for PHY device to switch 688 * into/out-of loopback mode. 689 */ 690 msleep(100); 691 } 692 693 return ret; 694 } 695 696 static int gpy115_loopback(struct phy_device *phydev, bool enable) 697 { 698 struct gpy_priv *priv = phydev->priv; 699 700 if (enable) 701 return gpy_loopback(phydev, enable); 702 703 if (priv->fw_minor > 0x76) 704 return gpy_loopback(phydev, 0); 705 706 return genphy_soft_reset(phydev); 707 } 708 709 static struct phy_driver gpy_drivers[] = { 710 { 711 PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx), 712 .name = "Maxlinear Ethernet GPY2xx", 713 .get_features = genphy_c45_pma_read_abilities, 714 .config_init = gpy_config_init, 715 .probe = gpy_probe, 716 .suspend = genphy_suspend, 717 .resume = genphy_resume, 718 .config_aneg = gpy_config_aneg, 719 .aneg_done = genphy_c45_aneg_done, 720 .read_status = gpy_read_status, 721 .config_intr = gpy_config_intr, 722 .handle_interrupt = gpy_handle_interrupt, 723 .set_wol = gpy_set_wol, 724 .get_wol = gpy_get_wol, 725 .set_loopback = gpy_loopback, 726 }, 727 { 728 .phy_id = PHY_ID_GPY115B, 729 .phy_id_mask = PHY_ID_GPYx15B_MASK, 730 .name = "Maxlinear Ethernet GPY115B", 731 .get_features = genphy_c45_pma_read_abilities, 732 .config_init = gpy_config_init, 733 .probe = gpy_probe, 734 .suspend = genphy_suspend, 735 .resume = genphy_resume, 736 .config_aneg = gpy_config_aneg, 737 .aneg_done = genphy_c45_aneg_done, 738 .read_status = gpy_read_status, 739 .config_intr = gpy_config_intr, 740 .handle_interrupt = gpy_handle_interrupt, 741 .set_wol = gpy_set_wol, 742 .get_wol = gpy_get_wol, 743 .set_loopback = gpy115_loopback, 744 }, 745 { 746 PHY_ID_MATCH_MODEL(PHY_ID_GPY115C), 747 .name = "Maxlinear Ethernet GPY115C", 748 .get_features = genphy_c45_pma_read_abilities, 749 .config_init = gpy_config_init, 750 .probe = gpy_probe, 751 .suspend = genphy_suspend, 752 .resume = genphy_resume, 753 .config_aneg = gpy_config_aneg, 754 .aneg_done = genphy_c45_aneg_done, 755 .read_status = gpy_read_status, 756 .config_intr = gpy_config_intr, 757 .handle_interrupt = gpy_handle_interrupt, 758 .set_wol = gpy_set_wol, 759 .get_wol = gpy_get_wol, 760 .set_loopback = gpy115_loopback, 761 }, 762 { 763 .phy_id = PHY_ID_GPY211B, 764 .phy_id_mask = PHY_ID_GPY21xB_MASK, 765 .name = "Maxlinear Ethernet GPY211B", 766 .get_features = genphy_c45_pma_read_abilities, 767 .config_init = gpy_config_init, 768 .probe = gpy_probe, 769 .suspend = genphy_suspend, 770 .resume = genphy_resume, 771 .config_aneg = gpy_config_aneg, 772 .aneg_done = genphy_c45_aneg_done, 773 .read_status = gpy_read_status, 774 .config_intr = gpy_config_intr, 775 .handle_interrupt = gpy_handle_interrupt, 776 .set_wol = gpy_set_wol, 777 .get_wol = gpy_get_wol, 778 .set_loopback = gpy_loopback, 779 }, 780 { 781 PHY_ID_MATCH_MODEL(PHY_ID_GPY211C), 782 .name = "Maxlinear Ethernet GPY211C", 783 .get_features = genphy_c45_pma_read_abilities, 784 .config_init = gpy_config_init, 785 .probe = gpy_probe, 786 .suspend = genphy_suspend, 787 .resume = genphy_resume, 788 .config_aneg = gpy_config_aneg, 789 .aneg_done = genphy_c45_aneg_done, 790 .read_status = gpy_read_status, 791 .config_intr = gpy_config_intr, 792 .handle_interrupt = gpy_handle_interrupt, 793 .set_wol = gpy_set_wol, 794 .get_wol = gpy_get_wol, 795 .set_loopback = gpy_loopback, 796 }, 797 { 798 .phy_id = PHY_ID_GPY212B, 799 .phy_id_mask = PHY_ID_GPY21xB_MASK, 800 .name = "Maxlinear Ethernet GPY212B", 801 .get_features = genphy_c45_pma_read_abilities, 802 .config_init = gpy_config_init, 803 .probe = gpy_probe, 804 .suspend = genphy_suspend, 805 .resume = genphy_resume, 806 .config_aneg = gpy_config_aneg, 807 .aneg_done = genphy_c45_aneg_done, 808 .read_status = gpy_read_status, 809 .config_intr = gpy_config_intr, 810 .handle_interrupt = gpy_handle_interrupt, 811 .set_wol = gpy_set_wol, 812 .get_wol = gpy_get_wol, 813 .set_loopback = gpy_loopback, 814 }, 815 { 816 PHY_ID_MATCH_MODEL(PHY_ID_GPY212C), 817 .name = "Maxlinear Ethernet GPY212C", 818 .get_features = genphy_c45_pma_read_abilities, 819 .config_init = gpy_config_init, 820 .probe = gpy_probe, 821 .suspend = genphy_suspend, 822 .resume = genphy_resume, 823 .config_aneg = gpy_config_aneg, 824 .aneg_done = genphy_c45_aneg_done, 825 .read_status = gpy_read_status, 826 .config_intr = gpy_config_intr, 827 .handle_interrupt = gpy_handle_interrupt, 828 .set_wol = gpy_set_wol, 829 .get_wol = gpy_get_wol, 830 .set_loopback = gpy_loopback, 831 }, 832 { 833 .phy_id = PHY_ID_GPY215B, 834 .phy_id_mask = PHY_ID_GPYx15B_MASK, 835 .name = "Maxlinear Ethernet GPY215B", 836 .get_features = genphy_c45_pma_read_abilities, 837 .config_init = gpy_config_init, 838 .probe = gpy_probe, 839 .suspend = genphy_suspend, 840 .resume = genphy_resume, 841 .config_aneg = gpy_config_aneg, 842 .aneg_done = genphy_c45_aneg_done, 843 .read_status = gpy_read_status, 844 .config_intr = gpy_config_intr, 845 .handle_interrupt = gpy_handle_interrupt, 846 .set_wol = gpy_set_wol, 847 .get_wol = gpy_get_wol, 848 .set_loopback = gpy_loopback, 849 }, 850 { 851 PHY_ID_MATCH_MODEL(PHY_ID_GPY215C), 852 .name = "Maxlinear Ethernet GPY215C", 853 .get_features = genphy_c45_pma_read_abilities, 854 .config_init = gpy_config_init, 855 .probe = gpy_probe, 856 .suspend = genphy_suspend, 857 .resume = genphy_resume, 858 .config_aneg = gpy_config_aneg, 859 .aneg_done = genphy_c45_aneg_done, 860 .read_status = gpy_read_status, 861 .config_intr = gpy_config_intr, 862 .handle_interrupt = gpy_handle_interrupt, 863 .set_wol = gpy_set_wol, 864 .get_wol = gpy_get_wol, 865 .set_loopback = gpy_loopback, 866 }, 867 { 868 PHY_ID_MATCH_MODEL(PHY_ID_GPY241B), 869 .name = "Maxlinear Ethernet GPY241B", 870 .get_features = genphy_c45_pma_read_abilities, 871 .config_init = gpy_config_init, 872 .probe = gpy_probe, 873 .suspend = genphy_suspend, 874 .resume = genphy_resume, 875 .config_aneg = gpy_config_aneg, 876 .aneg_done = genphy_c45_aneg_done, 877 .read_status = gpy_read_status, 878 .config_intr = gpy_config_intr, 879 .handle_interrupt = gpy_handle_interrupt, 880 .set_wol = gpy_set_wol, 881 .get_wol = gpy_get_wol, 882 .set_loopback = gpy_loopback, 883 }, 884 { 885 PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM), 886 .name = "Maxlinear Ethernet GPY241BM", 887 .get_features = genphy_c45_pma_read_abilities, 888 .config_init = gpy_config_init, 889 .probe = gpy_probe, 890 .suspend = genphy_suspend, 891 .resume = genphy_resume, 892 .config_aneg = gpy_config_aneg, 893 .aneg_done = genphy_c45_aneg_done, 894 .read_status = gpy_read_status, 895 .config_intr = gpy_config_intr, 896 .handle_interrupt = gpy_handle_interrupt, 897 .set_wol = gpy_set_wol, 898 .get_wol = gpy_get_wol, 899 .set_loopback = gpy_loopback, 900 }, 901 { 902 PHY_ID_MATCH_MODEL(PHY_ID_GPY245B), 903 .name = "Maxlinear Ethernet GPY245B", 904 .get_features = genphy_c45_pma_read_abilities, 905 .config_init = gpy_config_init, 906 .probe = gpy_probe, 907 .suspend = genphy_suspend, 908 .resume = genphy_resume, 909 .config_aneg = gpy_config_aneg, 910 .aneg_done = genphy_c45_aneg_done, 911 .read_status = gpy_read_status, 912 .config_intr = gpy_config_intr, 913 .handle_interrupt = gpy_handle_interrupt, 914 .set_wol = gpy_set_wol, 915 .get_wol = gpy_get_wol, 916 .set_loopback = gpy_loopback, 917 }, 918 }; 919 module_phy_driver(gpy_drivers); 920 921 static struct mdio_device_id __maybe_unused gpy_tbl[] = { 922 {PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx)}, 923 {PHY_ID_GPY115B, PHY_ID_GPYx15B_MASK}, 924 {PHY_ID_MATCH_MODEL(PHY_ID_GPY115C)}, 925 {PHY_ID_GPY211B, PHY_ID_GPY21xB_MASK}, 926 {PHY_ID_MATCH_MODEL(PHY_ID_GPY211C)}, 927 {PHY_ID_GPY212B, PHY_ID_GPY21xB_MASK}, 928 {PHY_ID_MATCH_MODEL(PHY_ID_GPY212C)}, 929 {PHY_ID_GPY215B, PHY_ID_GPYx15B_MASK}, 930 {PHY_ID_MATCH_MODEL(PHY_ID_GPY215C)}, 931 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241B)}, 932 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM)}, 933 {PHY_ID_MATCH_MODEL(PHY_ID_GPY245B)}, 934 { } 935 }; 936 MODULE_DEVICE_TABLE(mdio, gpy_tbl); 937 938 MODULE_DESCRIPTION("Maxlinear Ethernet GPY Driver"); 939 MODULE_AUTHOR("Xu Liang"); 940 MODULE_LICENSE("GPL"); 941