1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Motorcomm 8511/8521 PHY driver. 4 * 5 * Author: Peter Geis <pgwipeout@gmail.com> 6 * Author: Frank <Frank.Sae@motor-comm.com> 7 */ 8 9 #include <linux/etherdevice.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/phy.h> 13 14 #define PHY_ID_YT8511 0x0000010a 15 #define PHY_ID_YT8521 0x0000011A 16 17 /* YT8521 Register Overview 18 * UTP Register space | FIBER Register space 19 * ------------------------------------------------------------ 20 * | UTP MII | FIBER MII | 21 * | UTP MMD | | 22 * | UTP Extended | FIBER Extended | 23 * ------------------------------------------------------------ 24 * | Common Extended | 25 * ------------------------------------------------------------ 26 */ 27 28 /* 0x10 ~ 0x15 , 0x1E and 0x1F are common MII registers of yt phy */ 29 30 /* Specific Function Control Register */ 31 #define YTPHY_SPECIFIC_FUNCTION_CONTROL_REG 0x10 32 33 /* 2b00 Manual MDI configuration 34 * 2b01 Manual MDIX configuration 35 * 2b10 Reserved 36 * 2b11 Enable automatic crossover for all modes *default* 37 */ 38 #define YTPHY_SFCR_MDI_CROSSOVER_MODE_MASK (BIT(6) | BIT(5)) 39 #define YTPHY_SFCR_CROSSOVER_EN BIT(3) 40 #define YTPHY_SFCR_SQE_TEST_EN BIT(2) 41 #define YTPHY_SFCR_POLARITY_REVERSAL_EN BIT(1) 42 #define YTPHY_SFCR_JABBER_DIS BIT(0) 43 44 /* Specific Status Register */ 45 #define YTPHY_SPECIFIC_STATUS_REG 0x11 46 #define YTPHY_SSR_SPEED_MODE_OFFSET 14 47 48 #define YTPHY_SSR_SPEED_MODE_MASK (BIT(15) | BIT(14)) 49 #define YTPHY_SSR_SPEED_10M 0x0 50 #define YTPHY_SSR_SPEED_100M 0x1 51 #define YTPHY_SSR_SPEED_1000M 0x2 52 #define YTPHY_SSR_DUPLEX_OFFSET 13 53 #define YTPHY_SSR_DUPLEX BIT(13) 54 #define YTPHY_SSR_PAGE_RECEIVED BIT(12) 55 #define YTPHY_SSR_SPEED_DUPLEX_RESOLVED BIT(11) 56 #define YTPHY_SSR_LINK BIT(10) 57 #define YTPHY_SSR_MDIX_CROSSOVER BIT(6) 58 #define YTPHY_SSR_DOWNGRADE BIT(5) 59 #define YTPHY_SSR_TRANSMIT_PAUSE BIT(3) 60 #define YTPHY_SSR_RECEIVE_PAUSE BIT(2) 61 #define YTPHY_SSR_POLARITY BIT(1) 62 #define YTPHY_SSR_JABBER BIT(0) 63 64 /* Interrupt enable Register */ 65 #define YTPHY_INTERRUPT_ENABLE_REG 0x12 66 #define YTPHY_IER_WOL BIT(6) 67 68 /* Interrupt Status Register */ 69 #define YTPHY_INTERRUPT_STATUS_REG 0x13 70 #define YTPHY_ISR_AUTONEG_ERR BIT(15) 71 #define YTPHY_ISR_SPEED_CHANGED BIT(14) 72 #define YTPHY_ISR_DUPLEX_CHANGED BIT(13) 73 #define YTPHY_ISR_PAGE_RECEIVED BIT(12) 74 #define YTPHY_ISR_LINK_FAILED BIT(11) 75 #define YTPHY_ISR_LINK_SUCCESSED BIT(10) 76 #define YTPHY_ISR_WOL BIT(6) 77 #define YTPHY_ISR_WIRESPEED_DOWNGRADE BIT(5) 78 #define YTPHY_ISR_SERDES_LINK_FAILED BIT(3) 79 #define YTPHY_ISR_SERDES_LINK_SUCCESSED BIT(2) 80 #define YTPHY_ISR_POLARITY_CHANGED BIT(1) 81 #define YTPHY_ISR_JABBER_HAPPENED BIT(0) 82 83 /* Speed Auto Downgrade Control Register */ 84 #define YTPHY_SPEED_AUTO_DOWNGRADE_CONTROL_REG 0x14 85 #define YTPHY_SADCR_SPEED_DOWNGRADE_EN BIT(5) 86 87 /* If these bits are set to 3, the PHY attempts five times ( 3(set value) + 88 * additional 2) before downgrading, default 0x3 89 */ 90 #define YTPHY_SADCR_SPEED_RETRY_LIMIT (0x3 << 2) 91 92 /* Rx Error Counter Register */ 93 #define YTPHY_RX_ERROR_COUNTER_REG 0x15 94 95 /* Extended Register's Address Offset Register */ 96 #define YTPHY_PAGE_SELECT 0x1E 97 98 /* Extended Register's Data Register */ 99 #define YTPHY_PAGE_DATA 0x1F 100 101 /* FIBER Auto-Negotiation link partner ability */ 102 #define YTPHY_FLPA_PAUSE (0x3 << 7) 103 #define YTPHY_FLPA_ASYM_PAUSE (0x2 << 7) 104 105 #define YT8511_PAGE_SELECT 0x1e 106 #define YT8511_PAGE 0x1f 107 #define YT8511_EXT_CLK_GATE 0x0c 108 #define YT8511_EXT_DELAY_DRIVE 0x0d 109 #define YT8511_EXT_SLEEP_CTRL 0x27 110 111 /* 2b00 25m from pll 112 * 2b01 25m from xtl *default* 113 * 2b10 62.m from pll 114 * 2b11 125m from pll 115 */ 116 #define YT8511_CLK_125M (BIT(2) | BIT(1)) 117 #define YT8511_PLLON_SLP BIT(14) 118 119 /* RX Delay enabled = 1.8ns 1000T, 8ns 10/100T */ 120 #define YT8511_DELAY_RX BIT(0) 121 122 /* TX Gig-E Delay is bits 7:4, default 0x5 123 * TX Fast-E Delay is bits 15:12, default 0xf 124 * Delay = 150ps * N - 250ps 125 * On = 2000ps, off = 50ps 126 */ 127 #define YT8511_DELAY_GE_TX_EN (0xf << 4) 128 #define YT8511_DELAY_GE_TX_DIS (0x2 << 4) 129 #define YT8511_DELAY_FE_TX_EN (0xf << 12) 130 #define YT8511_DELAY_FE_TX_DIS (0x2 << 12) 131 132 /* Extended register is different from MMD Register and MII Register. 133 * We can use ytphy_read_ext/ytphy_write_ext/ytphy_modify_ext function to 134 * operate extended register. 135 * Extended Register start 136 */ 137 138 /* Phy gmii clock gating Register */ 139 #define YT8521_CLOCK_GATING_REG 0xC 140 #define YT8521_CGR_RX_CLK_EN BIT(12) 141 142 #define YT8521_EXTREG_SLEEP_CONTROL1_REG 0x27 143 #define YT8521_ESC1R_SLEEP_SW BIT(15) 144 #define YT8521_ESC1R_PLLON_SLP BIT(14) 145 146 /* Phy fiber Link timer cfg2 Register */ 147 #define YT8521_LINK_TIMER_CFG2_REG 0xA5 148 #define YT8521_LTCR_EN_AUTOSEN BIT(15) 149 150 /* 0xA000, 0xA001, 0xA003 ,and 0xA006 ~ 0xA00A are common ext registers 151 * of yt8521 phy. There is no need to switch reg space when operating these 152 * registers. 153 */ 154 155 #define YT8521_REG_SPACE_SELECT_REG 0xA000 156 #define YT8521_RSSR_SPACE_MASK BIT(1) 157 #define YT8521_RSSR_FIBER_SPACE (0x1 << 1) 158 #define YT8521_RSSR_UTP_SPACE (0x0 << 1) 159 #define YT8521_RSSR_TO_BE_ARBITRATED (0xFF) 160 161 #define YT8521_CHIP_CONFIG_REG 0xA001 162 #define YT8521_CCR_SW_RST BIT(15) 163 164 #define YT8521_CCR_MODE_SEL_MASK (BIT(2) | BIT(1) | BIT(0)) 165 #define YT8521_CCR_MODE_UTP_TO_RGMII 0 166 #define YT8521_CCR_MODE_FIBER_TO_RGMII 1 167 #define YT8521_CCR_MODE_UTP_FIBER_TO_RGMII 2 168 #define YT8521_CCR_MODE_UTP_TO_SGMII 3 169 #define YT8521_CCR_MODE_SGPHY_TO_RGMAC 4 170 #define YT8521_CCR_MODE_SGMAC_TO_RGPHY 5 171 #define YT8521_CCR_MODE_UTP_TO_FIBER_AUTO 6 172 #define YT8521_CCR_MODE_UTP_TO_FIBER_FORCE 7 173 174 /* 3 phy polling modes,poll mode combines utp and fiber mode*/ 175 #define YT8521_MODE_FIBER 0x1 176 #define YT8521_MODE_UTP 0x2 177 #define YT8521_MODE_POLL 0x3 178 179 #define YT8521_RGMII_CONFIG1_REG 0xA003 180 181 /* TX Gig-E Delay is bits 3:0, default 0x1 182 * TX Fast-E Delay is bits 7:4, default 0xf 183 * RX Delay is bits 13:10, default 0x0 184 * Delay = 150ps * N 185 * On = 2250ps, off = 0ps 186 */ 187 #define YT8521_RC1R_RX_DELAY_MASK (0xF << 10) 188 #define YT8521_RC1R_RX_DELAY_EN (0xF << 10) 189 #define YT8521_RC1R_RX_DELAY_DIS (0x0 << 10) 190 #define YT8521_RC1R_FE_TX_DELAY_MASK (0xF << 4) 191 #define YT8521_RC1R_FE_TX_DELAY_EN (0xF << 4) 192 #define YT8521_RC1R_FE_TX_DELAY_DIS (0x0 << 4) 193 #define YT8521_RC1R_GE_TX_DELAY_MASK (0xF << 0) 194 #define YT8521_RC1R_GE_TX_DELAY_EN (0xF << 0) 195 #define YT8521_RC1R_GE_TX_DELAY_DIS (0x0 << 0) 196 197 #define YTPHY_MISC_CONFIG_REG 0xA006 198 #define YTPHY_MCR_FIBER_SPEED_MASK BIT(0) 199 #define YTPHY_MCR_FIBER_1000BX (0x1 << 0) 200 #define YTPHY_MCR_FIBER_100FX (0x0 << 0) 201 202 /* WOL MAC ADDR: MACADDR2(highest), MACADDR1(middle), MACADDR0(lowest) */ 203 #define YTPHY_WOL_MACADDR2_REG 0xA007 204 #define YTPHY_WOL_MACADDR1_REG 0xA008 205 #define YTPHY_WOL_MACADDR0_REG 0xA009 206 207 #define YTPHY_WOL_CONFIG_REG 0xA00A 208 #define YTPHY_WCR_INTR_SEL BIT(6) 209 #define YTPHY_WCR_ENABLE BIT(3) 210 211 /* 2b00 84ms 212 * 2b01 168ms *default* 213 * 2b10 336ms 214 * 2b11 672ms 215 */ 216 #define YTPHY_WCR_PULSE_WIDTH_MASK (BIT(2) | BIT(1)) 217 #define YTPHY_WCR_PULSE_WIDTH_672MS (BIT(2) | BIT(1)) 218 219 /* 1b0 Interrupt and WOL events is level triggered and active LOW *default* 220 * 1b1 Interrupt and WOL events is pulse triggered and active LOW 221 */ 222 #define YTPHY_WCR_TYPE_PULSE BIT(0) 223 224 /* Extended Register end */ 225 226 struct yt8521_priv { 227 /* combo_advertising is used for case of YT8521 in combo mode, 228 * this means that yt8521 may work in utp or fiber mode which depends 229 * on which media is connected (YT8521_RSSR_TO_BE_ARBITRATED). 230 */ 231 __ETHTOOL_DECLARE_LINK_MODE_MASK(combo_advertising); 232 233 /* YT8521_MODE_FIBER / YT8521_MODE_UTP / YT8521_MODE_POLL*/ 234 u8 polling_mode; 235 u8 strap_mode; /* 8 working modes */ 236 /* current reg page of yt8521 phy: 237 * YT8521_RSSR_UTP_SPACE 238 * YT8521_RSSR_FIBER_SPACE 239 * YT8521_RSSR_TO_BE_ARBITRATED 240 */ 241 u8 reg_page; 242 }; 243 244 /** 245 * ytphy_read_ext() - read a PHY's extended register 246 * @phydev: a pointer to a &struct phy_device 247 * @regnum: register number to read 248 * 249 * NOTE:The caller must have taken the MDIO bus lock. 250 * 251 * returns the value of regnum reg or negative error code 252 */ 253 static int ytphy_read_ext(struct phy_device *phydev, u16 regnum) 254 { 255 int ret; 256 257 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum); 258 if (ret < 0) 259 return ret; 260 261 return __phy_read(phydev, YTPHY_PAGE_DATA); 262 } 263 264 /** 265 * ytphy_read_ext_with_lock() - read a PHY's extended register 266 * @phydev: a pointer to a &struct phy_device 267 * @regnum: register number to read 268 * 269 * returns the value of regnum reg or negative error code 270 */ 271 static int ytphy_read_ext_with_lock(struct phy_device *phydev, u16 regnum) 272 { 273 int ret; 274 275 phy_lock_mdio_bus(phydev); 276 ret = ytphy_read_ext(phydev, regnum); 277 phy_unlock_mdio_bus(phydev); 278 279 return ret; 280 } 281 282 /** 283 * ytphy_write_ext() - write a PHY's extended register 284 * @phydev: a pointer to a &struct phy_device 285 * @regnum: register number to write 286 * @val: value to write to @regnum 287 * 288 * NOTE:The caller must have taken the MDIO bus lock. 289 * 290 * returns 0 or negative error code 291 */ 292 static int ytphy_write_ext(struct phy_device *phydev, u16 regnum, u16 val) 293 { 294 int ret; 295 296 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum); 297 if (ret < 0) 298 return ret; 299 300 return __phy_write(phydev, YTPHY_PAGE_DATA, val); 301 } 302 303 /** 304 * ytphy_write_ext_with_lock() - write a PHY's extended register 305 * @phydev: a pointer to a &struct phy_device 306 * @regnum: register number to write 307 * @val: value to write to @regnum 308 * 309 * returns 0 or negative error code 310 */ 311 static int ytphy_write_ext_with_lock(struct phy_device *phydev, u16 regnum, 312 u16 val) 313 { 314 int ret; 315 316 phy_lock_mdio_bus(phydev); 317 ret = ytphy_write_ext(phydev, regnum, val); 318 phy_unlock_mdio_bus(phydev); 319 320 return ret; 321 } 322 323 /** 324 * ytphy_modify_ext() - bits modify a PHY's extended register 325 * @phydev: a pointer to a &struct phy_device 326 * @regnum: register number to write 327 * @mask: bit mask of bits to clear 328 * @set: bit mask of bits to set 329 * 330 * NOTE: Convenience function which allows a PHY's extended register to be 331 * modified as new register value = (old register value & ~mask) | set. 332 * The caller must have taken the MDIO bus lock. 333 * 334 * returns 0 or negative error code 335 */ 336 static int ytphy_modify_ext(struct phy_device *phydev, u16 regnum, u16 mask, 337 u16 set) 338 { 339 int ret; 340 341 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum); 342 if (ret < 0) 343 return ret; 344 345 return __phy_modify(phydev, YTPHY_PAGE_DATA, mask, set); 346 } 347 348 /** 349 * ytphy_modify_ext_with_lock() - bits modify a PHY's extended register 350 * @phydev: a pointer to a &struct phy_device 351 * @regnum: register number to write 352 * @mask: bit mask of bits to clear 353 * @set: bit mask of bits to set 354 * 355 * NOTE: Convenience function which allows a PHY's extended register to be 356 * modified as new register value = (old register value & ~mask) | set. 357 * 358 * returns 0 or negative error code 359 */ 360 static int ytphy_modify_ext_with_lock(struct phy_device *phydev, u16 regnum, 361 u16 mask, u16 set) 362 { 363 int ret; 364 365 phy_lock_mdio_bus(phydev); 366 ret = ytphy_modify_ext(phydev, regnum, mask, set); 367 phy_unlock_mdio_bus(phydev); 368 369 return ret; 370 } 371 372 /** 373 * ytphy_get_wol() - report whether wake-on-lan is enabled 374 * @phydev: a pointer to a &struct phy_device 375 * @wol: a pointer to a &struct ethtool_wolinfo 376 * 377 * NOTE: YTPHY_WOL_CONFIG_REG is common ext reg. 378 */ 379 static void ytphy_get_wol(struct phy_device *phydev, 380 struct ethtool_wolinfo *wol) 381 { 382 int wol_config; 383 384 wol->supported = WAKE_MAGIC; 385 wol->wolopts = 0; 386 387 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG); 388 if (wol_config < 0) 389 return; 390 391 if (wol_config & YTPHY_WCR_ENABLE) 392 wol->wolopts |= WAKE_MAGIC; 393 } 394 395 /** 396 * ytphy_set_wol() - turn wake-on-lan on or off 397 * @phydev: a pointer to a &struct phy_device 398 * @wol: a pointer to a &struct ethtool_wolinfo 399 * 400 * NOTE: YTPHY_WOL_CONFIG_REG, YTPHY_WOL_MACADDR2_REG, YTPHY_WOL_MACADDR1_REG 401 * and YTPHY_WOL_MACADDR0_REG are common ext reg. The 402 * YTPHY_INTERRUPT_ENABLE_REG of UTP is special, fiber also use this register. 403 * 404 * returns 0 or negative errno code 405 */ 406 static int ytphy_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) 407 { 408 struct net_device *p_attached_dev; 409 const u16 mac_addr_reg[] = { 410 YTPHY_WOL_MACADDR2_REG, 411 YTPHY_WOL_MACADDR1_REG, 412 YTPHY_WOL_MACADDR0_REG, 413 }; 414 const u8 *mac_addr; 415 int old_page; 416 int ret = 0; 417 u16 mask; 418 u16 val; 419 u8 i; 420 421 if (wol->wolopts & WAKE_MAGIC) { 422 p_attached_dev = phydev->attached_dev; 423 if (!p_attached_dev) 424 return -ENODEV; 425 426 mac_addr = (const u8 *)p_attached_dev->dev_addr; 427 if (!is_valid_ether_addr(mac_addr)) 428 return -EINVAL; 429 430 /* lock mdio bus then switch to utp reg space */ 431 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE); 432 if (old_page < 0) 433 goto err_restore_page; 434 435 /* Store the device address for the magic packet */ 436 for (i = 0; i < 3; i++) { 437 ret = ytphy_write_ext(phydev, mac_addr_reg[i], 438 ((mac_addr[i * 2] << 8)) | 439 (mac_addr[i * 2 + 1])); 440 if (ret < 0) 441 goto err_restore_page; 442 } 443 444 /* Enable WOL feature */ 445 mask = YTPHY_WCR_PULSE_WIDTH_MASK | YTPHY_WCR_INTR_SEL; 446 val = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL; 447 val |= YTPHY_WCR_TYPE_PULSE | YTPHY_WCR_PULSE_WIDTH_672MS; 448 ret = ytphy_modify_ext(phydev, YTPHY_WOL_CONFIG_REG, mask, val); 449 if (ret < 0) 450 goto err_restore_page; 451 452 /* Enable WOL interrupt */ 453 ret = __phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 0, 454 YTPHY_IER_WOL); 455 if (ret < 0) 456 goto err_restore_page; 457 458 } else { 459 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE); 460 if (old_page < 0) 461 goto err_restore_page; 462 463 /* Disable WOL feature */ 464 mask = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL; 465 ret = ytphy_modify_ext(phydev, YTPHY_WOL_CONFIG_REG, mask, 0); 466 467 /* Disable WOL interrupt */ 468 ret = __phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 469 YTPHY_IER_WOL, 0); 470 if (ret < 0) 471 goto err_restore_page; 472 } 473 474 err_restore_page: 475 return phy_restore_page(phydev, old_page, ret); 476 } 477 478 static int yt8511_read_page(struct phy_device *phydev) 479 { 480 return __phy_read(phydev, YT8511_PAGE_SELECT); 481 }; 482 483 static int yt8511_write_page(struct phy_device *phydev, int page) 484 { 485 return __phy_write(phydev, YT8511_PAGE_SELECT, page); 486 }; 487 488 static int yt8511_config_init(struct phy_device *phydev) 489 { 490 int oldpage, ret = 0; 491 unsigned int ge, fe; 492 493 oldpage = phy_select_page(phydev, YT8511_EXT_CLK_GATE); 494 if (oldpage < 0) 495 goto err_restore_page; 496 497 /* set rgmii delay mode */ 498 switch (phydev->interface) { 499 case PHY_INTERFACE_MODE_RGMII: 500 ge = YT8511_DELAY_GE_TX_DIS; 501 fe = YT8511_DELAY_FE_TX_DIS; 502 break; 503 case PHY_INTERFACE_MODE_RGMII_RXID: 504 ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_DIS; 505 fe = YT8511_DELAY_FE_TX_DIS; 506 break; 507 case PHY_INTERFACE_MODE_RGMII_TXID: 508 ge = YT8511_DELAY_GE_TX_EN; 509 fe = YT8511_DELAY_FE_TX_EN; 510 break; 511 case PHY_INTERFACE_MODE_RGMII_ID: 512 ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN; 513 fe = YT8511_DELAY_FE_TX_EN; 514 break; 515 default: /* do not support other modes */ 516 ret = -EOPNOTSUPP; 517 goto err_restore_page; 518 } 519 520 ret = __phy_modify(phydev, YT8511_PAGE, (YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN), ge); 521 if (ret < 0) 522 goto err_restore_page; 523 524 /* set clock mode to 125mhz */ 525 ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_CLK_125M); 526 if (ret < 0) 527 goto err_restore_page; 528 529 /* fast ethernet delay is in a separate page */ 530 ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_DELAY_DRIVE); 531 if (ret < 0) 532 goto err_restore_page; 533 534 ret = __phy_modify(phydev, YT8511_PAGE, YT8511_DELAY_FE_TX_EN, fe); 535 if (ret < 0) 536 goto err_restore_page; 537 538 /* leave pll enabled in sleep */ 539 ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_SLEEP_CTRL); 540 if (ret < 0) 541 goto err_restore_page; 542 543 ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_PLLON_SLP); 544 if (ret < 0) 545 goto err_restore_page; 546 547 err_restore_page: 548 return phy_restore_page(phydev, oldpage, ret); 549 } 550 551 /** 552 * yt8521_read_page() - read reg page 553 * @phydev: a pointer to a &struct phy_device 554 * 555 * returns current reg space of yt8521 (YT8521_RSSR_FIBER_SPACE/ 556 * YT8521_RSSR_UTP_SPACE) or negative errno code 557 */ 558 static int yt8521_read_page(struct phy_device *phydev) 559 { 560 int old_page; 561 562 old_page = ytphy_read_ext(phydev, YT8521_REG_SPACE_SELECT_REG); 563 if (old_page < 0) 564 return old_page; 565 566 if ((old_page & YT8521_RSSR_SPACE_MASK) == YT8521_RSSR_FIBER_SPACE) 567 return YT8521_RSSR_FIBER_SPACE; 568 569 return YT8521_RSSR_UTP_SPACE; 570 }; 571 572 /** 573 * yt8521_write_page() - write reg page 574 * @phydev: a pointer to a &struct phy_device 575 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to write. 576 * 577 * returns 0 or negative errno code 578 */ 579 static int yt8521_write_page(struct phy_device *phydev, int page) 580 { 581 int mask = YT8521_RSSR_SPACE_MASK; 582 int set; 583 584 if ((page & YT8521_RSSR_SPACE_MASK) == YT8521_RSSR_FIBER_SPACE) 585 set = YT8521_RSSR_FIBER_SPACE; 586 else 587 set = YT8521_RSSR_UTP_SPACE; 588 589 return ytphy_modify_ext(phydev, YT8521_REG_SPACE_SELECT_REG, mask, set); 590 }; 591 592 /** 593 * yt8521_probe() - read chip config then set suitable polling_mode 594 * @phydev: a pointer to a &struct phy_device 595 * 596 * returns 0 or negative errno code 597 */ 598 static int yt8521_probe(struct phy_device *phydev) 599 { 600 struct device *dev = &phydev->mdio.dev; 601 struct yt8521_priv *priv; 602 int chip_config; 603 int ret; 604 605 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 606 if (!priv) 607 return -ENOMEM; 608 609 phydev->priv = priv; 610 611 chip_config = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG); 612 if (chip_config < 0) 613 return chip_config; 614 615 priv->strap_mode = chip_config & YT8521_CCR_MODE_SEL_MASK; 616 switch (priv->strap_mode) { 617 case YT8521_CCR_MODE_FIBER_TO_RGMII: 618 case YT8521_CCR_MODE_SGPHY_TO_RGMAC: 619 case YT8521_CCR_MODE_SGMAC_TO_RGPHY: 620 priv->polling_mode = YT8521_MODE_FIBER; 621 priv->reg_page = YT8521_RSSR_FIBER_SPACE; 622 phydev->port = PORT_FIBRE; 623 break; 624 case YT8521_CCR_MODE_UTP_FIBER_TO_RGMII: 625 case YT8521_CCR_MODE_UTP_TO_FIBER_AUTO: 626 case YT8521_CCR_MODE_UTP_TO_FIBER_FORCE: 627 priv->polling_mode = YT8521_MODE_POLL; 628 priv->reg_page = YT8521_RSSR_TO_BE_ARBITRATED; 629 phydev->port = PORT_NONE; 630 break; 631 case YT8521_CCR_MODE_UTP_TO_SGMII: 632 case YT8521_CCR_MODE_UTP_TO_RGMII: 633 priv->polling_mode = YT8521_MODE_UTP; 634 priv->reg_page = YT8521_RSSR_UTP_SPACE; 635 phydev->port = PORT_TP; 636 break; 637 } 638 /* set default reg space */ 639 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 640 ret = ytphy_write_ext_with_lock(phydev, 641 YT8521_REG_SPACE_SELECT_REG, 642 priv->reg_page); 643 if (ret < 0) 644 return ret; 645 } 646 647 return 0; 648 } 649 650 /** 651 * ytphy_utp_read_lpa() - read LPA then setup lp_advertising for utp 652 * @phydev: a pointer to a &struct phy_device 653 * 654 * NOTE:The caller must have taken the MDIO bus lock. 655 * 656 * returns 0 or negative errno code 657 */ 658 static int ytphy_utp_read_lpa(struct phy_device *phydev) 659 { 660 int lpa, lpagb; 661 662 if (phydev->autoneg == AUTONEG_ENABLE) { 663 if (!phydev->autoneg_complete) { 664 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, 665 0); 666 mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 667 return 0; 668 } 669 670 if (phydev->is_gigabit_capable) { 671 lpagb = __phy_read(phydev, MII_STAT1000); 672 if (lpagb < 0) 673 return lpagb; 674 675 if (lpagb & LPA_1000MSFAIL) { 676 int adv = __phy_read(phydev, MII_CTRL1000); 677 678 if (adv < 0) 679 return adv; 680 681 if (adv & CTL1000_ENABLE_MASTER) 682 phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n"); 683 else 684 phydev_err(phydev, "Master/Slave resolution failed\n"); 685 return -ENOLINK; 686 } 687 688 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, 689 lpagb); 690 } 691 692 lpa = __phy_read(phydev, MII_LPA); 693 if (lpa < 0) 694 return lpa; 695 696 mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, lpa); 697 } else { 698 linkmode_zero(phydev->lp_advertising); 699 } 700 701 return 0; 702 } 703 704 /** 705 * yt8521_adjust_status() - update speed and duplex to phydev. when in fiber 706 * mode, adjust speed and duplex. 707 * @phydev: a pointer to a &struct phy_device 708 * @status: yt8521 status read from YTPHY_SPECIFIC_STATUS_REG 709 * @is_utp: false(yt8521 work in fiber mode) or true(yt8521 work in utp mode) 710 * 711 * NOTE:The caller must have taken the MDIO bus lock. 712 * 713 * returns 0 714 */ 715 static int yt8521_adjust_status(struct phy_device *phydev, int status, 716 bool is_utp) 717 { 718 int speed_mode, duplex; 719 int speed; 720 int err; 721 int lpa; 722 723 if (is_utp) 724 duplex = (status & YTPHY_SSR_DUPLEX) >> YTPHY_SSR_DUPLEX_OFFSET; 725 else 726 duplex = DUPLEX_FULL; /* for fiber, it always DUPLEX_FULL */ 727 728 speed_mode = (status & YTPHY_SSR_SPEED_MODE_MASK) >> 729 YTPHY_SSR_SPEED_MODE_OFFSET; 730 731 switch (speed_mode) { 732 case YTPHY_SSR_SPEED_10M: 733 if (is_utp) 734 speed = SPEED_10; 735 else 736 /* for fiber, it will never run here, default to 737 * SPEED_UNKNOWN 738 */ 739 speed = SPEED_UNKNOWN; 740 break; 741 case YTPHY_SSR_SPEED_100M: 742 speed = SPEED_100; 743 break; 744 case YTPHY_SSR_SPEED_1000M: 745 speed = SPEED_1000; 746 break; 747 default: 748 speed = SPEED_UNKNOWN; 749 break; 750 } 751 752 phydev->speed = speed; 753 phydev->duplex = duplex; 754 755 if (is_utp) { 756 err = ytphy_utp_read_lpa(phydev); 757 if (err < 0) 758 return err; 759 760 phy_resolve_aneg_pause(phydev); 761 } else { 762 lpa = __phy_read(phydev, MII_LPA); 763 if (lpa < 0) 764 return lpa; 765 766 /* only support 1000baseX Full */ 767 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 768 phydev->lp_advertising, lpa & LPA_1000XFULL); 769 770 if (!(lpa & YTPHY_FLPA_PAUSE)) { 771 phydev->pause = 0; 772 phydev->asym_pause = 0; 773 } else if ((lpa & YTPHY_FLPA_ASYM_PAUSE)) { 774 phydev->pause = 1; 775 phydev->asym_pause = 1; 776 } else { 777 phydev->pause = 1; 778 phydev->asym_pause = 0; 779 } 780 } 781 782 return 0; 783 } 784 785 /** 786 * yt8521_read_status_paged() - determines the speed and duplex of one page 787 * @phydev: a pointer to a &struct phy_device 788 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to 789 * operate. 790 * 791 * returns 1 (utp or fiber link),0 (no link) or negative errno code 792 */ 793 static int yt8521_read_status_paged(struct phy_device *phydev, int page) 794 { 795 int fiber_latch_val; 796 int fiber_curr_val; 797 int old_page; 798 int ret = 0; 799 int status; 800 int link; 801 802 linkmode_zero(phydev->lp_advertising); 803 phydev->duplex = DUPLEX_UNKNOWN; 804 phydev->speed = SPEED_UNKNOWN; 805 phydev->asym_pause = 0; 806 phydev->pause = 0; 807 808 /* YT8521 has two reg space (utp/fiber) for linkup with utp/fiber 809 * respectively. but for utp/fiber combo mode, reg space should be 810 * arbitrated based on media priority. by default, utp takes 811 * priority. reg space should be properly set before read 812 * YTPHY_SPECIFIC_STATUS_REG. 813 */ 814 815 page &= YT8521_RSSR_SPACE_MASK; 816 old_page = phy_select_page(phydev, page); 817 if (old_page < 0) 818 goto err_restore_page; 819 820 /* Read YTPHY_SPECIFIC_STATUS_REG, which indicates the speed and duplex 821 * of the PHY is actually using. 822 */ 823 ret = __phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG); 824 if (ret < 0) 825 goto err_restore_page; 826 827 status = ret; 828 link = !!(status & YTPHY_SSR_LINK); 829 830 /* When PHY is in fiber mode, speed transferred from 1000Mbps to 831 * 100Mbps,there is not link down from YTPHY_SPECIFIC_STATUS_REG, so 832 * we need check MII_BMSR to identify such case. 833 */ 834 if (page == YT8521_RSSR_FIBER_SPACE) { 835 ret = __phy_read(phydev, MII_BMSR); 836 if (ret < 0) 837 goto err_restore_page; 838 839 fiber_latch_val = ret; 840 ret = __phy_read(phydev, MII_BMSR); 841 if (ret < 0) 842 goto err_restore_page; 843 844 fiber_curr_val = ret; 845 if (link && fiber_latch_val != fiber_curr_val) { 846 link = 0; 847 phydev_info(phydev, 848 "%s, fiber link down detect, latch = %04x, curr = %04x\n", 849 __func__, fiber_latch_val, fiber_curr_val); 850 } 851 } else { 852 /* Read autonegotiation status */ 853 ret = __phy_read(phydev, MII_BMSR); 854 if (ret < 0) 855 goto err_restore_page; 856 857 phydev->autoneg_complete = ret & BMSR_ANEGCOMPLETE ? 1 : 0; 858 } 859 860 if (link) { 861 if (page == YT8521_RSSR_UTP_SPACE) 862 yt8521_adjust_status(phydev, status, true); 863 else 864 yt8521_adjust_status(phydev, status, false); 865 } 866 return phy_restore_page(phydev, old_page, link); 867 868 err_restore_page: 869 return phy_restore_page(phydev, old_page, ret); 870 } 871 872 /** 873 * yt8521_read_status() - determines the negotiated speed and duplex 874 * @phydev: a pointer to a &struct phy_device 875 * 876 * returns 0 or negative errno code 877 */ 878 static int yt8521_read_status(struct phy_device *phydev) 879 { 880 struct yt8521_priv *priv = phydev->priv; 881 int link_fiber = 0; 882 int link_utp; 883 int link; 884 int ret; 885 886 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 887 link = yt8521_read_status_paged(phydev, priv->reg_page); 888 if (link < 0) 889 return link; 890 } else { 891 /* when page is YT8521_RSSR_TO_BE_ARBITRATED, arbitration is 892 * needed. by default, utp is higher priority. 893 */ 894 895 link_utp = yt8521_read_status_paged(phydev, 896 YT8521_RSSR_UTP_SPACE); 897 if (link_utp < 0) 898 return link_utp; 899 900 if (!link_utp) { 901 link_fiber = yt8521_read_status_paged(phydev, 902 YT8521_RSSR_FIBER_SPACE); 903 if (link_fiber < 0) 904 return link_fiber; 905 } 906 907 link = link_utp || link_fiber; 908 } 909 910 if (link) { 911 if (phydev->link == 0) { 912 /* arbitrate reg space based on linkup media type. */ 913 if (priv->polling_mode == YT8521_MODE_POLL && 914 priv->reg_page == YT8521_RSSR_TO_BE_ARBITRATED) { 915 if (link_fiber) 916 priv->reg_page = 917 YT8521_RSSR_FIBER_SPACE; 918 else 919 priv->reg_page = YT8521_RSSR_UTP_SPACE; 920 921 ret = ytphy_write_ext_with_lock(phydev, 922 YT8521_REG_SPACE_SELECT_REG, 923 priv->reg_page); 924 if (ret < 0) 925 return ret; 926 927 phydev->port = link_fiber ? PORT_FIBRE : PORT_TP; 928 929 phydev_info(phydev, "%s, link up, media: %s\n", 930 __func__, 931 (phydev->port == PORT_TP) ? 932 "UTP" : "Fiber"); 933 } 934 } 935 phydev->link = 1; 936 } else { 937 if (phydev->link == 1) { 938 phydev_info(phydev, "%s, link down, media: %s\n", 939 __func__, (phydev->port == PORT_TP) ? 940 "UTP" : "Fiber"); 941 942 /* When in YT8521_MODE_POLL mode, need prepare for next 943 * arbitration. 944 */ 945 if (priv->polling_mode == YT8521_MODE_POLL) { 946 priv->reg_page = YT8521_RSSR_TO_BE_ARBITRATED; 947 phydev->port = PORT_NONE; 948 } 949 } 950 951 phydev->link = 0; 952 } 953 954 return 0; 955 } 956 957 /** 958 * yt8521_modify_bmcr_paged - bits modify a PHY's BMCR register of one page 959 * @phydev: the phy_device struct 960 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to operate 961 * @mask: bit mask of bits to clear 962 * @set: bit mask of bits to set 963 * 964 * NOTE: Convenience function which allows a PHY's BMCR register to be 965 * modified as new register value = (old register value & ~mask) | set. 966 * YT8521 has two space (utp/fiber) and three mode (utp/fiber/poll), each space 967 * has MII_BMCR. poll mode combines utp and faber,so need do both. 968 * If it is reset, it will wait for completion. 969 * 970 * returns 0 or negative errno code 971 */ 972 static int yt8521_modify_bmcr_paged(struct phy_device *phydev, int page, 973 u16 mask, u16 set) 974 { 975 int max_cnt = 500; /* the max wait time of reset ~ 500 ms */ 976 int old_page; 977 int ret = 0; 978 979 old_page = phy_select_page(phydev, page & YT8521_RSSR_SPACE_MASK); 980 if (old_page < 0) 981 goto err_restore_page; 982 983 ret = __phy_modify(phydev, MII_BMCR, mask, set); 984 if (ret < 0) 985 goto err_restore_page; 986 987 /* If it is reset, need to wait for the reset to complete */ 988 if (set == BMCR_RESET) { 989 while (max_cnt--) { 990 usleep_range(1000, 1100); 991 ret = __phy_read(phydev, MII_BMCR); 992 if (ret < 0) 993 goto err_restore_page; 994 995 if (!(ret & BMCR_RESET)) 996 return phy_restore_page(phydev, old_page, 0); 997 } 998 } 999 1000 err_restore_page: 1001 return phy_restore_page(phydev, old_page, ret); 1002 } 1003 1004 /** 1005 * yt8521_modify_utp_fiber_bmcr - bits modify a PHY's BMCR register 1006 * @phydev: the phy_device struct 1007 * @mask: bit mask of bits to clear 1008 * @set: bit mask of bits to set 1009 * 1010 * NOTE: Convenience function which allows a PHY's BMCR register to be 1011 * modified as new register value = (old register value & ~mask) | set. 1012 * YT8521 has two space (utp/fiber) and three mode (utp/fiber/poll), each space 1013 * has MII_BMCR. poll mode combines utp and faber,so need do both. 1014 * 1015 * returns 0 or negative errno code 1016 */ 1017 static int yt8521_modify_utp_fiber_bmcr(struct phy_device *phydev, u16 mask, 1018 u16 set) 1019 { 1020 struct yt8521_priv *priv = phydev->priv; 1021 int ret; 1022 1023 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 1024 ret = yt8521_modify_bmcr_paged(phydev, priv->reg_page, mask, 1025 set); 1026 if (ret < 0) 1027 return ret; 1028 } else { 1029 ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_UTP_SPACE, 1030 mask, set); 1031 if (ret < 0) 1032 return ret; 1033 1034 ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_FIBER_SPACE, 1035 mask, set); 1036 if (ret < 0) 1037 return ret; 1038 } 1039 return 0; 1040 } 1041 1042 /** 1043 * yt8521_soft_reset() - called to issue a PHY software reset 1044 * @phydev: a pointer to a &struct phy_device 1045 * 1046 * returns 0 or negative errno code 1047 */ 1048 static int yt8521_soft_reset(struct phy_device *phydev) 1049 { 1050 return yt8521_modify_utp_fiber_bmcr(phydev, 0, BMCR_RESET); 1051 } 1052 1053 /** 1054 * yt8521_suspend() - suspend the hardware 1055 * @phydev: a pointer to a &struct phy_device 1056 * 1057 * returns 0 or negative errno code 1058 */ 1059 static int yt8521_suspend(struct phy_device *phydev) 1060 { 1061 int wol_config; 1062 1063 /* YTPHY_WOL_CONFIG_REG is common ext reg */ 1064 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG); 1065 if (wol_config < 0) 1066 return wol_config; 1067 1068 /* if wol enable, do nothing */ 1069 if (wol_config & YTPHY_WCR_ENABLE) 1070 return 0; 1071 1072 return yt8521_modify_utp_fiber_bmcr(phydev, 0, BMCR_PDOWN); 1073 } 1074 1075 /** 1076 * yt8521_resume() - resume the hardware 1077 * @phydev: a pointer to a &struct phy_device 1078 * 1079 * returns 0 or negative errno code 1080 */ 1081 static int yt8521_resume(struct phy_device *phydev) 1082 { 1083 int ret; 1084 int wol_config; 1085 1086 /* disable auto sleep */ 1087 ret = ytphy_modify_ext_with_lock(phydev, 1088 YT8521_EXTREG_SLEEP_CONTROL1_REG, 1089 YT8521_ESC1R_SLEEP_SW, 0); 1090 if (ret < 0) 1091 return ret; 1092 1093 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG); 1094 if (wol_config < 0) 1095 return wol_config; 1096 1097 /* if wol enable, do nothing */ 1098 if (wol_config & YTPHY_WCR_ENABLE) 1099 return 0; 1100 1101 return yt8521_modify_utp_fiber_bmcr(phydev, BMCR_PDOWN, 0); 1102 } 1103 1104 /** 1105 * yt8521_config_init() - called to initialize the PHY 1106 * @phydev: a pointer to a &struct phy_device 1107 * 1108 * returns 0 or negative errno code 1109 */ 1110 static int yt8521_config_init(struct phy_device *phydev) 1111 { 1112 int old_page; 1113 int ret = 0; 1114 u16 val; 1115 1116 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE); 1117 if (old_page < 0) 1118 goto err_restore_page; 1119 1120 switch (phydev->interface) { 1121 case PHY_INTERFACE_MODE_RGMII: 1122 val = YT8521_RC1R_GE_TX_DELAY_DIS | YT8521_RC1R_GE_TX_DELAY_DIS; 1123 val |= YT8521_RC1R_RX_DELAY_DIS; 1124 break; 1125 case PHY_INTERFACE_MODE_RGMII_RXID: 1126 val = YT8521_RC1R_GE_TX_DELAY_DIS | YT8521_RC1R_GE_TX_DELAY_DIS; 1127 val |= YT8521_RC1R_RX_DELAY_EN; 1128 break; 1129 case PHY_INTERFACE_MODE_RGMII_TXID: 1130 val = YT8521_RC1R_GE_TX_DELAY_EN | YT8521_RC1R_GE_TX_DELAY_EN; 1131 val |= YT8521_RC1R_RX_DELAY_DIS; 1132 break; 1133 case PHY_INTERFACE_MODE_RGMII_ID: 1134 val = YT8521_RC1R_GE_TX_DELAY_EN | YT8521_RC1R_GE_TX_DELAY_EN; 1135 val |= YT8521_RC1R_RX_DELAY_EN; 1136 break; 1137 case PHY_INTERFACE_MODE_SGMII: 1138 break; 1139 default: /* do not support other modes */ 1140 ret = -EOPNOTSUPP; 1141 goto err_restore_page; 1142 } 1143 1144 /* set rgmii delay mode */ 1145 if (phydev->interface != PHY_INTERFACE_MODE_SGMII) { 1146 ret = ytphy_modify_ext(phydev, YT8521_RGMII_CONFIG1_REG, 1147 (YT8521_RC1R_RX_DELAY_MASK | 1148 YT8521_RC1R_FE_TX_DELAY_MASK | 1149 YT8521_RC1R_GE_TX_DELAY_MASK), 1150 val); 1151 if (ret < 0) 1152 goto err_restore_page; 1153 } 1154 1155 /* disable auto sleep */ 1156 ret = ytphy_modify_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1_REG, 1157 YT8521_ESC1R_SLEEP_SW, 0); 1158 if (ret < 0) 1159 goto err_restore_page; 1160 1161 /* enable RXC clock when no wire plug */ 1162 ret = ytphy_modify_ext(phydev, YT8521_CLOCK_GATING_REG, 1163 YT8521_CGR_RX_CLK_EN, 0); 1164 if (ret < 0) 1165 goto err_restore_page; 1166 1167 err_restore_page: 1168 return phy_restore_page(phydev, old_page, ret); 1169 } 1170 1171 /** 1172 * yt8521_prepare_fiber_features() - A small helper function that setup 1173 * fiber's features. 1174 * @phydev: a pointer to a &struct phy_device 1175 * @dst: a pointer to store fiber's features 1176 */ 1177 static void yt8521_prepare_fiber_features(struct phy_device *phydev, 1178 unsigned long *dst) 1179 { 1180 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, dst); 1181 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, dst); 1182 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, dst); 1183 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, dst); 1184 } 1185 1186 /** 1187 * yt8521_fiber_setup_forced - configures/forces speed from @phydev 1188 * @phydev: target phy_device struct 1189 * 1190 * NOTE:The caller must have taken the MDIO bus lock. 1191 * 1192 * returns 0 or negative errno code 1193 */ 1194 static int yt8521_fiber_setup_forced(struct phy_device *phydev) 1195 { 1196 u16 val; 1197 int ret; 1198 1199 if (phydev->speed == SPEED_1000) 1200 val = YTPHY_MCR_FIBER_1000BX; 1201 else if (phydev->speed == SPEED_100) 1202 val = YTPHY_MCR_FIBER_100FX; 1203 else 1204 return -EINVAL; 1205 1206 ret = __phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); 1207 if (ret < 0) 1208 return ret; 1209 1210 /* disable Fiber auto sensing */ 1211 ret = ytphy_modify_ext(phydev, YT8521_LINK_TIMER_CFG2_REG, 1212 YT8521_LTCR_EN_AUTOSEN, 0); 1213 if (ret < 0) 1214 return ret; 1215 1216 ret = ytphy_modify_ext(phydev, YTPHY_MISC_CONFIG_REG, 1217 YTPHY_MCR_FIBER_SPEED_MASK, val); 1218 if (ret < 0) 1219 return ret; 1220 1221 return ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG, 1222 YT8521_CCR_SW_RST, 0); 1223 } 1224 1225 /** 1226 * ytphy_check_and_restart_aneg - Enable and restart auto-negotiation 1227 * @phydev: target phy_device struct 1228 * @restart: whether aneg restart is requested 1229 * 1230 * NOTE:The caller must have taken the MDIO bus lock. 1231 * 1232 * returns 0 or negative errno code 1233 */ 1234 static int ytphy_check_and_restart_aneg(struct phy_device *phydev, bool restart) 1235 { 1236 int ret; 1237 1238 if (!restart) { 1239 /* Advertisement hasn't changed, but maybe aneg was never on to 1240 * begin with? Or maybe phy was isolated? 1241 */ 1242 ret = __phy_read(phydev, MII_BMCR); 1243 if (ret < 0) 1244 return ret; 1245 1246 if (!(ret & BMCR_ANENABLE) || (ret & BMCR_ISOLATE)) 1247 restart = true; 1248 } 1249 /* Enable and Restart Autonegotiation 1250 * Don't isolate the PHY if we're negotiating 1251 */ 1252 if (restart) 1253 return __phy_modify(phydev, MII_BMCR, BMCR_ISOLATE, 1254 BMCR_ANENABLE | BMCR_ANRESTART); 1255 1256 return 0; 1257 } 1258 1259 /** 1260 * yt8521_fiber_config_aneg - restart auto-negotiation or write 1261 * YTPHY_MISC_CONFIG_REG. 1262 * @phydev: target phy_device struct 1263 * 1264 * NOTE:The caller must have taken the MDIO bus lock. 1265 * 1266 * returns 0 or negative errno code 1267 */ 1268 static int yt8521_fiber_config_aneg(struct phy_device *phydev) 1269 { 1270 int err, changed = 0; 1271 int bmcr; 1272 u16 adv; 1273 1274 if (phydev->autoneg != AUTONEG_ENABLE) 1275 return yt8521_fiber_setup_forced(phydev); 1276 1277 /* enable Fiber auto sensing */ 1278 err = ytphy_modify_ext(phydev, YT8521_LINK_TIMER_CFG2_REG, 1279 0, YT8521_LTCR_EN_AUTOSEN); 1280 if (err < 0) 1281 return err; 1282 1283 err = ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG, 1284 YT8521_CCR_SW_RST, 0); 1285 if (err < 0) 1286 return err; 1287 1288 bmcr = __phy_read(phydev, MII_BMCR); 1289 if (bmcr < 0) 1290 return bmcr; 1291 1292 /* When it is coming from fiber forced mode, add bmcr power down 1293 * and power up to let aneg work fine. 1294 */ 1295 if (!(bmcr & BMCR_ANENABLE)) { 1296 __phy_modify(phydev, MII_BMCR, 0, BMCR_PDOWN); 1297 usleep_range(1000, 1100); 1298 __phy_modify(phydev, MII_BMCR, BMCR_PDOWN, 0); 1299 } 1300 1301 adv = linkmode_adv_to_mii_adv_x(phydev->advertising, 1302 ETHTOOL_LINK_MODE_1000baseX_Full_BIT); 1303 1304 /* Setup fiber advertisement */ 1305 err = __phy_modify_changed(phydev, MII_ADVERTISE, 1306 ADVERTISE_1000XHALF | ADVERTISE_1000XFULL | 1307 ADVERTISE_1000XPAUSE | 1308 ADVERTISE_1000XPSE_ASYM, 1309 adv); 1310 if (err < 0) 1311 return err; 1312 1313 if (err > 0) 1314 changed = 1; 1315 1316 return ytphy_check_and_restart_aneg(phydev, changed); 1317 } 1318 1319 /** 1320 * ytphy_setup_master_slave 1321 * @phydev: target phy_device struct 1322 * 1323 * NOTE: The caller must have taken the MDIO bus lock. 1324 * 1325 * returns 0 or negative errno code 1326 */ 1327 static int ytphy_setup_master_slave(struct phy_device *phydev) 1328 { 1329 u16 ctl = 0; 1330 1331 if (!phydev->is_gigabit_capable) 1332 return 0; 1333 1334 switch (phydev->master_slave_set) { 1335 case MASTER_SLAVE_CFG_MASTER_PREFERRED: 1336 ctl |= CTL1000_PREFER_MASTER; 1337 break; 1338 case MASTER_SLAVE_CFG_SLAVE_PREFERRED: 1339 break; 1340 case MASTER_SLAVE_CFG_MASTER_FORCE: 1341 ctl |= CTL1000_AS_MASTER; 1342 fallthrough; 1343 case MASTER_SLAVE_CFG_SLAVE_FORCE: 1344 ctl |= CTL1000_ENABLE_MASTER; 1345 break; 1346 case MASTER_SLAVE_CFG_UNKNOWN: 1347 case MASTER_SLAVE_CFG_UNSUPPORTED: 1348 return 0; 1349 default: 1350 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 1351 return -EOPNOTSUPP; 1352 } 1353 1354 return __phy_modify_changed(phydev, MII_CTRL1000, 1355 (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER | 1356 CTL1000_PREFER_MASTER), ctl); 1357 } 1358 1359 /** 1360 * ytphy_utp_config_advert - sanitize and advertise auto-negotiation parameters 1361 * @phydev: target phy_device struct 1362 * 1363 * NOTE: Writes MII_ADVERTISE with the appropriate values, 1364 * after sanitizing the values to make sure we only advertise 1365 * what is supported. Returns < 0 on error, 0 if the PHY's advertisement 1366 * hasn't changed, and > 0 if it has changed. 1367 * The caller must have taken the MDIO bus lock. 1368 * 1369 * returns 0 or negative errno code 1370 */ 1371 static int ytphy_utp_config_advert(struct phy_device *phydev) 1372 { 1373 int err, bmsr, changed = 0; 1374 u32 adv; 1375 1376 /* Only allow advertising what this PHY supports */ 1377 linkmode_and(phydev->advertising, phydev->advertising, 1378 phydev->supported); 1379 1380 adv = linkmode_adv_to_mii_adv_t(phydev->advertising); 1381 1382 /* Setup standard advertisement */ 1383 err = __phy_modify_changed(phydev, MII_ADVERTISE, 1384 ADVERTISE_ALL | ADVERTISE_100BASE4 | 1385 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM, 1386 adv); 1387 if (err < 0) 1388 return err; 1389 if (err > 0) 1390 changed = 1; 1391 1392 bmsr = __phy_read(phydev, MII_BMSR); 1393 if (bmsr < 0) 1394 return bmsr; 1395 1396 /* Per 802.3-2008, Section 22.2.4.2.16 Extended status all 1397 * 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a 1398 * logical 1. 1399 */ 1400 if (!(bmsr & BMSR_ESTATEN)) 1401 return changed; 1402 1403 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 1404 1405 err = __phy_modify_changed(phydev, MII_CTRL1000, 1406 ADVERTISE_1000FULL | ADVERTISE_1000HALF, 1407 adv); 1408 if (err < 0) 1409 return err; 1410 if (err > 0) 1411 changed = 1; 1412 1413 return changed; 1414 } 1415 1416 /** 1417 * ytphy_utp_config_aneg - restart auto-negotiation or write BMCR 1418 * @phydev: target phy_device struct 1419 * @changed: whether autoneg is requested 1420 * 1421 * NOTE: If auto-negotiation is enabled, we configure the 1422 * advertising, and then restart auto-negotiation. If it is not 1423 * enabled, then we write the BMCR. 1424 * The caller must have taken the MDIO bus lock. 1425 * 1426 * returns 0 or negative errno code 1427 */ 1428 static int ytphy_utp_config_aneg(struct phy_device *phydev, bool changed) 1429 { 1430 int err; 1431 u16 ctl; 1432 1433 err = ytphy_setup_master_slave(phydev); 1434 if (err < 0) 1435 return err; 1436 else if (err) 1437 changed = true; 1438 1439 if (phydev->autoneg != AUTONEG_ENABLE) { 1440 /* configures/forces speed/duplex from @phydev */ 1441 1442 ctl = mii_bmcr_encode_fixed(phydev->speed, phydev->duplex); 1443 1444 return __phy_modify(phydev, MII_BMCR, ~(BMCR_LOOPBACK | 1445 BMCR_ISOLATE | BMCR_PDOWN), ctl); 1446 } 1447 1448 err = ytphy_utp_config_advert(phydev); 1449 if (err < 0) /* error */ 1450 return err; 1451 else if (err) 1452 changed = true; 1453 1454 return ytphy_check_and_restart_aneg(phydev, changed); 1455 } 1456 1457 /** 1458 * yt8521_config_aneg_paged() - switch reg space then call genphy_config_aneg 1459 * of one page 1460 * @phydev: a pointer to a &struct phy_device 1461 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to 1462 * operate. 1463 * 1464 * returns 0 or negative errno code 1465 */ 1466 static int yt8521_config_aneg_paged(struct phy_device *phydev, int page) 1467 { 1468 __ETHTOOL_DECLARE_LINK_MODE_MASK(fiber_supported); 1469 struct yt8521_priv *priv = phydev->priv; 1470 int old_page; 1471 int ret = 0; 1472 1473 page &= YT8521_RSSR_SPACE_MASK; 1474 1475 old_page = phy_select_page(phydev, page); 1476 if (old_page < 0) 1477 goto err_restore_page; 1478 1479 /* If reg_page is YT8521_RSSR_TO_BE_ARBITRATED, 1480 * phydev->advertising should be updated. 1481 */ 1482 if (priv->reg_page == YT8521_RSSR_TO_BE_ARBITRATED) { 1483 linkmode_zero(fiber_supported); 1484 yt8521_prepare_fiber_features(phydev, fiber_supported); 1485 1486 /* prepare fiber_supported, then setup advertising. */ 1487 if (page == YT8521_RSSR_FIBER_SPACE) { 1488 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 1489 fiber_supported); 1490 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 1491 fiber_supported); 1492 linkmode_and(phydev->advertising, 1493 priv->combo_advertising, fiber_supported); 1494 } else { 1495 /* ETHTOOL_LINK_MODE_Autoneg_BIT is also used in utp */ 1496 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 1497 fiber_supported); 1498 linkmode_andnot(phydev->advertising, 1499 priv->combo_advertising, 1500 fiber_supported); 1501 } 1502 } 1503 1504 if (page == YT8521_RSSR_FIBER_SPACE) 1505 ret = yt8521_fiber_config_aneg(phydev); 1506 else 1507 ret = ytphy_utp_config_aneg(phydev, false); 1508 1509 err_restore_page: 1510 return phy_restore_page(phydev, old_page, ret); 1511 } 1512 1513 /** 1514 * yt8521_config_aneg() - change reg space then call yt8521_config_aneg_paged 1515 * @phydev: a pointer to a &struct phy_device 1516 * 1517 * returns 0 or negative errno code 1518 */ 1519 static int yt8521_config_aneg(struct phy_device *phydev) 1520 { 1521 struct yt8521_priv *priv = phydev->priv; 1522 int ret; 1523 1524 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 1525 ret = yt8521_config_aneg_paged(phydev, priv->reg_page); 1526 if (ret < 0) 1527 return ret; 1528 } else { 1529 /* If reg_page is YT8521_RSSR_TO_BE_ARBITRATED, 1530 * phydev->advertising need to be saved at first run. 1531 * Because it contains the advertising which supported by both 1532 * mac and yt8521(utp and fiber). 1533 */ 1534 if (linkmode_empty(priv->combo_advertising)) { 1535 linkmode_copy(priv->combo_advertising, 1536 phydev->advertising); 1537 } 1538 1539 ret = yt8521_config_aneg_paged(phydev, YT8521_RSSR_UTP_SPACE); 1540 if (ret < 0) 1541 return ret; 1542 1543 ret = yt8521_config_aneg_paged(phydev, YT8521_RSSR_FIBER_SPACE); 1544 if (ret < 0) 1545 return ret; 1546 1547 /* we don't known which will be link, so restore 1548 * phydev->advertising as default value. 1549 */ 1550 linkmode_copy(phydev->advertising, priv->combo_advertising); 1551 } 1552 return 0; 1553 } 1554 1555 /** 1556 * yt8521_aneg_done_paged() - determines the auto negotiation result of one 1557 * page. 1558 * @phydev: a pointer to a &struct phy_device 1559 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to 1560 * operate. 1561 * 1562 * returns 0(no link)or 1(fiber or utp link) or negative errno code 1563 */ 1564 static int yt8521_aneg_done_paged(struct phy_device *phydev, int page) 1565 { 1566 int old_page; 1567 int ret = 0; 1568 int link; 1569 1570 old_page = phy_select_page(phydev, page & YT8521_RSSR_SPACE_MASK); 1571 if (old_page < 0) 1572 goto err_restore_page; 1573 1574 ret = __phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG); 1575 if (ret < 0) 1576 goto err_restore_page; 1577 1578 link = !!(ret & YTPHY_SSR_LINK); 1579 ret = link; 1580 1581 err_restore_page: 1582 return phy_restore_page(phydev, old_page, ret); 1583 } 1584 1585 /** 1586 * yt8521_aneg_done() - determines the auto negotiation result 1587 * @phydev: a pointer to a &struct phy_device 1588 * 1589 * returns 0(no link)or 1(fiber or utp link) or negative errno code 1590 */ 1591 static int yt8521_aneg_done(struct phy_device *phydev) 1592 { 1593 struct yt8521_priv *priv = phydev->priv; 1594 int link_fiber = 0; 1595 int link_utp; 1596 int link; 1597 1598 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 1599 link = yt8521_aneg_done_paged(phydev, priv->reg_page); 1600 } else { 1601 link_utp = yt8521_aneg_done_paged(phydev, 1602 YT8521_RSSR_UTP_SPACE); 1603 if (link_utp < 0) 1604 return link_utp; 1605 1606 if (!link_utp) { 1607 link_fiber = yt8521_aneg_done_paged(phydev, 1608 YT8521_RSSR_FIBER_SPACE); 1609 if (link_fiber < 0) 1610 return link_fiber; 1611 } 1612 link = link_fiber || link_utp; 1613 phydev_info(phydev, "%s, link_fiber: %d, link_utp: %d\n", 1614 __func__, link_fiber, link_utp); 1615 } 1616 1617 return link; 1618 } 1619 1620 /** 1621 * ytphy_utp_read_abilities - read PHY abilities from Clause 22 registers 1622 * @phydev: target phy_device struct 1623 * 1624 * NOTE: Reads the PHY's abilities and populates 1625 * phydev->supported accordingly. 1626 * The caller must have taken the MDIO bus lock. 1627 * 1628 * returns 0 or negative errno code 1629 */ 1630 static int ytphy_utp_read_abilities(struct phy_device *phydev) 1631 { 1632 int val; 1633 1634 linkmode_set_bit_array(phy_basic_ports_array, 1635 ARRAY_SIZE(phy_basic_ports_array), 1636 phydev->supported); 1637 1638 val = __phy_read(phydev, MII_BMSR); 1639 if (val < 0) 1640 return val; 1641 1642 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported, 1643 val & BMSR_ANEGCAPABLE); 1644 1645 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, phydev->supported, 1646 val & BMSR_100FULL); 1647 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, phydev->supported, 1648 val & BMSR_100HALF); 1649 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, phydev->supported, 1650 val & BMSR_10FULL); 1651 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, phydev->supported, 1652 val & BMSR_10HALF); 1653 1654 if (val & BMSR_ESTATEN) { 1655 val = __phy_read(phydev, MII_ESTATUS); 1656 if (val < 0) 1657 return val; 1658 1659 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1660 phydev->supported, val & ESTATUS_1000_TFULL); 1661 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 1662 phydev->supported, val & ESTATUS_1000_THALF); 1663 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1664 phydev->supported, val & ESTATUS_1000_XFULL); 1665 } 1666 1667 return 0; 1668 } 1669 1670 /** 1671 * yt8521_get_features_paged() - read supported link modes for one page 1672 * @phydev: a pointer to a &struct phy_device 1673 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to 1674 * operate. 1675 * 1676 * returns 0 or negative errno code 1677 */ 1678 static int yt8521_get_features_paged(struct phy_device *phydev, int page) 1679 { 1680 int old_page; 1681 int ret = 0; 1682 1683 page &= YT8521_RSSR_SPACE_MASK; 1684 old_page = phy_select_page(phydev, page); 1685 if (old_page < 0) 1686 goto err_restore_page; 1687 1688 if (page == YT8521_RSSR_FIBER_SPACE) { 1689 linkmode_zero(phydev->supported); 1690 yt8521_prepare_fiber_features(phydev, phydev->supported); 1691 } else { 1692 ret = ytphy_utp_read_abilities(phydev); 1693 if (ret < 0) 1694 goto err_restore_page; 1695 } 1696 1697 err_restore_page: 1698 return phy_restore_page(phydev, old_page, ret); 1699 } 1700 1701 /** 1702 * yt8521_get_features - switch reg space then call yt8521_get_features_paged 1703 * @phydev: target phy_device struct 1704 * 1705 * returns 0 or negative errno code 1706 */ 1707 static int yt8521_get_features(struct phy_device *phydev) 1708 { 1709 struct yt8521_priv *priv = phydev->priv; 1710 int ret; 1711 1712 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 1713 ret = yt8521_get_features_paged(phydev, priv->reg_page); 1714 } else { 1715 ret = yt8521_get_features_paged(phydev, 1716 YT8521_RSSR_UTP_SPACE); 1717 if (ret < 0) 1718 return ret; 1719 1720 /* add fiber's features to phydev->supported */ 1721 yt8521_prepare_fiber_features(phydev, phydev->supported); 1722 } 1723 return ret; 1724 } 1725 1726 static struct phy_driver motorcomm_phy_drvs[] = { 1727 { 1728 PHY_ID_MATCH_EXACT(PHY_ID_YT8511), 1729 .name = "YT8511 Gigabit Ethernet", 1730 .config_init = yt8511_config_init, 1731 .suspend = genphy_suspend, 1732 .resume = genphy_resume, 1733 .read_page = yt8511_read_page, 1734 .write_page = yt8511_write_page, 1735 }, 1736 { 1737 PHY_ID_MATCH_EXACT(PHY_ID_YT8521), 1738 .name = "YT8521 Gigabit Ethernet", 1739 .get_features = yt8521_get_features, 1740 .probe = yt8521_probe, 1741 .read_page = yt8521_read_page, 1742 .write_page = yt8521_write_page, 1743 .get_wol = ytphy_get_wol, 1744 .set_wol = ytphy_set_wol, 1745 .config_aneg = yt8521_config_aneg, 1746 .aneg_done = yt8521_aneg_done, 1747 .config_init = yt8521_config_init, 1748 .read_status = yt8521_read_status, 1749 .soft_reset = yt8521_soft_reset, 1750 .suspend = yt8521_suspend, 1751 .resume = yt8521_resume, 1752 }, 1753 }; 1754 1755 module_phy_driver(motorcomm_phy_drvs); 1756 1757 MODULE_DESCRIPTION("Motorcomm 8511/8521 PHY driver"); 1758 MODULE_AUTHOR("Peter Geis"); 1759 MODULE_AUTHOR("Frank"); 1760 MODULE_LICENSE("GPL"); 1761 1762 static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = { 1763 { PHY_ID_MATCH_EXACT(PHY_ID_YT8511) }, 1764 { PHY_ID_MATCH_EXACT(PHY_ID_YT8521) }, 1765 { /* sentinal */ } 1766 }; 1767 1768 MODULE_DEVICE_TABLE(mdio, motorcomm_tbl); 1769