1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2015 Microchip Technology 4 */ 5 #include <linux/kernel.h> 6 #include <linux/module.h> 7 #include <linux/mii.h> 8 #include <linux/ethtool.h> 9 #include <linux/phy.h> 10 #include <linux/microchipphy.h> 11 #include <linux/delay.h> 12 #include <linux/of.h> 13 #include <dt-bindings/net/microchip-lan78xx.h> 14 15 #define DRIVER_AUTHOR "WOOJUNG HUH <woojung.huh@microchip.com>" 16 #define DRIVER_DESC "Microchip LAN88XX PHY driver" 17 18 struct lan88xx_priv { 19 int chip_id; 20 int chip_rev; 21 __u32 wolopts; 22 }; 23 24 static int lan88xx_read_page(struct phy_device *phydev) 25 { 26 return __phy_read(phydev, LAN88XX_EXT_PAGE_ACCESS); 27 } 28 29 static int lan88xx_write_page(struct phy_device *phydev, int page) 30 { 31 return __phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, page); 32 } 33 34 static int lan88xx_phy_config_intr(struct phy_device *phydev) 35 { 36 int rc; 37 38 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 39 /* unmask all source and clear them before enable */ 40 rc = phy_write(phydev, LAN88XX_INT_MASK, 0x7FFF); 41 rc = phy_read(phydev, LAN88XX_INT_STS); 42 rc = phy_write(phydev, LAN88XX_INT_MASK, 43 LAN88XX_INT_MASK_MDINTPIN_EN_ | 44 LAN88XX_INT_MASK_LINK_CHANGE_); 45 } else { 46 rc = phy_write(phydev, LAN88XX_INT_MASK, 0); 47 } 48 49 return rc < 0 ? rc : 0; 50 } 51 52 static int lan88xx_phy_ack_interrupt(struct phy_device *phydev) 53 { 54 int rc = phy_read(phydev, LAN88XX_INT_STS); 55 56 return rc < 0 ? rc : 0; 57 } 58 59 static int lan88xx_suspend(struct phy_device *phydev) 60 { 61 struct lan88xx_priv *priv = phydev->priv; 62 63 /* do not power down PHY when WOL is enabled */ 64 if (!priv->wolopts) 65 genphy_suspend(phydev); 66 67 return 0; 68 } 69 70 static int lan88xx_TR_reg_set(struct phy_device *phydev, u16 regaddr, 71 u32 data) 72 { 73 int val, save_page, ret = 0; 74 u16 buf; 75 76 /* Save current page */ 77 save_page = phy_save_page(phydev); 78 if (save_page < 0) { 79 phydev_warn(phydev, "Failed to get current page\n"); 80 goto err; 81 } 82 83 /* Switch to TR page */ 84 lan88xx_write_page(phydev, LAN88XX_EXT_PAGE_ACCESS_TR); 85 86 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_LOW_DATA, 87 (data & 0xFFFF)); 88 if (ret < 0) { 89 phydev_warn(phydev, "Failed to write TR low data\n"); 90 goto err; 91 } 92 93 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_HIGH_DATA, 94 (data & 0x00FF0000) >> 16); 95 if (ret < 0) { 96 phydev_warn(phydev, "Failed to write TR high data\n"); 97 goto err; 98 } 99 100 /* Config control bits [15:13] of register */ 101 buf = (regaddr & ~(0x3 << 13));/* Clr [14:13] to write data in reg */ 102 buf |= 0x8000; /* Set [15] to Packet transmit */ 103 104 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_CR, buf); 105 if (ret < 0) { 106 phydev_warn(phydev, "Failed to write data in reg\n"); 107 goto err; 108 } 109 110 usleep_range(1000, 2000);/* Wait for Data to be written */ 111 val = __phy_read(phydev, LAN88XX_EXT_PAGE_TR_CR); 112 if (!(val & 0x8000)) 113 phydev_warn(phydev, "TR Register[0x%X] configuration failed\n", 114 regaddr); 115 err: 116 return phy_restore_page(phydev, save_page, ret); 117 } 118 119 static void lan88xx_config_TR_regs(struct phy_device *phydev) 120 { 121 int err; 122 123 /* Get access to Channel 0x1, Node 0xF , Register 0x01. 124 * Write 24-bit value 0x12B00A to register. Setting MrvlTrFix1000Kf, 125 * MrvlTrFix1000Kp, MasterEnableTR bits. 126 */ 127 err = lan88xx_TR_reg_set(phydev, 0x0F82, 0x12B00A); 128 if (err < 0) 129 phydev_warn(phydev, "Failed to Set Register[0x0F82]\n"); 130 131 /* Get access to Channel b'10, Node b'1101, Register 0x06. 132 * Write 24-bit value 0xD2C46F to register. Setting SSTrKf1000Slv, 133 * SSTrKp1000Mas bits. 134 */ 135 err = lan88xx_TR_reg_set(phydev, 0x168C, 0xD2C46F); 136 if (err < 0) 137 phydev_warn(phydev, "Failed to Set Register[0x168C]\n"); 138 139 /* Get access to Channel b'10, Node b'1111, Register 0x11. 140 * Write 24-bit value 0x620 to register. Setting rem_upd_done_thresh 141 * bits 142 */ 143 err = lan88xx_TR_reg_set(phydev, 0x17A2, 0x620); 144 if (err < 0) 145 phydev_warn(phydev, "Failed to Set Register[0x17A2]\n"); 146 147 /* Get access to Channel b'10, Node b'1101, Register 0x10. 148 * Write 24-bit value 0xEEFFDD to register. Setting 149 * eee_TrKp1Long_1000, eee_TrKp2Long_1000, eee_TrKp3Long_1000, 150 * eee_TrKp1Short_1000,eee_TrKp2Short_1000, eee_TrKp3Short_1000 bits. 151 */ 152 err = lan88xx_TR_reg_set(phydev, 0x16A0, 0xEEFFDD); 153 if (err < 0) 154 phydev_warn(phydev, "Failed to Set Register[0x16A0]\n"); 155 156 /* Get access to Channel b'10, Node b'1101, Register 0x13. 157 * Write 24-bit value 0x071448 to register. Setting 158 * slv_lpi_tr_tmr_val1, slv_lpi_tr_tmr_val2 bits. 159 */ 160 err = lan88xx_TR_reg_set(phydev, 0x16A6, 0x071448); 161 if (err < 0) 162 phydev_warn(phydev, "Failed to Set Register[0x16A6]\n"); 163 164 /* Get access to Channel b'10, Node b'1101, Register 0x12. 165 * Write 24-bit value 0x13132F to register. Setting 166 * slv_sigdet_timer_val1, slv_sigdet_timer_val2 bits. 167 */ 168 err = lan88xx_TR_reg_set(phydev, 0x16A4, 0x13132F); 169 if (err < 0) 170 phydev_warn(phydev, "Failed to Set Register[0x16A4]\n"); 171 172 /* Get access to Channel b'10, Node b'1101, Register 0x14. 173 * Write 24-bit value 0x0 to register. Setting eee_3level_delay, 174 * eee_TrKf_freeze_delay bits. 175 */ 176 err = lan88xx_TR_reg_set(phydev, 0x16A8, 0x0); 177 if (err < 0) 178 phydev_warn(phydev, "Failed to Set Register[0x16A8]\n"); 179 180 /* Get access to Channel b'01, Node b'1111, Register 0x34. 181 * Write 24-bit value 0x91B06C to register. Setting 182 * FastMseSearchThreshLong1000, FastMseSearchThreshShort1000, 183 * FastMseSearchUpdGain1000 bits. 184 */ 185 err = lan88xx_TR_reg_set(phydev, 0x0FE8, 0x91B06C); 186 if (err < 0) 187 phydev_warn(phydev, "Failed to Set Register[0x0FE8]\n"); 188 189 /* Get access to Channel b'01, Node b'1111, Register 0x3E. 190 * Write 24-bit value 0xC0A028 to register. Setting 191 * FastMseKp2ThreshLong1000, FastMseKp2ThreshShort1000, 192 * FastMseKp2UpdGain1000, FastMseKp2ExitEn1000 bits. 193 */ 194 err = lan88xx_TR_reg_set(phydev, 0x0FFC, 0xC0A028); 195 if (err < 0) 196 phydev_warn(phydev, "Failed to Set Register[0x0FFC]\n"); 197 198 /* Get access to Channel b'01, Node b'1111, Register 0x35. 199 * Write 24-bit value 0x041600 to register. Setting 200 * FastMseSearchPhShNum1000, FastMseSearchClksPerPh1000, 201 * FastMsePhChangeDelay1000 bits. 202 */ 203 err = lan88xx_TR_reg_set(phydev, 0x0FEA, 0x041600); 204 if (err < 0) 205 phydev_warn(phydev, "Failed to Set Register[0x0FEA]\n"); 206 207 /* Get access to Channel b'10, Node b'1101, Register 0x03. 208 * Write 24-bit value 0x000004 to register. Setting TrFreeze bits. 209 */ 210 err = lan88xx_TR_reg_set(phydev, 0x1686, 0x000004); 211 if (err < 0) 212 phydev_warn(phydev, "Failed to Set Register[0x1686]\n"); 213 } 214 215 static int lan88xx_probe(struct phy_device *phydev) 216 { 217 struct device *dev = &phydev->mdio.dev; 218 struct lan88xx_priv *priv; 219 u32 led_modes[4]; 220 int len; 221 222 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 223 if (!priv) 224 return -ENOMEM; 225 226 priv->wolopts = 0; 227 228 len = of_property_read_variable_u32_array(dev->of_node, 229 "microchip,led-modes", 230 led_modes, 231 0, 232 ARRAY_SIZE(led_modes)); 233 if (len >= 0) { 234 u32 reg = 0; 235 int i; 236 237 for (i = 0; i < len; i++) { 238 if (led_modes[i] > 15) 239 return -EINVAL; 240 reg |= led_modes[i] << (i * 4); 241 } 242 for (; i < ARRAY_SIZE(led_modes); i++) 243 reg |= LAN78XX_FORCE_LED_OFF << (i * 4); 244 (void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg); 245 } else if (len == -EOVERFLOW) { 246 return -EINVAL; 247 } 248 249 /* these values can be used to identify internal PHY */ 250 priv->chip_id = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_ID); 251 priv->chip_rev = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_REV); 252 253 phydev->priv = priv; 254 255 return 0; 256 } 257 258 static void lan88xx_remove(struct phy_device *phydev) 259 { 260 struct device *dev = &phydev->mdio.dev; 261 struct lan88xx_priv *priv = phydev->priv; 262 263 if (priv) 264 devm_kfree(dev, priv); 265 } 266 267 static int lan88xx_set_wol(struct phy_device *phydev, 268 struct ethtool_wolinfo *wol) 269 { 270 struct lan88xx_priv *priv = phydev->priv; 271 272 priv->wolopts = wol->wolopts; 273 274 return 0; 275 } 276 277 static void lan88xx_set_mdix(struct phy_device *phydev) 278 { 279 int buf; 280 int val; 281 282 switch (phydev->mdix_ctrl) { 283 case ETH_TP_MDI: 284 val = LAN88XX_EXT_MODE_CTRL_MDI_; 285 break; 286 case ETH_TP_MDI_X: 287 val = LAN88XX_EXT_MODE_CTRL_MDI_X_; 288 break; 289 case ETH_TP_MDI_AUTO: 290 val = LAN88XX_EXT_MODE_CTRL_AUTO_MDIX_; 291 break; 292 default: 293 return; 294 } 295 296 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1); 297 buf = phy_read(phydev, LAN88XX_EXT_MODE_CTRL); 298 buf &= ~LAN88XX_EXT_MODE_CTRL_MDIX_MASK_; 299 buf |= val; 300 phy_write(phydev, LAN88XX_EXT_MODE_CTRL, buf); 301 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0); 302 } 303 304 static int lan88xx_config_init(struct phy_device *phydev) 305 { 306 int val; 307 308 genphy_config_init(phydev); 309 /*Zerodetect delay enable */ 310 val = phy_read_mmd(phydev, MDIO_MMD_PCS, 311 PHY_ARDENNES_MMD_DEV_3_PHY_CFG); 312 val |= PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_; 313 314 phy_write_mmd(phydev, MDIO_MMD_PCS, PHY_ARDENNES_MMD_DEV_3_PHY_CFG, 315 val); 316 317 /* Config DSP registers */ 318 lan88xx_config_TR_regs(phydev); 319 320 return 0; 321 } 322 323 static int lan88xx_config_aneg(struct phy_device *phydev) 324 { 325 lan88xx_set_mdix(phydev); 326 327 return genphy_config_aneg(phydev); 328 } 329 330 static struct phy_driver microchip_phy_driver[] = { 331 { 332 .phy_id = 0x0007c130, 333 .phy_id_mask = 0xfffffff0, 334 .name = "Microchip LAN88xx", 335 336 /* PHY_GBIT_FEATURES */ 337 338 .probe = lan88xx_probe, 339 .remove = lan88xx_remove, 340 341 .config_init = lan88xx_config_init, 342 .config_aneg = lan88xx_config_aneg, 343 344 .ack_interrupt = lan88xx_phy_ack_interrupt, 345 .config_intr = lan88xx_phy_config_intr, 346 347 .suspend = lan88xx_suspend, 348 .resume = genphy_resume, 349 .set_wol = lan88xx_set_wol, 350 .read_page = lan88xx_read_page, 351 .write_page = lan88xx_write_page, 352 } }; 353 354 module_phy_driver(microchip_phy_driver); 355 356 static struct mdio_device_id __maybe_unused microchip_tbl[] = { 357 { 0x0007c130, 0xfffffff0 }, 358 { } 359 }; 360 361 MODULE_DEVICE_TABLE(mdio, microchip_tbl); 362 363 MODULE_AUTHOR(DRIVER_AUTHOR); 364 MODULE_DESCRIPTION(DRIVER_DESC); 365 MODULE_LICENSE("GPL"); 366