1a2443fd1SAndrew Lunn // SPDX-License-Identifier: GPL-2.0+ 2792aec47SWoojung.Huh@microchip.com /* 3792aec47SWoojung.Huh@microchip.com * Copyright (C) 2015 Microchip Technology 4792aec47SWoojung.Huh@microchip.com */ 5792aec47SWoojung.Huh@microchip.com #include <linux/kernel.h> 6792aec47SWoojung.Huh@microchip.com #include <linux/module.h> 7792aec47SWoojung.Huh@microchip.com #include <linux/mii.h> 8792aec47SWoojung.Huh@microchip.com #include <linux/ethtool.h> 9792aec47SWoojung.Huh@microchip.com #include <linux/phy.h> 10792aec47SWoojung.Huh@microchip.com #include <linux/microchipphy.h> 111c2734b3SRaghuram Chary J #include <linux/delay.h> 121827b067SPhil Elwell #include <linux/of.h> 131827b067SPhil Elwell #include <dt-bindings/net/microchip-lan78xx.h> 14792aec47SWoojung.Huh@microchip.com 15792aec47SWoojung.Huh@microchip.com #define DRIVER_AUTHOR "WOOJUNG HUH <woojung.huh@microchip.com>" 16792aec47SWoojung.Huh@microchip.com #define DRIVER_DESC "Microchip LAN88XX PHY driver" 17792aec47SWoojung.Huh@microchip.com 18792aec47SWoojung.Huh@microchip.com struct lan88xx_priv { 19792aec47SWoojung.Huh@microchip.com int chip_id; 20792aec47SWoojung.Huh@microchip.com int chip_rev; 21792aec47SWoojung.Huh@microchip.com __u32 wolopts; 22792aec47SWoojung.Huh@microchip.com }; 23792aec47SWoojung.Huh@microchip.com 241c2734b3SRaghuram Chary J static int lan88xx_read_page(struct phy_device *phydev) 251c2734b3SRaghuram Chary J { 261c2734b3SRaghuram Chary J return __phy_read(phydev, LAN88XX_EXT_PAGE_ACCESS); 271c2734b3SRaghuram Chary J } 281c2734b3SRaghuram Chary J 291c2734b3SRaghuram Chary J static int lan88xx_write_page(struct phy_device *phydev, int page) 301c2734b3SRaghuram Chary J { 311c2734b3SRaghuram Chary J return __phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, page); 321c2734b3SRaghuram Chary J } 331c2734b3SRaghuram Chary J 34792aec47SWoojung.Huh@microchip.com static int lan88xx_phy_config_intr(struct phy_device *phydev) 35792aec47SWoojung.Huh@microchip.com { 36792aec47SWoojung.Huh@microchip.com int rc; 37792aec47SWoojung.Huh@microchip.com 38792aec47SWoojung.Huh@microchip.com if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 39792aec47SWoojung.Huh@microchip.com /* unmask all source and clear them before enable */ 40792aec47SWoojung.Huh@microchip.com rc = phy_write(phydev, LAN88XX_INT_MASK, 0x7FFF); 41792aec47SWoojung.Huh@microchip.com rc = phy_read(phydev, LAN88XX_INT_STS); 42792aec47SWoojung.Huh@microchip.com rc = phy_write(phydev, LAN88XX_INT_MASK, 43792aec47SWoojung.Huh@microchip.com LAN88XX_INT_MASK_MDINTPIN_EN_ | 44792aec47SWoojung.Huh@microchip.com LAN88XX_INT_MASK_LINK_CHANGE_); 45792aec47SWoojung.Huh@microchip.com } else { 46792aec47SWoojung.Huh@microchip.com rc = phy_write(phydev, LAN88XX_INT_MASK, 0); 47cf499391SIoana Ciornei if (rc) 48cf499391SIoana Ciornei return rc; 49792aec47SWoojung.Huh@microchip.com 50cf499391SIoana Ciornei /* Ack interrupts after they have been disabled */ 51cf499391SIoana Ciornei rc = phy_read(phydev, LAN88XX_INT_STS); 52792aec47SWoojung.Huh@microchip.com } 53792aec47SWoojung.Huh@microchip.com 54792aec47SWoojung.Huh@microchip.com return rc < 0 ? rc : 0; 55792aec47SWoojung.Huh@microchip.com } 56792aec47SWoojung.Huh@microchip.com 57e01a3febSIoana Ciornei static irqreturn_t lan88xx_handle_interrupt(struct phy_device *phydev) 58e01a3febSIoana Ciornei { 59e01a3febSIoana Ciornei int irq_status; 60e01a3febSIoana Ciornei 61e01a3febSIoana Ciornei irq_status = phy_read(phydev, LAN88XX_INT_STS); 62e01a3febSIoana Ciornei if (irq_status < 0) { 63e01a3febSIoana Ciornei phy_error(phydev); 64e01a3febSIoana Ciornei return IRQ_NONE; 65e01a3febSIoana Ciornei } 66e01a3febSIoana Ciornei 67e01a3febSIoana Ciornei if (!(irq_status & LAN88XX_INT_STS_LINK_CHANGE_)) 68e01a3febSIoana Ciornei return IRQ_NONE; 69e01a3febSIoana Ciornei 70e01a3febSIoana Ciornei phy_trigger_machine(phydev); 71e01a3febSIoana Ciornei 72e01a3febSIoana Ciornei return IRQ_HANDLED; 73e01a3febSIoana Ciornei } 74e01a3febSIoana Ciornei 7599408030SBaoyou Xie static int lan88xx_suspend(struct phy_device *phydev) 76792aec47SWoojung.Huh@microchip.com { 77792aec47SWoojung.Huh@microchip.com struct lan88xx_priv *priv = phydev->priv; 78792aec47SWoojung.Huh@microchip.com 79792aec47SWoojung.Huh@microchip.com /* do not power down PHY when WOL is enabled */ 80792aec47SWoojung.Huh@microchip.com if (!priv->wolopts) 81792aec47SWoojung.Huh@microchip.com genphy_suspend(phydev); 82792aec47SWoojung.Huh@microchip.com 83792aec47SWoojung.Huh@microchip.com return 0; 84792aec47SWoojung.Huh@microchip.com } 85792aec47SWoojung.Huh@microchip.com 861c2734b3SRaghuram Chary J static int lan88xx_TR_reg_set(struct phy_device *phydev, u16 regaddr, 871c2734b3SRaghuram Chary J u32 data) 881c2734b3SRaghuram Chary J { 891c2734b3SRaghuram Chary J int val, save_page, ret = 0; 901c2734b3SRaghuram Chary J u16 buf; 911c2734b3SRaghuram Chary J 921c2734b3SRaghuram Chary J /* Save current page */ 931c2734b3SRaghuram Chary J save_page = phy_save_page(phydev); 941c2734b3SRaghuram Chary J if (save_page < 0) { 95ab2a605fSAndrew Lunn phydev_warn(phydev, "Failed to get current page\n"); 961c2734b3SRaghuram Chary J goto err; 971c2734b3SRaghuram Chary J } 981c2734b3SRaghuram Chary J 991c2734b3SRaghuram Chary J /* Switch to TR page */ 1001c2734b3SRaghuram Chary J lan88xx_write_page(phydev, LAN88XX_EXT_PAGE_ACCESS_TR); 1011c2734b3SRaghuram Chary J 1021c2734b3SRaghuram Chary J ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_LOW_DATA, 1031c2734b3SRaghuram Chary J (data & 0xFFFF)); 1041c2734b3SRaghuram Chary J if (ret < 0) { 105ab2a605fSAndrew Lunn phydev_warn(phydev, "Failed to write TR low data\n"); 1061c2734b3SRaghuram Chary J goto err; 1071c2734b3SRaghuram Chary J } 1081c2734b3SRaghuram Chary J 1091c2734b3SRaghuram Chary J ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_HIGH_DATA, 1101c2734b3SRaghuram Chary J (data & 0x00FF0000) >> 16); 1111c2734b3SRaghuram Chary J if (ret < 0) { 112ab2a605fSAndrew Lunn phydev_warn(phydev, "Failed to write TR high data\n"); 1131c2734b3SRaghuram Chary J goto err; 1141c2734b3SRaghuram Chary J } 1151c2734b3SRaghuram Chary J 1161c2734b3SRaghuram Chary J /* Config control bits [15:13] of register */ 1171c2734b3SRaghuram Chary J buf = (regaddr & ~(0x3 << 13));/* Clr [14:13] to write data in reg */ 1181c2734b3SRaghuram Chary J buf |= 0x8000; /* Set [15] to Packet transmit */ 1191c2734b3SRaghuram Chary J 1201c2734b3SRaghuram Chary J ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_CR, buf); 1211c2734b3SRaghuram Chary J if (ret < 0) { 122ab2a605fSAndrew Lunn phydev_warn(phydev, "Failed to write data in reg\n"); 1231c2734b3SRaghuram Chary J goto err; 1241c2734b3SRaghuram Chary J } 1251c2734b3SRaghuram Chary J 1261c2734b3SRaghuram Chary J usleep_range(1000, 2000);/* Wait for Data to be written */ 1271c2734b3SRaghuram Chary J val = __phy_read(phydev, LAN88XX_EXT_PAGE_TR_CR); 1281c2734b3SRaghuram Chary J if (!(val & 0x8000)) 129ab2a605fSAndrew Lunn phydev_warn(phydev, "TR Register[0x%X] configuration failed\n", 130ab2a605fSAndrew Lunn regaddr); 1311c2734b3SRaghuram Chary J err: 1321c2734b3SRaghuram Chary J return phy_restore_page(phydev, save_page, ret); 1331c2734b3SRaghuram Chary J } 1341c2734b3SRaghuram Chary J 1351c2734b3SRaghuram Chary J static void lan88xx_config_TR_regs(struct phy_device *phydev) 1361c2734b3SRaghuram Chary J { 1371c2734b3SRaghuram Chary J int err; 1381c2734b3SRaghuram Chary J 1391c2734b3SRaghuram Chary J /* Get access to Channel 0x1, Node 0xF , Register 0x01. 1401c2734b3SRaghuram Chary J * Write 24-bit value 0x12B00A to register. Setting MrvlTrFix1000Kf, 1411c2734b3SRaghuram Chary J * MrvlTrFix1000Kp, MasterEnableTR bits. 1421c2734b3SRaghuram Chary J */ 1431c2734b3SRaghuram Chary J err = lan88xx_TR_reg_set(phydev, 0x0F82, 0x12B00A); 1441c2734b3SRaghuram Chary J if (err < 0) 145ab2a605fSAndrew Lunn phydev_warn(phydev, "Failed to Set Register[0x0F82]\n"); 1461c2734b3SRaghuram Chary J 1471c2734b3SRaghuram Chary J /* Get access to Channel b'10, Node b'1101, Register 0x06. 1481c2734b3SRaghuram Chary J * Write 24-bit value 0xD2C46F to register. Setting SSTrKf1000Slv, 1491c2734b3SRaghuram Chary J * SSTrKp1000Mas bits. 1501c2734b3SRaghuram Chary J */ 1511c2734b3SRaghuram Chary J err = lan88xx_TR_reg_set(phydev, 0x168C, 0xD2C46F); 1521c2734b3SRaghuram Chary J if (err < 0) 153ab2a605fSAndrew Lunn phydev_warn(phydev, "Failed to Set Register[0x168C]\n"); 1541c2734b3SRaghuram Chary J 1551c2734b3SRaghuram Chary J /* Get access to Channel b'10, Node b'1111, Register 0x11. 1561c2734b3SRaghuram Chary J * Write 24-bit value 0x620 to register. Setting rem_upd_done_thresh 1571c2734b3SRaghuram Chary J * bits 1581c2734b3SRaghuram Chary J */ 1591c2734b3SRaghuram Chary J err = lan88xx_TR_reg_set(phydev, 0x17A2, 0x620); 1601c2734b3SRaghuram Chary J if (err < 0) 161ab2a605fSAndrew Lunn phydev_warn(phydev, "Failed to Set Register[0x17A2]\n"); 1621c2734b3SRaghuram Chary J 1631c2734b3SRaghuram Chary J /* Get access to Channel b'10, Node b'1101, Register 0x10. 1641c2734b3SRaghuram Chary J * Write 24-bit value 0xEEFFDD to register. Setting 1651c2734b3SRaghuram Chary J * eee_TrKp1Long_1000, eee_TrKp2Long_1000, eee_TrKp3Long_1000, 1661c2734b3SRaghuram Chary J * eee_TrKp1Short_1000,eee_TrKp2Short_1000, eee_TrKp3Short_1000 bits. 1671c2734b3SRaghuram Chary J */ 1681c2734b3SRaghuram Chary J err = lan88xx_TR_reg_set(phydev, 0x16A0, 0xEEFFDD); 1691c2734b3SRaghuram Chary J if (err < 0) 170ab2a605fSAndrew Lunn phydev_warn(phydev, "Failed to Set Register[0x16A0]\n"); 1711c2734b3SRaghuram Chary J 1721c2734b3SRaghuram Chary J /* Get access to Channel b'10, Node b'1101, Register 0x13. 1731c2734b3SRaghuram Chary J * Write 24-bit value 0x071448 to register. Setting 1741c2734b3SRaghuram Chary J * slv_lpi_tr_tmr_val1, slv_lpi_tr_tmr_val2 bits. 1751c2734b3SRaghuram Chary J */ 1761c2734b3SRaghuram Chary J err = lan88xx_TR_reg_set(phydev, 0x16A6, 0x071448); 1771c2734b3SRaghuram Chary J if (err < 0) 178ab2a605fSAndrew Lunn phydev_warn(phydev, "Failed to Set Register[0x16A6]\n"); 1791c2734b3SRaghuram Chary J 1801c2734b3SRaghuram Chary J /* Get access to Channel b'10, Node b'1101, Register 0x12. 1811c2734b3SRaghuram Chary J * Write 24-bit value 0x13132F to register. Setting 1821c2734b3SRaghuram Chary J * slv_sigdet_timer_val1, slv_sigdet_timer_val2 bits. 1831c2734b3SRaghuram Chary J */ 1841c2734b3SRaghuram Chary J err = lan88xx_TR_reg_set(phydev, 0x16A4, 0x13132F); 1851c2734b3SRaghuram Chary J if (err < 0) 186ab2a605fSAndrew Lunn phydev_warn(phydev, "Failed to Set Register[0x16A4]\n"); 1871c2734b3SRaghuram Chary J 1881c2734b3SRaghuram Chary J /* Get access to Channel b'10, Node b'1101, Register 0x14. 1891c2734b3SRaghuram Chary J * Write 24-bit value 0x0 to register. Setting eee_3level_delay, 1901c2734b3SRaghuram Chary J * eee_TrKf_freeze_delay bits. 1911c2734b3SRaghuram Chary J */ 1921c2734b3SRaghuram Chary J err = lan88xx_TR_reg_set(phydev, 0x16A8, 0x0); 1931c2734b3SRaghuram Chary J if (err < 0) 194ab2a605fSAndrew Lunn phydev_warn(phydev, "Failed to Set Register[0x16A8]\n"); 1951c2734b3SRaghuram Chary J 1961c2734b3SRaghuram Chary J /* Get access to Channel b'01, Node b'1111, Register 0x34. 1971c2734b3SRaghuram Chary J * Write 24-bit value 0x91B06C to register. Setting 1981c2734b3SRaghuram Chary J * FastMseSearchThreshLong1000, FastMseSearchThreshShort1000, 1991c2734b3SRaghuram Chary J * FastMseSearchUpdGain1000 bits. 2001c2734b3SRaghuram Chary J */ 2011c2734b3SRaghuram Chary J err = lan88xx_TR_reg_set(phydev, 0x0FE8, 0x91B06C); 2021c2734b3SRaghuram Chary J if (err < 0) 203ab2a605fSAndrew Lunn phydev_warn(phydev, "Failed to Set Register[0x0FE8]\n"); 2041c2734b3SRaghuram Chary J 2051c2734b3SRaghuram Chary J /* Get access to Channel b'01, Node b'1111, Register 0x3E. 2061c2734b3SRaghuram Chary J * Write 24-bit value 0xC0A028 to register. Setting 2071c2734b3SRaghuram Chary J * FastMseKp2ThreshLong1000, FastMseKp2ThreshShort1000, 2081c2734b3SRaghuram Chary J * FastMseKp2UpdGain1000, FastMseKp2ExitEn1000 bits. 2091c2734b3SRaghuram Chary J */ 2101c2734b3SRaghuram Chary J err = lan88xx_TR_reg_set(phydev, 0x0FFC, 0xC0A028); 2111c2734b3SRaghuram Chary J if (err < 0) 212ab2a605fSAndrew Lunn phydev_warn(phydev, "Failed to Set Register[0x0FFC]\n"); 2131c2734b3SRaghuram Chary J 2141c2734b3SRaghuram Chary J /* Get access to Channel b'01, Node b'1111, Register 0x35. 2151c2734b3SRaghuram Chary J * Write 24-bit value 0x041600 to register. Setting 2161c2734b3SRaghuram Chary J * FastMseSearchPhShNum1000, FastMseSearchClksPerPh1000, 2171c2734b3SRaghuram Chary J * FastMsePhChangeDelay1000 bits. 2181c2734b3SRaghuram Chary J */ 2191c2734b3SRaghuram Chary J err = lan88xx_TR_reg_set(phydev, 0x0FEA, 0x041600); 2201c2734b3SRaghuram Chary J if (err < 0) 221ab2a605fSAndrew Lunn phydev_warn(phydev, "Failed to Set Register[0x0FEA]\n"); 2221c2734b3SRaghuram Chary J 2231c2734b3SRaghuram Chary J /* Get access to Channel b'10, Node b'1101, Register 0x03. 2241c2734b3SRaghuram Chary J * Write 24-bit value 0x000004 to register. Setting TrFreeze bits. 2251c2734b3SRaghuram Chary J */ 2261c2734b3SRaghuram Chary J err = lan88xx_TR_reg_set(phydev, 0x1686, 0x000004); 2271c2734b3SRaghuram Chary J if (err < 0) 228ab2a605fSAndrew Lunn phydev_warn(phydev, "Failed to Set Register[0x1686]\n"); 2291c2734b3SRaghuram Chary J } 2301c2734b3SRaghuram Chary J 231792aec47SWoojung.Huh@microchip.com static int lan88xx_probe(struct phy_device *phydev) 232792aec47SWoojung.Huh@microchip.com { 233e5a03bfdSAndrew Lunn struct device *dev = &phydev->mdio.dev; 234792aec47SWoojung.Huh@microchip.com struct lan88xx_priv *priv; 2351827b067SPhil Elwell u32 led_modes[4]; 2361827b067SPhil Elwell int len; 237792aec47SWoojung.Huh@microchip.com 238792aec47SWoojung.Huh@microchip.com priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 239792aec47SWoojung.Huh@microchip.com if (!priv) 240792aec47SWoojung.Huh@microchip.com return -ENOMEM; 241792aec47SWoojung.Huh@microchip.com 242792aec47SWoojung.Huh@microchip.com priv->wolopts = 0; 243792aec47SWoojung.Huh@microchip.com 2441827b067SPhil Elwell len = of_property_read_variable_u32_array(dev->of_node, 2451827b067SPhil Elwell "microchip,led-modes", 2461827b067SPhil Elwell led_modes, 2471827b067SPhil Elwell 0, 2481827b067SPhil Elwell ARRAY_SIZE(led_modes)); 2491827b067SPhil Elwell if (len >= 0) { 2501827b067SPhil Elwell u32 reg = 0; 2511827b067SPhil Elwell int i; 2521827b067SPhil Elwell 2531827b067SPhil Elwell for (i = 0; i < len; i++) { 2541827b067SPhil Elwell if (led_modes[i] > 15) 2551827b067SPhil Elwell return -EINVAL; 2561827b067SPhil Elwell reg |= led_modes[i] << (i * 4); 2571827b067SPhil Elwell } 2581827b067SPhil Elwell for (; i < ARRAY_SIZE(led_modes); i++) 2591827b067SPhil Elwell reg |= LAN78XX_FORCE_LED_OFF << (i * 4); 2601827b067SPhil Elwell (void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg); 2611827b067SPhil Elwell } else if (len == -EOVERFLOW) { 2621827b067SPhil Elwell return -EINVAL; 2631827b067SPhil Elwell } 2641827b067SPhil Elwell 265792aec47SWoojung.Huh@microchip.com /* these values can be used to identify internal PHY */ 266a6d99fcdSRussell King priv->chip_id = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_ID); 267a6d99fcdSRussell King priv->chip_rev = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_REV); 268792aec47SWoojung.Huh@microchip.com 269792aec47SWoojung.Huh@microchip.com phydev->priv = priv; 270792aec47SWoojung.Huh@microchip.com 271792aec47SWoojung.Huh@microchip.com return 0; 272792aec47SWoojung.Huh@microchip.com } 273792aec47SWoojung.Huh@microchip.com 274792aec47SWoojung.Huh@microchip.com static void lan88xx_remove(struct phy_device *phydev) 275792aec47SWoojung.Huh@microchip.com { 276e5a03bfdSAndrew Lunn struct device *dev = &phydev->mdio.dev; 277792aec47SWoojung.Huh@microchip.com struct lan88xx_priv *priv = phydev->priv; 278792aec47SWoojung.Huh@microchip.com 279792aec47SWoojung.Huh@microchip.com if (priv) 280792aec47SWoojung.Huh@microchip.com devm_kfree(dev, priv); 281792aec47SWoojung.Huh@microchip.com } 282792aec47SWoojung.Huh@microchip.com 283792aec47SWoojung.Huh@microchip.com static int lan88xx_set_wol(struct phy_device *phydev, 284792aec47SWoojung.Huh@microchip.com struct ethtool_wolinfo *wol) 285792aec47SWoojung.Huh@microchip.com { 286792aec47SWoojung.Huh@microchip.com struct lan88xx_priv *priv = phydev->priv; 287792aec47SWoojung.Huh@microchip.com 288792aec47SWoojung.Huh@microchip.com priv->wolopts = wol->wolopts; 289792aec47SWoojung.Huh@microchip.com 290792aec47SWoojung.Huh@microchip.com return 0; 291792aec47SWoojung.Huh@microchip.com } 292792aec47SWoojung.Huh@microchip.com 293f6e3ef3eSWoojung Huh static void lan88xx_set_mdix(struct phy_device *phydev) 294f6e3ef3eSWoojung Huh { 295f6e3ef3eSWoojung Huh int buf; 296f6e3ef3eSWoojung Huh int val; 297f6e3ef3eSWoojung Huh 2984e26c5c3SRaju Lakkaraju switch (phydev->mdix_ctrl) { 299f6e3ef3eSWoojung Huh case ETH_TP_MDI: 300f6e3ef3eSWoojung Huh val = LAN88XX_EXT_MODE_CTRL_MDI_; 301f6e3ef3eSWoojung Huh break; 302f6e3ef3eSWoojung Huh case ETH_TP_MDI_X: 303f6e3ef3eSWoojung Huh val = LAN88XX_EXT_MODE_CTRL_MDI_X_; 304f6e3ef3eSWoojung Huh break; 305f6e3ef3eSWoojung Huh case ETH_TP_MDI_AUTO: 306f6e3ef3eSWoojung Huh val = LAN88XX_EXT_MODE_CTRL_AUTO_MDIX_; 307f6e3ef3eSWoojung Huh break; 308f6e3ef3eSWoojung Huh default: 309f6e3ef3eSWoojung Huh return; 310f6e3ef3eSWoojung Huh } 311f6e3ef3eSWoojung Huh 312f6e3ef3eSWoojung Huh phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1); 313f6e3ef3eSWoojung Huh buf = phy_read(phydev, LAN88XX_EXT_MODE_CTRL); 314f6e3ef3eSWoojung Huh buf &= ~LAN88XX_EXT_MODE_CTRL_MDIX_MASK_; 315f6e3ef3eSWoojung Huh buf |= val; 316f6e3ef3eSWoojung Huh phy_write(phydev, LAN88XX_EXT_MODE_CTRL, buf); 317f6e3ef3eSWoojung Huh phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0); 318f6e3ef3eSWoojung Huh } 319f6e3ef3eSWoojung Huh 3201c2734b3SRaghuram Chary J static int lan88xx_config_init(struct phy_device *phydev) 3211c2734b3SRaghuram Chary J { 3221c2734b3SRaghuram Chary J int val; 3231c2734b3SRaghuram Chary J 3241c2734b3SRaghuram Chary J /*Zerodetect delay enable */ 3251c2734b3SRaghuram Chary J val = phy_read_mmd(phydev, MDIO_MMD_PCS, 3261c2734b3SRaghuram Chary J PHY_ARDENNES_MMD_DEV_3_PHY_CFG); 3271c2734b3SRaghuram Chary J val |= PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_; 3281c2734b3SRaghuram Chary J 3291c2734b3SRaghuram Chary J phy_write_mmd(phydev, MDIO_MMD_PCS, PHY_ARDENNES_MMD_DEV_3_PHY_CFG, 3301c2734b3SRaghuram Chary J val); 3311c2734b3SRaghuram Chary J 3321c2734b3SRaghuram Chary J /* Config DSP registers */ 3331c2734b3SRaghuram Chary J lan88xx_config_TR_regs(phydev); 3341c2734b3SRaghuram Chary J 3351c2734b3SRaghuram Chary J return 0; 3361c2734b3SRaghuram Chary J } 3371c2734b3SRaghuram Chary J 338f6e3ef3eSWoojung Huh static int lan88xx_config_aneg(struct phy_device *phydev) 339f6e3ef3eSWoojung Huh { 340f6e3ef3eSWoojung Huh lan88xx_set_mdix(phydev); 341f6e3ef3eSWoojung Huh 342f6e3ef3eSWoojung Huh return genphy_config_aneg(phydev); 343f6e3ef3eSWoojung Huh } 344f6e3ef3eSWoojung Huh 345792aec47SWoojung.Huh@microchip.com static struct phy_driver microchip_phy_driver[] = { 346792aec47SWoojung.Huh@microchip.com { 347e078286aSYuiko Oshino .phy_id = 0x0007c132, 348*70a40ecfSYuiko Oshino /* This mask (0xfffffff2) is to differentiate from 349*70a40ecfSYuiko Oshino * LAN8742 (phy_id 0x0007c130 and 0x0007c131) 350*70a40ecfSYuiko Oshino * and allows future phy_id revisions. 351*70a40ecfSYuiko Oshino */ 352e078286aSYuiko Oshino .phy_id_mask = 0xfffffff2, 353792aec47SWoojung.Huh@microchip.com .name = "Microchip LAN88xx", 354792aec47SWoojung.Huh@microchip.com 355dcdecdcfSHeiner Kallweit /* PHY_GBIT_FEATURES */ 356792aec47SWoojung.Huh@microchip.com 357792aec47SWoojung.Huh@microchip.com .probe = lan88xx_probe, 358792aec47SWoojung.Huh@microchip.com .remove = lan88xx_remove, 359792aec47SWoojung.Huh@microchip.com 3601c2734b3SRaghuram Chary J .config_init = lan88xx_config_init, 361f6e3ef3eSWoojung Huh .config_aneg = lan88xx_config_aneg, 362792aec47SWoojung.Huh@microchip.com 363792aec47SWoojung.Huh@microchip.com .config_intr = lan88xx_phy_config_intr, 364e01a3febSIoana Ciornei .handle_interrupt = lan88xx_handle_interrupt, 365792aec47SWoojung.Huh@microchip.com 366792aec47SWoojung.Huh@microchip.com .suspend = lan88xx_suspend, 367792aec47SWoojung.Huh@microchip.com .resume = genphy_resume, 368792aec47SWoojung.Huh@microchip.com .set_wol = lan88xx_set_wol, 3691c2734b3SRaghuram Chary J .read_page = lan88xx_read_page, 3701c2734b3SRaghuram Chary J .write_page = lan88xx_write_page, 371792aec47SWoojung.Huh@microchip.com } }; 372792aec47SWoojung.Huh@microchip.com 373792aec47SWoojung.Huh@microchip.com module_phy_driver(microchip_phy_driver); 374792aec47SWoojung.Huh@microchip.com 375792aec47SWoojung.Huh@microchip.com static struct mdio_device_id __maybe_unused microchip_tbl[] = { 376e078286aSYuiko Oshino { 0x0007c132, 0xfffffff2 }, 377792aec47SWoojung.Huh@microchip.com { } 378792aec47SWoojung.Huh@microchip.com }; 379792aec47SWoojung.Huh@microchip.com 380792aec47SWoojung.Huh@microchip.com MODULE_DEVICE_TABLE(mdio, microchip_tbl); 381792aec47SWoojung.Huh@microchip.com 382792aec47SWoojung.Huh@microchip.com MODULE_AUTHOR(DRIVER_AUTHOR); 383792aec47SWoojung.Huh@microchip.com MODULE_DESCRIPTION(DRIVER_DESC); 384792aec47SWoojung.Huh@microchip.com MODULE_LICENSE("GPL"); 385