1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/micrel.c 4 * 5 * Driver for Micrel PHYs 6 * 7 * Author: David J. Choi 8 * 9 * Copyright (c) 2010-2013 Micrel, Inc. 10 * Copyright (c) 2014 Johan Hovold <johan@kernel.org> 11 * 12 * Support : Micrel Phys: 13 * Giga phys: ksz9021, ksz9031, ksz9131 14 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041 15 * ksz8021, ksz8031, ksz8051, 16 * ksz8081, ksz8091, 17 * ksz8061, 18 * Switch : ksz8873, ksz886x 19 * ksz9477 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/phy.h> 25 #include <linux/micrel_phy.h> 26 #include <linux/of.h> 27 #include <linux/clk.h> 28 29 /* Operation Mode Strap Override */ 30 #define MII_KSZPHY_OMSO 0x16 31 #define KSZPHY_OMSO_B_CAST_OFF BIT(9) 32 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5) 33 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1) 34 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0) 35 36 /* general Interrupt control/status reg in vendor specific block. */ 37 #define MII_KSZPHY_INTCS 0x1B 38 #define KSZPHY_INTCS_JABBER BIT(15) 39 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14) 40 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13) 41 #define KSZPHY_INTCS_PARELLEL BIT(12) 42 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11) 43 #define KSZPHY_INTCS_LINK_DOWN BIT(10) 44 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9) 45 #define KSZPHY_INTCS_LINK_UP BIT(8) 46 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\ 47 KSZPHY_INTCS_LINK_DOWN) 48 49 /* PHY Control 1 */ 50 #define MII_KSZPHY_CTRL_1 0x1e 51 52 /* PHY Control 2 / PHY Control (if no PHY Control 1) */ 53 #define MII_KSZPHY_CTRL_2 0x1f 54 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2 55 /* bitmap of PHY register to set interrupt mode */ 56 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9) 57 #define KSZPHY_RMII_REF_CLK_SEL BIT(7) 58 59 /* Write/read to/from extended registers */ 60 #define MII_KSZPHY_EXTREG 0x0b 61 #define KSZPHY_EXTREG_WRITE 0x8000 62 63 #define MII_KSZPHY_EXTREG_WRITE 0x0c 64 #define MII_KSZPHY_EXTREG_READ 0x0d 65 66 /* Extended registers */ 67 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104 68 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105 69 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106 70 71 #define PS_TO_REG 200 72 73 struct kszphy_hw_stat { 74 const char *string; 75 u8 reg; 76 u8 bits; 77 }; 78 79 static struct kszphy_hw_stat kszphy_hw_stats[] = { 80 { "phy_receive_errors", 21, 16}, 81 { "phy_idle_errors", 10, 8 }, 82 }; 83 84 struct kszphy_type { 85 u32 led_mode_reg; 86 u16 interrupt_level_mask; 87 bool has_broadcast_disable; 88 bool has_nand_tree_disable; 89 bool has_rmii_ref_clk_sel; 90 }; 91 92 struct kszphy_priv { 93 const struct kszphy_type *type; 94 int led_mode; 95 bool rmii_ref_clk_sel; 96 bool rmii_ref_clk_sel_val; 97 u64 stats[ARRAY_SIZE(kszphy_hw_stats)]; 98 }; 99 100 static const struct kszphy_type ksz8021_type = { 101 .led_mode_reg = MII_KSZPHY_CTRL_2, 102 .has_broadcast_disable = true, 103 .has_nand_tree_disable = true, 104 .has_rmii_ref_clk_sel = true, 105 }; 106 107 static const struct kszphy_type ksz8041_type = { 108 .led_mode_reg = MII_KSZPHY_CTRL_1, 109 }; 110 111 static const struct kszphy_type ksz8051_type = { 112 .led_mode_reg = MII_KSZPHY_CTRL_2, 113 .has_nand_tree_disable = true, 114 }; 115 116 static const struct kszphy_type ksz8081_type = { 117 .led_mode_reg = MII_KSZPHY_CTRL_2, 118 .has_broadcast_disable = true, 119 .has_nand_tree_disable = true, 120 .has_rmii_ref_clk_sel = true, 121 }; 122 123 static const struct kszphy_type ks8737_type = { 124 .interrupt_level_mask = BIT(14), 125 }; 126 127 static const struct kszphy_type ksz9021_type = { 128 .interrupt_level_mask = BIT(14), 129 }; 130 131 static int kszphy_extended_write(struct phy_device *phydev, 132 u32 regnum, u16 val) 133 { 134 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum); 135 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); 136 } 137 138 static int kszphy_extended_read(struct phy_device *phydev, 139 u32 regnum) 140 { 141 phy_write(phydev, MII_KSZPHY_EXTREG, regnum); 142 return phy_read(phydev, MII_KSZPHY_EXTREG_READ); 143 } 144 145 static int kszphy_ack_interrupt(struct phy_device *phydev) 146 { 147 /* bit[7..0] int status, which is a read and clear register. */ 148 int rc; 149 150 rc = phy_read(phydev, MII_KSZPHY_INTCS); 151 152 return (rc < 0) ? rc : 0; 153 } 154 155 static int kszphy_config_intr(struct phy_device *phydev) 156 { 157 const struct kszphy_type *type = phydev->drv->driver_data; 158 int temp; 159 u16 mask; 160 161 if (type && type->interrupt_level_mask) 162 mask = type->interrupt_level_mask; 163 else 164 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH; 165 166 /* set the interrupt pin active low */ 167 temp = phy_read(phydev, MII_KSZPHY_CTRL); 168 if (temp < 0) 169 return temp; 170 temp &= ~mask; 171 phy_write(phydev, MII_KSZPHY_CTRL, temp); 172 173 /* enable / disable interrupts */ 174 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 175 temp = KSZPHY_INTCS_ALL; 176 else 177 temp = 0; 178 179 return phy_write(phydev, MII_KSZPHY_INTCS, temp); 180 } 181 182 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val) 183 { 184 int ctrl; 185 186 ctrl = phy_read(phydev, MII_KSZPHY_CTRL); 187 if (ctrl < 0) 188 return ctrl; 189 190 if (val) 191 ctrl |= KSZPHY_RMII_REF_CLK_SEL; 192 else 193 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL; 194 195 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl); 196 } 197 198 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val) 199 { 200 int rc, temp, shift; 201 202 switch (reg) { 203 case MII_KSZPHY_CTRL_1: 204 shift = 14; 205 break; 206 case MII_KSZPHY_CTRL_2: 207 shift = 4; 208 break; 209 default: 210 return -EINVAL; 211 } 212 213 temp = phy_read(phydev, reg); 214 if (temp < 0) { 215 rc = temp; 216 goto out; 217 } 218 219 temp &= ~(3 << shift); 220 temp |= val << shift; 221 rc = phy_write(phydev, reg, temp); 222 out: 223 if (rc < 0) 224 phydev_err(phydev, "failed to set led mode\n"); 225 226 return rc; 227 } 228 229 /* Disable PHY address 0 as the broadcast address, so that it can be used as a 230 * unique (non-broadcast) address on a shared bus. 231 */ 232 static int kszphy_broadcast_disable(struct phy_device *phydev) 233 { 234 int ret; 235 236 ret = phy_read(phydev, MII_KSZPHY_OMSO); 237 if (ret < 0) 238 goto out; 239 240 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF); 241 out: 242 if (ret) 243 phydev_err(phydev, "failed to disable broadcast address\n"); 244 245 return ret; 246 } 247 248 static int kszphy_nand_tree_disable(struct phy_device *phydev) 249 { 250 int ret; 251 252 ret = phy_read(phydev, MII_KSZPHY_OMSO); 253 if (ret < 0) 254 goto out; 255 256 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON)) 257 return 0; 258 259 ret = phy_write(phydev, MII_KSZPHY_OMSO, 260 ret & ~KSZPHY_OMSO_NAND_TREE_ON); 261 out: 262 if (ret) 263 phydev_err(phydev, "failed to disable NAND tree mode\n"); 264 265 return ret; 266 } 267 268 /* Some config bits need to be set again on resume, handle them here. */ 269 static int kszphy_config_reset(struct phy_device *phydev) 270 { 271 struct kszphy_priv *priv = phydev->priv; 272 int ret; 273 274 if (priv->rmii_ref_clk_sel) { 275 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val); 276 if (ret) { 277 phydev_err(phydev, 278 "failed to set rmii reference clock\n"); 279 return ret; 280 } 281 } 282 283 if (priv->led_mode >= 0) 284 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode); 285 286 return 0; 287 } 288 289 static int kszphy_config_init(struct phy_device *phydev) 290 { 291 struct kszphy_priv *priv = phydev->priv; 292 const struct kszphy_type *type; 293 294 if (!priv) 295 return 0; 296 297 type = priv->type; 298 299 if (type->has_broadcast_disable) 300 kszphy_broadcast_disable(phydev); 301 302 if (type->has_nand_tree_disable) 303 kszphy_nand_tree_disable(phydev); 304 305 return kszphy_config_reset(phydev); 306 } 307 308 static int ksz8041_config_init(struct phy_device *phydev) 309 { 310 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 311 312 struct device_node *of_node = phydev->mdio.dev.of_node; 313 314 /* Limit supported and advertised modes in fiber mode */ 315 if (of_property_read_bool(of_node, "micrel,fiber-mode")) { 316 phydev->dev_flags |= MICREL_PHY_FXEN; 317 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask); 318 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask); 319 320 linkmode_and(phydev->supported, phydev->supported, mask); 321 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 322 phydev->supported); 323 linkmode_and(phydev->advertising, phydev->advertising, mask); 324 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 325 phydev->advertising); 326 phydev->autoneg = AUTONEG_DISABLE; 327 } 328 329 return kszphy_config_init(phydev); 330 } 331 332 static int ksz8041_config_aneg(struct phy_device *phydev) 333 { 334 /* Skip auto-negotiation in fiber mode */ 335 if (phydev->dev_flags & MICREL_PHY_FXEN) { 336 phydev->speed = SPEED_100; 337 return 0; 338 } 339 340 return genphy_config_aneg(phydev); 341 } 342 343 static int ksz8061_config_init(struct phy_device *phydev) 344 { 345 int ret; 346 347 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A); 348 if (ret) 349 return ret; 350 351 return kszphy_config_init(phydev); 352 } 353 354 static int ksz9021_load_values_from_of(struct phy_device *phydev, 355 const struct device_node *of_node, 356 u16 reg, 357 const char *field1, const char *field2, 358 const char *field3, const char *field4) 359 { 360 int val1 = -1; 361 int val2 = -2; 362 int val3 = -3; 363 int val4 = -4; 364 int newval; 365 int matches = 0; 366 367 if (!of_property_read_u32(of_node, field1, &val1)) 368 matches++; 369 370 if (!of_property_read_u32(of_node, field2, &val2)) 371 matches++; 372 373 if (!of_property_read_u32(of_node, field3, &val3)) 374 matches++; 375 376 if (!of_property_read_u32(of_node, field4, &val4)) 377 matches++; 378 379 if (!matches) 380 return 0; 381 382 if (matches < 4) 383 newval = kszphy_extended_read(phydev, reg); 384 else 385 newval = 0; 386 387 if (val1 != -1) 388 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0); 389 390 if (val2 != -2) 391 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4); 392 393 if (val3 != -3) 394 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8); 395 396 if (val4 != -4) 397 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12); 398 399 return kszphy_extended_write(phydev, reg, newval); 400 } 401 402 static int ksz9021_config_init(struct phy_device *phydev) 403 { 404 const struct device *dev = &phydev->mdio.dev; 405 const struct device_node *of_node = dev->of_node; 406 const struct device *dev_walker; 407 408 /* The Micrel driver has a deprecated option to place phy OF 409 * properties in the MAC node. Walk up the tree of devices to 410 * find a device with an OF node. 411 */ 412 dev_walker = &phydev->mdio.dev; 413 do { 414 of_node = dev_walker->of_node; 415 dev_walker = dev_walker->parent; 416 417 } while (!of_node && dev_walker); 418 419 if (of_node) { 420 ksz9021_load_values_from_of(phydev, of_node, 421 MII_KSZPHY_CLK_CONTROL_PAD_SKEW, 422 "txen-skew-ps", "txc-skew-ps", 423 "rxdv-skew-ps", "rxc-skew-ps"); 424 ksz9021_load_values_from_of(phydev, of_node, 425 MII_KSZPHY_RX_DATA_PAD_SKEW, 426 "rxd0-skew-ps", "rxd1-skew-ps", 427 "rxd2-skew-ps", "rxd3-skew-ps"); 428 ksz9021_load_values_from_of(phydev, of_node, 429 MII_KSZPHY_TX_DATA_PAD_SKEW, 430 "txd0-skew-ps", "txd1-skew-ps", 431 "txd2-skew-ps", "txd3-skew-ps"); 432 } 433 return 0; 434 } 435 436 #define KSZ9031_PS_TO_REG 60 437 438 /* Extended registers */ 439 /* MMD Address 0x0 */ 440 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3 441 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4 442 443 /* MMD Address 0x2 */ 444 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4 445 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5 446 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6 447 #define MII_KSZ9031RN_CLK_PAD_SKEW 8 448 449 /* MMD Address 0x1C */ 450 #define MII_KSZ9031RN_EDPD 0x23 451 #define MII_KSZ9031RN_EDPD_ENABLE BIT(0) 452 453 static int ksz9031_of_load_skew_values(struct phy_device *phydev, 454 const struct device_node *of_node, 455 u16 reg, size_t field_sz, 456 const char *field[], u8 numfields) 457 { 458 int val[4] = {-1, -2, -3, -4}; 459 int matches = 0; 460 u16 mask; 461 u16 maxval; 462 u16 newval; 463 int i; 464 465 for (i = 0; i < numfields; i++) 466 if (!of_property_read_u32(of_node, field[i], val + i)) 467 matches++; 468 469 if (!matches) 470 return 0; 471 472 if (matches < numfields) 473 newval = phy_read_mmd(phydev, 2, reg); 474 else 475 newval = 0; 476 477 maxval = (field_sz == 4) ? 0xf : 0x1f; 478 for (i = 0; i < numfields; i++) 479 if (val[i] != -(i + 1)) { 480 mask = 0xffff; 481 mask ^= maxval << (field_sz * i); 482 newval = (newval & mask) | 483 (((val[i] / KSZ9031_PS_TO_REG) & maxval) 484 << (field_sz * i)); 485 } 486 487 return phy_write_mmd(phydev, 2, reg, newval); 488 } 489 490 /* Center KSZ9031RNX FLP timing at 16ms. */ 491 static int ksz9031_center_flp_timing(struct phy_device *phydev) 492 { 493 int result; 494 495 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI, 496 0x0006); 497 if (result) 498 return result; 499 500 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO, 501 0x1A80); 502 if (result) 503 return result; 504 505 return genphy_restart_aneg(phydev); 506 } 507 508 /* Enable energy-detect power-down mode */ 509 static int ksz9031_enable_edpd(struct phy_device *phydev) 510 { 511 int reg; 512 513 reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD); 514 if (reg < 0) 515 return reg; 516 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD, 517 reg | MII_KSZ9031RN_EDPD_ENABLE); 518 } 519 520 static int ksz9031_config_init(struct phy_device *phydev) 521 { 522 const struct device *dev = &phydev->mdio.dev; 523 const struct device_node *of_node = dev->of_node; 524 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"}; 525 static const char *rx_data_skews[4] = { 526 "rxd0-skew-ps", "rxd1-skew-ps", 527 "rxd2-skew-ps", "rxd3-skew-ps" 528 }; 529 static const char *tx_data_skews[4] = { 530 "txd0-skew-ps", "txd1-skew-ps", 531 "txd2-skew-ps", "txd3-skew-ps" 532 }; 533 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"}; 534 const struct device *dev_walker; 535 int result; 536 537 result = ksz9031_enable_edpd(phydev); 538 if (result < 0) 539 return result; 540 541 /* The Micrel driver has a deprecated option to place phy OF 542 * properties in the MAC node. Walk up the tree of devices to 543 * find a device with an OF node. 544 */ 545 dev_walker = &phydev->mdio.dev; 546 do { 547 of_node = dev_walker->of_node; 548 dev_walker = dev_walker->parent; 549 } while (!of_node && dev_walker); 550 551 if (of_node) { 552 ksz9031_of_load_skew_values(phydev, of_node, 553 MII_KSZ9031RN_CLK_PAD_SKEW, 5, 554 clk_skews, 2); 555 556 ksz9031_of_load_skew_values(phydev, of_node, 557 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, 558 control_skews, 2); 559 560 ksz9031_of_load_skew_values(phydev, of_node, 561 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, 562 rx_data_skews, 4); 563 564 ksz9031_of_load_skew_values(phydev, of_node, 565 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, 566 tx_data_skews, 4); 567 568 /* Silicon Errata Sheet (DS80000691D or DS80000692D): 569 * When the device links in the 1000BASE-T slave mode only, 570 * the optional 125MHz reference output clock (CLK125_NDO) 571 * has wide duty cycle variation. 572 * 573 * The optional CLK125_NDO clock does not meet the RGMII 574 * 45/55 percent (min/max) duty cycle requirement and therefore 575 * cannot be used directly by the MAC side for clocking 576 * applications that have setup/hold time requirements on 577 * rising and falling clock edges. 578 * 579 * Workaround: 580 * Force the phy to be the master to receive a stable clock 581 * which meets the duty cycle requirement. 582 */ 583 if (of_property_read_bool(of_node, "micrel,force-master")) { 584 result = phy_read(phydev, MII_CTRL1000); 585 if (result < 0) 586 goto err_force_master; 587 588 /* enable master mode, config & prefer master */ 589 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER; 590 result = phy_write(phydev, MII_CTRL1000, result); 591 if (result < 0) 592 goto err_force_master; 593 } 594 } 595 596 return ksz9031_center_flp_timing(phydev); 597 598 err_force_master: 599 phydev_err(phydev, "failed to force the phy to master mode\n"); 600 return result; 601 } 602 603 #define KSZ9131_SKEW_5BIT_MAX 2400 604 #define KSZ9131_SKEW_4BIT_MAX 800 605 #define KSZ9131_OFFSET 700 606 #define KSZ9131_STEP 100 607 608 static int ksz9131_of_load_skew_values(struct phy_device *phydev, 609 struct device_node *of_node, 610 u16 reg, size_t field_sz, 611 char *field[], u8 numfields) 612 { 613 int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET), 614 -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)}; 615 int skewval, skewmax = 0; 616 int matches = 0; 617 u16 maxval; 618 u16 newval; 619 u16 mask; 620 int i; 621 622 /* psec properties in dts should mean x pico seconds */ 623 if (field_sz == 5) 624 skewmax = KSZ9131_SKEW_5BIT_MAX; 625 else 626 skewmax = KSZ9131_SKEW_4BIT_MAX; 627 628 for (i = 0; i < numfields; i++) 629 if (!of_property_read_s32(of_node, field[i], &skewval)) { 630 if (skewval < -KSZ9131_OFFSET) 631 skewval = -KSZ9131_OFFSET; 632 else if (skewval > skewmax) 633 skewval = skewmax; 634 635 val[i] = skewval + KSZ9131_OFFSET; 636 matches++; 637 } 638 639 if (!matches) 640 return 0; 641 642 if (matches < numfields) 643 newval = phy_read_mmd(phydev, 2, reg); 644 else 645 newval = 0; 646 647 maxval = (field_sz == 4) ? 0xf : 0x1f; 648 for (i = 0; i < numfields; i++) 649 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) { 650 mask = 0xffff; 651 mask ^= maxval << (field_sz * i); 652 newval = (newval & mask) | 653 (((val[i] / KSZ9131_STEP) & maxval) 654 << (field_sz * i)); 655 } 656 657 return phy_write_mmd(phydev, 2, reg, newval); 658 } 659 660 static int ksz9131_config_init(struct phy_device *phydev) 661 { 662 const struct device *dev = &phydev->mdio.dev; 663 struct device_node *of_node = dev->of_node; 664 char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"}; 665 char *rx_data_skews[4] = { 666 "rxd0-skew-psec", "rxd1-skew-psec", 667 "rxd2-skew-psec", "rxd3-skew-psec" 668 }; 669 char *tx_data_skews[4] = { 670 "txd0-skew-psec", "txd1-skew-psec", 671 "txd2-skew-psec", "txd3-skew-psec" 672 }; 673 char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"}; 674 const struct device *dev_walker; 675 int ret; 676 677 dev_walker = &phydev->mdio.dev; 678 do { 679 of_node = dev_walker->of_node; 680 dev_walker = dev_walker->parent; 681 } while (!of_node && dev_walker); 682 683 if (!of_node) 684 return 0; 685 686 ret = ksz9131_of_load_skew_values(phydev, of_node, 687 MII_KSZ9031RN_CLK_PAD_SKEW, 5, 688 clk_skews, 2); 689 if (ret < 0) 690 return ret; 691 692 ret = ksz9131_of_load_skew_values(phydev, of_node, 693 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, 694 control_skews, 2); 695 if (ret < 0) 696 return ret; 697 698 ret = ksz9131_of_load_skew_values(phydev, of_node, 699 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, 700 rx_data_skews, 4); 701 if (ret < 0) 702 return ret; 703 704 ret = ksz9131_of_load_skew_values(phydev, of_node, 705 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, 706 tx_data_skews, 4); 707 if (ret < 0) 708 return ret; 709 710 return 0; 711 } 712 713 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06 714 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6) 715 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4) 716 static int ksz8873mll_read_status(struct phy_device *phydev) 717 { 718 int regval; 719 720 /* dummy read */ 721 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 722 723 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 724 725 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX) 726 phydev->duplex = DUPLEX_HALF; 727 else 728 phydev->duplex = DUPLEX_FULL; 729 730 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED) 731 phydev->speed = SPEED_10; 732 else 733 phydev->speed = SPEED_100; 734 735 phydev->link = 1; 736 phydev->pause = phydev->asym_pause = 0; 737 738 return 0; 739 } 740 741 static int ksz9031_read_status(struct phy_device *phydev) 742 { 743 int err; 744 int regval; 745 746 err = genphy_read_status(phydev); 747 if (err) 748 return err; 749 750 /* Make sure the PHY is not broken. Read idle error count, 751 * and reset the PHY if it is maxed out. 752 */ 753 regval = phy_read(phydev, MII_STAT1000); 754 if ((regval & 0xFF) == 0xFF) { 755 phy_init_hw(phydev); 756 phydev->link = 0; 757 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev)) 758 phydev->drv->config_intr(phydev); 759 return genphy_config_aneg(phydev); 760 } 761 762 return 0; 763 } 764 765 static int ksz8873mll_config_aneg(struct phy_device *phydev) 766 { 767 return 0; 768 } 769 770 static int kszphy_get_sset_count(struct phy_device *phydev) 771 { 772 return ARRAY_SIZE(kszphy_hw_stats); 773 } 774 775 static void kszphy_get_strings(struct phy_device *phydev, u8 *data) 776 { 777 int i; 778 779 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) { 780 strlcpy(data + i * ETH_GSTRING_LEN, 781 kszphy_hw_stats[i].string, ETH_GSTRING_LEN); 782 } 783 } 784 785 static u64 kszphy_get_stat(struct phy_device *phydev, int i) 786 { 787 struct kszphy_hw_stat stat = kszphy_hw_stats[i]; 788 struct kszphy_priv *priv = phydev->priv; 789 int val; 790 u64 ret; 791 792 val = phy_read(phydev, stat.reg); 793 if (val < 0) { 794 ret = U64_MAX; 795 } else { 796 val = val & ((1 << stat.bits) - 1); 797 priv->stats[i] += val; 798 ret = priv->stats[i]; 799 } 800 801 return ret; 802 } 803 804 static void kszphy_get_stats(struct phy_device *phydev, 805 struct ethtool_stats *stats, u64 *data) 806 { 807 int i; 808 809 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) 810 data[i] = kszphy_get_stat(phydev, i); 811 } 812 813 static int kszphy_suspend(struct phy_device *phydev) 814 { 815 /* Disable PHY Interrupts */ 816 if (phy_interrupt_is_valid(phydev)) { 817 phydev->interrupts = PHY_INTERRUPT_DISABLED; 818 if (phydev->drv->config_intr) 819 phydev->drv->config_intr(phydev); 820 } 821 822 return genphy_suspend(phydev); 823 } 824 825 static int kszphy_resume(struct phy_device *phydev) 826 { 827 int ret; 828 829 genphy_resume(phydev); 830 831 ret = kszphy_config_reset(phydev); 832 if (ret) 833 return ret; 834 835 /* Enable PHY Interrupts */ 836 if (phy_interrupt_is_valid(phydev)) { 837 phydev->interrupts = PHY_INTERRUPT_ENABLED; 838 if (phydev->drv->config_intr) 839 phydev->drv->config_intr(phydev); 840 } 841 842 return 0; 843 } 844 845 static int kszphy_probe(struct phy_device *phydev) 846 { 847 const struct kszphy_type *type = phydev->drv->driver_data; 848 const struct device_node *np = phydev->mdio.dev.of_node; 849 struct kszphy_priv *priv; 850 struct clk *clk; 851 int ret; 852 853 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 854 if (!priv) 855 return -ENOMEM; 856 857 phydev->priv = priv; 858 859 priv->type = type; 860 861 if (type->led_mode_reg) { 862 ret = of_property_read_u32(np, "micrel,led-mode", 863 &priv->led_mode); 864 if (ret) 865 priv->led_mode = -1; 866 867 if (priv->led_mode > 3) { 868 phydev_err(phydev, "invalid led mode: 0x%02x\n", 869 priv->led_mode); 870 priv->led_mode = -1; 871 } 872 } else { 873 priv->led_mode = -1; 874 } 875 876 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref"); 877 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */ 878 if (!IS_ERR_OR_NULL(clk)) { 879 unsigned long rate = clk_get_rate(clk); 880 bool rmii_ref_clk_sel_25_mhz; 881 882 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel; 883 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np, 884 "micrel,rmii-reference-clock-select-25-mhz"); 885 886 if (rate > 24500000 && rate < 25500000) { 887 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz; 888 } else if (rate > 49500000 && rate < 50500000) { 889 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz; 890 } else { 891 phydev_err(phydev, "Clock rate out of range: %ld\n", 892 rate); 893 return -EINVAL; 894 } 895 } 896 897 /* Support legacy board-file configuration */ 898 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) { 899 priv->rmii_ref_clk_sel = true; 900 priv->rmii_ref_clk_sel_val = true; 901 } 902 903 return 0; 904 } 905 906 static struct phy_driver ksphy_driver[] = { 907 { 908 .phy_id = PHY_ID_KS8737, 909 .phy_id_mask = MICREL_PHY_ID_MASK, 910 .name = "Micrel KS8737", 911 .features = PHY_BASIC_FEATURES, 912 .driver_data = &ks8737_type, 913 .config_init = kszphy_config_init, 914 .ack_interrupt = kszphy_ack_interrupt, 915 .config_intr = kszphy_config_intr, 916 .suspend = genphy_suspend, 917 .resume = genphy_resume, 918 }, { 919 .phy_id = PHY_ID_KSZ8021, 920 .phy_id_mask = 0x00ffffff, 921 .name = "Micrel KSZ8021 or KSZ8031", 922 .features = PHY_BASIC_FEATURES, 923 .driver_data = &ksz8021_type, 924 .probe = kszphy_probe, 925 .config_init = kszphy_config_init, 926 .ack_interrupt = kszphy_ack_interrupt, 927 .config_intr = kszphy_config_intr, 928 .get_sset_count = kszphy_get_sset_count, 929 .get_strings = kszphy_get_strings, 930 .get_stats = kszphy_get_stats, 931 .suspend = genphy_suspend, 932 .resume = genphy_resume, 933 }, { 934 .phy_id = PHY_ID_KSZ8031, 935 .phy_id_mask = 0x00ffffff, 936 .name = "Micrel KSZ8031", 937 .features = PHY_BASIC_FEATURES, 938 .driver_data = &ksz8021_type, 939 .probe = kszphy_probe, 940 .config_init = kszphy_config_init, 941 .ack_interrupt = kszphy_ack_interrupt, 942 .config_intr = kszphy_config_intr, 943 .get_sset_count = kszphy_get_sset_count, 944 .get_strings = kszphy_get_strings, 945 .get_stats = kszphy_get_stats, 946 .suspend = genphy_suspend, 947 .resume = genphy_resume, 948 }, { 949 .phy_id = PHY_ID_KSZ8041, 950 .phy_id_mask = MICREL_PHY_ID_MASK, 951 .name = "Micrel KSZ8041", 952 .features = PHY_BASIC_FEATURES, 953 .driver_data = &ksz8041_type, 954 .probe = kszphy_probe, 955 .config_init = ksz8041_config_init, 956 .config_aneg = ksz8041_config_aneg, 957 .ack_interrupt = kszphy_ack_interrupt, 958 .config_intr = kszphy_config_intr, 959 .get_sset_count = kszphy_get_sset_count, 960 .get_strings = kszphy_get_strings, 961 .get_stats = kszphy_get_stats, 962 .suspend = genphy_suspend, 963 .resume = genphy_resume, 964 }, { 965 .phy_id = PHY_ID_KSZ8041RNLI, 966 .phy_id_mask = MICREL_PHY_ID_MASK, 967 .name = "Micrel KSZ8041RNLI", 968 .features = PHY_BASIC_FEATURES, 969 .driver_data = &ksz8041_type, 970 .probe = kszphy_probe, 971 .config_init = kszphy_config_init, 972 .ack_interrupt = kszphy_ack_interrupt, 973 .config_intr = kszphy_config_intr, 974 .get_sset_count = kszphy_get_sset_count, 975 .get_strings = kszphy_get_strings, 976 .get_stats = kszphy_get_stats, 977 .suspend = genphy_suspend, 978 .resume = genphy_resume, 979 }, { 980 .phy_id = PHY_ID_KSZ8051, 981 .phy_id_mask = MICREL_PHY_ID_MASK, 982 .name = "Micrel KSZ8051", 983 .features = PHY_BASIC_FEATURES, 984 .driver_data = &ksz8051_type, 985 .probe = kszphy_probe, 986 .config_init = kszphy_config_init, 987 .ack_interrupt = kszphy_ack_interrupt, 988 .config_intr = kszphy_config_intr, 989 .get_sset_count = kszphy_get_sset_count, 990 .get_strings = kszphy_get_strings, 991 .get_stats = kszphy_get_stats, 992 .suspend = genphy_suspend, 993 .resume = genphy_resume, 994 }, { 995 .phy_id = PHY_ID_KSZ8001, 996 .name = "Micrel KSZ8001 or KS8721", 997 .phy_id_mask = 0x00fffffc, 998 .features = PHY_BASIC_FEATURES, 999 .driver_data = &ksz8041_type, 1000 .probe = kszphy_probe, 1001 .config_init = kszphy_config_init, 1002 .ack_interrupt = kszphy_ack_interrupt, 1003 .config_intr = kszphy_config_intr, 1004 .get_sset_count = kszphy_get_sset_count, 1005 .get_strings = kszphy_get_strings, 1006 .get_stats = kszphy_get_stats, 1007 .suspend = genphy_suspend, 1008 .resume = genphy_resume, 1009 }, { 1010 .phy_id = PHY_ID_KSZ8081, 1011 .name = "Micrel KSZ8081 or KSZ8091", 1012 .phy_id_mask = MICREL_PHY_ID_MASK, 1013 .features = PHY_BASIC_FEATURES, 1014 .driver_data = &ksz8081_type, 1015 .probe = kszphy_probe, 1016 .config_init = kszphy_config_init, 1017 .ack_interrupt = kszphy_ack_interrupt, 1018 .config_intr = kszphy_config_intr, 1019 .get_sset_count = kszphy_get_sset_count, 1020 .get_strings = kszphy_get_strings, 1021 .get_stats = kszphy_get_stats, 1022 .suspend = kszphy_suspend, 1023 .resume = kszphy_resume, 1024 }, { 1025 .phy_id = PHY_ID_KSZ8061, 1026 .name = "Micrel KSZ8061", 1027 .phy_id_mask = MICREL_PHY_ID_MASK, 1028 .features = PHY_BASIC_FEATURES, 1029 .config_init = ksz8061_config_init, 1030 .ack_interrupt = kszphy_ack_interrupt, 1031 .config_intr = kszphy_config_intr, 1032 .suspend = genphy_suspend, 1033 .resume = genphy_resume, 1034 }, { 1035 .phy_id = PHY_ID_KSZ9021, 1036 .phy_id_mask = 0x000ffffe, 1037 .name = "Micrel KSZ9021 Gigabit PHY", 1038 .features = PHY_GBIT_FEATURES, 1039 .driver_data = &ksz9021_type, 1040 .probe = kszphy_probe, 1041 .config_init = ksz9021_config_init, 1042 .ack_interrupt = kszphy_ack_interrupt, 1043 .config_intr = kszphy_config_intr, 1044 .get_sset_count = kszphy_get_sset_count, 1045 .get_strings = kszphy_get_strings, 1046 .get_stats = kszphy_get_stats, 1047 .suspend = genphy_suspend, 1048 .resume = genphy_resume, 1049 .read_mmd = genphy_read_mmd_unsupported, 1050 .write_mmd = genphy_write_mmd_unsupported, 1051 }, { 1052 .phy_id = PHY_ID_KSZ9031, 1053 .phy_id_mask = MICREL_PHY_ID_MASK, 1054 .name = "Micrel KSZ9031 Gigabit PHY", 1055 .features = PHY_GBIT_FEATURES, 1056 .driver_data = &ksz9021_type, 1057 .probe = kszphy_probe, 1058 .config_init = ksz9031_config_init, 1059 .soft_reset = genphy_soft_reset, 1060 .read_status = ksz9031_read_status, 1061 .ack_interrupt = kszphy_ack_interrupt, 1062 .config_intr = kszphy_config_intr, 1063 .get_sset_count = kszphy_get_sset_count, 1064 .get_strings = kszphy_get_strings, 1065 .get_stats = kszphy_get_stats, 1066 .suspend = genphy_suspend, 1067 .resume = kszphy_resume, 1068 }, { 1069 .phy_id = PHY_ID_KSZ9131, 1070 .phy_id_mask = MICREL_PHY_ID_MASK, 1071 .name = "Microchip KSZ9131 Gigabit PHY", 1072 .features = PHY_GBIT_FEATURES, 1073 .driver_data = &ksz9021_type, 1074 .probe = kszphy_probe, 1075 .config_init = ksz9131_config_init, 1076 .read_status = ksz9031_read_status, 1077 .ack_interrupt = kszphy_ack_interrupt, 1078 .config_intr = kszphy_config_intr, 1079 .get_sset_count = kszphy_get_sset_count, 1080 .get_strings = kszphy_get_strings, 1081 .get_stats = kszphy_get_stats, 1082 .suspend = genphy_suspend, 1083 .resume = kszphy_resume, 1084 }, { 1085 .phy_id = PHY_ID_KSZ8873MLL, 1086 .phy_id_mask = MICREL_PHY_ID_MASK, 1087 .name = "Micrel KSZ8873MLL Switch", 1088 .features = PHY_BASIC_FEATURES, 1089 .config_init = kszphy_config_init, 1090 .config_aneg = ksz8873mll_config_aneg, 1091 .read_status = ksz8873mll_read_status, 1092 .suspend = genphy_suspend, 1093 .resume = genphy_resume, 1094 }, { 1095 .phy_id = PHY_ID_KSZ886X, 1096 .phy_id_mask = MICREL_PHY_ID_MASK, 1097 .name = "Micrel KSZ886X Switch", 1098 .features = PHY_BASIC_FEATURES, 1099 .config_init = kszphy_config_init, 1100 .suspend = genphy_suspend, 1101 .resume = genphy_resume, 1102 }, { 1103 .phy_id = PHY_ID_KSZ8795, 1104 .phy_id_mask = MICREL_PHY_ID_MASK, 1105 .name = "Micrel KSZ8795", 1106 .features = PHY_BASIC_FEATURES, 1107 .config_init = kszphy_config_init, 1108 .config_aneg = ksz8873mll_config_aneg, 1109 .read_status = ksz8873mll_read_status, 1110 .suspend = genphy_suspend, 1111 .resume = genphy_resume, 1112 }, { 1113 .phy_id = PHY_ID_KSZ9477, 1114 .phy_id_mask = MICREL_PHY_ID_MASK, 1115 .name = "Microchip KSZ9477", 1116 .features = PHY_GBIT_FEATURES, 1117 .config_init = kszphy_config_init, 1118 .suspend = genphy_suspend, 1119 .resume = genphy_resume, 1120 } }; 1121 1122 module_phy_driver(ksphy_driver); 1123 1124 MODULE_DESCRIPTION("Micrel PHY driver"); 1125 MODULE_AUTHOR("David J. Choi"); 1126 MODULE_LICENSE("GPL"); 1127 1128 static struct mdio_device_id __maybe_unused micrel_tbl[] = { 1129 { PHY_ID_KSZ9021, 0x000ffffe }, 1130 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK }, 1131 { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK }, 1132 { PHY_ID_KSZ8001, 0x00fffffc }, 1133 { PHY_ID_KS8737, MICREL_PHY_ID_MASK }, 1134 { PHY_ID_KSZ8021, 0x00ffffff }, 1135 { PHY_ID_KSZ8031, 0x00ffffff }, 1136 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK }, 1137 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK }, 1138 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK }, 1139 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK }, 1140 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK }, 1141 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK }, 1142 { } 1143 }; 1144 1145 MODULE_DEVICE_TABLE(mdio, micrel_tbl); 1146