1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/micrel.c 4 * 5 * Driver for Micrel PHYs 6 * 7 * Author: David J. Choi 8 * 9 * Copyright (c) 2010-2013 Micrel, Inc. 10 * Copyright (c) 2014 Johan Hovold <johan@kernel.org> 11 * 12 * Support : Micrel Phys: 13 * Giga phys: ksz9021, ksz9031, ksz9131 14 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041 15 * ksz8021, ksz8031, ksz8051, 16 * ksz8081, ksz8091, 17 * ksz8061, 18 * Switch : ksz8873, ksz886x 19 * ksz9477 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/phy.h> 25 #include <linux/micrel_phy.h> 26 #include <linux/of.h> 27 #include <linux/clk.h> 28 29 /* Operation Mode Strap Override */ 30 #define MII_KSZPHY_OMSO 0x16 31 #define KSZPHY_OMSO_FACTORY_TEST BIT(15) 32 #define KSZPHY_OMSO_B_CAST_OFF BIT(9) 33 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5) 34 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1) 35 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0) 36 37 /* general Interrupt control/status reg in vendor specific block. */ 38 #define MII_KSZPHY_INTCS 0x1B 39 #define KSZPHY_INTCS_JABBER BIT(15) 40 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14) 41 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13) 42 #define KSZPHY_INTCS_PARELLEL BIT(12) 43 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11) 44 #define KSZPHY_INTCS_LINK_DOWN BIT(10) 45 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9) 46 #define KSZPHY_INTCS_LINK_UP BIT(8) 47 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\ 48 KSZPHY_INTCS_LINK_DOWN) 49 50 /* PHY Control 1 */ 51 #define MII_KSZPHY_CTRL_1 0x1e 52 53 /* PHY Control 2 / PHY Control (if no PHY Control 1) */ 54 #define MII_KSZPHY_CTRL_2 0x1f 55 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2 56 /* bitmap of PHY register to set interrupt mode */ 57 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9) 58 #define KSZPHY_RMII_REF_CLK_SEL BIT(7) 59 60 /* Write/read to/from extended registers */ 61 #define MII_KSZPHY_EXTREG 0x0b 62 #define KSZPHY_EXTREG_WRITE 0x8000 63 64 #define MII_KSZPHY_EXTREG_WRITE 0x0c 65 #define MII_KSZPHY_EXTREG_READ 0x0d 66 67 /* Extended registers */ 68 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104 69 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105 70 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106 71 72 #define PS_TO_REG 200 73 74 struct kszphy_hw_stat { 75 const char *string; 76 u8 reg; 77 u8 bits; 78 }; 79 80 static struct kszphy_hw_stat kszphy_hw_stats[] = { 81 { "phy_receive_errors", 21, 16}, 82 { "phy_idle_errors", 10, 8 }, 83 }; 84 85 struct kszphy_type { 86 u32 led_mode_reg; 87 u16 interrupt_level_mask; 88 bool has_broadcast_disable; 89 bool has_nand_tree_disable; 90 bool has_rmii_ref_clk_sel; 91 }; 92 93 struct kszphy_priv { 94 const struct kszphy_type *type; 95 int led_mode; 96 bool rmii_ref_clk_sel; 97 bool rmii_ref_clk_sel_val; 98 u64 stats[ARRAY_SIZE(kszphy_hw_stats)]; 99 }; 100 101 static const struct kszphy_type ksz8021_type = { 102 .led_mode_reg = MII_KSZPHY_CTRL_2, 103 .has_broadcast_disable = true, 104 .has_nand_tree_disable = true, 105 .has_rmii_ref_clk_sel = true, 106 }; 107 108 static const struct kszphy_type ksz8041_type = { 109 .led_mode_reg = MII_KSZPHY_CTRL_1, 110 }; 111 112 static const struct kszphy_type ksz8051_type = { 113 .led_mode_reg = MII_KSZPHY_CTRL_2, 114 .has_nand_tree_disable = true, 115 }; 116 117 static const struct kszphy_type ksz8081_type = { 118 .led_mode_reg = MII_KSZPHY_CTRL_2, 119 .has_broadcast_disable = true, 120 .has_nand_tree_disable = true, 121 .has_rmii_ref_clk_sel = true, 122 }; 123 124 static const struct kszphy_type ks8737_type = { 125 .interrupt_level_mask = BIT(14), 126 }; 127 128 static const struct kszphy_type ksz9021_type = { 129 .interrupt_level_mask = BIT(14), 130 }; 131 132 static int kszphy_extended_write(struct phy_device *phydev, 133 u32 regnum, u16 val) 134 { 135 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum); 136 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); 137 } 138 139 static int kszphy_extended_read(struct phy_device *phydev, 140 u32 regnum) 141 { 142 phy_write(phydev, MII_KSZPHY_EXTREG, regnum); 143 return phy_read(phydev, MII_KSZPHY_EXTREG_READ); 144 } 145 146 static int kszphy_ack_interrupt(struct phy_device *phydev) 147 { 148 /* bit[7..0] int status, which is a read and clear register. */ 149 int rc; 150 151 rc = phy_read(phydev, MII_KSZPHY_INTCS); 152 153 return (rc < 0) ? rc : 0; 154 } 155 156 static int kszphy_config_intr(struct phy_device *phydev) 157 { 158 const struct kszphy_type *type = phydev->drv->driver_data; 159 int temp; 160 u16 mask; 161 162 if (type && type->interrupt_level_mask) 163 mask = type->interrupt_level_mask; 164 else 165 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH; 166 167 /* set the interrupt pin active low */ 168 temp = phy_read(phydev, MII_KSZPHY_CTRL); 169 if (temp < 0) 170 return temp; 171 temp &= ~mask; 172 phy_write(phydev, MII_KSZPHY_CTRL, temp); 173 174 /* enable / disable interrupts */ 175 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 176 temp = KSZPHY_INTCS_ALL; 177 else 178 temp = 0; 179 180 return phy_write(phydev, MII_KSZPHY_INTCS, temp); 181 } 182 183 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val) 184 { 185 int ctrl; 186 187 ctrl = phy_read(phydev, MII_KSZPHY_CTRL); 188 if (ctrl < 0) 189 return ctrl; 190 191 if (val) 192 ctrl |= KSZPHY_RMII_REF_CLK_SEL; 193 else 194 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL; 195 196 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl); 197 } 198 199 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val) 200 { 201 int rc, temp, shift; 202 203 switch (reg) { 204 case MII_KSZPHY_CTRL_1: 205 shift = 14; 206 break; 207 case MII_KSZPHY_CTRL_2: 208 shift = 4; 209 break; 210 default: 211 return -EINVAL; 212 } 213 214 temp = phy_read(phydev, reg); 215 if (temp < 0) { 216 rc = temp; 217 goto out; 218 } 219 220 temp &= ~(3 << shift); 221 temp |= val << shift; 222 rc = phy_write(phydev, reg, temp); 223 out: 224 if (rc < 0) 225 phydev_err(phydev, "failed to set led mode\n"); 226 227 return rc; 228 } 229 230 /* Disable PHY address 0 as the broadcast address, so that it can be used as a 231 * unique (non-broadcast) address on a shared bus. 232 */ 233 static int kszphy_broadcast_disable(struct phy_device *phydev) 234 { 235 int ret; 236 237 ret = phy_read(phydev, MII_KSZPHY_OMSO); 238 if (ret < 0) 239 goto out; 240 241 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF); 242 out: 243 if (ret) 244 phydev_err(phydev, "failed to disable broadcast address\n"); 245 246 return ret; 247 } 248 249 static int kszphy_nand_tree_disable(struct phy_device *phydev) 250 { 251 int ret; 252 253 ret = phy_read(phydev, MII_KSZPHY_OMSO); 254 if (ret < 0) 255 goto out; 256 257 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON)) 258 return 0; 259 260 ret = phy_write(phydev, MII_KSZPHY_OMSO, 261 ret & ~KSZPHY_OMSO_NAND_TREE_ON); 262 out: 263 if (ret) 264 phydev_err(phydev, "failed to disable NAND tree mode\n"); 265 266 return ret; 267 } 268 269 /* Some config bits need to be set again on resume, handle them here. */ 270 static int kszphy_config_reset(struct phy_device *phydev) 271 { 272 struct kszphy_priv *priv = phydev->priv; 273 int ret; 274 275 if (priv->rmii_ref_clk_sel) { 276 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val); 277 if (ret) { 278 phydev_err(phydev, 279 "failed to set rmii reference clock\n"); 280 return ret; 281 } 282 } 283 284 if (priv->led_mode >= 0) 285 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode); 286 287 return 0; 288 } 289 290 static int kszphy_config_init(struct phy_device *phydev) 291 { 292 struct kszphy_priv *priv = phydev->priv; 293 const struct kszphy_type *type; 294 295 if (!priv) 296 return 0; 297 298 type = priv->type; 299 300 if (type->has_broadcast_disable) 301 kszphy_broadcast_disable(phydev); 302 303 if (type->has_nand_tree_disable) 304 kszphy_nand_tree_disable(phydev); 305 306 return kszphy_config_reset(phydev); 307 } 308 309 static int ksz8041_config_init(struct phy_device *phydev) 310 { 311 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 312 313 struct device_node *of_node = phydev->mdio.dev.of_node; 314 315 /* Limit supported and advertised modes in fiber mode */ 316 if (of_property_read_bool(of_node, "micrel,fiber-mode")) { 317 phydev->dev_flags |= MICREL_PHY_FXEN; 318 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask); 319 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask); 320 321 linkmode_and(phydev->supported, phydev->supported, mask); 322 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 323 phydev->supported); 324 linkmode_and(phydev->advertising, phydev->advertising, mask); 325 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 326 phydev->advertising); 327 phydev->autoneg = AUTONEG_DISABLE; 328 } 329 330 return kszphy_config_init(phydev); 331 } 332 333 static int ksz8041_config_aneg(struct phy_device *phydev) 334 { 335 /* Skip auto-negotiation in fiber mode */ 336 if (phydev->dev_flags & MICREL_PHY_FXEN) { 337 phydev->speed = SPEED_100; 338 return 0; 339 } 340 341 return genphy_config_aneg(phydev); 342 } 343 344 static int ksz8081_config_init(struct phy_device *phydev) 345 { 346 /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line 347 * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a 348 * pull-down is missing, the factory test mode should be cleared by 349 * manually writing a 0. 350 */ 351 phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST); 352 353 return kszphy_config_init(phydev); 354 } 355 356 static int ksz8061_config_init(struct phy_device *phydev) 357 { 358 int ret; 359 360 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A); 361 if (ret) 362 return ret; 363 364 return kszphy_config_init(phydev); 365 } 366 367 static int ksz9021_load_values_from_of(struct phy_device *phydev, 368 const struct device_node *of_node, 369 u16 reg, 370 const char *field1, const char *field2, 371 const char *field3, const char *field4) 372 { 373 int val1 = -1; 374 int val2 = -2; 375 int val3 = -3; 376 int val4 = -4; 377 int newval; 378 int matches = 0; 379 380 if (!of_property_read_u32(of_node, field1, &val1)) 381 matches++; 382 383 if (!of_property_read_u32(of_node, field2, &val2)) 384 matches++; 385 386 if (!of_property_read_u32(of_node, field3, &val3)) 387 matches++; 388 389 if (!of_property_read_u32(of_node, field4, &val4)) 390 matches++; 391 392 if (!matches) 393 return 0; 394 395 if (matches < 4) 396 newval = kszphy_extended_read(phydev, reg); 397 else 398 newval = 0; 399 400 if (val1 != -1) 401 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0); 402 403 if (val2 != -2) 404 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4); 405 406 if (val3 != -3) 407 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8); 408 409 if (val4 != -4) 410 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12); 411 412 return kszphy_extended_write(phydev, reg, newval); 413 } 414 415 static int ksz9021_config_init(struct phy_device *phydev) 416 { 417 const struct device *dev = &phydev->mdio.dev; 418 const struct device_node *of_node = dev->of_node; 419 const struct device *dev_walker; 420 421 /* The Micrel driver has a deprecated option to place phy OF 422 * properties in the MAC node. Walk up the tree of devices to 423 * find a device with an OF node. 424 */ 425 dev_walker = &phydev->mdio.dev; 426 do { 427 of_node = dev_walker->of_node; 428 dev_walker = dev_walker->parent; 429 430 } while (!of_node && dev_walker); 431 432 if (of_node) { 433 ksz9021_load_values_from_of(phydev, of_node, 434 MII_KSZPHY_CLK_CONTROL_PAD_SKEW, 435 "txen-skew-ps", "txc-skew-ps", 436 "rxdv-skew-ps", "rxc-skew-ps"); 437 ksz9021_load_values_from_of(phydev, of_node, 438 MII_KSZPHY_RX_DATA_PAD_SKEW, 439 "rxd0-skew-ps", "rxd1-skew-ps", 440 "rxd2-skew-ps", "rxd3-skew-ps"); 441 ksz9021_load_values_from_of(phydev, of_node, 442 MII_KSZPHY_TX_DATA_PAD_SKEW, 443 "txd0-skew-ps", "txd1-skew-ps", 444 "txd2-skew-ps", "txd3-skew-ps"); 445 } 446 return 0; 447 } 448 449 #define KSZ9031_PS_TO_REG 60 450 451 /* Extended registers */ 452 /* MMD Address 0x0 */ 453 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3 454 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4 455 456 /* MMD Address 0x2 */ 457 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4 458 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5 459 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6 460 #define MII_KSZ9031RN_CLK_PAD_SKEW 8 461 462 /* MMD Address 0x1C */ 463 #define MII_KSZ9031RN_EDPD 0x23 464 #define MII_KSZ9031RN_EDPD_ENABLE BIT(0) 465 466 static int ksz9031_of_load_skew_values(struct phy_device *phydev, 467 const struct device_node *of_node, 468 u16 reg, size_t field_sz, 469 const char *field[], u8 numfields) 470 { 471 int val[4] = {-1, -2, -3, -4}; 472 int matches = 0; 473 u16 mask; 474 u16 maxval; 475 u16 newval; 476 int i; 477 478 for (i = 0; i < numfields; i++) 479 if (!of_property_read_u32(of_node, field[i], val + i)) 480 matches++; 481 482 if (!matches) 483 return 0; 484 485 if (matches < numfields) 486 newval = phy_read_mmd(phydev, 2, reg); 487 else 488 newval = 0; 489 490 maxval = (field_sz == 4) ? 0xf : 0x1f; 491 for (i = 0; i < numfields; i++) 492 if (val[i] != -(i + 1)) { 493 mask = 0xffff; 494 mask ^= maxval << (field_sz * i); 495 newval = (newval & mask) | 496 (((val[i] / KSZ9031_PS_TO_REG) & maxval) 497 << (field_sz * i)); 498 } 499 500 return phy_write_mmd(phydev, 2, reg, newval); 501 } 502 503 /* Center KSZ9031RNX FLP timing at 16ms. */ 504 static int ksz9031_center_flp_timing(struct phy_device *phydev) 505 { 506 int result; 507 508 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI, 509 0x0006); 510 if (result) 511 return result; 512 513 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO, 514 0x1A80); 515 if (result) 516 return result; 517 518 return genphy_restart_aneg(phydev); 519 } 520 521 /* Enable energy-detect power-down mode */ 522 static int ksz9031_enable_edpd(struct phy_device *phydev) 523 { 524 int reg; 525 526 reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD); 527 if (reg < 0) 528 return reg; 529 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD, 530 reg | MII_KSZ9031RN_EDPD_ENABLE); 531 } 532 533 static int ksz9031_config_init(struct phy_device *phydev) 534 { 535 const struct device *dev = &phydev->mdio.dev; 536 const struct device_node *of_node = dev->of_node; 537 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"}; 538 static const char *rx_data_skews[4] = { 539 "rxd0-skew-ps", "rxd1-skew-ps", 540 "rxd2-skew-ps", "rxd3-skew-ps" 541 }; 542 static const char *tx_data_skews[4] = { 543 "txd0-skew-ps", "txd1-skew-ps", 544 "txd2-skew-ps", "txd3-skew-ps" 545 }; 546 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"}; 547 const struct device *dev_walker; 548 int result; 549 550 result = ksz9031_enable_edpd(phydev); 551 if (result < 0) 552 return result; 553 554 /* The Micrel driver has a deprecated option to place phy OF 555 * properties in the MAC node. Walk up the tree of devices to 556 * find a device with an OF node. 557 */ 558 dev_walker = &phydev->mdio.dev; 559 do { 560 of_node = dev_walker->of_node; 561 dev_walker = dev_walker->parent; 562 } while (!of_node && dev_walker); 563 564 if (of_node) { 565 ksz9031_of_load_skew_values(phydev, of_node, 566 MII_KSZ9031RN_CLK_PAD_SKEW, 5, 567 clk_skews, 2); 568 569 ksz9031_of_load_skew_values(phydev, of_node, 570 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, 571 control_skews, 2); 572 573 ksz9031_of_load_skew_values(phydev, of_node, 574 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, 575 rx_data_skews, 4); 576 577 ksz9031_of_load_skew_values(phydev, of_node, 578 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, 579 tx_data_skews, 4); 580 581 /* Silicon Errata Sheet (DS80000691D or DS80000692D): 582 * When the device links in the 1000BASE-T slave mode only, 583 * the optional 125MHz reference output clock (CLK125_NDO) 584 * has wide duty cycle variation. 585 * 586 * The optional CLK125_NDO clock does not meet the RGMII 587 * 45/55 percent (min/max) duty cycle requirement and therefore 588 * cannot be used directly by the MAC side for clocking 589 * applications that have setup/hold time requirements on 590 * rising and falling clock edges. 591 * 592 * Workaround: 593 * Force the phy to be the master to receive a stable clock 594 * which meets the duty cycle requirement. 595 */ 596 if (of_property_read_bool(of_node, "micrel,force-master")) { 597 result = phy_read(phydev, MII_CTRL1000); 598 if (result < 0) 599 goto err_force_master; 600 601 /* enable master mode, config & prefer master */ 602 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER; 603 result = phy_write(phydev, MII_CTRL1000, result); 604 if (result < 0) 605 goto err_force_master; 606 } 607 } 608 609 return ksz9031_center_flp_timing(phydev); 610 611 err_force_master: 612 phydev_err(phydev, "failed to force the phy to master mode\n"); 613 return result; 614 } 615 616 #define KSZ9131_SKEW_5BIT_MAX 2400 617 #define KSZ9131_SKEW_4BIT_MAX 800 618 #define KSZ9131_OFFSET 700 619 #define KSZ9131_STEP 100 620 621 static int ksz9131_of_load_skew_values(struct phy_device *phydev, 622 struct device_node *of_node, 623 u16 reg, size_t field_sz, 624 char *field[], u8 numfields) 625 { 626 int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET), 627 -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)}; 628 int skewval, skewmax = 0; 629 int matches = 0; 630 u16 maxval; 631 u16 newval; 632 u16 mask; 633 int i; 634 635 /* psec properties in dts should mean x pico seconds */ 636 if (field_sz == 5) 637 skewmax = KSZ9131_SKEW_5BIT_MAX; 638 else 639 skewmax = KSZ9131_SKEW_4BIT_MAX; 640 641 for (i = 0; i < numfields; i++) 642 if (!of_property_read_s32(of_node, field[i], &skewval)) { 643 if (skewval < -KSZ9131_OFFSET) 644 skewval = -KSZ9131_OFFSET; 645 else if (skewval > skewmax) 646 skewval = skewmax; 647 648 val[i] = skewval + KSZ9131_OFFSET; 649 matches++; 650 } 651 652 if (!matches) 653 return 0; 654 655 if (matches < numfields) 656 newval = phy_read_mmd(phydev, 2, reg); 657 else 658 newval = 0; 659 660 maxval = (field_sz == 4) ? 0xf : 0x1f; 661 for (i = 0; i < numfields; i++) 662 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) { 663 mask = 0xffff; 664 mask ^= maxval << (field_sz * i); 665 newval = (newval & mask) | 666 (((val[i] / KSZ9131_STEP) & maxval) 667 << (field_sz * i)); 668 } 669 670 return phy_write_mmd(phydev, 2, reg, newval); 671 } 672 673 static int ksz9131_config_init(struct phy_device *phydev) 674 { 675 const struct device *dev = &phydev->mdio.dev; 676 struct device_node *of_node = dev->of_node; 677 char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"}; 678 char *rx_data_skews[4] = { 679 "rxd0-skew-psec", "rxd1-skew-psec", 680 "rxd2-skew-psec", "rxd3-skew-psec" 681 }; 682 char *tx_data_skews[4] = { 683 "txd0-skew-psec", "txd1-skew-psec", 684 "txd2-skew-psec", "txd3-skew-psec" 685 }; 686 char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"}; 687 const struct device *dev_walker; 688 int ret; 689 690 dev_walker = &phydev->mdio.dev; 691 do { 692 of_node = dev_walker->of_node; 693 dev_walker = dev_walker->parent; 694 } while (!of_node && dev_walker); 695 696 if (!of_node) 697 return 0; 698 699 ret = ksz9131_of_load_skew_values(phydev, of_node, 700 MII_KSZ9031RN_CLK_PAD_SKEW, 5, 701 clk_skews, 2); 702 if (ret < 0) 703 return ret; 704 705 ret = ksz9131_of_load_skew_values(phydev, of_node, 706 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, 707 control_skews, 2); 708 if (ret < 0) 709 return ret; 710 711 ret = ksz9131_of_load_skew_values(phydev, of_node, 712 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, 713 rx_data_skews, 4); 714 if (ret < 0) 715 return ret; 716 717 ret = ksz9131_of_load_skew_values(phydev, of_node, 718 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, 719 tx_data_skews, 4); 720 if (ret < 0) 721 return ret; 722 723 return 0; 724 } 725 726 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06 727 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6) 728 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4) 729 static int ksz8873mll_read_status(struct phy_device *phydev) 730 { 731 int regval; 732 733 /* dummy read */ 734 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 735 736 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 737 738 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX) 739 phydev->duplex = DUPLEX_HALF; 740 else 741 phydev->duplex = DUPLEX_FULL; 742 743 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED) 744 phydev->speed = SPEED_10; 745 else 746 phydev->speed = SPEED_100; 747 748 phydev->link = 1; 749 phydev->pause = phydev->asym_pause = 0; 750 751 return 0; 752 } 753 754 static int ksz9031_get_features(struct phy_device *phydev) 755 { 756 int ret; 757 758 ret = genphy_read_abilities(phydev); 759 if (ret < 0) 760 return ret; 761 762 /* Silicon Errata Sheet (DS80000691D or DS80000692D): 763 * Whenever the device's Asymmetric Pause capability is set to 1, 764 * link-up may fail after a link-up to link-down transition. 765 * 766 * The Errata Sheet is for ksz9031, but ksz9021 has the same issue 767 * 768 * Workaround: 769 * Do not enable the Asymmetric Pause capability bit. 770 */ 771 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported); 772 773 /* We force setting the Pause capability as the core will force the 774 * Asymmetric Pause capability to 1 otherwise. 775 */ 776 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported); 777 778 return 0; 779 } 780 781 static int ksz9031_read_status(struct phy_device *phydev) 782 { 783 int err; 784 int regval; 785 786 err = genphy_read_status(phydev); 787 if (err) 788 return err; 789 790 /* Make sure the PHY is not broken. Read idle error count, 791 * and reset the PHY if it is maxed out. 792 */ 793 regval = phy_read(phydev, MII_STAT1000); 794 if ((regval & 0xFF) == 0xFF) { 795 phy_init_hw(phydev); 796 phydev->link = 0; 797 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev)) 798 phydev->drv->config_intr(phydev); 799 return genphy_config_aneg(phydev); 800 } 801 802 return 0; 803 } 804 805 static int ksz8873mll_config_aneg(struct phy_device *phydev) 806 { 807 return 0; 808 } 809 810 static int kszphy_get_sset_count(struct phy_device *phydev) 811 { 812 return ARRAY_SIZE(kszphy_hw_stats); 813 } 814 815 static void kszphy_get_strings(struct phy_device *phydev, u8 *data) 816 { 817 int i; 818 819 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) { 820 strlcpy(data + i * ETH_GSTRING_LEN, 821 kszphy_hw_stats[i].string, ETH_GSTRING_LEN); 822 } 823 } 824 825 static u64 kszphy_get_stat(struct phy_device *phydev, int i) 826 { 827 struct kszphy_hw_stat stat = kszphy_hw_stats[i]; 828 struct kszphy_priv *priv = phydev->priv; 829 int val; 830 u64 ret; 831 832 val = phy_read(phydev, stat.reg); 833 if (val < 0) { 834 ret = U64_MAX; 835 } else { 836 val = val & ((1 << stat.bits) - 1); 837 priv->stats[i] += val; 838 ret = priv->stats[i]; 839 } 840 841 return ret; 842 } 843 844 static void kszphy_get_stats(struct phy_device *phydev, 845 struct ethtool_stats *stats, u64 *data) 846 { 847 int i; 848 849 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) 850 data[i] = kszphy_get_stat(phydev, i); 851 } 852 853 static int kszphy_suspend(struct phy_device *phydev) 854 { 855 /* Disable PHY Interrupts */ 856 if (phy_interrupt_is_valid(phydev)) { 857 phydev->interrupts = PHY_INTERRUPT_DISABLED; 858 if (phydev->drv->config_intr) 859 phydev->drv->config_intr(phydev); 860 } 861 862 return genphy_suspend(phydev); 863 } 864 865 static int kszphy_resume(struct phy_device *phydev) 866 { 867 int ret; 868 869 genphy_resume(phydev); 870 871 ret = kszphy_config_reset(phydev); 872 if (ret) 873 return ret; 874 875 /* Enable PHY Interrupts */ 876 if (phy_interrupt_is_valid(phydev)) { 877 phydev->interrupts = PHY_INTERRUPT_ENABLED; 878 if (phydev->drv->config_intr) 879 phydev->drv->config_intr(phydev); 880 } 881 882 return 0; 883 } 884 885 static int kszphy_probe(struct phy_device *phydev) 886 { 887 const struct kszphy_type *type = phydev->drv->driver_data; 888 const struct device_node *np = phydev->mdio.dev.of_node; 889 struct kszphy_priv *priv; 890 struct clk *clk; 891 int ret; 892 893 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 894 if (!priv) 895 return -ENOMEM; 896 897 phydev->priv = priv; 898 899 priv->type = type; 900 901 if (type->led_mode_reg) { 902 ret = of_property_read_u32(np, "micrel,led-mode", 903 &priv->led_mode); 904 if (ret) 905 priv->led_mode = -1; 906 907 if (priv->led_mode > 3) { 908 phydev_err(phydev, "invalid led mode: 0x%02x\n", 909 priv->led_mode); 910 priv->led_mode = -1; 911 } 912 } else { 913 priv->led_mode = -1; 914 } 915 916 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref"); 917 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */ 918 if (!IS_ERR_OR_NULL(clk)) { 919 unsigned long rate = clk_get_rate(clk); 920 bool rmii_ref_clk_sel_25_mhz; 921 922 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel; 923 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np, 924 "micrel,rmii-reference-clock-select-25-mhz"); 925 926 if (rate > 24500000 && rate < 25500000) { 927 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz; 928 } else if (rate > 49500000 && rate < 50500000) { 929 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz; 930 } else { 931 phydev_err(phydev, "Clock rate out of range: %ld\n", 932 rate); 933 return -EINVAL; 934 } 935 } 936 937 /* Support legacy board-file configuration */ 938 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) { 939 priv->rmii_ref_clk_sel = true; 940 priv->rmii_ref_clk_sel_val = true; 941 } 942 943 return 0; 944 } 945 946 static struct phy_driver ksphy_driver[] = { 947 { 948 .phy_id = PHY_ID_KS8737, 949 .phy_id_mask = MICREL_PHY_ID_MASK, 950 .name = "Micrel KS8737", 951 /* PHY_BASIC_FEATURES */ 952 .driver_data = &ks8737_type, 953 .config_init = kszphy_config_init, 954 .ack_interrupt = kszphy_ack_interrupt, 955 .config_intr = kszphy_config_intr, 956 .suspend = genphy_suspend, 957 .resume = genphy_resume, 958 }, { 959 .phy_id = PHY_ID_KSZ8021, 960 .phy_id_mask = 0x00ffffff, 961 .name = "Micrel KSZ8021 or KSZ8031", 962 /* PHY_BASIC_FEATURES */ 963 .driver_data = &ksz8021_type, 964 .probe = kszphy_probe, 965 .config_init = kszphy_config_init, 966 .ack_interrupt = kszphy_ack_interrupt, 967 .config_intr = kszphy_config_intr, 968 .get_sset_count = kszphy_get_sset_count, 969 .get_strings = kszphy_get_strings, 970 .get_stats = kszphy_get_stats, 971 .suspend = genphy_suspend, 972 .resume = genphy_resume, 973 }, { 974 .phy_id = PHY_ID_KSZ8031, 975 .phy_id_mask = 0x00ffffff, 976 .name = "Micrel KSZ8031", 977 /* PHY_BASIC_FEATURES */ 978 .driver_data = &ksz8021_type, 979 .probe = kszphy_probe, 980 .config_init = kszphy_config_init, 981 .ack_interrupt = kszphy_ack_interrupt, 982 .config_intr = kszphy_config_intr, 983 .get_sset_count = kszphy_get_sset_count, 984 .get_strings = kszphy_get_strings, 985 .get_stats = kszphy_get_stats, 986 .suspend = genphy_suspend, 987 .resume = genphy_resume, 988 }, { 989 .phy_id = PHY_ID_KSZ8041, 990 .phy_id_mask = MICREL_PHY_ID_MASK, 991 .name = "Micrel KSZ8041", 992 /* PHY_BASIC_FEATURES */ 993 .driver_data = &ksz8041_type, 994 .probe = kszphy_probe, 995 .config_init = ksz8041_config_init, 996 .config_aneg = ksz8041_config_aneg, 997 .ack_interrupt = kszphy_ack_interrupt, 998 .config_intr = kszphy_config_intr, 999 .get_sset_count = kszphy_get_sset_count, 1000 .get_strings = kszphy_get_strings, 1001 .get_stats = kszphy_get_stats, 1002 .suspend = genphy_suspend, 1003 .resume = genphy_resume, 1004 }, { 1005 .phy_id = PHY_ID_KSZ8041RNLI, 1006 .phy_id_mask = MICREL_PHY_ID_MASK, 1007 .name = "Micrel KSZ8041RNLI", 1008 /* PHY_BASIC_FEATURES */ 1009 .driver_data = &ksz8041_type, 1010 .probe = kszphy_probe, 1011 .config_init = kszphy_config_init, 1012 .ack_interrupt = kszphy_ack_interrupt, 1013 .config_intr = kszphy_config_intr, 1014 .get_sset_count = kszphy_get_sset_count, 1015 .get_strings = kszphy_get_strings, 1016 .get_stats = kszphy_get_stats, 1017 .suspend = genphy_suspend, 1018 .resume = genphy_resume, 1019 }, { 1020 .phy_id = PHY_ID_KSZ8051, 1021 .phy_id_mask = MICREL_PHY_ID_MASK, 1022 .name = "Micrel KSZ8051", 1023 /* PHY_BASIC_FEATURES */ 1024 .driver_data = &ksz8051_type, 1025 .probe = kszphy_probe, 1026 .config_init = kszphy_config_init, 1027 .ack_interrupt = kszphy_ack_interrupt, 1028 .config_intr = kszphy_config_intr, 1029 .get_sset_count = kszphy_get_sset_count, 1030 .get_strings = kszphy_get_strings, 1031 .get_stats = kszphy_get_stats, 1032 .suspend = genphy_suspend, 1033 .resume = genphy_resume, 1034 }, { 1035 .phy_id = PHY_ID_KSZ8001, 1036 .name = "Micrel KSZ8001 or KS8721", 1037 .phy_id_mask = 0x00fffffc, 1038 /* PHY_BASIC_FEATURES */ 1039 .driver_data = &ksz8041_type, 1040 .probe = kszphy_probe, 1041 .config_init = kszphy_config_init, 1042 .ack_interrupt = kszphy_ack_interrupt, 1043 .config_intr = kszphy_config_intr, 1044 .get_sset_count = kszphy_get_sset_count, 1045 .get_strings = kszphy_get_strings, 1046 .get_stats = kszphy_get_stats, 1047 .suspend = genphy_suspend, 1048 .resume = genphy_resume, 1049 }, { 1050 .phy_id = PHY_ID_KSZ8081, 1051 .name = "Micrel KSZ8081 or KSZ8091", 1052 .phy_id_mask = MICREL_PHY_ID_MASK, 1053 /* PHY_BASIC_FEATURES */ 1054 .driver_data = &ksz8081_type, 1055 .probe = kszphy_probe, 1056 .config_init = ksz8081_config_init, 1057 .ack_interrupt = kszphy_ack_interrupt, 1058 .config_intr = kszphy_config_intr, 1059 .get_sset_count = kszphy_get_sset_count, 1060 .get_strings = kszphy_get_strings, 1061 .get_stats = kszphy_get_stats, 1062 .suspend = kszphy_suspend, 1063 .resume = kszphy_resume, 1064 }, { 1065 .phy_id = PHY_ID_KSZ8061, 1066 .name = "Micrel KSZ8061", 1067 .phy_id_mask = MICREL_PHY_ID_MASK, 1068 /* PHY_BASIC_FEATURES */ 1069 .config_init = ksz8061_config_init, 1070 .ack_interrupt = kszphy_ack_interrupt, 1071 .config_intr = kszphy_config_intr, 1072 .suspend = genphy_suspend, 1073 .resume = genphy_resume, 1074 }, { 1075 .phy_id = PHY_ID_KSZ9021, 1076 .phy_id_mask = 0x000ffffe, 1077 .name = "Micrel KSZ9021 Gigabit PHY", 1078 /* PHY_GBIT_FEATURES */ 1079 .driver_data = &ksz9021_type, 1080 .probe = kszphy_probe, 1081 .get_features = ksz9031_get_features, 1082 .config_init = ksz9021_config_init, 1083 .ack_interrupt = kszphy_ack_interrupt, 1084 .config_intr = kszphy_config_intr, 1085 .get_sset_count = kszphy_get_sset_count, 1086 .get_strings = kszphy_get_strings, 1087 .get_stats = kszphy_get_stats, 1088 .suspend = genphy_suspend, 1089 .resume = genphy_resume, 1090 .read_mmd = genphy_read_mmd_unsupported, 1091 .write_mmd = genphy_write_mmd_unsupported, 1092 }, { 1093 .phy_id = PHY_ID_KSZ9031, 1094 .phy_id_mask = MICREL_PHY_ID_MASK, 1095 .name = "Micrel KSZ9031 Gigabit PHY", 1096 .driver_data = &ksz9021_type, 1097 .probe = kszphy_probe, 1098 .get_features = ksz9031_get_features, 1099 .config_init = ksz9031_config_init, 1100 .soft_reset = genphy_soft_reset, 1101 .read_status = ksz9031_read_status, 1102 .ack_interrupt = kszphy_ack_interrupt, 1103 .config_intr = kszphy_config_intr, 1104 .get_sset_count = kszphy_get_sset_count, 1105 .get_strings = kszphy_get_strings, 1106 .get_stats = kszphy_get_stats, 1107 .suspend = genphy_suspend, 1108 .resume = kszphy_resume, 1109 }, { 1110 .phy_id = PHY_ID_KSZ9131, 1111 .phy_id_mask = MICREL_PHY_ID_MASK, 1112 .name = "Microchip KSZ9131 Gigabit PHY", 1113 /* PHY_GBIT_FEATURES */ 1114 .driver_data = &ksz9021_type, 1115 .probe = kszphy_probe, 1116 .config_init = ksz9131_config_init, 1117 .read_status = ksz9031_read_status, 1118 .ack_interrupt = kszphy_ack_interrupt, 1119 .config_intr = kszphy_config_intr, 1120 .get_sset_count = kszphy_get_sset_count, 1121 .get_strings = kszphy_get_strings, 1122 .get_stats = kszphy_get_stats, 1123 .suspend = genphy_suspend, 1124 .resume = kszphy_resume, 1125 }, { 1126 .phy_id = PHY_ID_KSZ8873MLL, 1127 .phy_id_mask = MICREL_PHY_ID_MASK, 1128 .name = "Micrel KSZ8873MLL Switch", 1129 /* PHY_BASIC_FEATURES */ 1130 .config_init = kszphy_config_init, 1131 .config_aneg = ksz8873mll_config_aneg, 1132 .read_status = ksz8873mll_read_status, 1133 .suspend = genphy_suspend, 1134 .resume = genphy_resume, 1135 }, { 1136 .phy_id = PHY_ID_KSZ886X, 1137 .phy_id_mask = MICREL_PHY_ID_MASK, 1138 .name = "Micrel KSZ886X Switch", 1139 /* PHY_BASIC_FEATURES */ 1140 .config_init = kszphy_config_init, 1141 .suspend = genphy_suspend, 1142 .resume = genphy_resume, 1143 }, { 1144 .phy_id = PHY_ID_KSZ8795, 1145 .phy_id_mask = MICREL_PHY_ID_MASK, 1146 .name = "Micrel KSZ8795", 1147 /* PHY_BASIC_FEATURES */ 1148 .config_init = kszphy_config_init, 1149 .config_aneg = ksz8873mll_config_aneg, 1150 .read_status = ksz8873mll_read_status, 1151 .suspend = genphy_suspend, 1152 .resume = genphy_resume, 1153 }, { 1154 .phy_id = PHY_ID_KSZ9477, 1155 .phy_id_mask = MICREL_PHY_ID_MASK, 1156 .name = "Microchip KSZ9477", 1157 /* PHY_GBIT_FEATURES */ 1158 .config_init = kszphy_config_init, 1159 .suspend = genphy_suspend, 1160 .resume = genphy_resume, 1161 } }; 1162 1163 module_phy_driver(ksphy_driver); 1164 1165 MODULE_DESCRIPTION("Micrel PHY driver"); 1166 MODULE_AUTHOR("David J. Choi"); 1167 MODULE_LICENSE("GPL"); 1168 1169 static struct mdio_device_id __maybe_unused micrel_tbl[] = { 1170 { PHY_ID_KSZ9021, 0x000ffffe }, 1171 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK }, 1172 { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK }, 1173 { PHY_ID_KSZ8001, 0x00fffffc }, 1174 { PHY_ID_KS8737, MICREL_PHY_ID_MASK }, 1175 { PHY_ID_KSZ8021, 0x00ffffff }, 1176 { PHY_ID_KSZ8031, 0x00ffffff }, 1177 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK }, 1178 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK }, 1179 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK }, 1180 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK }, 1181 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK }, 1182 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK }, 1183 { } 1184 }; 1185 1186 MODULE_DEVICE_TABLE(mdio, micrel_tbl); 1187