1 /* 2 * drivers/net/phy/micrel.c 3 * 4 * Driver for Micrel PHYs 5 * 6 * Author: David J. Choi 7 * 8 * Copyright (c) 2010-2013 Micrel, Inc. 9 * Copyright (c) 2014 Johan Hovold <johan@kernel.org> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * Support : Micrel Phys: 17 * Giga phys: ksz9021, ksz9031 18 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041 19 * ksz8021, ksz8031, ksz8051, 20 * ksz8081, ksz8091, 21 * ksz8061, 22 * Switch : ksz8873, ksz886x 23 * ksz9477 24 */ 25 26 #include <linux/kernel.h> 27 #include <linux/module.h> 28 #include <linux/phy.h> 29 #include <linux/micrel_phy.h> 30 #include <linux/of.h> 31 #include <linux/clk.h> 32 33 /* Operation Mode Strap Override */ 34 #define MII_KSZPHY_OMSO 0x16 35 #define KSZPHY_OMSO_B_CAST_OFF BIT(9) 36 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5) 37 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1) 38 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0) 39 40 /* general Interrupt control/status reg in vendor specific block. */ 41 #define MII_KSZPHY_INTCS 0x1B 42 #define KSZPHY_INTCS_JABBER BIT(15) 43 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14) 44 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13) 45 #define KSZPHY_INTCS_PARELLEL BIT(12) 46 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11) 47 #define KSZPHY_INTCS_LINK_DOWN BIT(10) 48 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9) 49 #define KSZPHY_INTCS_LINK_UP BIT(8) 50 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\ 51 KSZPHY_INTCS_LINK_DOWN) 52 53 /* PHY Control 1 */ 54 #define MII_KSZPHY_CTRL_1 0x1e 55 56 /* PHY Control 2 / PHY Control (if no PHY Control 1) */ 57 #define MII_KSZPHY_CTRL_2 0x1f 58 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2 59 /* bitmap of PHY register to set interrupt mode */ 60 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9) 61 #define KSZPHY_RMII_REF_CLK_SEL BIT(7) 62 63 /* Write/read to/from extended registers */ 64 #define MII_KSZPHY_EXTREG 0x0b 65 #define KSZPHY_EXTREG_WRITE 0x8000 66 67 #define MII_KSZPHY_EXTREG_WRITE 0x0c 68 #define MII_KSZPHY_EXTREG_READ 0x0d 69 70 /* Extended registers */ 71 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104 72 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105 73 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106 74 75 #define PS_TO_REG 200 76 77 struct kszphy_hw_stat { 78 const char *string; 79 u8 reg; 80 u8 bits; 81 }; 82 83 static struct kszphy_hw_stat kszphy_hw_stats[] = { 84 { "phy_receive_errors", 21, 16}, 85 { "phy_idle_errors", 10, 8 }, 86 }; 87 88 struct kszphy_type { 89 u32 led_mode_reg; 90 u16 interrupt_level_mask; 91 bool has_broadcast_disable; 92 bool has_nand_tree_disable; 93 bool has_rmii_ref_clk_sel; 94 }; 95 96 struct kszphy_priv { 97 const struct kszphy_type *type; 98 int led_mode; 99 bool rmii_ref_clk_sel; 100 bool rmii_ref_clk_sel_val; 101 u64 stats[ARRAY_SIZE(kszphy_hw_stats)]; 102 }; 103 104 static const struct kszphy_type ksz8021_type = { 105 .led_mode_reg = MII_KSZPHY_CTRL_2, 106 .has_broadcast_disable = true, 107 .has_nand_tree_disable = true, 108 .has_rmii_ref_clk_sel = true, 109 }; 110 111 static const struct kszphy_type ksz8041_type = { 112 .led_mode_reg = MII_KSZPHY_CTRL_1, 113 }; 114 115 static const struct kszphy_type ksz8051_type = { 116 .led_mode_reg = MII_KSZPHY_CTRL_2, 117 .has_nand_tree_disable = true, 118 }; 119 120 static const struct kszphy_type ksz8081_type = { 121 .led_mode_reg = MII_KSZPHY_CTRL_2, 122 .has_broadcast_disable = true, 123 .has_nand_tree_disable = true, 124 .has_rmii_ref_clk_sel = true, 125 }; 126 127 static const struct kszphy_type ks8737_type = { 128 .interrupt_level_mask = BIT(14), 129 }; 130 131 static const struct kszphy_type ksz9021_type = { 132 .interrupt_level_mask = BIT(14), 133 }; 134 135 static int kszphy_extended_write(struct phy_device *phydev, 136 u32 regnum, u16 val) 137 { 138 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum); 139 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); 140 } 141 142 static int kszphy_extended_read(struct phy_device *phydev, 143 u32 regnum) 144 { 145 phy_write(phydev, MII_KSZPHY_EXTREG, regnum); 146 return phy_read(phydev, MII_KSZPHY_EXTREG_READ); 147 } 148 149 static int kszphy_ack_interrupt(struct phy_device *phydev) 150 { 151 /* bit[7..0] int status, which is a read and clear register. */ 152 int rc; 153 154 rc = phy_read(phydev, MII_KSZPHY_INTCS); 155 156 return (rc < 0) ? rc : 0; 157 } 158 159 static int kszphy_config_intr(struct phy_device *phydev) 160 { 161 const struct kszphy_type *type = phydev->drv->driver_data; 162 int temp; 163 u16 mask; 164 165 if (type && type->interrupt_level_mask) 166 mask = type->interrupt_level_mask; 167 else 168 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH; 169 170 /* set the interrupt pin active low */ 171 temp = phy_read(phydev, MII_KSZPHY_CTRL); 172 if (temp < 0) 173 return temp; 174 temp &= ~mask; 175 phy_write(phydev, MII_KSZPHY_CTRL, temp); 176 177 /* enable / disable interrupts */ 178 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 179 temp = KSZPHY_INTCS_ALL; 180 else 181 temp = 0; 182 183 return phy_write(phydev, MII_KSZPHY_INTCS, temp); 184 } 185 186 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val) 187 { 188 int ctrl; 189 190 ctrl = phy_read(phydev, MII_KSZPHY_CTRL); 191 if (ctrl < 0) 192 return ctrl; 193 194 if (val) 195 ctrl |= KSZPHY_RMII_REF_CLK_SEL; 196 else 197 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL; 198 199 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl); 200 } 201 202 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val) 203 { 204 int rc, temp, shift; 205 206 switch (reg) { 207 case MII_KSZPHY_CTRL_1: 208 shift = 14; 209 break; 210 case MII_KSZPHY_CTRL_2: 211 shift = 4; 212 break; 213 default: 214 return -EINVAL; 215 } 216 217 temp = phy_read(phydev, reg); 218 if (temp < 0) { 219 rc = temp; 220 goto out; 221 } 222 223 temp &= ~(3 << shift); 224 temp |= val << shift; 225 rc = phy_write(phydev, reg, temp); 226 out: 227 if (rc < 0) 228 phydev_err(phydev, "failed to set led mode\n"); 229 230 return rc; 231 } 232 233 /* Disable PHY address 0 as the broadcast address, so that it can be used as a 234 * unique (non-broadcast) address on a shared bus. 235 */ 236 static int kszphy_broadcast_disable(struct phy_device *phydev) 237 { 238 int ret; 239 240 ret = phy_read(phydev, MII_KSZPHY_OMSO); 241 if (ret < 0) 242 goto out; 243 244 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF); 245 out: 246 if (ret) 247 phydev_err(phydev, "failed to disable broadcast address\n"); 248 249 return ret; 250 } 251 252 static int kszphy_nand_tree_disable(struct phy_device *phydev) 253 { 254 int ret; 255 256 ret = phy_read(phydev, MII_KSZPHY_OMSO); 257 if (ret < 0) 258 goto out; 259 260 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON)) 261 return 0; 262 263 ret = phy_write(phydev, MII_KSZPHY_OMSO, 264 ret & ~KSZPHY_OMSO_NAND_TREE_ON); 265 out: 266 if (ret) 267 phydev_err(phydev, "failed to disable NAND tree mode\n"); 268 269 return ret; 270 } 271 272 /* Some config bits need to be set again on resume, handle them here. */ 273 static int kszphy_config_reset(struct phy_device *phydev) 274 { 275 struct kszphy_priv *priv = phydev->priv; 276 int ret; 277 278 if (priv->rmii_ref_clk_sel) { 279 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val); 280 if (ret) { 281 phydev_err(phydev, 282 "failed to set rmii reference clock\n"); 283 return ret; 284 } 285 } 286 287 if (priv->led_mode >= 0) 288 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode); 289 290 return 0; 291 } 292 293 static int kszphy_config_init(struct phy_device *phydev) 294 { 295 struct kszphy_priv *priv = phydev->priv; 296 const struct kszphy_type *type; 297 298 if (!priv) 299 return 0; 300 301 type = priv->type; 302 303 if (type->has_broadcast_disable) 304 kszphy_broadcast_disable(phydev); 305 306 if (type->has_nand_tree_disable) 307 kszphy_nand_tree_disable(phydev); 308 309 return kszphy_config_reset(phydev); 310 } 311 312 static int ksz8041_config_init(struct phy_device *phydev) 313 { 314 struct device_node *of_node = phydev->mdio.dev.of_node; 315 316 /* Limit supported and advertised modes in fiber mode */ 317 if (of_property_read_bool(of_node, "micrel,fiber-mode")) { 318 phydev->dev_flags |= MICREL_PHY_FXEN; 319 phydev->supported &= SUPPORTED_100baseT_Full | 320 SUPPORTED_100baseT_Half; 321 phydev->supported |= SUPPORTED_FIBRE; 322 phydev->advertising &= ADVERTISED_100baseT_Full | 323 ADVERTISED_100baseT_Half; 324 phydev->advertising |= ADVERTISED_FIBRE; 325 phydev->autoneg = AUTONEG_DISABLE; 326 } 327 328 return kszphy_config_init(phydev); 329 } 330 331 static int ksz8041_config_aneg(struct phy_device *phydev) 332 { 333 /* Skip auto-negotiation in fiber mode */ 334 if (phydev->dev_flags & MICREL_PHY_FXEN) { 335 phydev->speed = SPEED_100; 336 return 0; 337 } 338 339 return genphy_config_aneg(phydev); 340 } 341 342 static int ksz9021_load_values_from_of(struct phy_device *phydev, 343 const struct device_node *of_node, 344 u16 reg, 345 const char *field1, const char *field2, 346 const char *field3, const char *field4) 347 { 348 int val1 = -1; 349 int val2 = -2; 350 int val3 = -3; 351 int val4 = -4; 352 int newval; 353 int matches = 0; 354 355 if (!of_property_read_u32(of_node, field1, &val1)) 356 matches++; 357 358 if (!of_property_read_u32(of_node, field2, &val2)) 359 matches++; 360 361 if (!of_property_read_u32(of_node, field3, &val3)) 362 matches++; 363 364 if (!of_property_read_u32(of_node, field4, &val4)) 365 matches++; 366 367 if (!matches) 368 return 0; 369 370 if (matches < 4) 371 newval = kszphy_extended_read(phydev, reg); 372 else 373 newval = 0; 374 375 if (val1 != -1) 376 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0); 377 378 if (val2 != -2) 379 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4); 380 381 if (val3 != -3) 382 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8); 383 384 if (val4 != -4) 385 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12); 386 387 return kszphy_extended_write(phydev, reg, newval); 388 } 389 390 static int ksz9021_config_init(struct phy_device *phydev) 391 { 392 const struct device *dev = &phydev->mdio.dev; 393 const struct device_node *of_node = dev->of_node; 394 const struct device *dev_walker; 395 396 /* The Micrel driver has a deprecated option to place phy OF 397 * properties in the MAC node. Walk up the tree of devices to 398 * find a device with an OF node. 399 */ 400 dev_walker = &phydev->mdio.dev; 401 do { 402 of_node = dev_walker->of_node; 403 dev_walker = dev_walker->parent; 404 405 } while (!of_node && dev_walker); 406 407 if (of_node) { 408 ksz9021_load_values_from_of(phydev, of_node, 409 MII_KSZPHY_CLK_CONTROL_PAD_SKEW, 410 "txen-skew-ps", "txc-skew-ps", 411 "rxdv-skew-ps", "rxc-skew-ps"); 412 ksz9021_load_values_from_of(phydev, of_node, 413 MII_KSZPHY_RX_DATA_PAD_SKEW, 414 "rxd0-skew-ps", "rxd1-skew-ps", 415 "rxd2-skew-ps", "rxd3-skew-ps"); 416 ksz9021_load_values_from_of(phydev, of_node, 417 MII_KSZPHY_TX_DATA_PAD_SKEW, 418 "txd0-skew-ps", "txd1-skew-ps", 419 "txd2-skew-ps", "txd3-skew-ps"); 420 } 421 return 0; 422 } 423 424 #define MII_KSZ9031RN_MMD_CTRL_REG 0x0d 425 #define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e 426 #define OP_DATA 1 427 #define KSZ9031_PS_TO_REG 60 428 429 /* Extended registers */ 430 /* MMD Address 0x0 */ 431 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3 432 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4 433 434 /* MMD Address 0x2 */ 435 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4 436 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5 437 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6 438 #define MII_KSZ9031RN_CLK_PAD_SKEW 8 439 440 /* MMD Address 0x1C */ 441 #define MII_KSZ9031RN_EDPD 0x23 442 #define MII_KSZ9031RN_EDPD_ENABLE BIT(0) 443 444 static int ksz9031_extended_write(struct phy_device *phydev, 445 u8 mode, u32 dev_addr, u32 regnum, u16 val) 446 { 447 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr); 448 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum); 449 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr); 450 return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val); 451 } 452 453 static int ksz9031_extended_read(struct phy_device *phydev, 454 u8 mode, u32 dev_addr, u32 regnum) 455 { 456 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr); 457 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum); 458 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr); 459 return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG); 460 } 461 462 static int ksz9031_of_load_skew_values(struct phy_device *phydev, 463 const struct device_node *of_node, 464 u16 reg, size_t field_sz, 465 const char *field[], u8 numfields) 466 { 467 int val[4] = {-1, -2, -3, -4}; 468 int matches = 0; 469 u16 mask; 470 u16 maxval; 471 u16 newval; 472 int i; 473 474 for (i = 0; i < numfields; i++) 475 if (!of_property_read_u32(of_node, field[i], val + i)) 476 matches++; 477 478 if (!matches) 479 return 0; 480 481 if (matches < numfields) 482 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg); 483 else 484 newval = 0; 485 486 maxval = (field_sz == 4) ? 0xf : 0x1f; 487 for (i = 0; i < numfields; i++) 488 if (val[i] != -(i + 1)) { 489 mask = 0xffff; 490 mask ^= maxval << (field_sz * i); 491 newval = (newval & mask) | 492 (((val[i] / KSZ9031_PS_TO_REG) & maxval) 493 << (field_sz * i)); 494 } 495 496 return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval); 497 } 498 499 /* Center KSZ9031RNX FLP timing at 16ms. */ 500 static int ksz9031_center_flp_timing(struct phy_device *phydev) 501 { 502 int result; 503 504 result = ksz9031_extended_write(phydev, OP_DATA, 0, 505 MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006); 506 if (result) 507 return result; 508 509 result = ksz9031_extended_write(phydev, OP_DATA, 0, 510 MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80); 511 if (result) 512 return result; 513 514 return genphy_restart_aneg(phydev); 515 } 516 517 /* Enable energy-detect power-down mode */ 518 static int ksz9031_enable_edpd(struct phy_device *phydev) 519 { 520 int reg; 521 522 reg = ksz9031_extended_read(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD); 523 if (reg < 0) 524 return reg; 525 return ksz9031_extended_write(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD, 526 reg | MII_KSZ9031RN_EDPD_ENABLE); 527 } 528 529 static int ksz9031_config_init(struct phy_device *phydev) 530 { 531 const struct device *dev = &phydev->mdio.dev; 532 const struct device_node *of_node = dev->of_node; 533 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"}; 534 static const char *rx_data_skews[4] = { 535 "rxd0-skew-ps", "rxd1-skew-ps", 536 "rxd2-skew-ps", "rxd3-skew-ps" 537 }; 538 static const char *tx_data_skews[4] = { 539 "txd0-skew-ps", "txd1-skew-ps", 540 "txd2-skew-ps", "txd3-skew-ps" 541 }; 542 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"}; 543 const struct device *dev_walker; 544 int result; 545 546 result = ksz9031_enable_edpd(phydev); 547 if (result < 0) 548 return result; 549 550 /* The Micrel driver has a deprecated option to place phy OF 551 * properties in the MAC node. Walk up the tree of devices to 552 * find a device with an OF node. 553 */ 554 dev_walker = &phydev->mdio.dev; 555 do { 556 of_node = dev_walker->of_node; 557 dev_walker = dev_walker->parent; 558 } while (!of_node && dev_walker); 559 560 if (of_node) { 561 ksz9031_of_load_skew_values(phydev, of_node, 562 MII_KSZ9031RN_CLK_PAD_SKEW, 5, 563 clk_skews, 2); 564 565 ksz9031_of_load_skew_values(phydev, of_node, 566 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, 567 control_skews, 2); 568 569 ksz9031_of_load_skew_values(phydev, of_node, 570 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, 571 rx_data_skews, 4); 572 573 ksz9031_of_load_skew_values(phydev, of_node, 574 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, 575 tx_data_skews, 4); 576 } 577 578 return ksz9031_center_flp_timing(phydev); 579 } 580 581 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06 582 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6) 583 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4) 584 static int ksz8873mll_read_status(struct phy_device *phydev) 585 { 586 int regval; 587 588 /* dummy read */ 589 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 590 591 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 592 593 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX) 594 phydev->duplex = DUPLEX_HALF; 595 else 596 phydev->duplex = DUPLEX_FULL; 597 598 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED) 599 phydev->speed = SPEED_10; 600 else 601 phydev->speed = SPEED_100; 602 603 phydev->link = 1; 604 phydev->pause = phydev->asym_pause = 0; 605 606 return 0; 607 } 608 609 static int ksz9031_read_status(struct phy_device *phydev) 610 { 611 int err; 612 int regval; 613 614 err = genphy_read_status(phydev); 615 if (err) 616 return err; 617 618 /* Make sure the PHY is not broken. Read idle error count, 619 * and reset the PHY if it is maxed out. 620 */ 621 regval = phy_read(phydev, MII_STAT1000); 622 if ((regval & 0xFF) == 0xFF) { 623 phy_init_hw(phydev); 624 phydev->link = 0; 625 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev)) 626 phydev->drv->config_intr(phydev); 627 return genphy_config_aneg(phydev); 628 } 629 630 return 0; 631 } 632 633 static int ksz8873mll_config_aneg(struct phy_device *phydev) 634 { 635 return 0; 636 } 637 638 static int kszphy_get_sset_count(struct phy_device *phydev) 639 { 640 return ARRAY_SIZE(kszphy_hw_stats); 641 } 642 643 static void kszphy_get_strings(struct phy_device *phydev, u8 *data) 644 { 645 int i; 646 647 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) { 648 strlcpy(data + i * ETH_GSTRING_LEN, 649 kszphy_hw_stats[i].string, ETH_GSTRING_LEN); 650 } 651 } 652 653 #ifndef UINT64_MAX 654 #define UINT64_MAX (u64)(~((u64)0)) 655 #endif 656 static u64 kszphy_get_stat(struct phy_device *phydev, int i) 657 { 658 struct kszphy_hw_stat stat = kszphy_hw_stats[i]; 659 struct kszphy_priv *priv = phydev->priv; 660 int val; 661 u64 ret; 662 663 val = phy_read(phydev, stat.reg); 664 if (val < 0) { 665 ret = UINT64_MAX; 666 } else { 667 val = val & ((1 << stat.bits) - 1); 668 priv->stats[i] += val; 669 ret = priv->stats[i]; 670 } 671 672 return ret; 673 } 674 675 static void kszphy_get_stats(struct phy_device *phydev, 676 struct ethtool_stats *stats, u64 *data) 677 { 678 int i; 679 680 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) 681 data[i] = kszphy_get_stat(phydev, i); 682 } 683 684 static int kszphy_suspend(struct phy_device *phydev) 685 { 686 /* Disable PHY Interrupts */ 687 if (phy_interrupt_is_valid(phydev)) { 688 phydev->interrupts = PHY_INTERRUPT_DISABLED; 689 if (phydev->drv->config_intr) 690 phydev->drv->config_intr(phydev); 691 } 692 693 return genphy_suspend(phydev); 694 } 695 696 static int kszphy_resume(struct phy_device *phydev) 697 { 698 int ret; 699 700 genphy_resume(phydev); 701 702 ret = kszphy_config_reset(phydev); 703 if (ret) 704 return ret; 705 706 /* Enable PHY Interrupts */ 707 if (phy_interrupt_is_valid(phydev)) { 708 phydev->interrupts = PHY_INTERRUPT_ENABLED; 709 if (phydev->drv->config_intr) 710 phydev->drv->config_intr(phydev); 711 } 712 713 return 0; 714 } 715 716 static int kszphy_probe(struct phy_device *phydev) 717 { 718 const struct kszphy_type *type = phydev->drv->driver_data; 719 const struct device_node *np = phydev->mdio.dev.of_node; 720 struct kszphy_priv *priv; 721 struct clk *clk; 722 int ret; 723 724 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 725 if (!priv) 726 return -ENOMEM; 727 728 phydev->priv = priv; 729 730 priv->type = type; 731 732 if (type->led_mode_reg) { 733 ret = of_property_read_u32(np, "micrel,led-mode", 734 &priv->led_mode); 735 if (ret) 736 priv->led_mode = -1; 737 738 if (priv->led_mode > 3) { 739 phydev_err(phydev, "invalid led mode: 0x%02x\n", 740 priv->led_mode); 741 priv->led_mode = -1; 742 } 743 } else { 744 priv->led_mode = -1; 745 } 746 747 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref"); 748 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */ 749 if (!IS_ERR_OR_NULL(clk)) { 750 unsigned long rate = clk_get_rate(clk); 751 bool rmii_ref_clk_sel_25_mhz; 752 753 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel; 754 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np, 755 "micrel,rmii-reference-clock-select-25-mhz"); 756 757 if (rate > 24500000 && rate < 25500000) { 758 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz; 759 } else if (rate > 49500000 && rate < 50500000) { 760 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz; 761 } else { 762 phydev_err(phydev, "Clock rate out of range: %ld\n", 763 rate); 764 return -EINVAL; 765 } 766 } 767 768 /* Support legacy board-file configuration */ 769 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) { 770 priv->rmii_ref_clk_sel = true; 771 priv->rmii_ref_clk_sel_val = true; 772 } 773 774 return 0; 775 } 776 777 static struct phy_driver ksphy_driver[] = { 778 { 779 .phy_id = PHY_ID_KS8737, 780 .phy_id_mask = MICREL_PHY_ID_MASK, 781 .name = "Micrel KS8737", 782 .features = PHY_BASIC_FEATURES, 783 .flags = PHY_HAS_INTERRUPT, 784 .driver_data = &ks8737_type, 785 .config_init = kszphy_config_init, 786 .ack_interrupt = kszphy_ack_interrupt, 787 .config_intr = kszphy_config_intr, 788 .suspend = genphy_suspend, 789 .resume = genphy_resume, 790 }, { 791 .phy_id = PHY_ID_KSZ8021, 792 .phy_id_mask = 0x00ffffff, 793 .name = "Micrel KSZ8021 or KSZ8031", 794 .features = PHY_BASIC_FEATURES, 795 .flags = PHY_HAS_INTERRUPT, 796 .driver_data = &ksz8021_type, 797 .probe = kszphy_probe, 798 .config_init = kszphy_config_init, 799 .ack_interrupt = kszphy_ack_interrupt, 800 .config_intr = kszphy_config_intr, 801 .get_sset_count = kszphy_get_sset_count, 802 .get_strings = kszphy_get_strings, 803 .get_stats = kszphy_get_stats, 804 .suspend = genphy_suspend, 805 .resume = genphy_resume, 806 }, { 807 .phy_id = PHY_ID_KSZ8031, 808 .phy_id_mask = 0x00ffffff, 809 .name = "Micrel KSZ8031", 810 .features = PHY_BASIC_FEATURES, 811 .flags = PHY_HAS_INTERRUPT, 812 .driver_data = &ksz8021_type, 813 .probe = kszphy_probe, 814 .config_init = kszphy_config_init, 815 .ack_interrupt = kszphy_ack_interrupt, 816 .config_intr = kszphy_config_intr, 817 .get_sset_count = kszphy_get_sset_count, 818 .get_strings = kszphy_get_strings, 819 .get_stats = kszphy_get_stats, 820 .suspend = genphy_suspend, 821 .resume = genphy_resume, 822 }, { 823 .phy_id = PHY_ID_KSZ8041, 824 .phy_id_mask = MICREL_PHY_ID_MASK, 825 .name = "Micrel KSZ8041", 826 .features = PHY_BASIC_FEATURES, 827 .flags = PHY_HAS_INTERRUPT, 828 .driver_data = &ksz8041_type, 829 .probe = kszphy_probe, 830 .config_init = ksz8041_config_init, 831 .config_aneg = ksz8041_config_aneg, 832 .ack_interrupt = kszphy_ack_interrupt, 833 .config_intr = kszphy_config_intr, 834 .get_sset_count = kszphy_get_sset_count, 835 .get_strings = kszphy_get_strings, 836 .get_stats = kszphy_get_stats, 837 .suspend = genphy_suspend, 838 .resume = genphy_resume, 839 }, { 840 .phy_id = PHY_ID_KSZ8041RNLI, 841 .phy_id_mask = MICREL_PHY_ID_MASK, 842 .name = "Micrel KSZ8041RNLI", 843 .features = PHY_BASIC_FEATURES, 844 .flags = PHY_HAS_INTERRUPT, 845 .driver_data = &ksz8041_type, 846 .probe = kszphy_probe, 847 .config_init = kszphy_config_init, 848 .ack_interrupt = kszphy_ack_interrupt, 849 .config_intr = kszphy_config_intr, 850 .get_sset_count = kszphy_get_sset_count, 851 .get_strings = kszphy_get_strings, 852 .get_stats = kszphy_get_stats, 853 .suspend = genphy_suspend, 854 .resume = genphy_resume, 855 }, { 856 .phy_id = PHY_ID_KSZ8051, 857 .phy_id_mask = MICREL_PHY_ID_MASK, 858 .name = "Micrel KSZ8051", 859 .features = PHY_BASIC_FEATURES, 860 .flags = PHY_HAS_INTERRUPT, 861 .driver_data = &ksz8051_type, 862 .probe = kszphy_probe, 863 .config_init = kszphy_config_init, 864 .ack_interrupt = kszphy_ack_interrupt, 865 .config_intr = kszphy_config_intr, 866 .get_sset_count = kszphy_get_sset_count, 867 .get_strings = kszphy_get_strings, 868 .get_stats = kszphy_get_stats, 869 .suspend = genphy_suspend, 870 .resume = genphy_resume, 871 }, { 872 .phy_id = PHY_ID_KSZ8001, 873 .name = "Micrel KSZ8001 or KS8721", 874 .phy_id_mask = 0x00fffffc, 875 .features = PHY_BASIC_FEATURES, 876 .flags = PHY_HAS_INTERRUPT, 877 .driver_data = &ksz8041_type, 878 .probe = kszphy_probe, 879 .config_init = kszphy_config_init, 880 .ack_interrupt = kszphy_ack_interrupt, 881 .config_intr = kszphy_config_intr, 882 .get_sset_count = kszphy_get_sset_count, 883 .get_strings = kszphy_get_strings, 884 .get_stats = kszphy_get_stats, 885 .suspend = genphy_suspend, 886 .resume = genphy_resume, 887 }, { 888 .phy_id = PHY_ID_KSZ8081, 889 .name = "Micrel KSZ8081 or KSZ8091", 890 .phy_id_mask = MICREL_PHY_ID_MASK, 891 .features = PHY_BASIC_FEATURES, 892 .flags = PHY_HAS_INTERRUPT, 893 .driver_data = &ksz8081_type, 894 .probe = kszphy_probe, 895 .config_init = kszphy_config_init, 896 .ack_interrupt = kszphy_ack_interrupt, 897 .config_intr = kszphy_config_intr, 898 .get_sset_count = kszphy_get_sset_count, 899 .get_strings = kszphy_get_strings, 900 .get_stats = kszphy_get_stats, 901 .suspend = kszphy_suspend, 902 .resume = kszphy_resume, 903 }, { 904 .phy_id = PHY_ID_KSZ8061, 905 .name = "Micrel KSZ8061", 906 .phy_id_mask = MICREL_PHY_ID_MASK, 907 .features = PHY_BASIC_FEATURES, 908 .flags = PHY_HAS_INTERRUPT, 909 .config_init = kszphy_config_init, 910 .ack_interrupt = kszphy_ack_interrupt, 911 .config_intr = kszphy_config_intr, 912 .suspend = genphy_suspend, 913 .resume = genphy_resume, 914 }, { 915 .phy_id = PHY_ID_KSZ9021, 916 .phy_id_mask = 0x000ffffe, 917 .name = "Micrel KSZ9021 Gigabit PHY", 918 .features = PHY_GBIT_FEATURES, 919 .flags = PHY_HAS_INTERRUPT, 920 .driver_data = &ksz9021_type, 921 .probe = kszphy_probe, 922 .config_init = ksz9021_config_init, 923 .ack_interrupt = kszphy_ack_interrupt, 924 .config_intr = kszphy_config_intr, 925 .get_sset_count = kszphy_get_sset_count, 926 .get_strings = kszphy_get_strings, 927 .get_stats = kszphy_get_stats, 928 .suspend = genphy_suspend, 929 .resume = genphy_resume, 930 .read_mmd = genphy_read_mmd_unsupported, 931 .write_mmd = genphy_write_mmd_unsupported, 932 }, { 933 .phy_id = PHY_ID_KSZ9031, 934 .phy_id_mask = MICREL_PHY_ID_MASK, 935 .name = "Micrel KSZ9031 Gigabit PHY", 936 .features = PHY_GBIT_FEATURES, 937 .flags = PHY_HAS_INTERRUPT, 938 .driver_data = &ksz9021_type, 939 .probe = kszphy_probe, 940 .config_init = ksz9031_config_init, 941 .read_status = ksz9031_read_status, 942 .ack_interrupt = kszphy_ack_interrupt, 943 .config_intr = kszphy_config_intr, 944 .get_sset_count = kszphy_get_sset_count, 945 .get_strings = kszphy_get_strings, 946 .get_stats = kszphy_get_stats, 947 .suspend = genphy_suspend, 948 .resume = kszphy_resume, 949 }, { 950 .phy_id = PHY_ID_KSZ8873MLL, 951 .phy_id_mask = MICREL_PHY_ID_MASK, 952 .name = "Micrel KSZ8873MLL Switch", 953 .config_init = kszphy_config_init, 954 .config_aneg = ksz8873mll_config_aneg, 955 .read_status = ksz8873mll_read_status, 956 .suspend = genphy_suspend, 957 .resume = genphy_resume, 958 }, { 959 .phy_id = PHY_ID_KSZ886X, 960 .phy_id_mask = MICREL_PHY_ID_MASK, 961 .name = "Micrel KSZ886X Switch", 962 .features = PHY_BASIC_FEATURES, 963 .flags = PHY_HAS_INTERRUPT, 964 .config_init = kszphy_config_init, 965 .suspend = genphy_suspend, 966 .resume = genphy_resume, 967 }, { 968 .phy_id = PHY_ID_KSZ8795, 969 .phy_id_mask = MICREL_PHY_ID_MASK, 970 .name = "Micrel KSZ8795", 971 .features = PHY_BASIC_FEATURES, 972 .flags = PHY_HAS_INTERRUPT, 973 .config_init = kszphy_config_init, 974 .config_aneg = ksz8873mll_config_aneg, 975 .read_status = ksz8873mll_read_status, 976 .suspend = genphy_suspend, 977 .resume = genphy_resume, 978 }, { 979 .phy_id = PHY_ID_KSZ9477, 980 .phy_id_mask = MICREL_PHY_ID_MASK, 981 .name = "Microchip KSZ9477", 982 .features = PHY_GBIT_FEATURES, 983 .config_init = kszphy_config_init, 984 .suspend = genphy_suspend, 985 .resume = genphy_resume, 986 } }; 987 988 module_phy_driver(ksphy_driver); 989 990 MODULE_DESCRIPTION("Micrel PHY driver"); 991 MODULE_AUTHOR("David J. Choi"); 992 MODULE_LICENSE("GPL"); 993 994 static struct mdio_device_id __maybe_unused micrel_tbl[] = { 995 { PHY_ID_KSZ9021, 0x000ffffe }, 996 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK }, 997 { PHY_ID_KSZ8001, 0x00fffffc }, 998 { PHY_ID_KS8737, MICREL_PHY_ID_MASK }, 999 { PHY_ID_KSZ8021, 0x00ffffff }, 1000 { PHY_ID_KSZ8031, 0x00ffffff }, 1001 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK }, 1002 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK }, 1003 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK }, 1004 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK }, 1005 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK }, 1006 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK }, 1007 { } 1008 }; 1009 1010 MODULE_DEVICE_TABLE(mdio, micrel_tbl); 1011