1 /* 2 * drivers/net/phy/micrel.c 3 * 4 * Driver for Micrel PHYs 5 * 6 * Author: David J. Choi 7 * 8 * Copyright (c) 2010-2013 Micrel, Inc. 9 * Copyright (c) 2014 Johan Hovold <johan@kernel.org> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * Support : Micrel Phys: 17 * Giga phys: ksz9021, ksz9031 18 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041 19 * ksz8021, ksz8031, ksz8051, 20 * ksz8081, ksz8091, 21 * ksz8061, 22 * Switch : ksz8873, ksz886x 23 */ 24 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/phy.h> 28 #include <linux/micrel_phy.h> 29 #include <linux/of.h> 30 #include <linux/clk.h> 31 32 /* Operation Mode Strap Override */ 33 #define MII_KSZPHY_OMSO 0x16 34 #define KSZPHY_OMSO_B_CAST_OFF BIT(9) 35 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5) 36 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1) 37 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0) 38 39 /* general Interrupt control/status reg in vendor specific block. */ 40 #define MII_KSZPHY_INTCS 0x1B 41 #define KSZPHY_INTCS_JABBER BIT(15) 42 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14) 43 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13) 44 #define KSZPHY_INTCS_PARELLEL BIT(12) 45 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11) 46 #define KSZPHY_INTCS_LINK_DOWN BIT(10) 47 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9) 48 #define KSZPHY_INTCS_LINK_UP BIT(8) 49 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\ 50 KSZPHY_INTCS_LINK_DOWN) 51 52 /* PHY Control 1 */ 53 #define MII_KSZPHY_CTRL_1 0x1e 54 55 /* PHY Control 2 / PHY Control (if no PHY Control 1) */ 56 #define MII_KSZPHY_CTRL_2 0x1f 57 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2 58 /* bitmap of PHY register to set interrupt mode */ 59 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9) 60 #define KSZPHY_RMII_REF_CLK_SEL BIT(7) 61 62 /* Write/read to/from extended registers */ 63 #define MII_KSZPHY_EXTREG 0x0b 64 #define KSZPHY_EXTREG_WRITE 0x8000 65 66 #define MII_KSZPHY_EXTREG_WRITE 0x0c 67 #define MII_KSZPHY_EXTREG_READ 0x0d 68 69 /* Extended registers */ 70 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104 71 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105 72 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106 73 74 #define PS_TO_REG 200 75 76 struct kszphy_hw_stat { 77 const char *string; 78 u8 reg; 79 u8 bits; 80 }; 81 82 static struct kszphy_hw_stat kszphy_hw_stats[] = { 83 { "phy_receive_errors", 21, 16}, 84 { "phy_idle_errors", 10, 8 }, 85 }; 86 87 struct kszphy_type { 88 u32 led_mode_reg; 89 u16 interrupt_level_mask; 90 bool has_broadcast_disable; 91 bool has_nand_tree_disable; 92 bool has_rmii_ref_clk_sel; 93 }; 94 95 struct kszphy_priv { 96 const struct kszphy_type *type; 97 int led_mode; 98 bool rmii_ref_clk_sel; 99 bool rmii_ref_clk_sel_val; 100 u64 stats[ARRAY_SIZE(kszphy_hw_stats)]; 101 }; 102 103 static const struct kszphy_type ksz8021_type = { 104 .led_mode_reg = MII_KSZPHY_CTRL_2, 105 .has_broadcast_disable = true, 106 .has_nand_tree_disable = true, 107 .has_rmii_ref_clk_sel = true, 108 }; 109 110 static const struct kszphy_type ksz8041_type = { 111 .led_mode_reg = MII_KSZPHY_CTRL_1, 112 }; 113 114 static const struct kszphy_type ksz8051_type = { 115 .led_mode_reg = MII_KSZPHY_CTRL_2, 116 .has_nand_tree_disable = true, 117 }; 118 119 static const struct kszphy_type ksz8081_type = { 120 .led_mode_reg = MII_KSZPHY_CTRL_2, 121 .has_broadcast_disable = true, 122 .has_nand_tree_disable = true, 123 .has_rmii_ref_clk_sel = true, 124 }; 125 126 static const struct kszphy_type ks8737_type = { 127 .interrupt_level_mask = BIT(14), 128 }; 129 130 static const struct kszphy_type ksz9021_type = { 131 .interrupt_level_mask = BIT(14), 132 }; 133 134 static int kszphy_extended_write(struct phy_device *phydev, 135 u32 regnum, u16 val) 136 { 137 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum); 138 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); 139 } 140 141 static int kszphy_extended_read(struct phy_device *phydev, 142 u32 regnum) 143 { 144 phy_write(phydev, MII_KSZPHY_EXTREG, regnum); 145 return phy_read(phydev, MII_KSZPHY_EXTREG_READ); 146 } 147 148 static int kszphy_ack_interrupt(struct phy_device *phydev) 149 { 150 /* bit[7..0] int status, which is a read and clear register. */ 151 int rc; 152 153 rc = phy_read(phydev, MII_KSZPHY_INTCS); 154 155 return (rc < 0) ? rc : 0; 156 } 157 158 static int kszphy_config_intr(struct phy_device *phydev) 159 { 160 const struct kszphy_type *type = phydev->drv->driver_data; 161 int temp; 162 u16 mask; 163 164 if (type && type->interrupt_level_mask) 165 mask = type->interrupt_level_mask; 166 else 167 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH; 168 169 /* set the interrupt pin active low */ 170 temp = phy_read(phydev, MII_KSZPHY_CTRL); 171 if (temp < 0) 172 return temp; 173 temp &= ~mask; 174 phy_write(phydev, MII_KSZPHY_CTRL, temp); 175 176 /* enable / disable interrupts */ 177 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 178 temp = KSZPHY_INTCS_ALL; 179 else 180 temp = 0; 181 182 return phy_write(phydev, MII_KSZPHY_INTCS, temp); 183 } 184 185 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val) 186 { 187 int ctrl; 188 189 ctrl = phy_read(phydev, MII_KSZPHY_CTRL); 190 if (ctrl < 0) 191 return ctrl; 192 193 if (val) 194 ctrl |= KSZPHY_RMII_REF_CLK_SEL; 195 else 196 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL; 197 198 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl); 199 } 200 201 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val) 202 { 203 int rc, temp, shift; 204 205 switch (reg) { 206 case MII_KSZPHY_CTRL_1: 207 shift = 14; 208 break; 209 case MII_KSZPHY_CTRL_2: 210 shift = 4; 211 break; 212 default: 213 return -EINVAL; 214 } 215 216 temp = phy_read(phydev, reg); 217 if (temp < 0) { 218 rc = temp; 219 goto out; 220 } 221 222 temp &= ~(3 << shift); 223 temp |= val << shift; 224 rc = phy_write(phydev, reg, temp); 225 out: 226 if (rc < 0) 227 phydev_err(phydev, "failed to set led mode\n"); 228 229 return rc; 230 } 231 232 /* Disable PHY address 0 as the broadcast address, so that it can be used as a 233 * unique (non-broadcast) address on a shared bus. 234 */ 235 static int kszphy_broadcast_disable(struct phy_device *phydev) 236 { 237 int ret; 238 239 ret = phy_read(phydev, MII_KSZPHY_OMSO); 240 if (ret < 0) 241 goto out; 242 243 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF); 244 out: 245 if (ret) 246 phydev_err(phydev, "failed to disable broadcast address\n"); 247 248 return ret; 249 } 250 251 static int kszphy_nand_tree_disable(struct phy_device *phydev) 252 { 253 int ret; 254 255 ret = phy_read(phydev, MII_KSZPHY_OMSO); 256 if (ret < 0) 257 goto out; 258 259 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON)) 260 return 0; 261 262 ret = phy_write(phydev, MII_KSZPHY_OMSO, 263 ret & ~KSZPHY_OMSO_NAND_TREE_ON); 264 out: 265 if (ret) 266 phydev_err(phydev, "failed to disable NAND tree mode\n"); 267 268 return ret; 269 } 270 271 static int kszphy_config_init(struct phy_device *phydev) 272 { 273 struct kszphy_priv *priv = phydev->priv; 274 const struct kszphy_type *type; 275 int ret; 276 277 if (!priv) 278 return 0; 279 280 type = priv->type; 281 282 if (type->has_broadcast_disable) 283 kszphy_broadcast_disable(phydev); 284 285 if (type->has_nand_tree_disable) 286 kszphy_nand_tree_disable(phydev); 287 288 if (priv->rmii_ref_clk_sel) { 289 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val); 290 if (ret) { 291 phydev_err(phydev, 292 "failed to set rmii reference clock\n"); 293 return ret; 294 } 295 } 296 297 if (priv->led_mode >= 0) 298 kszphy_setup_led(phydev, type->led_mode_reg, priv->led_mode); 299 300 return 0; 301 } 302 303 static int ksz8041_config_init(struct phy_device *phydev) 304 { 305 struct device_node *of_node = phydev->mdio.dev.of_node; 306 307 /* Limit supported and advertised modes in fiber mode */ 308 if (of_property_read_bool(of_node, "micrel,fiber-mode")) { 309 phydev->dev_flags |= MICREL_PHY_FXEN; 310 phydev->supported &= SUPPORTED_100baseT_Full | 311 SUPPORTED_100baseT_Half; 312 phydev->supported |= SUPPORTED_FIBRE; 313 phydev->advertising &= ADVERTISED_100baseT_Full | 314 ADVERTISED_100baseT_Half; 315 phydev->advertising |= ADVERTISED_FIBRE; 316 phydev->autoneg = AUTONEG_DISABLE; 317 } 318 319 return kszphy_config_init(phydev); 320 } 321 322 static int ksz8041_config_aneg(struct phy_device *phydev) 323 { 324 /* Skip auto-negotiation in fiber mode */ 325 if (phydev->dev_flags & MICREL_PHY_FXEN) { 326 phydev->speed = SPEED_100; 327 return 0; 328 } 329 330 return genphy_config_aneg(phydev); 331 } 332 333 static int ksz9021_load_values_from_of(struct phy_device *phydev, 334 const struct device_node *of_node, 335 u16 reg, 336 const char *field1, const char *field2, 337 const char *field3, const char *field4) 338 { 339 int val1 = -1; 340 int val2 = -2; 341 int val3 = -3; 342 int val4 = -4; 343 int newval; 344 int matches = 0; 345 346 if (!of_property_read_u32(of_node, field1, &val1)) 347 matches++; 348 349 if (!of_property_read_u32(of_node, field2, &val2)) 350 matches++; 351 352 if (!of_property_read_u32(of_node, field3, &val3)) 353 matches++; 354 355 if (!of_property_read_u32(of_node, field4, &val4)) 356 matches++; 357 358 if (!matches) 359 return 0; 360 361 if (matches < 4) 362 newval = kszphy_extended_read(phydev, reg); 363 else 364 newval = 0; 365 366 if (val1 != -1) 367 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0); 368 369 if (val2 != -2) 370 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4); 371 372 if (val3 != -3) 373 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8); 374 375 if (val4 != -4) 376 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12); 377 378 return kszphy_extended_write(phydev, reg, newval); 379 } 380 381 static int ksz9021_config_init(struct phy_device *phydev) 382 { 383 const struct device *dev = &phydev->mdio.dev; 384 const struct device_node *of_node = dev->of_node; 385 const struct device *dev_walker; 386 387 /* The Micrel driver has a deprecated option to place phy OF 388 * properties in the MAC node. Walk up the tree of devices to 389 * find a device with an OF node. 390 */ 391 dev_walker = &phydev->mdio.dev; 392 do { 393 of_node = dev_walker->of_node; 394 dev_walker = dev_walker->parent; 395 396 } while (!of_node && dev_walker); 397 398 if (of_node) { 399 ksz9021_load_values_from_of(phydev, of_node, 400 MII_KSZPHY_CLK_CONTROL_PAD_SKEW, 401 "txen-skew-ps", "txc-skew-ps", 402 "rxdv-skew-ps", "rxc-skew-ps"); 403 ksz9021_load_values_from_of(phydev, of_node, 404 MII_KSZPHY_RX_DATA_PAD_SKEW, 405 "rxd0-skew-ps", "rxd1-skew-ps", 406 "rxd2-skew-ps", "rxd3-skew-ps"); 407 ksz9021_load_values_from_of(phydev, of_node, 408 MII_KSZPHY_TX_DATA_PAD_SKEW, 409 "txd0-skew-ps", "txd1-skew-ps", 410 "txd2-skew-ps", "txd3-skew-ps"); 411 } 412 return 0; 413 } 414 415 #define MII_KSZ9031RN_MMD_CTRL_REG 0x0d 416 #define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e 417 #define OP_DATA 1 418 #define KSZ9031_PS_TO_REG 60 419 420 /* Extended registers */ 421 /* MMD Address 0x0 */ 422 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3 423 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4 424 425 /* MMD Address 0x2 */ 426 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4 427 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5 428 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6 429 #define MII_KSZ9031RN_CLK_PAD_SKEW 8 430 431 /* MMD Address 0x1C */ 432 #define MII_KSZ9031RN_EDPD 0x23 433 #define MII_KSZ9031RN_EDPD_ENABLE BIT(0) 434 435 static int ksz9031_extended_write(struct phy_device *phydev, 436 u8 mode, u32 dev_addr, u32 regnum, u16 val) 437 { 438 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr); 439 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum); 440 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr); 441 return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val); 442 } 443 444 static int ksz9031_extended_read(struct phy_device *phydev, 445 u8 mode, u32 dev_addr, u32 regnum) 446 { 447 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr); 448 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum); 449 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr); 450 return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG); 451 } 452 453 static int ksz9031_of_load_skew_values(struct phy_device *phydev, 454 const struct device_node *of_node, 455 u16 reg, size_t field_sz, 456 const char *field[], u8 numfields) 457 { 458 int val[4] = {-1, -2, -3, -4}; 459 int matches = 0; 460 u16 mask; 461 u16 maxval; 462 u16 newval; 463 int i; 464 465 for (i = 0; i < numfields; i++) 466 if (!of_property_read_u32(of_node, field[i], val + i)) 467 matches++; 468 469 if (!matches) 470 return 0; 471 472 if (matches < numfields) 473 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg); 474 else 475 newval = 0; 476 477 maxval = (field_sz == 4) ? 0xf : 0x1f; 478 for (i = 0; i < numfields; i++) 479 if (val[i] != -(i + 1)) { 480 mask = 0xffff; 481 mask ^= maxval << (field_sz * i); 482 newval = (newval & mask) | 483 (((val[i] / KSZ9031_PS_TO_REG) & maxval) 484 << (field_sz * i)); 485 } 486 487 return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval); 488 } 489 490 static int ksz9031_center_flp_timing(struct phy_device *phydev) 491 { 492 int result; 493 494 /* Center KSZ9031RNX FLP timing at 16ms. */ 495 result = ksz9031_extended_write(phydev, OP_DATA, 0, 496 MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006); 497 result = ksz9031_extended_write(phydev, OP_DATA, 0, 498 MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80); 499 500 if (result) 501 return result; 502 503 return genphy_restart_aneg(phydev); 504 } 505 506 /* Enable energy-detect power-down mode */ 507 static int ksz9031_enable_edpd(struct phy_device *phydev) 508 { 509 int reg; 510 511 reg = ksz9031_extended_read(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD); 512 if (reg < 0) 513 return reg; 514 return ksz9031_extended_write(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD, 515 reg | MII_KSZ9031RN_EDPD_ENABLE); 516 } 517 518 static int ksz9031_config_init(struct phy_device *phydev) 519 { 520 const struct device *dev = &phydev->mdio.dev; 521 const struct device_node *of_node = dev->of_node; 522 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"}; 523 static const char *rx_data_skews[4] = { 524 "rxd0-skew-ps", "rxd1-skew-ps", 525 "rxd2-skew-ps", "rxd3-skew-ps" 526 }; 527 static const char *tx_data_skews[4] = { 528 "txd0-skew-ps", "txd1-skew-ps", 529 "txd2-skew-ps", "txd3-skew-ps" 530 }; 531 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"}; 532 const struct device *dev_walker; 533 int result; 534 535 result = ksz9031_enable_edpd(phydev); 536 if (result < 0) 537 return result; 538 539 /* The Micrel driver has a deprecated option to place phy OF 540 * properties in the MAC node. Walk up the tree of devices to 541 * find a device with an OF node. 542 */ 543 dev_walker = &phydev->mdio.dev; 544 do { 545 of_node = dev_walker->of_node; 546 dev_walker = dev_walker->parent; 547 } while (!of_node && dev_walker); 548 549 if (of_node) { 550 ksz9031_of_load_skew_values(phydev, of_node, 551 MII_KSZ9031RN_CLK_PAD_SKEW, 5, 552 clk_skews, 2); 553 554 ksz9031_of_load_skew_values(phydev, of_node, 555 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, 556 control_skews, 2); 557 558 ksz9031_of_load_skew_values(phydev, of_node, 559 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, 560 rx_data_skews, 4); 561 562 ksz9031_of_load_skew_values(phydev, of_node, 563 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, 564 tx_data_skews, 4); 565 } 566 567 return ksz9031_center_flp_timing(phydev); 568 } 569 570 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06 571 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6) 572 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4) 573 static int ksz8873mll_read_status(struct phy_device *phydev) 574 { 575 int regval; 576 577 /* dummy read */ 578 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 579 580 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 581 582 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX) 583 phydev->duplex = DUPLEX_HALF; 584 else 585 phydev->duplex = DUPLEX_FULL; 586 587 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED) 588 phydev->speed = SPEED_10; 589 else 590 phydev->speed = SPEED_100; 591 592 phydev->link = 1; 593 phydev->pause = phydev->asym_pause = 0; 594 595 return 0; 596 } 597 598 static int ksz9031_read_status(struct phy_device *phydev) 599 { 600 int err; 601 int regval; 602 603 err = genphy_read_status(phydev); 604 if (err) 605 return err; 606 607 /* Make sure the PHY is not broken. Read idle error count, 608 * and reset the PHY if it is maxed out. 609 */ 610 regval = phy_read(phydev, MII_STAT1000); 611 if ((regval & 0xFF) == 0xFF) { 612 phy_init_hw(phydev); 613 phydev->link = 0; 614 } 615 616 return 0; 617 } 618 619 static int ksz8873mll_config_aneg(struct phy_device *phydev) 620 { 621 return 0; 622 } 623 624 /* This routine returns -1 as an indication to the caller that the 625 * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE 626 * MMD extended PHY registers. 627 */ 628 static int 629 ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int devad, u16 regnum) 630 { 631 return -1; 632 } 633 634 /* This routine does nothing since the Micrel ksz9021 does not support 635 * standard IEEE MMD extended PHY registers. 636 */ 637 static int 638 ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int devad, u16 regnum, u16 val) 639 { 640 return -1; 641 } 642 643 static int kszphy_get_sset_count(struct phy_device *phydev) 644 { 645 return ARRAY_SIZE(kszphy_hw_stats); 646 } 647 648 static void kszphy_get_strings(struct phy_device *phydev, u8 *data) 649 { 650 int i; 651 652 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) { 653 memcpy(data + i * ETH_GSTRING_LEN, 654 kszphy_hw_stats[i].string, ETH_GSTRING_LEN); 655 } 656 } 657 658 #ifndef UINT64_MAX 659 #define UINT64_MAX (u64)(~((u64)0)) 660 #endif 661 static u64 kszphy_get_stat(struct phy_device *phydev, int i) 662 { 663 struct kszphy_hw_stat stat = kszphy_hw_stats[i]; 664 struct kszphy_priv *priv = phydev->priv; 665 int val; 666 u64 ret; 667 668 val = phy_read(phydev, stat.reg); 669 if (val < 0) { 670 ret = UINT64_MAX; 671 } else { 672 val = val & ((1 << stat.bits) - 1); 673 priv->stats[i] += val; 674 ret = priv->stats[i]; 675 } 676 677 return ret; 678 } 679 680 static void kszphy_get_stats(struct phy_device *phydev, 681 struct ethtool_stats *stats, u64 *data) 682 { 683 int i; 684 685 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) 686 data[i] = kszphy_get_stat(phydev, i); 687 } 688 689 static int kszphy_suspend(struct phy_device *phydev) 690 { 691 /* Disable PHY Interrupts */ 692 if (phy_interrupt_is_valid(phydev)) { 693 phydev->interrupts = PHY_INTERRUPT_DISABLED; 694 if (phydev->drv->config_intr) 695 phydev->drv->config_intr(phydev); 696 } 697 698 return genphy_suspend(phydev); 699 } 700 701 static int kszphy_resume(struct phy_device *phydev) 702 { 703 genphy_resume(phydev); 704 705 /* Enable PHY Interrupts */ 706 if (phy_interrupt_is_valid(phydev)) { 707 phydev->interrupts = PHY_INTERRUPT_ENABLED; 708 if (phydev->drv->config_intr) 709 phydev->drv->config_intr(phydev); 710 } 711 712 return 0; 713 } 714 715 static int kszphy_probe(struct phy_device *phydev) 716 { 717 const struct kszphy_type *type = phydev->drv->driver_data; 718 const struct device_node *np = phydev->mdio.dev.of_node; 719 struct kszphy_priv *priv; 720 struct clk *clk; 721 int ret; 722 723 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 724 if (!priv) 725 return -ENOMEM; 726 727 phydev->priv = priv; 728 729 priv->type = type; 730 731 if (type->led_mode_reg) { 732 ret = of_property_read_u32(np, "micrel,led-mode", 733 &priv->led_mode); 734 if (ret) 735 priv->led_mode = -1; 736 737 if (priv->led_mode > 3) { 738 phydev_err(phydev, "invalid led mode: 0x%02x\n", 739 priv->led_mode); 740 priv->led_mode = -1; 741 } 742 } else { 743 priv->led_mode = -1; 744 } 745 746 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref"); 747 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */ 748 if (!IS_ERR_OR_NULL(clk)) { 749 unsigned long rate = clk_get_rate(clk); 750 bool rmii_ref_clk_sel_25_mhz; 751 752 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel; 753 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np, 754 "micrel,rmii-reference-clock-select-25-mhz"); 755 756 if (rate > 24500000 && rate < 25500000) { 757 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz; 758 } else if (rate > 49500000 && rate < 50500000) { 759 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz; 760 } else { 761 phydev_err(phydev, "Clock rate out of range: %ld\n", 762 rate); 763 return -EINVAL; 764 } 765 } 766 767 /* Support legacy board-file configuration */ 768 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) { 769 priv->rmii_ref_clk_sel = true; 770 priv->rmii_ref_clk_sel_val = true; 771 } 772 773 return 0; 774 } 775 776 static struct phy_driver ksphy_driver[] = { 777 { 778 .phy_id = PHY_ID_KS8737, 779 .phy_id_mask = MICREL_PHY_ID_MASK, 780 .name = "Micrel KS8737", 781 .features = PHY_BASIC_FEATURES, 782 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 783 .driver_data = &ks8737_type, 784 .config_init = kszphy_config_init, 785 .config_aneg = genphy_config_aneg, 786 .read_status = genphy_read_status, 787 .ack_interrupt = kszphy_ack_interrupt, 788 .config_intr = kszphy_config_intr, 789 .suspend = genphy_suspend, 790 .resume = genphy_resume, 791 }, { 792 .phy_id = PHY_ID_KSZ8021, 793 .phy_id_mask = 0x00ffffff, 794 .name = "Micrel KSZ8021 or KSZ8031", 795 .features = PHY_BASIC_FEATURES, 796 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 797 .driver_data = &ksz8021_type, 798 .probe = kszphy_probe, 799 .config_init = kszphy_config_init, 800 .config_aneg = genphy_config_aneg, 801 .read_status = genphy_read_status, 802 .ack_interrupt = kszphy_ack_interrupt, 803 .config_intr = kszphy_config_intr, 804 .get_sset_count = kszphy_get_sset_count, 805 .get_strings = kszphy_get_strings, 806 .get_stats = kszphy_get_stats, 807 .suspend = genphy_suspend, 808 .resume = genphy_resume, 809 }, { 810 .phy_id = PHY_ID_KSZ8031, 811 .phy_id_mask = 0x00ffffff, 812 .name = "Micrel KSZ8031", 813 .features = PHY_BASIC_FEATURES, 814 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 815 .driver_data = &ksz8021_type, 816 .probe = kszphy_probe, 817 .config_init = kszphy_config_init, 818 .config_aneg = genphy_config_aneg, 819 .read_status = genphy_read_status, 820 .ack_interrupt = kszphy_ack_interrupt, 821 .config_intr = kszphy_config_intr, 822 .get_sset_count = kszphy_get_sset_count, 823 .get_strings = kszphy_get_strings, 824 .get_stats = kszphy_get_stats, 825 .suspend = genphy_suspend, 826 .resume = genphy_resume, 827 }, { 828 .phy_id = PHY_ID_KSZ8041, 829 .phy_id_mask = MICREL_PHY_ID_MASK, 830 .name = "Micrel KSZ8041", 831 .features = PHY_BASIC_FEATURES, 832 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 833 .driver_data = &ksz8041_type, 834 .probe = kszphy_probe, 835 .config_init = ksz8041_config_init, 836 .config_aneg = ksz8041_config_aneg, 837 .read_status = genphy_read_status, 838 .ack_interrupt = kszphy_ack_interrupt, 839 .config_intr = kszphy_config_intr, 840 .get_sset_count = kszphy_get_sset_count, 841 .get_strings = kszphy_get_strings, 842 .get_stats = kszphy_get_stats, 843 .suspend = genphy_suspend, 844 .resume = genphy_resume, 845 }, { 846 .phy_id = PHY_ID_KSZ8041RNLI, 847 .phy_id_mask = MICREL_PHY_ID_MASK, 848 .name = "Micrel KSZ8041RNLI", 849 .features = PHY_BASIC_FEATURES, 850 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 851 .driver_data = &ksz8041_type, 852 .probe = kszphy_probe, 853 .config_init = kszphy_config_init, 854 .config_aneg = genphy_config_aneg, 855 .read_status = genphy_read_status, 856 .ack_interrupt = kszphy_ack_interrupt, 857 .config_intr = kszphy_config_intr, 858 .get_sset_count = kszphy_get_sset_count, 859 .get_strings = kszphy_get_strings, 860 .get_stats = kszphy_get_stats, 861 .suspend = genphy_suspend, 862 .resume = genphy_resume, 863 }, { 864 .phy_id = PHY_ID_KSZ8051, 865 .phy_id_mask = MICREL_PHY_ID_MASK, 866 .name = "Micrel KSZ8051", 867 .features = PHY_BASIC_FEATURES, 868 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 869 .driver_data = &ksz8051_type, 870 .probe = kszphy_probe, 871 .config_init = kszphy_config_init, 872 .config_aneg = genphy_config_aneg, 873 .read_status = genphy_read_status, 874 .ack_interrupt = kszphy_ack_interrupt, 875 .config_intr = kszphy_config_intr, 876 .get_sset_count = kszphy_get_sset_count, 877 .get_strings = kszphy_get_strings, 878 .get_stats = kszphy_get_stats, 879 .suspend = genphy_suspend, 880 .resume = genphy_resume, 881 }, { 882 .phy_id = PHY_ID_KSZ8001, 883 .name = "Micrel KSZ8001 or KS8721", 884 .phy_id_mask = 0x00fffffc, 885 .features = PHY_BASIC_FEATURES, 886 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 887 .driver_data = &ksz8041_type, 888 .probe = kszphy_probe, 889 .config_init = kszphy_config_init, 890 .config_aneg = genphy_config_aneg, 891 .read_status = genphy_read_status, 892 .ack_interrupt = kszphy_ack_interrupt, 893 .config_intr = kszphy_config_intr, 894 .get_sset_count = kszphy_get_sset_count, 895 .get_strings = kszphy_get_strings, 896 .get_stats = kszphy_get_stats, 897 .suspend = genphy_suspend, 898 .resume = genphy_resume, 899 }, { 900 .phy_id = PHY_ID_KSZ8081, 901 .name = "Micrel KSZ8081 or KSZ8091", 902 .phy_id_mask = MICREL_PHY_ID_MASK, 903 .features = PHY_BASIC_FEATURES, 904 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 905 .driver_data = &ksz8081_type, 906 .probe = kszphy_probe, 907 .config_init = kszphy_config_init, 908 .config_aneg = genphy_config_aneg, 909 .read_status = genphy_read_status, 910 .ack_interrupt = kszphy_ack_interrupt, 911 .config_intr = kszphy_config_intr, 912 .get_sset_count = kszphy_get_sset_count, 913 .get_strings = kszphy_get_strings, 914 .get_stats = kszphy_get_stats, 915 .suspend = kszphy_suspend, 916 .resume = kszphy_resume, 917 }, { 918 .phy_id = PHY_ID_KSZ8061, 919 .name = "Micrel KSZ8061", 920 .phy_id_mask = MICREL_PHY_ID_MASK, 921 .features = PHY_BASIC_FEATURES, 922 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 923 .config_init = kszphy_config_init, 924 .config_aneg = genphy_config_aneg, 925 .read_status = genphy_read_status, 926 .ack_interrupt = kszphy_ack_interrupt, 927 .config_intr = kszphy_config_intr, 928 .suspend = genphy_suspend, 929 .resume = genphy_resume, 930 }, { 931 .phy_id = PHY_ID_KSZ9021, 932 .phy_id_mask = 0x000ffffe, 933 .name = "Micrel KSZ9021 Gigabit PHY", 934 .features = PHY_GBIT_FEATURES, 935 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 936 .driver_data = &ksz9021_type, 937 .probe = kszphy_probe, 938 .config_init = ksz9021_config_init, 939 .config_aneg = genphy_config_aneg, 940 .read_status = genphy_read_status, 941 .ack_interrupt = kszphy_ack_interrupt, 942 .config_intr = kszphy_config_intr, 943 .get_sset_count = kszphy_get_sset_count, 944 .get_strings = kszphy_get_strings, 945 .get_stats = kszphy_get_stats, 946 .suspend = genphy_suspend, 947 .resume = genphy_resume, 948 .read_mmd = ksz9021_rd_mmd_phyreg, 949 .write_mmd = ksz9021_wr_mmd_phyreg, 950 }, { 951 .phy_id = PHY_ID_KSZ9031, 952 .phy_id_mask = MICREL_PHY_ID_MASK, 953 .name = "Micrel KSZ9031 Gigabit PHY", 954 .features = PHY_GBIT_FEATURES, 955 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 956 .driver_data = &ksz9021_type, 957 .probe = kszphy_probe, 958 .config_init = ksz9031_config_init, 959 .config_aneg = genphy_config_aneg, 960 .read_status = ksz9031_read_status, 961 .ack_interrupt = kszphy_ack_interrupt, 962 .config_intr = kszphy_config_intr, 963 .get_sset_count = kszphy_get_sset_count, 964 .get_strings = kszphy_get_strings, 965 .get_stats = kszphy_get_stats, 966 .suspend = genphy_suspend, 967 .resume = kszphy_resume, 968 }, { 969 .phy_id = PHY_ID_KSZ8873MLL, 970 .phy_id_mask = MICREL_PHY_ID_MASK, 971 .name = "Micrel KSZ8873MLL Switch", 972 .flags = PHY_HAS_MAGICANEG, 973 .config_init = kszphy_config_init, 974 .config_aneg = ksz8873mll_config_aneg, 975 .read_status = ksz8873mll_read_status, 976 .suspend = genphy_suspend, 977 .resume = genphy_resume, 978 }, { 979 .phy_id = PHY_ID_KSZ886X, 980 .phy_id_mask = MICREL_PHY_ID_MASK, 981 .name = "Micrel KSZ886X Switch", 982 .features = PHY_BASIC_FEATURES, 983 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 984 .config_init = kszphy_config_init, 985 .config_aneg = genphy_config_aneg, 986 .read_status = genphy_read_status, 987 .suspend = genphy_suspend, 988 .resume = genphy_resume, 989 }, { 990 .phy_id = PHY_ID_KSZ8795, 991 .phy_id_mask = MICREL_PHY_ID_MASK, 992 .name = "Micrel KSZ8795", 993 .features = PHY_BASIC_FEATURES, 994 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 995 .config_init = kszphy_config_init, 996 .config_aneg = ksz8873mll_config_aneg, 997 .read_status = ksz8873mll_read_status, 998 .suspend = genphy_suspend, 999 .resume = genphy_resume, 1000 } }; 1001 1002 module_phy_driver(ksphy_driver); 1003 1004 MODULE_DESCRIPTION("Micrel PHY driver"); 1005 MODULE_AUTHOR("David J. Choi"); 1006 MODULE_LICENSE("GPL"); 1007 1008 static struct mdio_device_id __maybe_unused micrel_tbl[] = { 1009 { PHY_ID_KSZ9021, 0x000ffffe }, 1010 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK }, 1011 { PHY_ID_KSZ8001, 0x00fffffc }, 1012 { PHY_ID_KS8737, MICREL_PHY_ID_MASK }, 1013 { PHY_ID_KSZ8021, 0x00ffffff }, 1014 { PHY_ID_KSZ8031, 0x00ffffff }, 1015 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK }, 1016 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK }, 1017 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK }, 1018 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK }, 1019 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK }, 1020 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK }, 1021 { } 1022 }; 1023 1024 MODULE_DEVICE_TABLE(mdio, micrel_tbl); 1025