1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/micrel.c 4 * 5 * Driver for Micrel PHYs 6 * 7 * Author: David J. Choi 8 * 9 * Copyright (c) 2010-2013 Micrel, Inc. 10 * Copyright (c) 2014 Johan Hovold <johan@kernel.org> 11 * 12 * Support : Micrel Phys: 13 * Giga phys: ksz9021, ksz9031, ksz9131 14 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041 15 * ksz8021, ksz8031, ksz8051, 16 * ksz8081, ksz8091, 17 * ksz8061, 18 * Switch : ksz8873, ksz886x 19 * ksz9477 20 */ 21 22 #include <linux/bitfield.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/phy.h> 26 #include <linux/micrel_phy.h> 27 #include <linux/of.h> 28 #include <linux/clk.h> 29 #include <linux/delay.h> 30 31 /* Operation Mode Strap Override */ 32 #define MII_KSZPHY_OMSO 0x16 33 #define KSZPHY_OMSO_FACTORY_TEST BIT(15) 34 #define KSZPHY_OMSO_B_CAST_OFF BIT(9) 35 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5) 36 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1) 37 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0) 38 39 /* general Interrupt control/status reg in vendor specific block. */ 40 #define MII_KSZPHY_INTCS 0x1B 41 #define KSZPHY_INTCS_JABBER BIT(15) 42 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14) 43 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13) 44 #define KSZPHY_INTCS_PARELLEL BIT(12) 45 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11) 46 #define KSZPHY_INTCS_LINK_DOWN BIT(10) 47 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9) 48 #define KSZPHY_INTCS_LINK_UP BIT(8) 49 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\ 50 KSZPHY_INTCS_LINK_DOWN) 51 #define KSZPHY_INTCS_LINK_DOWN_STATUS BIT(2) 52 #define KSZPHY_INTCS_LINK_UP_STATUS BIT(0) 53 #define KSZPHY_INTCS_STATUS (KSZPHY_INTCS_LINK_DOWN_STATUS |\ 54 KSZPHY_INTCS_LINK_UP_STATUS) 55 56 /* PHY Control 1 */ 57 #define MII_KSZPHY_CTRL_1 0x1e 58 59 /* PHY Control 2 / PHY Control (if no PHY Control 1) */ 60 #define MII_KSZPHY_CTRL_2 0x1f 61 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2 62 /* bitmap of PHY register to set interrupt mode */ 63 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9) 64 #define KSZPHY_RMII_REF_CLK_SEL BIT(7) 65 66 /* Write/read to/from extended registers */ 67 #define MII_KSZPHY_EXTREG 0x0b 68 #define KSZPHY_EXTREG_WRITE 0x8000 69 70 #define MII_KSZPHY_EXTREG_WRITE 0x0c 71 #define MII_KSZPHY_EXTREG_READ 0x0d 72 73 /* Extended registers */ 74 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104 75 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105 76 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106 77 78 #define PS_TO_REG 200 79 80 struct kszphy_hw_stat { 81 const char *string; 82 u8 reg; 83 u8 bits; 84 }; 85 86 static struct kszphy_hw_stat kszphy_hw_stats[] = { 87 { "phy_receive_errors", 21, 16}, 88 { "phy_idle_errors", 10, 8 }, 89 }; 90 91 struct kszphy_type { 92 u32 led_mode_reg; 93 u16 interrupt_level_mask; 94 bool has_broadcast_disable; 95 bool has_nand_tree_disable; 96 bool has_rmii_ref_clk_sel; 97 }; 98 99 struct kszphy_priv { 100 const struct kszphy_type *type; 101 int led_mode; 102 bool rmii_ref_clk_sel; 103 bool rmii_ref_clk_sel_val; 104 u64 stats[ARRAY_SIZE(kszphy_hw_stats)]; 105 }; 106 107 static const struct kszphy_type ksz8021_type = { 108 .led_mode_reg = MII_KSZPHY_CTRL_2, 109 .has_broadcast_disable = true, 110 .has_nand_tree_disable = true, 111 .has_rmii_ref_clk_sel = true, 112 }; 113 114 static const struct kszphy_type ksz8041_type = { 115 .led_mode_reg = MII_KSZPHY_CTRL_1, 116 }; 117 118 static const struct kszphy_type ksz8051_type = { 119 .led_mode_reg = MII_KSZPHY_CTRL_2, 120 .has_nand_tree_disable = true, 121 }; 122 123 static const struct kszphy_type ksz8081_type = { 124 .led_mode_reg = MII_KSZPHY_CTRL_2, 125 .has_broadcast_disable = true, 126 .has_nand_tree_disable = true, 127 .has_rmii_ref_clk_sel = true, 128 }; 129 130 static const struct kszphy_type ks8737_type = { 131 .interrupt_level_mask = BIT(14), 132 }; 133 134 static const struct kszphy_type ksz9021_type = { 135 .interrupt_level_mask = BIT(14), 136 }; 137 138 static int kszphy_extended_write(struct phy_device *phydev, 139 u32 regnum, u16 val) 140 { 141 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum); 142 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); 143 } 144 145 static int kszphy_extended_read(struct phy_device *phydev, 146 u32 regnum) 147 { 148 phy_write(phydev, MII_KSZPHY_EXTREG, regnum); 149 return phy_read(phydev, MII_KSZPHY_EXTREG_READ); 150 } 151 152 static int kszphy_ack_interrupt(struct phy_device *phydev) 153 { 154 /* bit[7..0] int status, which is a read and clear register. */ 155 int rc; 156 157 rc = phy_read(phydev, MII_KSZPHY_INTCS); 158 159 return (rc < 0) ? rc : 0; 160 } 161 162 static int kszphy_config_intr(struct phy_device *phydev) 163 { 164 const struct kszphy_type *type = phydev->drv->driver_data; 165 int temp, err; 166 u16 mask; 167 168 if (type && type->interrupt_level_mask) 169 mask = type->interrupt_level_mask; 170 else 171 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH; 172 173 /* set the interrupt pin active low */ 174 temp = phy_read(phydev, MII_KSZPHY_CTRL); 175 if (temp < 0) 176 return temp; 177 temp &= ~mask; 178 phy_write(phydev, MII_KSZPHY_CTRL, temp); 179 180 /* enable / disable interrupts */ 181 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 182 err = kszphy_ack_interrupt(phydev); 183 if (err) 184 return err; 185 186 temp = KSZPHY_INTCS_ALL; 187 err = phy_write(phydev, MII_KSZPHY_INTCS, temp); 188 } else { 189 temp = 0; 190 err = phy_write(phydev, MII_KSZPHY_INTCS, temp); 191 if (err) 192 return err; 193 194 err = kszphy_ack_interrupt(phydev); 195 } 196 197 return err; 198 } 199 200 static irqreturn_t kszphy_handle_interrupt(struct phy_device *phydev) 201 { 202 int irq_status; 203 204 irq_status = phy_read(phydev, MII_KSZPHY_INTCS); 205 if (irq_status < 0) { 206 phy_error(phydev); 207 return IRQ_NONE; 208 } 209 210 if (!(irq_status & KSZPHY_INTCS_STATUS)) 211 return IRQ_NONE; 212 213 phy_trigger_machine(phydev); 214 215 return IRQ_HANDLED; 216 } 217 218 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val) 219 { 220 int ctrl; 221 222 ctrl = phy_read(phydev, MII_KSZPHY_CTRL); 223 if (ctrl < 0) 224 return ctrl; 225 226 if (val) 227 ctrl |= KSZPHY_RMII_REF_CLK_SEL; 228 else 229 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL; 230 231 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl); 232 } 233 234 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val) 235 { 236 int rc, temp, shift; 237 238 switch (reg) { 239 case MII_KSZPHY_CTRL_1: 240 shift = 14; 241 break; 242 case MII_KSZPHY_CTRL_2: 243 shift = 4; 244 break; 245 default: 246 return -EINVAL; 247 } 248 249 temp = phy_read(phydev, reg); 250 if (temp < 0) { 251 rc = temp; 252 goto out; 253 } 254 255 temp &= ~(3 << shift); 256 temp |= val << shift; 257 rc = phy_write(phydev, reg, temp); 258 out: 259 if (rc < 0) 260 phydev_err(phydev, "failed to set led mode\n"); 261 262 return rc; 263 } 264 265 /* Disable PHY address 0 as the broadcast address, so that it can be used as a 266 * unique (non-broadcast) address on a shared bus. 267 */ 268 static int kszphy_broadcast_disable(struct phy_device *phydev) 269 { 270 int ret; 271 272 ret = phy_read(phydev, MII_KSZPHY_OMSO); 273 if (ret < 0) 274 goto out; 275 276 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF); 277 out: 278 if (ret) 279 phydev_err(phydev, "failed to disable broadcast address\n"); 280 281 return ret; 282 } 283 284 static int kszphy_nand_tree_disable(struct phy_device *phydev) 285 { 286 int ret; 287 288 ret = phy_read(phydev, MII_KSZPHY_OMSO); 289 if (ret < 0) 290 goto out; 291 292 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON)) 293 return 0; 294 295 ret = phy_write(phydev, MII_KSZPHY_OMSO, 296 ret & ~KSZPHY_OMSO_NAND_TREE_ON); 297 out: 298 if (ret) 299 phydev_err(phydev, "failed to disable NAND tree mode\n"); 300 301 return ret; 302 } 303 304 /* Some config bits need to be set again on resume, handle them here. */ 305 static int kszphy_config_reset(struct phy_device *phydev) 306 { 307 struct kszphy_priv *priv = phydev->priv; 308 int ret; 309 310 if (priv->rmii_ref_clk_sel) { 311 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val); 312 if (ret) { 313 phydev_err(phydev, 314 "failed to set rmii reference clock\n"); 315 return ret; 316 } 317 } 318 319 if (priv->led_mode >= 0) 320 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode); 321 322 return 0; 323 } 324 325 static int kszphy_config_init(struct phy_device *phydev) 326 { 327 struct kszphy_priv *priv = phydev->priv; 328 const struct kszphy_type *type; 329 330 if (!priv) 331 return 0; 332 333 type = priv->type; 334 335 if (type->has_broadcast_disable) 336 kszphy_broadcast_disable(phydev); 337 338 if (type->has_nand_tree_disable) 339 kszphy_nand_tree_disable(phydev); 340 341 return kszphy_config_reset(phydev); 342 } 343 344 static int ksz8041_fiber_mode(struct phy_device *phydev) 345 { 346 struct device_node *of_node = phydev->mdio.dev.of_node; 347 348 return of_property_read_bool(of_node, "micrel,fiber-mode"); 349 } 350 351 static int ksz8041_config_init(struct phy_device *phydev) 352 { 353 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 354 355 /* Limit supported and advertised modes in fiber mode */ 356 if (ksz8041_fiber_mode(phydev)) { 357 phydev->dev_flags |= MICREL_PHY_FXEN; 358 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask); 359 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask); 360 361 linkmode_and(phydev->supported, phydev->supported, mask); 362 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 363 phydev->supported); 364 linkmode_and(phydev->advertising, phydev->advertising, mask); 365 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 366 phydev->advertising); 367 phydev->autoneg = AUTONEG_DISABLE; 368 } 369 370 return kszphy_config_init(phydev); 371 } 372 373 static int ksz8041_config_aneg(struct phy_device *phydev) 374 { 375 /* Skip auto-negotiation in fiber mode */ 376 if (phydev->dev_flags & MICREL_PHY_FXEN) { 377 phydev->speed = SPEED_100; 378 return 0; 379 } 380 381 return genphy_config_aneg(phydev); 382 } 383 384 static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev, 385 const u32 ksz_phy_id) 386 { 387 int ret; 388 389 if ((phydev->phy_id & MICREL_PHY_ID_MASK) != ksz_phy_id) 390 return 0; 391 392 ret = phy_read(phydev, MII_BMSR); 393 if (ret < 0) 394 return ret; 395 396 /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same 397 * exact PHY ID. However, they can be told apart by the extended 398 * capability registers presence. The KSZ8051 PHY has them while 399 * the switch does not. 400 */ 401 ret &= BMSR_ERCAP; 402 if (ksz_phy_id == PHY_ID_KSZ8051) 403 return ret; 404 else 405 return !ret; 406 } 407 408 static int ksz8051_match_phy_device(struct phy_device *phydev) 409 { 410 return ksz8051_ksz8795_match_phy_device(phydev, PHY_ID_KSZ8051); 411 } 412 413 static int ksz8081_config_init(struct phy_device *phydev) 414 { 415 /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line 416 * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a 417 * pull-down is missing, the factory test mode should be cleared by 418 * manually writing a 0. 419 */ 420 phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST); 421 422 return kszphy_config_init(phydev); 423 } 424 425 static int ksz8061_config_init(struct phy_device *phydev) 426 { 427 int ret; 428 429 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A); 430 if (ret) 431 return ret; 432 433 return kszphy_config_init(phydev); 434 } 435 436 static int ksz8795_match_phy_device(struct phy_device *phydev) 437 { 438 return ksz8051_ksz8795_match_phy_device(phydev, PHY_ID_KSZ87XX); 439 } 440 441 static int ksz9021_load_values_from_of(struct phy_device *phydev, 442 const struct device_node *of_node, 443 u16 reg, 444 const char *field1, const char *field2, 445 const char *field3, const char *field4) 446 { 447 int val1 = -1; 448 int val2 = -2; 449 int val3 = -3; 450 int val4 = -4; 451 int newval; 452 int matches = 0; 453 454 if (!of_property_read_u32(of_node, field1, &val1)) 455 matches++; 456 457 if (!of_property_read_u32(of_node, field2, &val2)) 458 matches++; 459 460 if (!of_property_read_u32(of_node, field3, &val3)) 461 matches++; 462 463 if (!of_property_read_u32(of_node, field4, &val4)) 464 matches++; 465 466 if (!matches) 467 return 0; 468 469 if (matches < 4) 470 newval = kszphy_extended_read(phydev, reg); 471 else 472 newval = 0; 473 474 if (val1 != -1) 475 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0); 476 477 if (val2 != -2) 478 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4); 479 480 if (val3 != -3) 481 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8); 482 483 if (val4 != -4) 484 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12); 485 486 return kszphy_extended_write(phydev, reg, newval); 487 } 488 489 static int ksz9021_config_init(struct phy_device *phydev) 490 { 491 const struct device_node *of_node; 492 const struct device *dev_walker; 493 494 /* The Micrel driver has a deprecated option to place phy OF 495 * properties in the MAC node. Walk up the tree of devices to 496 * find a device with an OF node. 497 */ 498 dev_walker = &phydev->mdio.dev; 499 do { 500 of_node = dev_walker->of_node; 501 dev_walker = dev_walker->parent; 502 503 } while (!of_node && dev_walker); 504 505 if (of_node) { 506 ksz9021_load_values_from_of(phydev, of_node, 507 MII_KSZPHY_CLK_CONTROL_PAD_SKEW, 508 "txen-skew-ps", "txc-skew-ps", 509 "rxdv-skew-ps", "rxc-skew-ps"); 510 ksz9021_load_values_from_of(phydev, of_node, 511 MII_KSZPHY_RX_DATA_PAD_SKEW, 512 "rxd0-skew-ps", "rxd1-skew-ps", 513 "rxd2-skew-ps", "rxd3-skew-ps"); 514 ksz9021_load_values_from_of(phydev, of_node, 515 MII_KSZPHY_TX_DATA_PAD_SKEW, 516 "txd0-skew-ps", "txd1-skew-ps", 517 "txd2-skew-ps", "txd3-skew-ps"); 518 } 519 return 0; 520 } 521 522 #define KSZ9031_PS_TO_REG 60 523 524 /* Extended registers */ 525 /* MMD Address 0x0 */ 526 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3 527 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4 528 529 /* MMD Address 0x2 */ 530 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4 531 #define MII_KSZ9031RN_RX_CTL_M GENMASK(7, 4) 532 #define MII_KSZ9031RN_TX_CTL_M GENMASK(3, 0) 533 534 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5 535 #define MII_KSZ9031RN_RXD3 GENMASK(15, 12) 536 #define MII_KSZ9031RN_RXD2 GENMASK(11, 8) 537 #define MII_KSZ9031RN_RXD1 GENMASK(7, 4) 538 #define MII_KSZ9031RN_RXD0 GENMASK(3, 0) 539 540 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6 541 #define MII_KSZ9031RN_TXD3 GENMASK(15, 12) 542 #define MII_KSZ9031RN_TXD2 GENMASK(11, 8) 543 #define MII_KSZ9031RN_TXD1 GENMASK(7, 4) 544 #define MII_KSZ9031RN_TXD0 GENMASK(3, 0) 545 546 #define MII_KSZ9031RN_CLK_PAD_SKEW 8 547 #define MII_KSZ9031RN_GTX_CLK GENMASK(9, 5) 548 #define MII_KSZ9031RN_RX_CLK GENMASK(4, 0) 549 550 /* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To 551 * provide different RGMII options we need to configure delay offset 552 * for each pad relative to build in delay. 553 */ 554 /* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of 555 * 1.80ns 556 */ 557 #define RX_ID 0x7 558 #define RX_CLK_ID 0x19 559 560 /* set rx to +0.30ns and rx_clk to -0.90ns to compensate the 561 * internal 1.2ns delay. 562 */ 563 #define RX_ND 0xc 564 #define RX_CLK_ND 0x0 565 566 /* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */ 567 #define TX_ID 0x0 568 #define TX_CLK_ID 0x1f 569 570 /* set tx and tx_clk to "No delay adjustment" to keep 0ns 571 * dealy 572 */ 573 #define TX_ND 0x7 574 #define TX_CLK_ND 0xf 575 576 /* MMD Address 0x1C */ 577 #define MII_KSZ9031RN_EDPD 0x23 578 #define MII_KSZ9031RN_EDPD_ENABLE BIT(0) 579 580 static int ksz9031_of_load_skew_values(struct phy_device *phydev, 581 const struct device_node *of_node, 582 u16 reg, size_t field_sz, 583 const char *field[], u8 numfields, 584 bool *update) 585 { 586 int val[4] = {-1, -2, -3, -4}; 587 int matches = 0; 588 u16 mask; 589 u16 maxval; 590 u16 newval; 591 int i; 592 593 for (i = 0; i < numfields; i++) 594 if (!of_property_read_u32(of_node, field[i], val + i)) 595 matches++; 596 597 if (!matches) 598 return 0; 599 600 *update |= true; 601 602 if (matches < numfields) 603 newval = phy_read_mmd(phydev, 2, reg); 604 else 605 newval = 0; 606 607 maxval = (field_sz == 4) ? 0xf : 0x1f; 608 for (i = 0; i < numfields; i++) 609 if (val[i] != -(i + 1)) { 610 mask = 0xffff; 611 mask ^= maxval << (field_sz * i); 612 newval = (newval & mask) | 613 (((val[i] / KSZ9031_PS_TO_REG) & maxval) 614 << (field_sz * i)); 615 } 616 617 return phy_write_mmd(phydev, 2, reg, newval); 618 } 619 620 /* Center KSZ9031RNX FLP timing at 16ms. */ 621 static int ksz9031_center_flp_timing(struct phy_device *phydev) 622 { 623 int result; 624 625 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI, 626 0x0006); 627 if (result) 628 return result; 629 630 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO, 631 0x1A80); 632 if (result) 633 return result; 634 635 return genphy_restart_aneg(phydev); 636 } 637 638 /* Enable energy-detect power-down mode */ 639 static int ksz9031_enable_edpd(struct phy_device *phydev) 640 { 641 int reg; 642 643 reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD); 644 if (reg < 0) 645 return reg; 646 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD, 647 reg | MII_KSZ9031RN_EDPD_ENABLE); 648 } 649 650 static int ksz9031_config_rgmii_delay(struct phy_device *phydev) 651 { 652 u16 rx, tx, rx_clk, tx_clk; 653 int ret; 654 655 switch (phydev->interface) { 656 case PHY_INTERFACE_MODE_RGMII: 657 tx = TX_ND; 658 tx_clk = TX_CLK_ND; 659 rx = RX_ND; 660 rx_clk = RX_CLK_ND; 661 break; 662 case PHY_INTERFACE_MODE_RGMII_ID: 663 tx = TX_ID; 664 tx_clk = TX_CLK_ID; 665 rx = RX_ID; 666 rx_clk = RX_CLK_ID; 667 break; 668 case PHY_INTERFACE_MODE_RGMII_RXID: 669 tx = TX_ND; 670 tx_clk = TX_CLK_ND; 671 rx = RX_ID; 672 rx_clk = RX_CLK_ID; 673 break; 674 case PHY_INTERFACE_MODE_RGMII_TXID: 675 tx = TX_ID; 676 tx_clk = TX_CLK_ID; 677 rx = RX_ND; 678 rx_clk = RX_CLK_ND; 679 break; 680 default: 681 return 0; 682 } 683 684 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW, 685 FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) | 686 FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx)); 687 if (ret < 0) 688 return ret; 689 690 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW, 691 FIELD_PREP(MII_KSZ9031RN_RXD3, rx) | 692 FIELD_PREP(MII_KSZ9031RN_RXD2, rx) | 693 FIELD_PREP(MII_KSZ9031RN_RXD1, rx) | 694 FIELD_PREP(MII_KSZ9031RN_RXD0, rx)); 695 if (ret < 0) 696 return ret; 697 698 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW, 699 FIELD_PREP(MII_KSZ9031RN_TXD3, tx) | 700 FIELD_PREP(MII_KSZ9031RN_TXD2, tx) | 701 FIELD_PREP(MII_KSZ9031RN_TXD1, tx) | 702 FIELD_PREP(MII_KSZ9031RN_TXD0, tx)); 703 if (ret < 0) 704 return ret; 705 706 return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW, 707 FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) | 708 FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk)); 709 } 710 711 static int ksz9031_config_init(struct phy_device *phydev) 712 { 713 const struct device_node *of_node; 714 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"}; 715 static const char *rx_data_skews[4] = { 716 "rxd0-skew-ps", "rxd1-skew-ps", 717 "rxd2-skew-ps", "rxd3-skew-ps" 718 }; 719 static const char *tx_data_skews[4] = { 720 "txd0-skew-ps", "txd1-skew-ps", 721 "txd2-skew-ps", "txd3-skew-ps" 722 }; 723 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"}; 724 const struct device *dev_walker; 725 int result; 726 727 result = ksz9031_enable_edpd(phydev); 728 if (result < 0) 729 return result; 730 731 /* The Micrel driver has a deprecated option to place phy OF 732 * properties in the MAC node. Walk up the tree of devices to 733 * find a device with an OF node. 734 */ 735 dev_walker = &phydev->mdio.dev; 736 do { 737 of_node = dev_walker->of_node; 738 dev_walker = dev_walker->parent; 739 } while (!of_node && dev_walker); 740 741 if (of_node) { 742 bool update = false; 743 744 if (phy_interface_is_rgmii(phydev)) { 745 result = ksz9031_config_rgmii_delay(phydev); 746 if (result < 0) 747 return result; 748 } 749 750 ksz9031_of_load_skew_values(phydev, of_node, 751 MII_KSZ9031RN_CLK_PAD_SKEW, 5, 752 clk_skews, 2, &update); 753 754 ksz9031_of_load_skew_values(phydev, of_node, 755 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, 756 control_skews, 2, &update); 757 758 ksz9031_of_load_skew_values(phydev, of_node, 759 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, 760 rx_data_skews, 4, &update); 761 762 ksz9031_of_load_skew_values(phydev, of_node, 763 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, 764 tx_data_skews, 4, &update); 765 766 if (update && phydev->interface != PHY_INTERFACE_MODE_RGMII) 767 phydev_warn(phydev, 768 "*-skew-ps values should be used only with phy-mode = \"rgmii\"\n"); 769 770 /* Silicon Errata Sheet (DS80000691D or DS80000692D): 771 * When the device links in the 1000BASE-T slave mode only, 772 * the optional 125MHz reference output clock (CLK125_NDO) 773 * has wide duty cycle variation. 774 * 775 * The optional CLK125_NDO clock does not meet the RGMII 776 * 45/55 percent (min/max) duty cycle requirement and therefore 777 * cannot be used directly by the MAC side for clocking 778 * applications that have setup/hold time requirements on 779 * rising and falling clock edges. 780 * 781 * Workaround: 782 * Force the phy to be the master to receive a stable clock 783 * which meets the duty cycle requirement. 784 */ 785 if (of_property_read_bool(of_node, "micrel,force-master")) { 786 result = phy_read(phydev, MII_CTRL1000); 787 if (result < 0) 788 goto err_force_master; 789 790 /* enable master mode, config & prefer master */ 791 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER; 792 result = phy_write(phydev, MII_CTRL1000, result); 793 if (result < 0) 794 goto err_force_master; 795 } 796 } 797 798 return ksz9031_center_flp_timing(phydev); 799 800 err_force_master: 801 phydev_err(phydev, "failed to force the phy to master mode\n"); 802 return result; 803 } 804 805 #define KSZ9131_SKEW_5BIT_MAX 2400 806 #define KSZ9131_SKEW_4BIT_MAX 800 807 #define KSZ9131_OFFSET 700 808 #define KSZ9131_STEP 100 809 810 static int ksz9131_of_load_skew_values(struct phy_device *phydev, 811 struct device_node *of_node, 812 u16 reg, size_t field_sz, 813 char *field[], u8 numfields) 814 { 815 int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET), 816 -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)}; 817 int skewval, skewmax = 0; 818 int matches = 0; 819 u16 maxval; 820 u16 newval; 821 u16 mask; 822 int i; 823 824 /* psec properties in dts should mean x pico seconds */ 825 if (field_sz == 5) 826 skewmax = KSZ9131_SKEW_5BIT_MAX; 827 else 828 skewmax = KSZ9131_SKEW_4BIT_MAX; 829 830 for (i = 0; i < numfields; i++) 831 if (!of_property_read_s32(of_node, field[i], &skewval)) { 832 if (skewval < -KSZ9131_OFFSET) 833 skewval = -KSZ9131_OFFSET; 834 else if (skewval > skewmax) 835 skewval = skewmax; 836 837 val[i] = skewval + KSZ9131_OFFSET; 838 matches++; 839 } 840 841 if (!matches) 842 return 0; 843 844 if (matches < numfields) 845 newval = phy_read_mmd(phydev, 2, reg); 846 else 847 newval = 0; 848 849 maxval = (field_sz == 4) ? 0xf : 0x1f; 850 for (i = 0; i < numfields; i++) 851 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) { 852 mask = 0xffff; 853 mask ^= maxval << (field_sz * i); 854 newval = (newval & mask) | 855 (((val[i] / KSZ9131_STEP) & maxval) 856 << (field_sz * i)); 857 } 858 859 return phy_write_mmd(phydev, 2, reg, newval); 860 } 861 862 #define KSZ9131RN_MMD_COMMON_CTRL_REG 2 863 #define KSZ9131RN_RXC_DLL_CTRL 76 864 #define KSZ9131RN_TXC_DLL_CTRL 77 865 #define KSZ9131RN_DLL_CTRL_BYPASS BIT_MASK(12) 866 #define KSZ9131RN_DLL_ENABLE_DELAY 0 867 #define KSZ9131RN_DLL_DISABLE_DELAY BIT(12) 868 869 static int ksz9131_config_rgmii_delay(struct phy_device *phydev) 870 { 871 u16 rxcdll_val, txcdll_val; 872 int ret; 873 874 switch (phydev->interface) { 875 case PHY_INTERFACE_MODE_RGMII: 876 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY; 877 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY; 878 break; 879 case PHY_INTERFACE_MODE_RGMII_ID: 880 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; 881 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; 882 break; 883 case PHY_INTERFACE_MODE_RGMII_RXID: 884 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; 885 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY; 886 break; 887 case PHY_INTERFACE_MODE_RGMII_TXID: 888 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY; 889 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; 890 break; 891 default: 892 return 0; 893 } 894 895 ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, 896 KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS, 897 rxcdll_val); 898 if (ret < 0) 899 return ret; 900 901 return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, 902 KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS, 903 txcdll_val); 904 } 905 906 static int ksz9131_config_init(struct phy_device *phydev) 907 { 908 struct device_node *of_node; 909 char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"}; 910 char *rx_data_skews[4] = { 911 "rxd0-skew-psec", "rxd1-skew-psec", 912 "rxd2-skew-psec", "rxd3-skew-psec" 913 }; 914 char *tx_data_skews[4] = { 915 "txd0-skew-psec", "txd1-skew-psec", 916 "txd2-skew-psec", "txd3-skew-psec" 917 }; 918 char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"}; 919 const struct device *dev_walker; 920 int ret; 921 922 dev_walker = &phydev->mdio.dev; 923 do { 924 of_node = dev_walker->of_node; 925 dev_walker = dev_walker->parent; 926 } while (!of_node && dev_walker); 927 928 if (!of_node) 929 return 0; 930 931 if (phy_interface_is_rgmii(phydev)) { 932 ret = ksz9131_config_rgmii_delay(phydev); 933 if (ret < 0) 934 return ret; 935 } 936 937 ret = ksz9131_of_load_skew_values(phydev, of_node, 938 MII_KSZ9031RN_CLK_PAD_SKEW, 5, 939 clk_skews, 2); 940 if (ret < 0) 941 return ret; 942 943 ret = ksz9131_of_load_skew_values(phydev, of_node, 944 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, 945 control_skews, 2); 946 if (ret < 0) 947 return ret; 948 949 ret = ksz9131_of_load_skew_values(phydev, of_node, 950 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, 951 rx_data_skews, 4); 952 if (ret < 0) 953 return ret; 954 955 ret = ksz9131_of_load_skew_values(phydev, of_node, 956 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, 957 tx_data_skews, 4); 958 if (ret < 0) 959 return ret; 960 961 return 0; 962 } 963 964 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06 965 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6) 966 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4) 967 static int ksz8873mll_read_status(struct phy_device *phydev) 968 { 969 int regval; 970 971 /* dummy read */ 972 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 973 974 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 975 976 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX) 977 phydev->duplex = DUPLEX_HALF; 978 else 979 phydev->duplex = DUPLEX_FULL; 980 981 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED) 982 phydev->speed = SPEED_10; 983 else 984 phydev->speed = SPEED_100; 985 986 phydev->link = 1; 987 phydev->pause = phydev->asym_pause = 0; 988 989 return 0; 990 } 991 992 static int ksz9031_get_features(struct phy_device *phydev) 993 { 994 int ret; 995 996 ret = genphy_read_abilities(phydev); 997 if (ret < 0) 998 return ret; 999 1000 /* Silicon Errata Sheet (DS80000691D or DS80000692D): 1001 * Whenever the device's Asymmetric Pause capability is set to 1, 1002 * link-up may fail after a link-up to link-down transition. 1003 * 1004 * The Errata Sheet is for ksz9031, but ksz9021 has the same issue 1005 * 1006 * Workaround: 1007 * Do not enable the Asymmetric Pause capability bit. 1008 */ 1009 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported); 1010 1011 /* We force setting the Pause capability as the core will force the 1012 * Asymmetric Pause capability to 1 otherwise. 1013 */ 1014 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported); 1015 1016 return 0; 1017 } 1018 1019 static int ksz9031_read_status(struct phy_device *phydev) 1020 { 1021 int err; 1022 int regval; 1023 1024 err = genphy_read_status(phydev); 1025 if (err) 1026 return err; 1027 1028 /* Make sure the PHY is not broken. Read idle error count, 1029 * and reset the PHY if it is maxed out. 1030 */ 1031 regval = phy_read(phydev, MII_STAT1000); 1032 if ((regval & 0xFF) == 0xFF) { 1033 phy_init_hw(phydev); 1034 phydev->link = 0; 1035 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev)) 1036 phydev->drv->config_intr(phydev); 1037 return genphy_config_aneg(phydev); 1038 } 1039 1040 return 0; 1041 } 1042 1043 static int ksz8873mll_config_aneg(struct phy_device *phydev) 1044 { 1045 return 0; 1046 } 1047 1048 static int ksz886x_config_mdix(struct phy_device *phydev, u8 ctrl) 1049 { 1050 u16 val; 1051 1052 switch (ctrl) { 1053 case ETH_TP_MDI: 1054 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX; 1055 break; 1056 case ETH_TP_MDI_X: 1057 /* Note: The naming of the bit KSZ886X_BMCR_FORCE_MDI is bit 1058 * counter intuitive, the "-X" in "1 = Force MDI" in the data 1059 * sheet seems to be missing: 1060 * 1 = Force MDI (sic!) (transmit on RX+/RX- pins) 1061 * 0 = Normal operation (transmit on TX+/TX- pins) 1062 */ 1063 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX | KSZ886X_BMCR_FORCE_MDI; 1064 break; 1065 case ETH_TP_MDI_AUTO: 1066 val = 0; 1067 break; 1068 default: 1069 return 0; 1070 } 1071 1072 return phy_modify(phydev, MII_BMCR, 1073 KSZ886X_BMCR_HP_MDIX | KSZ886X_BMCR_FORCE_MDI | 1074 KSZ886X_BMCR_DISABLE_AUTO_MDIX, 1075 KSZ886X_BMCR_HP_MDIX | val); 1076 } 1077 1078 static int ksz886x_config_aneg(struct phy_device *phydev) 1079 { 1080 int ret; 1081 1082 ret = genphy_config_aneg(phydev); 1083 if (ret) 1084 return ret; 1085 1086 /* The MDI-X configuration is automatically changed by the PHY after 1087 * switching from autoneg off to on. So, take MDI-X configuration under 1088 * own control and set it after autoneg configuration was done. 1089 */ 1090 return ksz886x_config_mdix(phydev, phydev->mdix_ctrl); 1091 } 1092 1093 static int ksz886x_mdix_update(struct phy_device *phydev) 1094 { 1095 int ret; 1096 1097 ret = phy_read(phydev, MII_BMCR); 1098 if (ret < 0) 1099 return ret; 1100 1101 if (ret & KSZ886X_BMCR_DISABLE_AUTO_MDIX) { 1102 if (ret & KSZ886X_BMCR_FORCE_MDI) 1103 phydev->mdix_ctrl = ETH_TP_MDI_X; 1104 else 1105 phydev->mdix_ctrl = ETH_TP_MDI; 1106 } else { 1107 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 1108 } 1109 1110 ret = phy_read(phydev, MII_KSZPHY_CTRL); 1111 if (ret < 0) 1112 return ret; 1113 1114 /* Same reverse logic as KSZ886X_BMCR_FORCE_MDI */ 1115 if (ret & KSZ886X_CTRL_MDIX_STAT) 1116 phydev->mdix = ETH_TP_MDI_X; 1117 else 1118 phydev->mdix = ETH_TP_MDI; 1119 1120 return 0; 1121 } 1122 1123 static int ksz886x_read_status(struct phy_device *phydev) 1124 { 1125 int ret; 1126 1127 ret = ksz886x_mdix_update(phydev); 1128 if (ret < 0) 1129 return ret; 1130 1131 return genphy_read_status(phydev); 1132 } 1133 1134 static int kszphy_get_sset_count(struct phy_device *phydev) 1135 { 1136 return ARRAY_SIZE(kszphy_hw_stats); 1137 } 1138 1139 static void kszphy_get_strings(struct phy_device *phydev, u8 *data) 1140 { 1141 int i; 1142 1143 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) { 1144 strlcpy(data + i * ETH_GSTRING_LEN, 1145 kszphy_hw_stats[i].string, ETH_GSTRING_LEN); 1146 } 1147 } 1148 1149 static u64 kszphy_get_stat(struct phy_device *phydev, int i) 1150 { 1151 struct kszphy_hw_stat stat = kszphy_hw_stats[i]; 1152 struct kszphy_priv *priv = phydev->priv; 1153 int val; 1154 u64 ret; 1155 1156 val = phy_read(phydev, stat.reg); 1157 if (val < 0) { 1158 ret = U64_MAX; 1159 } else { 1160 val = val & ((1 << stat.bits) - 1); 1161 priv->stats[i] += val; 1162 ret = priv->stats[i]; 1163 } 1164 1165 return ret; 1166 } 1167 1168 static void kszphy_get_stats(struct phy_device *phydev, 1169 struct ethtool_stats *stats, u64 *data) 1170 { 1171 int i; 1172 1173 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) 1174 data[i] = kszphy_get_stat(phydev, i); 1175 } 1176 1177 static int kszphy_suspend(struct phy_device *phydev) 1178 { 1179 /* Disable PHY Interrupts */ 1180 if (phy_interrupt_is_valid(phydev)) { 1181 phydev->interrupts = PHY_INTERRUPT_DISABLED; 1182 if (phydev->drv->config_intr) 1183 phydev->drv->config_intr(phydev); 1184 } 1185 1186 return genphy_suspend(phydev); 1187 } 1188 1189 static int kszphy_resume(struct phy_device *phydev) 1190 { 1191 int ret; 1192 1193 genphy_resume(phydev); 1194 1195 /* After switching from power-down to normal mode, an internal global 1196 * reset is automatically generated. Wait a minimum of 1 ms before 1197 * read/write access to the PHY registers. 1198 */ 1199 usleep_range(1000, 2000); 1200 1201 ret = kszphy_config_reset(phydev); 1202 if (ret) 1203 return ret; 1204 1205 /* Enable PHY Interrupts */ 1206 if (phy_interrupt_is_valid(phydev)) { 1207 phydev->interrupts = PHY_INTERRUPT_ENABLED; 1208 if (phydev->drv->config_intr) 1209 phydev->drv->config_intr(phydev); 1210 } 1211 1212 return 0; 1213 } 1214 1215 static int kszphy_probe(struct phy_device *phydev) 1216 { 1217 const struct kszphy_type *type = phydev->drv->driver_data; 1218 const struct device_node *np = phydev->mdio.dev.of_node; 1219 struct kszphy_priv *priv; 1220 struct clk *clk; 1221 int ret; 1222 1223 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 1224 if (!priv) 1225 return -ENOMEM; 1226 1227 phydev->priv = priv; 1228 1229 priv->type = type; 1230 1231 if (type->led_mode_reg) { 1232 ret = of_property_read_u32(np, "micrel,led-mode", 1233 &priv->led_mode); 1234 if (ret) 1235 priv->led_mode = -1; 1236 1237 if (priv->led_mode > 3) { 1238 phydev_err(phydev, "invalid led mode: 0x%02x\n", 1239 priv->led_mode); 1240 priv->led_mode = -1; 1241 } 1242 } else { 1243 priv->led_mode = -1; 1244 } 1245 1246 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref"); 1247 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */ 1248 if (!IS_ERR_OR_NULL(clk)) { 1249 unsigned long rate = clk_get_rate(clk); 1250 bool rmii_ref_clk_sel_25_mhz; 1251 1252 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel; 1253 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np, 1254 "micrel,rmii-reference-clock-select-25-mhz"); 1255 1256 if (rate > 24500000 && rate < 25500000) { 1257 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz; 1258 } else if (rate > 49500000 && rate < 50500000) { 1259 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz; 1260 } else { 1261 phydev_err(phydev, "Clock rate out of range: %ld\n", 1262 rate); 1263 return -EINVAL; 1264 } 1265 } 1266 1267 if (ksz8041_fiber_mode(phydev)) 1268 phydev->port = PORT_FIBRE; 1269 1270 /* Support legacy board-file configuration */ 1271 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) { 1272 priv->rmii_ref_clk_sel = true; 1273 priv->rmii_ref_clk_sel_val = true; 1274 } 1275 1276 return 0; 1277 } 1278 1279 static struct phy_driver ksphy_driver[] = { 1280 { 1281 .phy_id = PHY_ID_KS8737, 1282 .phy_id_mask = MICREL_PHY_ID_MASK, 1283 .name = "Micrel KS8737", 1284 /* PHY_BASIC_FEATURES */ 1285 .driver_data = &ks8737_type, 1286 .config_init = kszphy_config_init, 1287 .config_intr = kszphy_config_intr, 1288 .handle_interrupt = kszphy_handle_interrupt, 1289 .suspend = genphy_suspend, 1290 .resume = genphy_resume, 1291 }, { 1292 .phy_id = PHY_ID_KSZ8021, 1293 .phy_id_mask = 0x00ffffff, 1294 .name = "Micrel KSZ8021 or KSZ8031", 1295 /* PHY_BASIC_FEATURES */ 1296 .driver_data = &ksz8021_type, 1297 .probe = kszphy_probe, 1298 .config_init = kszphy_config_init, 1299 .config_intr = kszphy_config_intr, 1300 .handle_interrupt = kszphy_handle_interrupt, 1301 .get_sset_count = kszphy_get_sset_count, 1302 .get_strings = kszphy_get_strings, 1303 .get_stats = kszphy_get_stats, 1304 .suspend = genphy_suspend, 1305 .resume = genphy_resume, 1306 }, { 1307 .phy_id = PHY_ID_KSZ8031, 1308 .phy_id_mask = 0x00ffffff, 1309 .name = "Micrel KSZ8031", 1310 /* PHY_BASIC_FEATURES */ 1311 .driver_data = &ksz8021_type, 1312 .probe = kszphy_probe, 1313 .config_init = kszphy_config_init, 1314 .config_intr = kszphy_config_intr, 1315 .handle_interrupt = kszphy_handle_interrupt, 1316 .get_sset_count = kszphy_get_sset_count, 1317 .get_strings = kszphy_get_strings, 1318 .get_stats = kszphy_get_stats, 1319 .suspend = genphy_suspend, 1320 .resume = genphy_resume, 1321 }, { 1322 .phy_id = PHY_ID_KSZ8041, 1323 .phy_id_mask = MICREL_PHY_ID_MASK, 1324 .name = "Micrel KSZ8041", 1325 /* PHY_BASIC_FEATURES */ 1326 .driver_data = &ksz8041_type, 1327 .probe = kszphy_probe, 1328 .config_init = ksz8041_config_init, 1329 .config_aneg = ksz8041_config_aneg, 1330 .config_intr = kszphy_config_intr, 1331 .handle_interrupt = kszphy_handle_interrupt, 1332 .get_sset_count = kszphy_get_sset_count, 1333 .get_strings = kszphy_get_strings, 1334 .get_stats = kszphy_get_stats, 1335 .suspend = genphy_suspend, 1336 .resume = genphy_resume, 1337 }, { 1338 .phy_id = PHY_ID_KSZ8041RNLI, 1339 .phy_id_mask = MICREL_PHY_ID_MASK, 1340 .name = "Micrel KSZ8041RNLI", 1341 /* PHY_BASIC_FEATURES */ 1342 .driver_data = &ksz8041_type, 1343 .probe = kszphy_probe, 1344 .config_init = kszphy_config_init, 1345 .config_intr = kszphy_config_intr, 1346 .handle_interrupt = kszphy_handle_interrupt, 1347 .get_sset_count = kszphy_get_sset_count, 1348 .get_strings = kszphy_get_strings, 1349 .get_stats = kszphy_get_stats, 1350 .suspend = genphy_suspend, 1351 .resume = genphy_resume, 1352 }, { 1353 .name = "Micrel KSZ8051", 1354 /* PHY_BASIC_FEATURES */ 1355 .driver_data = &ksz8051_type, 1356 .probe = kszphy_probe, 1357 .config_init = kszphy_config_init, 1358 .config_intr = kszphy_config_intr, 1359 .handle_interrupt = kszphy_handle_interrupt, 1360 .get_sset_count = kszphy_get_sset_count, 1361 .get_strings = kszphy_get_strings, 1362 .get_stats = kszphy_get_stats, 1363 .match_phy_device = ksz8051_match_phy_device, 1364 .suspend = genphy_suspend, 1365 .resume = genphy_resume, 1366 }, { 1367 .phy_id = PHY_ID_KSZ8001, 1368 .name = "Micrel KSZ8001 or KS8721", 1369 .phy_id_mask = 0x00fffffc, 1370 /* PHY_BASIC_FEATURES */ 1371 .driver_data = &ksz8041_type, 1372 .probe = kszphy_probe, 1373 .config_init = kszphy_config_init, 1374 .config_intr = kszphy_config_intr, 1375 .handle_interrupt = kszphy_handle_interrupt, 1376 .get_sset_count = kszphy_get_sset_count, 1377 .get_strings = kszphy_get_strings, 1378 .get_stats = kszphy_get_stats, 1379 .suspend = genphy_suspend, 1380 .resume = genphy_resume, 1381 }, { 1382 .phy_id = PHY_ID_KSZ8081, 1383 .name = "Micrel KSZ8081 or KSZ8091", 1384 .phy_id_mask = MICREL_PHY_ID_MASK, 1385 /* PHY_BASIC_FEATURES */ 1386 .driver_data = &ksz8081_type, 1387 .probe = kszphy_probe, 1388 .config_init = ksz8081_config_init, 1389 .soft_reset = genphy_soft_reset, 1390 .config_intr = kszphy_config_intr, 1391 .handle_interrupt = kszphy_handle_interrupt, 1392 .get_sset_count = kszphy_get_sset_count, 1393 .get_strings = kszphy_get_strings, 1394 .get_stats = kszphy_get_stats, 1395 .suspend = kszphy_suspend, 1396 .resume = kszphy_resume, 1397 }, { 1398 .phy_id = PHY_ID_KSZ8061, 1399 .name = "Micrel KSZ8061", 1400 .phy_id_mask = MICREL_PHY_ID_MASK, 1401 /* PHY_BASIC_FEATURES */ 1402 .config_init = ksz8061_config_init, 1403 .config_intr = kszphy_config_intr, 1404 .handle_interrupt = kszphy_handle_interrupt, 1405 .suspend = genphy_suspend, 1406 .resume = genphy_resume, 1407 }, { 1408 .phy_id = PHY_ID_KSZ9021, 1409 .phy_id_mask = 0x000ffffe, 1410 .name = "Micrel KSZ9021 Gigabit PHY", 1411 /* PHY_GBIT_FEATURES */ 1412 .driver_data = &ksz9021_type, 1413 .probe = kszphy_probe, 1414 .get_features = ksz9031_get_features, 1415 .config_init = ksz9021_config_init, 1416 .config_intr = kszphy_config_intr, 1417 .handle_interrupt = kszphy_handle_interrupt, 1418 .get_sset_count = kszphy_get_sset_count, 1419 .get_strings = kszphy_get_strings, 1420 .get_stats = kszphy_get_stats, 1421 .suspend = genphy_suspend, 1422 .resume = genphy_resume, 1423 .read_mmd = genphy_read_mmd_unsupported, 1424 .write_mmd = genphy_write_mmd_unsupported, 1425 }, { 1426 .phy_id = PHY_ID_KSZ9031, 1427 .phy_id_mask = MICREL_PHY_ID_MASK, 1428 .name = "Micrel KSZ9031 Gigabit PHY", 1429 .driver_data = &ksz9021_type, 1430 .probe = kszphy_probe, 1431 .get_features = ksz9031_get_features, 1432 .config_init = ksz9031_config_init, 1433 .soft_reset = genphy_soft_reset, 1434 .read_status = ksz9031_read_status, 1435 .config_intr = kszphy_config_intr, 1436 .handle_interrupt = kszphy_handle_interrupt, 1437 .get_sset_count = kszphy_get_sset_count, 1438 .get_strings = kszphy_get_strings, 1439 .get_stats = kszphy_get_stats, 1440 .suspend = genphy_suspend, 1441 .resume = kszphy_resume, 1442 }, { 1443 .phy_id = PHY_ID_LAN8814, 1444 .phy_id_mask = MICREL_PHY_ID_MASK, 1445 .name = "Microchip INDY Gigabit Quad PHY", 1446 .driver_data = &ksz9021_type, 1447 .probe = kszphy_probe, 1448 .soft_reset = genphy_soft_reset, 1449 .read_status = ksz9031_read_status, 1450 .get_sset_count = kszphy_get_sset_count, 1451 .get_strings = kszphy_get_strings, 1452 .get_stats = kszphy_get_stats, 1453 .suspend = genphy_suspend, 1454 .resume = kszphy_resume, 1455 }, { 1456 .phy_id = PHY_ID_KSZ9131, 1457 .phy_id_mask = MICREL_PHY_ID_MASK, 1458 .name = "Microchip KSZ9131 Gigabit PHY", 1459 /* PHY_GBIT_FEATURES */ 1460 .driver_data = &ksz9021_type, 1461 .probe = kszphy_probe, 1462 .config_init = ksz9131_config_init, 1463 .config_intr = kszphy_config_intr, 1464 .handle_interrupt = kszphy_handle_interrupt, 1465 .get_sset_count = kszphy_get_sset_count, 1466 .get_strings = kszphy_get_strings, 1467 .get_stats = kszphy_get_stats, 1468 .suspend = genphy_suspend, 1469 .resume = kszphy_resume, 1470 }, { 1471 .phy_id = PHY_ID_KSZ8873MLL, 1472 .phy_id_mask = MICREL_PHY_ID_MASK, 1473 .name = "Micrel KSZ8873MLL Switch", 1474 /* PHY_BASIC_FEATURES */ 1475 .config_init = kszphy_config_init, 1476 .config_aneg = ksz8873mll_config_aneg, 1477 .read_status = ksz8873mll_read_status, 1478 .suspend = genphy_suspend, 1479 .resume = genphy_resume, 1480 }, { 1481 .phy_id = PHY_ID_KSZ886X, 1482 .phy_id_mask = MICREL_PHY_ID_MASK, 1483 .name = "Micrel KSZ8851 Ethernet MAC or KSZ886X Switch", 1484 /* PHY_BASIC_FEATURES */ 1485 .config_init = kszphy_config_init, 1486 .config_aneg = ksz886x_config_aneg, 1487 .read_status = ksz886x_read_status, 1488 .suspend = genphy_suspend, 1489 .resume = genphy_resume, 1490 }, { 1491 .name = "Micrel KSZ87XX Switch", 1492 /* PHY_BASIC_FEATURES */ 1493 .config_init = kszphy_config_init, 1494 .config_aneg = ksz8873mll_config_aneg, 1495 .read_status = ksz8873mll_read_status, 1496 .match_phy_device = ksz8795_match_phy_device, 1497 .suspend = genphy_suspend, 1498 .resume = genphy_resume, 1499 }, { 1500 .phy_id = PHY_ID_KSZ9477, 1501 .phy_id_mask = MICREL_PHY_ID_MASK, 1502 .name = "Microchip KSZ9477", 1503 /* PHY_GBIT_FEATURES */ 1504 .config_init = kszphy_config_init, 1505 .suspend = genphy_suspend, 1506 .resume = genphy_resume, 1507 } }; 1508 1509 module_phy_driver(ksphy_driver); 1510 1511 MODULE_DESCRIPTION("Micrel PHY driver"); 1512 MODULE_AUTHOR("David J. Choi"); 1513 MODULE_LICENSE("GPL"); 1514 1515 static struct mdio_device_id __maybe_unused micrel_tbl[] = { 1516 { PHY_ID_KSZ9021, 0x000ffffe }, 1517 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK }, 1518 { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK }, 1519 { PHY_ID_KSZ8001, 0x00fffffc }, 1520 { PHY_ID_KS8737, MICREL_PHY_ID_MASK }, 1521 { PHY_ID_KSZ8021, 0x00ffffff }, 1522 { PHY_ID_KSZ8031, 0x00ffffff }, 1523 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK }, 1524 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK }, 1525 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK }, 1526 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK }, 1527 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK }, 1528 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK }, 1529 { PHY_ID_LAN8814, MICREL_PHY_ID_MASK }, 1530 { } 1531 }; 1532 1533 MODULE_DEVICE_TABLE(mdio, micrel_tbl); 1534