1 /* 2 * drivers/net/phy/micrel.c 3 * 4 * Driver for Micrel PHYs 5 * 6 * Author: David J. Choi 7 * 8 * Copyright (c) 2010-2013 Micrel, Inc. 9 * Copyright (c) 2014 Johan Hovold <johan@kernel.org> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * Support : Micrel Phys: 17 * Giga phys: ksz9021, ksz9031 18 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041 19 * ksz8021, ksz8031, ksz8051, 20 * ksz8081, ksz8091, 21 * ksz8061, 22 * Switch : ksz8873, ksz886x 23 * ksz9477 24 */ 25 26 #include <linux/kernel.h> 27 #include <linux/module.h> 28 #include <linux/phy.h> 29 #include <linux/micrel_phy.h> 30 #include <linux/of.h> 31 #include <linux/clk.h> 32 33 /* Operation Mode Strap Override */ 34 #define MII_KSZPHY_OMSO 0x16 35 #define KSZPHY_OMSO_B_CAST_OFF BIT(9) 36 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5) 37 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1) 38 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0) 39 40 /* general Interrupt control/status reg in vendor specific block. */ 41 #define MII_KSZPHY_INTCS 0x1B 42 #define KSZPHY_INTCS_JABBER BIT(15) 43 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14) 44 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13) 45 #define KSZPHY_INTCS_PARELLEL BIT(12) 46 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11) 47 #define KSZPHY_INTCS_LINK_DOWN BIT(10) 48 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9) 49 #define KSZPHY_INTCS_LINK_UP BIT(8) 50 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\ 51 KSZPHY_INTCS_LINK_DOWN) 52 53 /* PHY Control 1 */ 54 #define MII_KSZPHY_CTRL_1 0x1e 55 56 /* PHY Control 2 / PHY Control (if no PHY Control 1) */ 57 #define MII_KSZPHY_CTRL_2 0x1f 58 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2 59 /* bitmap of PHY register to set interrupt mode */ 60 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9) 61 #define KSZPHY_RMII_REF_CLK_SEL BIT(7) 62 63 /* Write/read to/from extended registers */ 64 #define MII_KSZPHY_EXTREG 0x0b 65 #define KSZPHY_EXTREG_WRITE 0x8000 66 67 #define MII_KSZPHY_EXTREG_WRITE 0x0c 68 #define MII_KSZPHY_EXTREG_READ 0x0d 69 70 /* Extended registers */ 71 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104 72 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105 73 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106 74 75 #define PS_TO_REG 200 76 77 struct kszphy_hw_stat { 78 const char *string; 79 u8 reg; 80 u8 bits; 81 }; 82 83 static struct kszphy_hw_stat kszphy_hw_stats[] = { 84 { "phy_receive_errors", 21, 16}, 85 { "phy_idle_errors", 10, 8 }, 86 }; 87 88 struct kszphy_type { 89 u32 led_mode_reg; 90 u16 interrupt_level_mask; 91 bool has_broadcast_disable; 92 bool has_nand_tree_disable; 93 bool has_rmii_ref_clk_sel; 94 }; 95 96 struct kszphy_priv { 97 const struct kszphy_type *type; 98 int led_mode; 99 bool rmii_ref_clk_sel; 100 bool rmii_ref_clk_sel_val; 101 u64 stats[ARRAY_SIZE(kszphy_hw_stats)]; 102 }; 103 104 static const struct kszphy_type ksz8021_type = { 105 .led_mode_reg = MII_KSZPHY_CTRL_2, 106 .has_broadcast_disable = true, 107 .has_nand_tree_disable = true, 108 .has_rmii_ref_clk_sel = true, 109 }; 110 111 static const struct kszphy_type ksz8041_type = { 112 .led_mode_reg = MII_KSZPHY_CTRL_1, 113 }; 114 115 static const struct kszphy_type ksz8051_type = { 116 .led_mode_reg = MII_KSZPHY_CTRL_2, 117 .has_nand_tree_disable = true, 118 }; 119 120 static const struct kszphy_type ksz8081_type = { 121 .led_mode_reg = MII_KSZPHY_CTRL_2, 122 .has_broadcast_disable = true, 123 .has_nand_tree_disable = true, 124 .has_rmii_ref_clk_sel = true, 125 }; 126 127 static const struct kszphy_type ks8737_type = { 128 .interrupt_level_mask = BIT(14), 129 }; 130 131 static const struct kszphy_type ksz9021_type = { 132 .interrupt_level_mask = BIT(14), 133 }; 134 135 static int kszphy_extended_write(struct phy_device *phydev, 136 u32 regnum, u16 val) 137 { 138 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum); 139 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); 140 } 141 142 static int kszphy_extended_read(struct phy_device *phydev, 143 u32 regnum) 144 { 145 phy_write(phydev, MII_KSZPHY_EXTREG, regnum); 146 return phy_read(phydev, MII_KSZPHY_EXTREG_READ); 147 } 148 149 static int kszphy_ack_interrupt(struct phy_device *phydev) 150 { 151 /* bit[7..0] int status, which is a read and clear register. */ 152 int rc; 153 154 rc = phy_read(phydev, MII_KSZPHY_INTCS); 155 156 return (rc < 0) ? rc : 0; 157 } 158 159 static int kszphy_config_intr(struct phy_device *phydev) 160 { 161 const struct kszphy_type *type = phydev->drv->driver_data; 162 int temp; 163 u16 mask; 164 165 if (type && type->interrupt_level_mask) 166 mask = type->interrupt_level_mask; 167 else 168 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH; 169 170 /* set the interrupt pin active low */ 171 temp = phy_read(phydev, MII_KSZPHY_CTRL); 172 if (temp < 0) 173 return temp; 174 temp &= ~mask; 175 phy_write(phydev, MII_KSZPHY_CTRL, temp); 176 177 /* enable / disable interrupts */ 178 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 179 temp = KSZPHY_INTCS_ALL; 180 else 181 temp = 0; 182 183 return phy_write(phydev, MII_KSZPHY_INTCS, temp); 184 } 185 186 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val) 187 { 188 int ctrl; 189 190 ctrl = phy_read(phydev, MII_KSZPHY_CTRL); 191 if (ctrl < 0) 192 return ctrl; 193 194 if (val) 195 ctrl |= KSZPHY_RMII_REF_CLK_SEL; 196 else 197 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL; 198 199 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl); 200 } 201 202 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val) 203 { 204 int rc, temp, shift; 205 206 switch (reg) { 207 case MII_KSZPHY_CTRL_1: 208 shift = 14; 209 break; 210 case MII_KSZPHY_CTRL_2: 211 shift = 4; 212 break; 213 default: 214 return -EINVAL; 215 } 216 217 temp = phy_read(phydev, reg); 218 if (temp < 0) { 219 rc = temp; 220 goto out; 221 } 222 223 temp &= ~(3 << shift); 224 temp |= val << shift; 225 rc = phy_write(phydev, reg, temp); 226 out: 227 if (rc < 0) 228 phydev_err(phydev, "failed to set led mode\n"); 229 230 return rc; 231 } 232 233 /* Disable PHY address 0 as the broadcast address, so that it can be used as a 234 * unique (non-broadcast) address on a shared bus. 235 */ 236 static int kszphy_broadcast_disable(struct phy_device *phydev) 237 { 238 int ret; 239 240 ret = phy_read(phydev, MII_KSZPHY_OMSO); 241 if (ret < 0) 242 goto out; 243 244 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF); 245 out: 246 if (ret) 247 phydev_err(phydev, "failed to disable broadcast address\n"); 248 249 return ret; 250 } 251 252 static int kszphy_nand_tree_disable(struct phy_device *phydev) 253 { 254 int ret; 255 256 ret = phy_read(phydev, MII_KSZPHY_OMSO); 257 if (ret < 0) 258 goto out; 259 260 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON)) 261 return 0; 262 263 ret = phy_write(phydev, MII_KSZPHY_OMSO, 264 ret & ~KSZPHY_OMSO_NAND_TREE_ON); 265 out: 266 if (ret) 267 phydev_err(phydev, "failed to disable NAND tree mode\n"); 268 269 return ret; 270 } 271 272 /* Some config bits need to be set again on resume, handle them here. */ 273 static int kszphy_config_reset(struct phy_device *phydev) 274 { 275 struct kszphy_priv *priv = phydev->priv; 276 int ret; 277 278 if (priv->rmii_ref_clk_sel) { 279 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val); 280 if (ret) { 281 phydev_err(phydev, 282 "failed to set rmii reference clock\n"); 283 return ret; 284 } 285 } 286 287 if (priv->led_mode >= 0) 288 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode); 289 290 return 0; 291 } 292 293 static int kszphy_config_init(struct phy_device *phydev) 294 { 295 struct kszphy_priv *priv = phydev->priv; 296 const struct kszphy_type *type; 297 298 if (!priv) 299 return 0; 300 301 type = priv->type; 302 303 if (type->has_broadcast_disable) 304 kszphy_broadcast_disable(phydev); 305 306 if (type->has_nand_tree_disable) 307 kszphy_nand_tree_disable(phydev); 308 309 return kszphy_config_reset(phydev); 310 } 311 312 static int ksz8041_config_init(struct phy_device *phydev) 313 { 314 struct device_node *of_node = phydev->mdio.dev.of_node; 315 316 /* Limit supported and advertised modes in fiber mode */ 317 if (of_property_read_bool(of_node, "micrel,fiber-mode")) { 318 phydev->dev_flags |= MICREL_PHY_FXEN; 319 phydev->supported &= SUPPORTED_100baseT_Full | 320 SUPPORTED_100baseT_Half; 321 phydev->supported |= SUPPORTED_FIBRE; 322 phydev->advertising &= ADVERTISED_100baseT_Full | 323 ADVERTISED_100baseT_Half; 324 phydev->advertising |= ADVERTISED_FIBRE; 325 phydev->autoneg = AUTONEG_DISABLE; 326 } 327 328 return kszphy_config_init(phydev); 329 } 330 331 static int ksz8041_config_aneg(struct phy_device *phydev) 332 { 333 /* Skip auto-negotiation in fiber mode */ 334 if (phydev->dev_flags & MICREL_PHY_FXEN) { 335 phydev->speed = SPEED_100; 336 return 0; 337 } 338 339 return genphy_config_aneg(phydev); 340 } 341 342 static int ksz9021_load_values_from_of(struct phy_device *phydev, 343 const struct device_node *of_node, 344 u16 reg, 345 const char *field1, const char *field2, 346 const char *field3, const char *field4) 347 { 348 int val1 = -1; 349 int val2 = -2; 350 int val3 = -3; 351 int val4 = -4; 352 int newval; 353 int matches = 0; 354 355 if (!of_property_read_u32(of_node, field1, &val1)) 356 matches++; 357 358 if (!of_property_read_u32(of_node, field2, &val2)) 359 matches++; 360 361 if (!of_property_read_u32(of_node, field3, &val3)) 362 matches++; 363 364 if (!of_property_read_u32(of_node, field4, &val4)) 365 matches++; 366 367 if (!matches) 368 return 0; 369 370 if (matches < 4) 371 newval = kszphy_extended_read(phydev, reg); 372 else 373 newval = 0; 374 375 if (val1 != -1) 376 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0); 377 378 if (val2 != -2) 379 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4); 380 381 if (val3 != -3) 382 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8); 383 384 if (val4 != -4) 385 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12); 386 387 return kszphy_extended_write(phydev, reg, newval); 388 } 389 390 static int ksz9021_config_init(struct phy_device *phydev) 391 { 392 const struct device *dev = &phydev->mdio.dev; 393 const struct device_node *of_node = dev->of_node; 394 const struct device *dev_walker; 395 396 /* The Micrel driver has a deprecated option to place phy OF 397 * properties in the MAC node. Walk up the tree of devices to 398 * find a device with an OF node. 399 */ 400 dev_walker = &phydev->mdio.dev; 401 do { 402 of_node = dev_walker->of_node; 403 dev_walker = dev_walker->parent; 404 405 } while (!of_node && dev_walker); 406 407 if (of_node) { 408 ksz9021_load_values_from_of(phydev, of_node, 409 MII_KSZPHY_CLK_CONTROL_PAD_SKEW, 410 "txen-skew-ps", "txc-skew-ps", 411 "rxdv-skew-ps", "rxc-skew-ps"); 412 ksz9021_load_values_from_of(phydev, of_node, 413 MII_KSZPHY_RX_DATA_PAD_SKEW, 414 "rxd0-skew-ps", "rxd1-skew-ps", 415 "rxd2-skew-ps", "rxd3-skew-ps"); 416 ksz9021_load_values_from_of(phydev, of_node, 417 MII_KSZPHY_TX_DATA_PAD_SKEW, 418 "txd0-skew-ps", "txd1-skew-ps", 419 "txd2-skew-ps", "txd3-skew-ps"); 420 } 421 return 0; 422 } 423 424 #define MII_KSZ9031RN_MMD_CTRL_REG 0x0d 425 #define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e 426 #define OP_DATA 1 427 #define KSZ9031_PS_TO_REG 60 428 429 /* Extended registers */ 430 /* MMD Address 0x0 */ 431 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3 432 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4 433 434 /* MMD Address 0x2 */ 435 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4 436 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5 437 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6 438 #define MII_KSZ9031RN_CLK_PAD_SKEW 8 439 440 /* MMD Address 0x1C */ 441 #define MII_KSZ9031RN_EDPD 0x23 442 #define MII_KSZ9031RN_EDPD_ENABLE BIT(0) 443 444 static int ksz9031_extended_write(struct phy_device *phydev, 445 u8 mode, u32 dev_addr, u32 regnum, u16 val) 446 { 447 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr); 448 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum); 449 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr); 450 return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val); 451 } 452 453 static int ksz9031_extended_read(struct phy_device *phydev, 454 u8 mode, u32 dev_addr, u32 regnum) 455 { 456 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr); 457 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum); 458 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr); 459 return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG); 460 } 461 462 static int ksz9031_of_load_skew_values(struct phy_device *phydev, 463 const struct device_node *of_node, 464 u16 reg, size_t field_sz, 465 const char *field[], u8 numfields) 466 { 467 int val[4] = {-1, -2, -3, -4}; 468 int matches = 0; 469 u16 mask; 470 u16 maxval; 471 u16 newval; 472 int i; 473 474 for (i = 0; i < numfields; i++) 475 if (!of_property_read_u32(of_node, field[i], val + i)) 476 matches++; 477 478 if (!matches) 479 return 0; 480 481 if (matches < numfields) 482 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg); 483 else 484 newval = 0; 485 486 maxval = (field_sz == 4) ? 0xf : 0x1f; 487 for (i = 0; i < numfields; i++) 488 if (val[i] != -(i + 1)) { 489 mask = 0xffff; 490 mask ^= maxval << (field_sz * i); 491 newval = (newval & mask) | 492 (((val[i] / KSZ9031_PS_TO_REG) & maxval) 493 << (field_sz * i)); 494 } 495 496 return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval); 497 } 498 499 static int ksz9031_center_flp_timing(struct phy_device *phydev) 500 { 501 int result; 502 503 /* Center KSZ9031RNX FLP timing at 16ms. */ 504 result = ksz9031_extended_write(phydev, OP_DATA, 0, 505 MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006); 506 result = ksz9031_extended_write(phydev, OP_DATA, 0, 507 MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80); 508 509 if (result) 510 return result; 511 512 return genphy_restart_aneg(phydev); 513 } 514 515 /* Enable energy-detect power-down mode */ 516 static int ksz9031_enable_edpd(struct phy_device *phydev) 517 { 518 int reg; 519 520 reg = ksz9031_extended_read(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD); 521 if (reg < 0) 522 return reg; 523 return ksz9031_extended_write(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD, 524 reg | MII_KSZ9031RN_EDPD_ENABLE); 525 } 526 527 static int ksz9031_config_init(struct phy_device *phydev) 528 { 529 const struct device *dev = &phydev->mdio.dev; 530 const struct device_node *of_node = dev->of_node; 531 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"}; 532 static const char *rx_data_skews[4] = { 533 "rxd0-skew-ps", "rxd1-skew-ps", 534 "rxd2-skew-ps", "rxd3-skew-ps" 535 }; 536 static const char *tx_data_skews[4] = { 537 "txd0-skew-ps", "txd1-skew-ps", 538 "txd2-skew-ps", "txd3-skew-ps" 539 }; 540 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"}; 541 const struct device *dev_walker; 542 int result; 543 544 result = ksz9031_enable_edpd(phydev); 545 if (result < 0) 546 return result; 547 548 /* The Micrel driver has a deprecated option to place phy OF 549 * properties in the MAC node. Walk up the tree of devices to 550 * find a device with an OF node. 551 */ 552 dev_walker = &phydev->mdio.dev; 553 do { 554 of_node = dev_walker->of_node; 555 dev_walker = dev_walker->parent; 556 } while (!of_node && dev_walker); 557 558 if (of_node) { 559 ksz9031_of_load_skew_values(phydev, of_node, 560 MII_KSZ9031RN_CLK_PAD_SKEW, 5, 561 clk_skews, 2); 562 563 ksz9031_of_load_skew_values(phydev, of_node, 564 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, 565 control_skews, 2); 566 567 ksz9031_of_load_skew_values(phydev, of_node, 568 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, 569 rx_data_skews, 4); 570 571 ksz9031_of_load_skew_values(phydev, of_node, 572 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, 573 tx_data_skews, 4); 574 } 575 576 return ksz9031_center_flp_timing(phydev); 577 } 578 579 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06 580 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6) 581 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4) 582 static int ksz8873mll_read_status(struct phy_device *phydev) 583 { 584 int regval; 585 586 /* dummy read */ 587 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 588 589 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 590 591 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX) 592 phydev->duplex = DUPLEX_HALF; 593 else 594 phydev->duplex = DUPLEX_FULL; 595 596 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED) 597 phydev->speed = SPEED_10; 598 else 599 phydev->speed = SPEED_100; 600 601 phydev->link = 1; 602 phydev->pause = phydev->asym_pause = 0; 603 604 return 0; 605 } 606 607 static int ksz9031_read_status(struct phy_device *phydev) 608 { 609 int err; 610 int regval; 611 612 err = genphy_read_status(phydev); 613 if (err) 614 return err; 615 616 /* Make sure the PHY is not broken. Read idle error count, 617 * and reset the PHY if it is maxed out. 618 */ 619 regval = phy_read(phydev, MII_STAT1000); 620 if ((regval & 0xFF) == 0xFF) { 621 phy_init_hw(phydev); 622 phydev->link = 0; 623 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev)) 624 phydev->drv->config_intr(phydev); 625 } 626 627 return 0; 628 } 629 630 static int ksz8873mll_config_aneg(struct phy_device *phydev) 631 { 632 return 0; 633 } 634 635 /* This routine returns -1 as an indication to the caller that the 636 * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE 637 * MMD extended PHY registers. 638 */ 639 static int 640 ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int devad, u16 regnum) 641 { 642 return -1; 643 } 644 645 /* This routine does nothing since the Micrel ksz9021 does not support 646 * standard IEEE MMD extended PHY registers. 647 */ 648 static int 649 ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int devad, u16 regnum, u16 val) 650 { 651 return -1; 652 } 653 654 static int kszphy_get_sset_count(struct phy_device *phydev) 655 { 656 return ARRAY_SIZE(kszphy_hw_stats); 657 } 658 659 static void kszphy_get_strings(struct phy_device *phydev, u8 *data) 660 { 661 int i; 662 663 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) { 664 memcpy(data + i * ETH_GSTRING_LEN, 665 kszphy_hw_stats[i].string, ETH_GSTRING_LEN); 666 } 667 } 668 669 #ifndef UINT64_MAX 670 #define UINT64_MAX (u64)(~((u64)0)) 671 #endif 672 static u64 kszphy_get_stat(struct phy_device *phydev, int i) 673 { 674 struct kszphy_hw_stat stat = kszphy_hw_stats[i]; 675 struct kszphy_priv *priv = phydev->priv; 676 int val; 677 u64 ret; 678 679 val = phy_read(phydev, stat.reg); 680 if (val < 0) { 681 ret = UINT64_MAX; 682 } else { 683 val = val & ((1 << stat.bits) - 1); 684 priv->stats[i] += val; 685 ret = priv->stats[i]; 686 } 687 688 return ret; 689 } 690 691 static void kszphy_get_stats(struct phy_device *phydev, 692 struct ethtool_stats *stats, u64 *data) 693 { 694 int i; 695 696 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) 697 data[i] = kszphy_get_stat(phydev, i); 698 } 699 700 static int kszphy_suspend(struct phy_device *phydev) 701 { 702 /* Disable PHY Interrupts */ 703 if (phy_interrupt_is_valid(phydev)) { 704 phydev->interrupts = PHY_INTERRUPT_DISABLED; 705 if (phydev->drv->config_intr) 706 phydev->drv->config_intr(phydev); 707 } 708 709 return genphy_suspend(phydev); 710 } 711 712 static int kszphy_resume(struct phy_device *phydev) 713 { 714 int ret; 715 716 genphy_resume(phydev); 717 718 ret = kszphy_config_reset(phydev); 719 if (ret) 720 return ret; 721 722 /* Enable PHY Interrupts */ 723 if (phy_interrupt_is_valid(phydev)) { 724 phydev->interrupts = PHY_INTERRUPT_ENABLED; 725 if (phydev->drv->config_intr) 726 phydev->drv->config_intr(phydev); 727 } 728 729 return 0; 730 } 731 732 static int kszphy_probe(struct phy_device *phydev) 733 { 734 const struct kszphy_type *type = phydev->drv->driver_data; 735 const struct device_node *np = phydev->mdio.dev.of_node; 736 struct kszphy_priv *priv; 737 struct clk *clk; 738 int ret; 739 740 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 741 if (!priv) 742 return -ENOMEM; 743 744 phydev->priv = priv; 745 746 priv->type = type; 747 748 if (type->led_mode_reg) { 749 ret = of_property_read_u32(np, "micrel,led-mode", 750 &priv->led_mode); 751 if (ret) 752 priv->led_mode = -1; 753 754 if (priv->led_mode > 3) { 755 phydev_err(phydev, "invalid led mode: 0x%02x\n", 756 priv->led_mode); 757 priv->led_mode = -1; 758 } 759 } else { 760 priv->led_mode = -1; 761 } 762 763 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref"); 764 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */ 765 if (!IS_ERR_OR_NULL(clk)) { 766 unsigned long rate = clk_get_rate(clk); 767 bool rmii_ref_clk_sel_25_mhz; 768 769 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel; 770 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np, 771 "micrel,rmii-reference-clock-select-25-mhz"); 772 773 if (rate > 24500000 && rate < 25500000) { 774 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz; 775 } else if (rate > 49500000 && rate < 50500000) { 776 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz; 777 } else { 778 phydev_err(phydev, "Clock rate out of range: %ld\n", 779 rate); 780 return -EINVAL; 781 } 782 } 783 784 /* Support legacy board-file configuration */ 785 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) { 786 priv->rmii_ref_clk_sel = true; 787 priv->rmii_ref_clk_sel_val = true; 788 } 789 790 return 0; 791 } 792 793 static struct phy_driver ksphy_driver[] = { 794 { 795 .phy_id = PHY_ID_KS8737, 796 .phy_id_mask = MICREL_PHY_ID_MASK, 797 .name = "Micrel KS8737", 798 .features = PHY_BASIC_FEATURES, 799 .flags = PHY_HAS_INTERRUPT, 800 .driver_data = &ks8737_type, 801 .config_init = kszphy_config_init, 802 .config_aneg = genphy_config_aneg, 803 .read_status = genphy_read_status, 804 .ack_interrupt = kszphy_ack_interrupt, 805 .config_intr = kszphy_config_intr, 806 .suspend = genphy_suspend, 807 .resume = genphy_resume, 808 }, { 809 .phy_id = PHY_ID_KSZ8021, 810 .phy_id_mask = 0x00ffffff, 811 .name = "Micrel KSZ8021 or KSZ8031", 812 .features = PHY_BASIC_FEATURES, 813 .flags = PHY_HAS_INTERRUPT, 814 .driver_data = &ksz8021_type, 815 .probe = kszphy_probe, 816 .config_init = kszphy_config_init, 817 .config_aneg = genphy_config_aneg, 818 .read_status = genphy_read_status, 819 .ack_interrupt = kszphy_ack_interrupt, 820 .config_intr = kszphy_config_intr, 821 .get_sset_count = kszphy_get_sset_count, 822 .get_strings = kszphy_get_strings, 823 .get_stats = kszphy_get_stats, 824 .suspend = genphy_suspend, 825 .resume = genphy_resume, 826 }, { 827 .phy_id = PHY_ID_KSZ8031, 828 .phy_id_mask = 0x00ffffff, 829 .name = "Micrel KSZ8031", 830 .features = PHY_BASIC_FEATURES, 831 .flags = PHY_HAS_INTERRUPT, 832 .driver_data = &ksz8021_type, 833 .probe = kszphy_probe, 834 .config_init = kszphy_config_init, 835 .config_aneg = genphy_config_aneg, 836 .read_status = genphy_read_status, 837 .ack_interrupt = kszphy_ack_interrupt, 838 .config_intr = kszphy_config_intr, 839 .get_sset_count = kszphy_get_sset_count, 840 .get_strings = kszphy_get_strings, 841 .get_stats = kszphy_get_stats, 842 .suspend = genphy_suspend, 843 .resume = genphy_resume, 844 }, { 845 .phy_id = PHY_ID_KSZ8041, 846 .phy_id_mask = MICREL_PHY_ID_MASK, 847 .name = "Micrel KSZ8041", 848 .features = PHY_BASIC_FEATURES, 849 .flags = PHY_HAS_INTERRUPT, 850 .driver_data = &ksz8041_type, 851 .probe = kszphy_probe, 852 .config_init = ksz8041_config_init, 853 .config_aneg = ksz8041_config_aneg, 854 .read_status = genphy_read_status, 855 .ack_interrupt = kszphy_ack_interrupt, 856 .config_intr = kszphy_config_intr, 857 .get_sset_count = kszphy_get_sset_count, 858 .get_strings = kszphy_get_strings, 859 .get_stats = kszphy_get_stats, 860 .suspend = genphy_suspend, 861 .resume = genphy_resume, 862 }, { 863 .phy_id = PHY_ID_KSZ8041RNLI, 864 .phy_id_mask = MICREL_PHY_ID_MASK, 865 .name = "Micrel KSZ8041RNLI", 866 .features = PHY_BASIC_FEATURES, 867 .flags = PHY_HAS_INTERRUPT, 868 .driver_data = &ksz8041_type, 869 .probe = kszphy_probe, 870 .config_init = kszphy_config_init, 871 .config_aneg = genphy_config_aneg, 872 .read_status = genphy_read_status, 873 .ack_interrupt = kszphy_ack_interrupt, 874 .config_intr = kszphy_config_intr, 875 .get_sset_count = kszphy_get_sset_count, 876 .get_strings = kszphy_get_strings, 877 .get_stats = kszphy_get_stats, 878 .suspend = genphy_suspend, 879 .resume = genphy_resume, 880 }, { 881 .phy_id = PHY_ID_KSZ8051, 882 .phy_id_mask = MICREL_PHY_ID_MASK, 883 .name = "Micrel KSZ8051", 884 .features = PHY_BASIC_FEATURES, 885 .flags = PHY_HAS_INTERRUPT, 886 .driver_data = &ksz8051_type, 887 .probe = kszphy_probe, 888 .config_init = kszphy_config_init, 889 .config_aneg = genphy_config_aneg, 890 .read_status = genphy_read_status, 891 .ack_interrupt = kszphy_ack_interrupt, 892 .config_intr = kszphy_config_intr, 893 .get_sset_count = kszphy_get_sset_count, 894 .get_strings = kszphy_get_strings, 895 .get_stats = kszphy_get_stats, 896 .suspend = genphy_suspend, 897 .resume = genphy_resume, 898 }, { 899 .phy_id = PHY_ID_KSZ8001, 900 .name = "Micrel KSZ8001 or KS8721", 901 .phy_id_mask = 0x00fffffc, 902 .features = PHY_BASIC_FEATURES, 903 .flags = PHY_HAS_INTERRUPT, 904 .driver_data = &ksz8041_type, 905 .probe = kszphy_probe, 906 .config_init = kszphy_config_init, 907 .config_aneg = genphy_config_aneg, 908 .read_status = genphy_read_status, 909 .ack_interrupt = kszphy_ack_interrupt, 910 .config_intr = kszphy_config_intr, 911 .get_sset_count = kszphy_get_sset_count, 912 .get_strings = kszphy_get_strings, 913 .get_stats = kszphy_get_stats, 914 .suspend = genphy_suspend, 915 .resume = genphy_resume, 916 }, { 917 .phy_id = PHY_ID_KSZ8081, 918 .name = "Micrel KSZ8081 or KSZ8091", 919 .phy_id_mask = MICREL_PHY_ID_MASK, 920 .features = PHY_BASIC_FEATURES, 921 .flags = PHY_HAS_INTERRUPT, 922 .driver_data = &ksz8081_type, 923 .probe = kszphy_probe, 924 .config_init = kszphy_config_init, 925 .config_aneg = genphy_config_aneg, 926 .read_status = genphy_read_status, 927 .ack_interrupt = kszphy_ack_interrupt, 928 .config_intr = kszphy_config_intr, 929 .get_sset_count = kszphy_get_sset_count, 930 .get_strings = kszphy_get_strings, 931 .get_stats = kszphy_get_stats, 932 .suspend = kszphy_suspend, 933 .resume = kszphy_resume, 934 }, { 935 .phy_id = PHY_ID_KSZ8061, 936 .name = "Micrel KSZ8061", 937 .phy_id_mask = MICREL_PHY_ID_MASK, 938 .features = PHY_BASIC_FEATURES, 939 .flags = PHY_HAS_INTERRUPT, 940 .config_init = kszphy_config_init, 941 .config_aneg = genphy_config_aneg, 942 .read_status = genphy_read_status, 943 .ack_interrupt = kszphy_ack_interrupt, 944 .config_intr = kszphy_config_intr, 945 .suspend = genphy_suspend, 946 .resume = genphy_resume, 947 }, { 948 .phy_id = PHY_ID_KSZ9021, 949 .phy_id_mask = 0x000ffffe, 950 .name = "Micrel KSZ9021 Gigabit PHY", 951 .features = PHY_GBIT_FEATURES, 952 .flags = PHY_HAS_INTERRUPT, 953 .driver_data = &ksz9021_type, 954 .probe = kszphy_probe, 955 .config_init = ksz9021_config_init, 956 .config_aneg = genphy_config_aneg, 957 .read_status = genphy_read_status, 958 .ack_interrupt = kszphy_ack_interrupt, 959 .config_intr = kszphy_config_intr, 960 .get_sset_count = kszphy_get_sset_count, 961 .get_strings = kszphy_get_strings, 962 .get_stats = kszphy_get_stats, 963 .suspend = genphy_suspend, 964 .resume = genphy_resume, 965 .read_mmd = ksz9021_rd_mmd_phyreg, 966 .write_mmd = ksz9021_wr_mmd_phyreg, 967 }, { 968 .phy_id = PHY_ID_KSZ9031, 969 .phy_id_mask = MICREL_PHY_ID_MASK, 970 .name = "Micrel KSZ9031 Gigabit PHY", 971 .features = PHY_GBIT_FEATURES, 972 .flags = PHY_HAS_INTERRUPT, 973 .driver_data = &ksz9021_type, 974 .probe = kszphy_probe, 975 .config_init = ksz9031_config_init, 976 .config_aneg = genphy_config_aneg, 977 .read_status = ksz9031_read_status, 978 .ack_interrupt = kszphy_ack_interrupt, 979 .config_intr = kszphy_config_intr, 980 .get_sset_count = kszphy_get_sset_count, 981 .get_strings = kszphy_get_strings, 982 .get_stats = kszphy_get_stats, 983 .suspend = genphy_suspend, 984 .resume = kszphy_resume, 985 }, { 986 .phy_id = PHY_ID_KSZ8873MLL, 987 .phy_id_mask = MICREL_PHY_ID_MASK, 988 .name = "Micrel KSZ8873MLL Switch", 989 .config_init = kszphy_config_init, 990 .config_aneg = ksz8873mll_config_aneg, 991 .read_status = ksz8873mll_read_status, 992 .suspend = genphy_suspend, 993 .resume = genphy_resume, 994 }, { 995 .phy_id = PHY_ID_KSZ886X, 996 .phy_id_mask = MICREL_PHY_ID_MASK, 997 .name = "Micrel KSZ886X Switch", 998 .features = PHY_BASIC_FEATURES, 999 .flags = PHY_HAS_INTERRUPT, 1000 .config_init = kszphy_config_init, 1001 .config_aneg = genphy_config_aneg, 1002 .read_status = genphy_read_status, 1003 .suspend = genphy_suspend, 1004 .resume = genphy_resume, 1005 }, { 1006 .phy_id = PHY_ID_KSZ8795, 1007 .phy_id_mask = MICREL_PHY_ID_MASK, 1008 .name = "Micrel KSZ8795", 1009 .features = PHY_BASIC_FEATURES, 1010 .flags = PHY_HAS_INTERRUPT, 1011 .config_init = kszphy_config_init, 1012 .config_aneg = ksz8873mll_config_aneg, 1013 .read_status = ksz8873mll_read_status, 1014 .suspend = genphy_suspend, 1015 .resume = genphy_resume, 1016 }, { 1017 .phy_id = PHY_ID_KSZ9477, 1018 .phy_id_mask = MICREL_PHY_ID_MASK, 1019 .name = "Microchip KSZ9477", 1020 .features = PHY_GBIT_FEATURES, 1021 .config_init = kszphy_config_init, 1022 .config_aneg = genphy_config_aneg, 1023 .read_status = genphy_read_status, 1024 .suspend = genphy_suspend, 1025 .resume = genphy_resume, 1026 } }; 1027 1028 module_phy_driver(ksphy_driver); 1029 1030 MODULE_DESCRIPTION("Micrel PHY driver"); 1031 MODULE_AUTHOR("David J. Choi"); 1032 MODULE_LICENSE("GPL"); 1033 1034 static struct mdio_device_id __maybe_unused micrel_tbl[] = { 1035 { PHY_ID_KSZ9021, 0x000ffffe }, 1036 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK }, 1037 { PHY_ID_KSZ8001, 0x00fffffc }, 1038 { PHY_ID_KS8737, MICREL_PHY_ID_MASK }, 1039 { PHY_ID_KSZ8021, 0x00ffffff }, 1040 { PHY_ID_KSZ8031, 0x00ffffff }, 1041 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK }, 1042 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK }, 1043 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK }, 1044 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK }, 1045 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK }, 1046 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK }, 1047 { } 1048 }; 1049 1050 MODULE_DEVICE_TABLE(mdio, micrel_tbl); 1051