1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/micrel.c 4 * 5 * Driver for Micrel PHYs 6 * 7 * Author: David J. Choi 8 * 9 * Copyright (c) 2010-2013 Micrel, Inc. 10 * Copyright (c) 2014 Johan Hovold <johan@kernel.org> 11 * 12 * Support : Micrel Phys: 13 * Giga phys: ksz9021, ksz9031, ksz9131 14 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041 15 * ksz8021, ksz8031, ksz8051, 16 * ksz8081, ksz8091, 17 * ksz8061, 18 * Switch : ksz8873, ksz886x 19 * ksz9477 20 */ 21 22 #include <linux/bitfield.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/phy.h> 26 #include <linux/micrel_phy.h> 27 #include <linux/of.h> 28 #include <linux/clk.h> 29 #include <linux/delay.h> 30 31 /* Operation Mode Strap Override */ 32 #define MII_KSZPHY_OMSO 0x16 33 #define KSZPHY_OMSO_FACTORY_TEST BIT(15) 34 #define KSZPHY_OMSO_B_CAST_OFF BIT(9) 35 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5) 36 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1) 37 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0) 38 39 /* general Interrupt control/status reg in vendor specific block. */ 40 #define MII_KSZPHY_INTCS 0x1B 41 #define KSZPHY_INTCS_JABBER BIT(15) 42 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14) 43 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13) 44 #define KSZPHY_INTCS_PARELLEL BIT(12) 45 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11) 46 #define KSZPHY_INTCS_LINK_DOWN BIT(10) 47 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9) 48 #define KSZPHY_INTCS_LINK_UP BIT(8) 49 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\ 50 KSZPHY_INTCS_LINK_DOWN) 51 #define KSZPHY_INTCS_LINK_DOWN_STATUS BIT(2) 52 #define KSZPHY_INTCS_LINK_UP_STATUS BIT(0) 53 #define KSZPHY_INTCS_STATUS (KSZPHY_INTCS_LINK_DOWN_STATUS |\ 54 KSZPHY_INTCS_LINK_UP_STATUS) 55 56 /* PHY Control 1 */ 57 #define MII_KSZPHY_CTRL_1 0x1e 58 59 /* PHY Control 2 / PHY Control (if no PHY Control 1) */ 60 #define MII_KSZPHY_CTRL_2 0x1f 61 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2 62 /* bitmap of PHY register to set interrupt mode */ 63 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9) 64 #define KSZPHY_RMII_REF_CLK_SEL BIT(7) 65 66 /* Write/read to/from extended registers */ 67 #define MII_KSZPHY_EXTREG 0x0b 68 #define KSZPHY_EXTREG_WRITE 0x8000 69 70 #define MII_KSZPHY_EXTREG_WRITE 0x0c 71 #define MII_KSZPHY_EXTREG_READ 0x0d 72 73 /* Extended registers */ 74 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104 75 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105 76 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106 77 78 #define PS_TO_REG 200 79 80 struct kszphy_hw_stat { 81 const char *string; 82 u8 reg; 83 u8 bits; 84 }; 85 86 static struct kszphy_hw_stat kszphy_hw_stats[] = { 87 { "phy_receive_errors", 21, 16}, 88 { "phy_idle_errors", 10, 8 }, 89 }; 90 91 struct kszphy_type { 92 u32 led_mode_reg; 93 u16 interrupt_level_mask; 94 bool has_broadcast_disable; 95 bool has_nand_tree_disable; 96 bool has_rmii_ref_clk_sel; 97 }; 98 99 struct kszphy_priv { 100 const struct kszphy_type *type; 101 int led_mode; 102 bool rmii_ref_clk_sel; 103 bool rmii_ref_clk_sel_val; 104 u64 stats[ARRAY_SIZE(kszphy_hw_stats)]; 105 }; 106 107 static const struct kszphy_type ksz8021_type = { 108 .led_mode_reg = MII_KSZPHY_CTRL_2, 109 .has_broadcast_disable = true, 110 .has_nand_tree_disable = true, 111 .has_rmii_ref_clk_sel = true, 112 }; 113 114 static const struct kszphy_type ksz8041_type = { 115 .led_mode_reg = MII_KSZPHY_CTRL_1, 116 }; 117 118 static const struct kszphy_type ksz8051_type = { 119 .led_mode_reg = MII_KSZPHY_CTRL_2, 120 .has_nand_tree_disable = true, 121 }; 122 123 static const struct kszphy_type ksz8081_type = { 124 .led_mode_reg = MII_KSZPHY_CTRL_2, 125 .has_broadcast_disable = true, 126 .has_nand_tree_disable = true, 127 .has_rmii_ref_clk_sel = true, 128 }; 129 130 static const struct kszphy_type ks8737_type = { 131 .interrupt_level_mask = BIT(14), 132 }; 133 134 static const struct kszphy_type ksz9021_type = { 135 .interrupt_level_mask = BIT(14), 136 }; 137 138 static int kszphy_extended_write(struct phy_device *phydev, 139 u32 regnum, u16 val) 140 { 141 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum); 142 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); 143 } 144 145 static int kszphy_extended_read(struct phy_device *phydev, 146 u32 regnum) 147 { 148 phy_write(phydev, MII_KSZPHY_EXTREG, regnum); 149 return phy_read(phydev, MII_KSZPHY_EXTREG_READ); 150 } 151 152 static int kszphy_ack_interrupt(struct phy_device *phydev) 153 { 154 /* bit[7..0] int status, which is a read and clear register. */ 155 int rc; 156 157 rc = phy_read(phydev, MII_KSZPHY_INTCS); 158 159 return (rc < 0) ? rc : 0; 160 } 161 162 static int kszphy_config_intr(struct phy_device *phydev) 163 { 164 const struct kszphy_type *type = phydev->drv->driver_data; 165 int temp, err; 166 u16 mask; 167 168 if (type && type->interrupt_level_mask) 169 mask = type->interrupt_level_mask; 170 else 171 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH; 172 173 /* set the interrupt pin active low */ 174 temp = phy_read(phydev, MII_KSZPHY_CTRL); 175 if (temp < 0) 176 return temp; 177 temp &= ~mask; 178 phy_write(phydev, MII_KSZPHY_CTRL, temp); 179 180 /* enable / disable interrupts */ 181 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 182 err = kszphy_ack_interrupt(phydev); 183 if (err) 184 return err; 185 186 temp = KSZPHY_INTCS_ALL; 187 err = phy_write(phydev, MII_KSZPHY_INTCS, temp); 188 } else { 189 temp = 0; 190 err = phy_write(phydev, MII_KSZPHY_INTCS, temp); 191 if (err) 192 return err; 193 194 err = kszphy_ack_interrupt(phydev); 195 } 196 197 return err; 198 } 199 200 static irqreturn_t kszphy_handle_interrupt(struct phy_device *phydev) 201 { 202 int irq_status; 203 204 irq_status = phy_read(phydev, MII_KSZPHY_INTCS); 205 if (irq_status < 0) { 206 phy_error(phydev); 207 return IRQ_NONE; 208 } 209 210 if (!(irq_status & KSZPHY_INTCS_STATUS)) 211 return IRQ_NONE; 212 213 phy_trigger_machine(phydev); 214 215 return IRQ_HANDLED; 216 } 217 218 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val) 219 { 220 int ctrl; 221 222 ctrl = phy_read(phydev, MII_KSZPHY_CTRL); 223 if (ctrl < 0) 224 return ctrl; 225 226 if (val) 227 ctrl |= KSZPHY_RMII_REF_CLK_SEL; 228 else 229 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL; 230 231 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl); 232 } 233 234 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val) 235 { 236 int rc, temp, shift; 237 238 switch (reg) { 239 case MII_KSZPHY_CTRL_1: 240 shift = 14; 241 break; 242 case MII_KSZPHY_CTRL_2: 243 shift = 4; 244 break; 245 default: 246 return -EINVAL; 247 } 248 249 temp = phy_read(phydev, reg); 250 if (temp < 0) { 251 rc = temp; 252 goto out; 253 } 254 255 temp &= ~(3 << shift); 256 temp |= val << shift; 257 rc = phy_write(phydev, reg, temp); 258 out: 259 if (rc < 0) 260 phydev_err(phydev, "failed to set led mode\n"); 261 262 return rc; 263 } 264 265 /* Disable PHY address 0 as the broadcast address, so that it can be used as a 266 * unique (non-broadcast) address on a shared bus. 267 */ 268 static int kszphy_broadcast_disable(struct phy_device *phydev) 269 { 270 int ret; 271 272 ret = phy_read(phydev, MII_KSZPHY_OMSO); 273 if (ret < 0) 274 goto out; 275 276 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF); 277 out: 278 if (ret) 279 phydev_err(phydev, "failed to disable broadcast address\n"); 280 281 return ret; 282 } 283 284 static int kszphy_nand_tree_disable(struct phy_device *phydev) 285 { 286 int ret; 287 288 ret = phy_read(phydev, MII_KSZPHY_OMSO); 289 if (ret < 0) 290 goto out; 291 292 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON)) 293 return 0; 294 295 ret = phy_write(phydev, MII_KSZPHY_OMSO, 296 ret & ~KSZPHY_OMSO_NAND_TREE_ON); 297 out: 298 if (ret) 299 phydev_err(phydev, "failed to disable NAND tree mode\n"); 300 301 return ret; 302 } 303 304 /* Some config bits need to be set again on resume, handle them here. */ 305 static int kszphy_config_reset(struct phy_device *phydev) 306 { 307 struct kszphy_priv *priv = phydev->priv; 308 int ret; 309 310 if (priv->rmii_ref_clk_sel) { 311 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val); 312 if (ret) { 313 phydev_err(phydev, 314 "failed to set rmii reference clock\n"); 315 return ret; 316 } 317 } 318 319 if (priv->led_mode >= 0) 320 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode); 321 322 return 0; 323 } 324 325 static int kszphy_config_init(struct phy_device *phydev) 326 { 327 struct kszphy_priv *priv = phydev->priv; 328 const struct kszphy_type *type; 329 330 if (!priv) 331 return 0; 332 333 type = priv->type; 334 335 if (type->has_broadcast_disable) 336 kszphy_broadcast_disable(phydev); 337 338 if (type->has_nand_tree_disable) 339 kszphy_nand_tree_disable(phydev); 340 341 return kszphy_config_reset(phydev); 342 } 343 344 static int ksz8041_config_init(struct phy_device *phydev) 345 { 346 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 347 348 struct device_node *of_node = phydev->mdio.dev.of_node; 349 350 /* Limit supported and advertised modes in fiber mode */ 351 if (of_property_read_bool(of_node, "micrel,fiber-mode")) { 352 phydev->dev_flags |= MICREL_PHY_FXEN; 353 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask); 354 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask); 355 356 linkmode_and(phydev->supported, phydev->supported, mask); 357 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 358 phydev->supported); 359 linkmode_and(phydev->advertising, phydev->advertising, mask); 360 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 361 phydev->advertising); 362 phydev->autoneg = AUTONEG_DISABLE; 363 } 364 365 return kszphy_config_init(phydev); 366 } 367 368 static int ksz8041_config_aneg(struct phy_device *phydev) 369 { 370 /* Skip auto-negotiation in fiber mode */ 371 if (phydev->dev_flags & MICREL_PHY_FXEN) { 372 phydev->speed = SPEED_100; 373 return 0; 374 } 375 376 return genphy_config_aneg(phydev); 377 } 378 379 static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev, 380 const u32 ksz_phy_id) 381 { 382 int ret; 383 384 if ((phydev->phy_id & MICREL_PHY_ID_MASK) != ksz_phy_id) 385 return 0; 386 387 ret = phy_read(phydev, MII_BMSR); 388 if (ret < 0) 389 return ret; 390 391 /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same 392 * exact PHY ID. However, they can be told apart by the extended 393 * capability registers presence. The KSZ8051 PHY has them while 394 * the switch does not. 395 */ 396 ret &= BMSR_ERCAP; 397 if (ksz_phy_id == PHY_ID_KSZ8051) 398 return ret; 399 else 400 return !ret; 401 } 402 403 static int ksz8051_match_phy_device(struct phy_device *phydev) 404 { 405 return ksz8051_ksz8795_match_phy_device(phydev, PHY_ID_KSZ8051); 406 } 407 408 static int ksz8081_config_init(struct phy_device *phydev) 409 { 410 /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line 411 * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a 412 * pull-down is missing, the factory test mode should be cleared by 413 * manually writing a 0. 414 */ 415 phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST); 416 417 return kszphy_config_init(phydev); 418 } 419 420 static int ksz8061_config_init(struct phy_device *phydev) 421 { 422 int ret; 423 424 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A); 425 if (ret) 426 return ret; 427 428 return kszphy_config_init(phydev); 429 } 430 431 static int ksz8795_match_phy_device(struct phy_device *phydev) 432 { 433 return ksz8051_ksz8795_match_phy_device(phydev, PHY_ID_KSZ87XX); 434 } 435 436 static int ksz9021_load_values_from_of(struct phy_device *phydev, 437 const struct device_node *of_node, 438 u16 reg, 439 const char *field1, const char *field2, 440 const char *field3, const char *field4) 441 { 442 int val1 = -1; 443 int val2 = -2; 444 int val3 = -3; 445 int val4 = -4; 446 int newval; 447 int matches = 0; 448 449 if (!of_property_read_u32(of_node, field1, &val1)) 450 matches++; 451 452 if (!of_property_read_u32(of_node, field2, &val2)) 453 matches++; 454 455 if (!of_property_read_u32(of_node, field3, &val3)) 456 matches++; 457 458 if (!of_property_read_u32(of_node, field4, &val4)) 459 matches++; 460 461 if (!matches) 462 return 0; 463 464 if (matches < 4) 465 newval = kszphy_extended_read(phydev, reg); 466 else 467 newval = 0; 468 469 if (val1 != -1) 470 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0); 471 472 if (val2 != -2) 473 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4); 474 475 if (val3 != -3) 476 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8); 477 478 if (val4 != -4) 479 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12); 480 481 return kszphy_extended_write(phydev, reg, newval); 482 } 483 484 static int ksz9021_config_init(struct phy_device *phydev) 485 { 486 const struct device *dev = &phydev->mdio.dev; 487 const struct device_node *of_node = dev->of_node; 488 const struct device *dev_walker; 489 490 /* The Micrel driver has a deprecated option to place phy OF 491 * properties in the MAC node. Walk up the tree of devices to 492 * find a device with an OF node. 493 */ 494 dev_walker = &phydev->mdio.dev; 495 do { 496 of_node = dev_walker->of_node; 497 dev_walker = dev_walker->parent; 498 499 } while (!of_node && dev_walker); 500 501 if (of_node) { 502 ksz9021_load_values_from_of(phydev, of_node, 503 MII_KSZPHY_CLK_CONTROL_PAD_SKEW, 504 "txen-skew-ps", "txc-skew-ps", 505 "rxdv-skew-ps", "rxc-skew-ps"); 506 ksz9021_load_values_from_of(phydev, of_node, 507 MII_KSZPHY_RX_DATA_PAD_SKEW, 508 "rxd0-skew-ps", "rxd1-skew-ps", 509 "rxd2-skew-ps", "rxd3-skew-ps"); 510 ksz9021_load_values_from_of(phydev, of_node, 511 MII_KSZPHY_TX_DATA_PAD_SKEW, 512 "txd0-skew-ps", "txd1-skew-ps", 513 "txd2-skew-ps", "txd3-skew-ps"); 514 } 515 return 0; 516 } 517 518 #define KSZ9031_PS_TO_REG 60 519 520 /* Extended registers */ 521 /* MMD Address 0x0 */ 522 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3 523 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4 524 525 /* MMD Address 0x2 */ 526 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4 527 #define MII_KSZ9031RN_RX_CTL_M GENMASK(7, 4) 528 #define MII_KSZ9031RN_TX_CTL_M GENMASK(3, 0) 529 530 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5 531 #define MII_KSZ9031RN_RXD3 GENMASK(15, 12) 532 #define MII_KSZ9031RN_RXD2 GENMASK(11, 8) 533 #define MII_KSZ9031RN_RXD1 GENMASK(7, 4) 534 #define MII_KSZ9031RN_RXD0 GENMASK(3, 0) 535 536 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6 537 #define MII_KSZ9031RN_TXD3 GENMASK(15, 12) 538 #define MII_KSZ9031RN_TXD2 GENMASK(11, 8) 539 #define MII_KSZ9031RN_TXD1 GENMASK(7, 4) 540 #define MII_KSZ9031RN_TXD0 GENMASK(3, 0) 541 542 #define MII_KSZ9031RN_CLK_PAD_SKEW 8 543 #define MII_KSZ9031RN_GTX_CLK GENMASK(9, 5) 544 #define MII_KSZ9031RN_RX_CLK GENMASK(4, 0) 545 546 /* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To 547 * provide different RGMII options we need to configure delay offset 548 * for each pad relative to build in delay. 549 */ 550 /* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of 551 * 1.80ns 552 */ 553 #define RX_ID 0x7 554 #define RX_CLK_ID 0x19 555 556 /* set rx to +0.30ns and rx_clk to -0.90ns to compensate the 557 * internal 1.2ns delay. 558 */ 559 #define RX_ND 0xc 560 #define RX_CLK_ND 0x0 561 562 /* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */ 563 #define TX_ID 0x0 564 #define TX_CLK_ID 0x1f 565 566 /* set tx and tx_clk to "No delay adjustment" to keep 0ns 567 * dealy 568 */ 569 #define TX_ND 0x7 570 #define TX_CLK_ND 0xf 571 572 /* MMD Address 0x1C */ 573 #define MII_KSZ9031RN_EDPD 0x23 574 #define MII_KSZ9031RN_EDPD_ENABLE BIT(0) 575 576 static int ksz9031_of_load_skew_values(struct phy_device *phydev, 577 const struct device_node *of_node, 578 u16 reg, size_t field_sz, 579 const char *field[], u8 numfields, 580 bool *update) 581 { 582 int val[4] = {-1, -2, -3, -4}; 583 int matches = 0; 584 u16 mask; 585 u16 maxval; 586 u16 newval; 587 int i; 588 589 for (i = 0; i < numfields; i++) 590 if (!of_property_read_u32(of_node, field[i], val + i)) 591 matches++; 592 593 if (!matches) 594 return 0; 595 596 *update |= true; 597 598 if (matches < numfields) 599 newval = phy_read_mmd(phydev, 2, reg); 600 else 601 newval = 0; 602 603 maxval = (field_sz == 4) ? 0xf : 0x1f; 604 for (i = 0; i < numfields; i++) 605 if (val[i] != -(i + 1)) { 606 mask = 0xffff; 607 mask ^= maxval << (field_sz * i); 608 newval = (newval & mask) | 609 (((val[i] / KSZ9031_PS_TO_REG) & maxval) 610 << (field_sz * i)); 611 } 612 613 return phy_write_mmd(phydev, 2, reg, newval); 614 } 615 616 /* Center KSZ9031RNX FLP timing at 16ms. */ 617 static int ksz9031_center_flp_timing(struct phy_device *phydev) 618 { 619 int result; 620 621 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI, 622 0x0006); 623 if (result) 624 return result; 625 626 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO, 627 0x1A80); 628 if (result) 629 return result; 630 631 return genphy_restart_aneg(phydev); 632 } 633 634 /* Enable energy-detect power-down mode */ 635 static int ksz9031_enable_edpd(struct phy_device *phydev) 636 { 637 int reg; 638 639 reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD); 640 if (reg < 0) 641 return reg; 642 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD, 643 reg | MII_KSZ9031RN_EDPD_ENABLE); 644 } 645 646 static int ksz9031_config_rgmii_delay(struct phy_device *phydev) 647 { 648 u16 rx, tx, rx_clk, tx_clk; 649 int ret; 650 651 switch (phydev->interface) { 652 case PHY_INTERFACE_MODE_RGMII: 653 tx = TX_ND; 654 tx_clk = TX_CLK_ND; 655 rx = RX_ND; 656 rx_clk = RX_CLK_ND; 657 break; 658 case PHY_INTERFACE_MODE_RGMII_ID: 659 tx = TX_ID; 660 tx_clk = TX_CLK_ID; 661 rx = RX_ID; 662 rx_clk = RX_CLK_ID; 663 break; 664 case PHY_INTERFACE_MODE_RGMII_RXID: 665 tx = TX_ND; 666 tx_clk = TX_CLK_ND; 667 rx = RX_ID; 668 rx_clk = RX_CLK_ID; 669 break; 670 case PHY_INTERFACE_MODE_RGMII_TXID: 671 tx = TX_ID; 672 tx_clk = TX_CLK_ID; 673 rx = RX_ND; 674 rx_clk = RX_CLK_ND; 675 break; 676 default: 677 return 0; 678 } 679 680 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW, 681 FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) | 682 FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx)); 683 if (ret < 0) 684 return ret; 685 686 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW, 687 FIELD_PREP(MII_KSZ9031RN_RXD3, rx) | 688 FIELD_PREP(MII_KSZ9031RN_RXD2, rx) | 689 FIELD_PREP(MII_KSZ9031RN_RXD1, rx) | 690 FIELD_PREP(MII_KSZ9031RN_RXD0, rx)); 691 if (ret < 0) 692 return ret; 693 694 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW, 695 FIELD_PREP(MII_KSZ9031RN_TXD3, tx) | 696 FIELD_PREP(MII_KSZ9031RN_TXD2, tx) | 697 FIELD_PREP(MII_KSZ9031RN_TXD1, tx) | 698 FIELD_PREP(MII_KSZ9031RN_TXD0, tx)); 699 if (ret < 0) 700 return ret; 701 702 return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW, 703 FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) | 704 FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk)); 705 } 706 707 static int ksz9031_config_init(struct phy_device *phydev) 708 { 709 const struct device *dev = &phydev->mdio.dev; 710 const struct device_node *of_node = dev->of_node; 711 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"}; 712 static const char *rx_data_skews[4] = { 713 "rxd0-skew-ps", "rxd1-skew-ps", 714 "rxd2-skew-ps", "rxd3-skew-ps" 715 }; 716 static const char *tx_data_skews[4] = { 717 "txd0-skew-ps", "txd1-skew-ps", 718 "txd2-skew-ps", "txd3-skew-ps" 719 }; 720 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"}; 721 const struct device *dev_walker; 722 int result; 723 724 result = ksz9031_enable_edpd(phydev); 725 if (result < 0) 726 return result; 727 728 /* The Micrel driver has a deprecated option to place phy OF 729 * properties in the MAC node. Walk up the tree of devices to 730 * find a device with an OF node. 731 */ 732 dev_walker = &phydev->mdio.dev; 733 do { 734 of_node = dev_walker->of_node; 735 dev_walker = dev_walker->parent; 736 } while (!of_node && dev_walker); 737 738 if (of_node) { 739 bool update = false; 740 741 if (phy_interface_is_rgmii(phydev)) { 742 result = ksz9031_config_rgmii_delay(phydev); 743 if (result < 0) 744 return result; 745 } 746 747 ksz9031_of_load_skew_values(phydev, of_node, 748 MII_KSZ9031RN_CLK_PAD_SKEW, 5, 749 clk_skews, 2, &update); 750 751 ksz9031_of_load_skew_values(phydev, of_node, 752 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, 753 control_skews, 2, &update); 754 755 ksz9031_of_load_skew_values(phydev, of_node, 756 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, 757 rx_data_skews, 4, &update); 758 759 ksz9031_of_load_skew_values(phydev, of_node, 760 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, 761 tx_data_skews, 4, &update); 762 763 if (update && phydev->interface != PHY_INTERFACE_MODE_RGMII) 764 phydev_warn(phydev, 765 "*-skew-ps values should be used only with phy-mode = \"rgmii\"\n"); 766 767 /* Silicon Errata Sheet (DS80000691D or DS80000692D): 768 * When the device links in the 1000BASE-T slave mode only, 769 * the optional 125MHz reference output clock (CLK125_NDO) 770 * has wide duty cycle variation. 771 * 772 * The optional CLK125_NDO clock does not meet the RGMII 773 * 45/55 percent (min/max) duty cycle requirement and therefore 774 * cannot be used directly by the MAC side for clocking 775 * applications that have setup/hold time requirements on 776 * rising and falling clock edges. 777 * 778 * Workaround: 779 * Force the phy to be the master to receive a stable clock 780 * which meets the duty cycle requirement. 781 */ 782 if (of_property_read_bool(of_node, "micrel,force-master")) { 783 result = phy_read(phydev, MII_CTRL1000); 784 if (result < 0) 785 goto err_force_master; 786 787 /* enable master mode, config & prefer master */ 788 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER; 789 result = phy_write(phydev, MII_CTRL1000, result); 790 if (result < 0) 791 goto err_force_master; 792 } 793 } 794 795 return ksz9031_center_flp_timing(phydev); 796 797 err_force_master: 798 phydev_err(phydev, "failed to force the phy to master mode\n"); 799 return result; 800 } 801 802 #define KSZ9131_SKEW_5BIT_MAX 2400 803 #define KSZ9131_SKEW_4BIT_MAX 800 804 #define KSZ9131_OFFSET 700 805 #define KSZ9131_STEP 100 806 807 static int ksz9131_of_load_skew_values(struct phy_device *phydev, 808 struct device_node *of_node, 809 u16 reg, size_t field_sz, 810 char *field[], u8 numfields) 811 { 812 int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET), 813 -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)}; 814 int skewval, skewmax = 0; 815 int matches = 0; 816 u16 maxval; 817 u16 newval; 818 u16 mask; 819 int i; 820 821 /* psec properties in dts should mean x pico seconds */ 822 if (field_sz == 5) 823 skewmax = KSZ9131_SKEW_5BIT_MAX; 824 else 825 skewmax = KSZ9131_SKEW_4BIT_MAX; 826 827 for (i = 0; i < numfields; i++) 828 if (!of_property_read_s32(of_node, field[i], &skewval)) { 829 if (skewval < -KSZ9131_OFFSET) 830 skewval = -KSZ9131_OFFSET; 831 else if (skewval > skewmax) 832 skewval = skewmax; 833 834 val[i] = skewval + KSZ9131_OFFSET; 835 matches++; 836 } 837 838 if (!matches) 839 return 0; 840 841 if (matches < numfields) 842 newval = phy_read_mmd(phydev, 2, reg); 843 else 844 newval = 0; 845 846 maxval = (field_sz == 4) ? 0xf : 0x1f; 847 for (i = 0; i < numfields; i++) 848 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) { 849 mask = 0xffff; 850 mask ^= maxval << (field_sz * i); 851 newval = (newval & mask) | 852 (((val[i] / KSZ9131_STEP) & maxval) 853 << (field_sz * i)); 854 } 855 856 return phy_write_mmd(phydev, 2, reg, newval); 857 } 858 859 #define KSZ9131RN_MMD_COMMON_CTRL_REG 2 860 #define KSZ9131RN_RXC_DLL_CTRL 76 861 #define KSZ9131RN_TXC_DLL_CTRL 77 862 #define KSZ9131RN_DLL_CTRL_BYPASS BIT_MASK(12) 863 #define KSZ9131RN_DLL_ENABLE_DELAY 0 864 #define KSZ9131RN_DLL_DISABLE_DELAY BIT(12) 865 866 static int ksz9131_config_rgmii_delay(struct phy_device *phydev) 867 { 868 u16 rxcdll_val, txcdll_val; 869 int ret; 870 871 switch (phydev->interface) { 872 case PHY_INTERFACE_MODE_RGMII: 873 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY; 874 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY; 875 break; 876 case PHY_INTERFACE_MODE_RGMII_ID: 877 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; 878 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; 879 break; 880 case PHY_INTERFACE_MODE_RGMII_RXID: 881 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; 882 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY; 883 break; 884 case PHY_INTERFACE_MODE_RGMII_TXID: 885 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY; 886 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; 887 break; 888 default: 889 return 0; 890 } 891 892 ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, 893 KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS, 894 rxcdll_val); 895 if (ret < 0) 896 return ret; 897 898 return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, 899 KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS, 900 txcdll_val); 901 } 902 903 static int ksz9131_config_init(struct phy_device *phydev) 904 { 905 const struct device *dev = &phydev->mdio.dev; 906 struct device_node *of_node = dev->of_node; 907 char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"}; 908 char *rx_data_skews[4] = { 909 "rxd0-skew-psec", "rxd1-skew-psec", 910 "rxd2-skew-psec", "rxd3-skew-psec" 911 }; 912 char *tx_data_skews[4] = { 913 "txd0-skew-psec", "txd1-skew-psec", 914 "txd2-skew-psec", "txd3-skew-psec" 915 }; 916 char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"}; 917 const struct device *dev_walker; 918 int ret; 919 920 dev_walker = &phydev->mdio.dev; 921 do { 922 of_node = dev_walker->of_node; 923 dev_walker = dev_walker->parent; 924 } while (!of_node && dev_walker); 925 926 if (!of_node) 927 return 0; 928 929 if (phy_interface_is_rgmii(phydev)) { 930 ret = ksz9131_config_rgmii_delay(phydev); 931 if (ret < 0) 932 return ret; 933 } 934 935 ret = ksz9131_of_load_skew_values(phydev, of_node, 936 MII_KSZ9031RN_CLK_PAD_SKEW, 5, 937 clk_skews, 2); 938 if (ret < 0) 939 return ret; 940 941 ret = ksz9131_of_load_skew_values(phydev, of_node, 942 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, 943 control_skews, 2); 944 if (ret < 0) 945 return ret; 946 947 ret = ksz9131_of_load_skew_values(phydev, of_node, 948 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, 949 rx_data_skews, 4); 950 if (ret < 0) 951 return ret; 952 953 ret = ksz9131_of_load_skew_values(phydev, of_node, 954 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, 955 tx_data_skews, 4); 956 if (ret < 0) 957 return ret; 958 959 return 0; 960 } 961 962 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06 963 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6) 964 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4) 965 static int ksz8873mll_read_status(struct phy_device *phydev) 966 { 967 int regval; 968 969 /* dummy read */ 970 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 971 972 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 973 974 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX) 975 phydev->duplex = DUPLEX_HALF; 976 else 977 phydev->duplex = DUPLEX_FULL; 978 979 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED) 980 phydev->speed = SPEED_10; 981 else 982 phydev->speed = SPEED_100; 983 984 phydev->link = 1; 985 phydev->pause = phydev->asym_pause = 0; 986 987 return 0; 988 } 989 990 static int ksz9031_get_features(struct phy_device *phydev) 991 { 992 int ret; 993 994 ret = genphy_read_abilities(phydev); 995 if (ret < 0) 996 return ret; 997 998 /* Silicon Errata Sheet (DS80000691D or DS80000692D): 999 * Whenever the device's Asymmetric Pause capability is set to 1, 1000 * link-up may fail after a link-up to link-down transition. 1001 * 1002 * The Errata Sheet is for ksz9031, but ksz9021 has the same issue 1003 * 1004 * Workaround: 1005 * Do not enable the Asymmetric Pause capability bit. 1006 */ 1007 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported); 1008 1009 /* We force setting the Pause capability as the core will force the 1010 * Asymmetric Pause capability to 1 otherwise. 1011 */ 1012 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported); 1013 1014 return 0; 1015 } 1016 1017 static int ksz9031_read_status(struct phy_device *phydev) 1018 { 1019 int err; 1020 int regval; 1021 1022 err = genphy_read_status(phydev); 1023 if (err) 1024 return err; 1025 1026 /* Make sure the PHY is not broken. Read idle error count, 1027 * and reset the PHY if it is maxed out. 1028 */ 1029 regval = phy_read(phydev, MII_STAT1000); 1030 if ((regval & 0xFF) == 0xFF) { 1031 phy_init_hw(phydev); 1032 phydev->link = 0; 1033 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev)) 1034 phydev->drv->config_intr(phydev); 1035 return genphy_config_aneg(phydev); 1036 } 1037 1038 return 0; 1039 } 1040 1041 static int ksz8873mll_config_aneg(struct phy_device *phydev) 1042 { 1043 return 0; 1044 } 1045 1046 static int kszphy_get_sset_count(struct phy_device *phydev) 1047 { 1048 return ARRAY_SIZE(kszphy_hw_stats); 1049 } 1050 1051 static void kszphy_get_strings(struct phy_device *phydev, u8 *data) 1052 { 1053 int i; 1054 1055 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) { 1056 strlcpy(data + i * ETH_GSTRING_LEN, 1057 kszphy_hw_stats[i].string, ETH_GSTRING_LEN); 1058 } 1059 } 1060 1061 static u64 kszphy_get_stat(struct phy_device *phydev, int i) 1062 { 1063 struct kszphy_hw_stat stat = kszphy_hw_stats[i]; 1064 struct kszphy_priv *priv = phydev->priv; 1065 int val; 1066 u64 ret; 1067 1068 val = phy_read(phydev, stat.reg); 1069 if (val < 0) { 1070 ret = U64_MAX; 1071 } else { 1072 val = val & ((1 << stat.bits) - 1); 1073 priv->stats[i] += val; 1074 ret = priv->stats[i]; 1075 } 1076 1077 return ret; 1078 } 1079 1080 static void kszphy_get_stats(struct phy_device *phydev, 1081 struct ethtool_stats *stats, u64 *data) 1082 { 1083 int i; 1084 1085 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) 1086 data[i] = kszphy_get_stat(phydev, i); 1087 } 1088 1089 static int kszphy_suspend(struct phy_device *phydev) 1090 { 1091 /* Disable PHY Interrupts */ 1092 if (phy_interrupt_is_valid(phydev)) { 1093 phydev->interrupts = PHY_INTERRUPT_DISABLED; 1094 if (phydev->drv->config_intr) 1095 phydev->drv->config_intr(phydev); 1096 } 1097 1098 return genphy_suspend(phydev); 1099 } 1100 1101 static int kszphy_resume(struct phy_device *phydev) 1102 { 1103 int ret; 1104 1105 genphy_resume(phydev); 1106 1107 /* After switching from power-down to normal mode, an internal global 1108 * reset is automatically generated. Wait a minimum of 1 ms before 1109 * read/write access to the PHY registers. 1110 */ 1111 usleep_range(1000, 2000); 1112 1113 ret = kszphy_config_reset(phydev); 1114 if (ret) 1115 return ret; 1116 1117 /* Enable PHY Interrupts */ 1118 if (phy_interrupt_is_valid(phydev)) { 1119 phydev->interrupts = PHY_INTERRUPT_ENABLED; 1120 if (phydev->drv->config_intr) 1121 phydev->drv->config_intr(phydev); 1122 } 1123 1124 return 0; 1125 } 1126 1127 static int kszphy_probe(struct phy_device *phydev) 1128 { 1129 const struct kszphy_type *type = phydev->drv->driver_data; 1130 const struct device_node *np = phydev->mdio.dev.of_node; 1131 struct kszphy_priv *priv; 1132 struct clk *clk; 1133 int ret; 1134 1135 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 1136 if (!priv) 1137 return -ENOMEM; 1138 1139 phydev->priv = priv; 1140 1141 priv->type = type; 1142 1143 if (type->led_mode_reg) { 1144 ret = of_property_read_u32(np, "micrel,led-mode", 1145 &priv->led_mode); 1146 if (ret) 1147 priv->led_mode = -1; 1148 1149 if (priv->led_mode > 3) { 1150 phydev_err(phydev, "invalid led mode: 0x%02x\n", 1151 priv->led_mode); 1152 priv->led_mode = -1; 1153 } 1154 } else { 1155 priv->led_mode = -1; 1156 } 1157 1158 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref"); 1159 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */ 1160 if (!IS_ERR_OR_NULL(clk)) { 1161 unsigned long rate = clk_get_rate(clk); 1162 bool rmii_ref_clk_sel_25_mhz; 1163 1164 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel; 1165 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np, 1166 "micrel,rmii-reference-clock-select-25-mhz"); 1167 1168 if (rate > 24500000 && rate < 25500000) { 1169 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz; 1170 } else if (rate > 49500000 && rate < 50500000) { 1171 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz; 1172 } else { 1173 phydev_err(phydev, "Clock rate out of range: %ld\n", 1174 rate); 1175 return -EINVAL; 1176 } 1177 } 1178 1179 /* Support legacy board-file configuration */ 1180 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) { 1181 priv->rmii_ref_clk_sel = true; 1182 priv->rmii_ref_clk_sel_val = true; 1183 } 1184 1185 return 0; 1186 } 1187 1188 static struct phy_driver ksphy_driver[] = { 1189 { 1190 .phy_id = PHY_ID_KS8737, 1191 .phy_id_mask = MICREL_PHY_ID_MASK, 1192 .name = "Micrel KS8737", 1193 /* PHY_BASIC_FEATURES */ 1194 .driver_data = &ks8737_type, 1195 .config_init = kszphy_config_init, 1196 .config_intr = kszphy_config_intr, 1197 .handle_interrupt = kszphy_handle_interrupt, 1198 .suspend = genphy_suspend, 1199 .resume = genphy_resume, 1200 }, { 1201 .phy_id = PHY_ID_KSZ8021, 1202 .phy_id_mask = 0x00ffffff, 1203 .name = "Micrel KSZ8021 or KSZ8031", 1204 /* PHY_BASIC_FEATURES */ 1205 .driver_data = &ksz8021_type, 1206 .probe = kszphy_probe, 1207 .config_init = kszphy_config_init, 1208 .config_intr = kszphy_config_intr, 1209 .handle_interrupt = kszphy_handle_interrupt, 1210 .get_sset_count = kszphy_get_sset_count, 1211 .get_strings = kszphy_get_strings, 1212 .get_stats = kszphy_get_stats, 1213 .suspend = genphy_suspend, 1214 .resume = genphy_resume, 1215 }, { 1216 .phy_id = PHY_ID_KSZ8031, 1217 .phy_id_mask = 0x00ffffff, 1218 .name = "Micrel KSZ8031", 1219 /* PHY_BASIC_FEATURES */ 1220 .driver_data = &ksz8021_type, 1221 .probe = kszphy_probe, 1222 .config_init = kszphy_config_init, 1223 .config_intr = kszphy_config_intr, 1224 .handle_interrupt = kszphy_handle_interrupt, 1225 .get_sset_count = kszphy_get_sset_count, 1226 .get_strings = kszphy_get_strings, 1227 .get_stats = kszphy_get_stats, 1228 .suspend = genphy_suspend, 1229 .resume = genphy_resume, 1230 }, { 1231 .phy_id = PHY_ID_KSZ8041, 1232 .phy_id_mask = MICREL_PHY_ID_MASK, 1233 .name = "Micrel KSZ8041", 1234 /* PHY_BASIC_FEATURES */ 1235 .driver_data = &ksz8041_type, 1236 .probe = kszphy_probe, 1237 .config_init = ksz8041_config_init, 1238 .config_aneg = ksz8041_config_aneg, 1239 .config_intr = kszphy_config_intr, 1240 .handle_interrupt = kszphy_handle_interrupt, 1241 .get_sset_count = kszphy_get_sset_count, 1242 .get_strings = kszphy_get_strings, 1243 .get_stats = kszphy_get_stats, 1244 .suspend = genphy_suspend, 1245 .resume = genphy_resume, 1246 }, { 1247 .phy_id = PHY_ID_KSZ8041RNLI, 1248 .phy_id_mask = MICREL_PHY_ID_MASK, 1249 .name = "Micrel KSZ8041RNLI", 1250 /* PHY_BASIC_FEATURES */ 1251 .driver_data = &ksz8041_type, 1252 .probe = kszphy_probe, 1253 .config_init = kszphy_config_init, 1254 .config_intr = kszphy_config_intr, 1255 .handle_interrupt = kszphy_handle_interrupt, 1256 .get_sset_count = kszphy_get_sset_count, 1257 .get_strings = kszphy_get_strings, 1258 .get_stats = kszphy_get_stats, 1259 .suspend = genphy_suspend, 1260 .resume = genphy_resume, 1261 }, { 1262 .name = "Micrel KSZ8051", 1263 /* PHY_BASIC_FEATURES */ 1264 .driver_data = &ksz8051_type, 1265 .probe = kszphy_probe, 1266 .config_init = kszphy_config_init, 1267 .config_intr = kszphy_config_intr, 1268 .handle_interrupt = kszphy_handle_interrupt, 1269 .get_sset_count = kszphy_get_sset_count, 1270 .get_strings = kszphy_get_strings, 1271 .get_stats = kszphy_get_stats, 1272 .match_phy_device = ksz8051_match_phy_device, 1273 .suspend = genphy_suspend, 1274 .resume = genphy_resume, 1275 }, { 1276 .phy_id = PHY_ID_KSZ8001, 1277 .name = "Micrel KSZ8001 or KS8721", 1278 .phy_id_mask = 0x00fffffc, 1279 /* PHY_BASIC_FEATURES */ 1280 .driver_data = &ksz8041_type, 1281 .probe = kszphy_probe, 1282 .config_init = kszphy_config_init, 1283 .config_intr = kszphy_config_intr, 1284 .handle_interrupt = kszphy_handle_interrupt, 1285 .get_sset_count = kszphy_get_sset_count, 1286 .get_strings = kszphy_get_strings, 1287 .get_stats = kszphy_get_stats, 1288 .suspend = genphy_suspend, 1289 .resume = genphy_resume, 1290 }, { 1291 .phy_id = PHY_ID_KSZ8081, 1292 .name = "Micrel KSZ8081 or KSZ8091", 1293 .phy_id_mask = MICREL_PHY_ID_MASK, 1294 /* PHY_BASIC_FEATURES */ 1295 .driver_data = &ksz8081_type, 1296 .probe = kszphy_probe, 1297 .config_init = ksz8081_config_init, 1298 .config_intr = kszphy_config_intr, 1299 .handle_interrupt = kszphy_handle_interrupt, 1300 .get_sset_count = kszphy_get_sset_count, 1301 .get_strings = kszphy_get_strings, 1302 .get_stats = kszphy_get_stats, 1303 .suspend = kszphy_suspend, 1304 .resume = kszphy_resume, 1305 }, { 1306 .phy_id = PHY_ID_KSZ8061, 1307 .name = "Micrel KSZ8061", 1308 .phy_id_mask = MICREL_PHY_ID_MASK, 1309 /* PHY_BASIC_FEATURES */ 1310 .config_init = ksz8061_config_init, 1311 .config_intr = kszphy_config_intr, 1312 .handle_interrupt = kszphy_handle_interrupt, 1313 .suspend = genphy_suspend, 1314 .resume = genphy_resume, 1315 }, { 1316 .phy_id = PHY_ID_KSZ9021, 1317 .phy_id_mask = 0x000ffffe, 1318 .name = "Micrel KSZ9021 Gigabit PHY", 1319 /* PHY_GBIT_FEATURES */ 1320 .driver_data = &ksz9021_type, 1321 .probe = kszphy_probe, 1322 .get_features = ksz9031_get_features, 1323 .config_init = ksz9021_config_init, 1324 .config_intr = kszphy_config_intr, 1325 .handle_interrupt = kszphy_handle_interrupt, 1326 .get_sset_count = kszphy_get_sset_count, 1327 .get_strings = kszphy_get_strings, 1328 .get_stats = kszphy_get_stats, 1329 .suspend = genphy_suspend, 1330 .resume = genphy_resume, 1331 .read_mmd = genphy_read_mmd_unsupported, 1332 .write_mmd = genphy_write_mmd_unsupported, 1333 }, { 1334 .phy_id = PHY_ID_KSZ9031, 1335 .phy_id_mask = MICREL_PHY_ID_MASK, 1336 .name = "Micrel KSZ9031 Gigabit PHY", 1337 .driver_data = &ksz9021_type, 1338 .probe = kszphy_probe, 1339 .get_features = ksz9031_get_features, 1340 .config_init = ksz9031_config_init, 1341 .soft_reset = genphy_soft_reset, 1342 .read_status = ksz9031_read_status, 1343 .config_intr = kszphy_config_intr, 1344 .handle_interrupt = kszphy_handle_interrupt, 1345 .get_sset_count = kszphy_get_sset_count, 1346 .get_strings = kszphy_get_strings, 1347 .get_stats = kszphy_get_stats, 1348 .suspend = genphy_suspend, 1349 .resume = kszphy_resume, 1350 }, { 1351 .phy_id = PHY_ID_LAN8814, 1352 .phy_id_mask = MICREL_PHY_ID_MASK, 1353 .name = "Microchip INDY Gigabit Quad PHY", 1354 .driver_data = &ksz9021_type, 1355 .probe = kszphy_probe, 1356 .soft_reset = genphy_soft_reset, 1357 .read_status = ksz9031_read_status, 1358 .get_sset_count = kszphy_get_sset_count, 1359 .get_strings = kszphy_get_strings, 1360 .get_stats = kszphy_get_stats, 1361 .suspend = genphy_suspend, 1362 .resume = kszphy_resume, 1363 }, { 1364 .phy_id = PHY_ID_KSZ9131, 1365 .phy_id_mask = MICREL_PHY_ID_MASK, 1366 .name = "Microchip KSZ9131 Gigabit PHY", 1367 /* PHY_GBIT_FEATURES */ 1368 .driver_data = &ksz9021_type, 1369 .probe = kszphy_probe, 1370 .config_init = ksz9131_config_init, 1371 .read_status = genphy_read_status, 1372 .config_intr = kszphy_config_intr, 1373 .handle_interrupt = kszphy_handle_interrupt, 1374 .get_sset_count = kszphy_get_sset_count, 1375 .get_strings = kszphy_get_strings, 1376 .get_stats = kszphy_get_stats, 1377 .suspend = genphy_suspend, 1378 .resume = kszphy_resume, 1379 }, { 1380 .phy_id = PHY_ID_KSZ8873MLL, 1381 .phy_id_mask = MICREL_PHY_ID_MASK, 1382 .name = "Micrel KSZ8873MLL Switch", 1383 /* PHY_BASIC_FEATURES */ 1384 .config_init = kszphy_config_init, 1385 .config_aneg = ksz8873mll_config_aneg, 1386 .read_status = ksz8873mll_read_status, 1387 .suspend = genphy_suspend, 1388 .resume = genphy_resume, 1389 }, { 1390 .phy_id = PHY_ID_KSZ886X, 1391 .phy_id_mask = MICREL_PHY_ID_MASK, 1392 .name = "Micrel KSZ886X Switch", 1393 /* PHY_BASIC_FEATURES */ 1394 .config_init = kszphy_config_init, 1395 .suspend = genphy_suspend, 1396 .resume = genphy_resume, 1397 }, { 1398 .name = "Micrel KSZ87XX Switch", 1399 /* PHY_BASIC_FEATURES */ 1400 .config_init = kszphy_config_init, 1401 .config_aneg = ksz8873mll_config_aneg, 1402 .read_status = ksz8873mll_read_status, 1403 .match_phy_device = ksz8795_match_phy_device, 1404 .suspend = genphy_suspend, 1405 .resume = genphy_resume, 1406 }, { 1407 .phy_id = PHY_ID_KSZ9477, 1408 .phy_id_mask = MICREL_PHY_ID_MASK, 1409 .name = "Microchip KSZ9477", 1410 /* PHY_GBIT_FEATURES */ 1411 .config_init = kszphy_config_init, 1412 .suspend = genphy_suspend, 1413 .resume = genphy_resume, 1414 } }; 1415 1416 module_phy_driver(ksphy_driver); 1417 1418 MODULE_DESCRIPTION("Micrel PHY driver"); 1419 MODULE_AUTHOR("David J. Choi"); 1420 MODULE_LICENSE("GPL"); 1421 1422 static struct mdio_device_id __maybe_unused micrel_tbl[] = { 1423 { PHY_ID_KSZ9021, 0x000ffffe }, 1424 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK }, 1425 { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK }, 1426 { PHY_ID_KSZ8001, 0x00fffffc }, 1427 { PHY_ID_KS8737, MICREL_PHY_ID_MASK }, 1428 { PHY_ID_KSZ8021, 0x00ffffff }, 1429 { PHY_ID_KSZ8031, 0x00ffffff }, 1430 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK }, 1431 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK }, 1432 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK }, 1433 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK }, 1434 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK }, 1435 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK }, 1436 { PHY_ID_LAN8814, MICREL_PHY_ID_MASK }, 1437 { } 1438 }; 1439 1440 MODULE_DEVICE_TABLE(mdio, micrel_tbl); 1441