1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/micrel.c 4 * 5 * Driver for Micrel PHYs 6 * 7 * Author: David J. Choi 8 * 9 * Copyright (c) 2010-2013 Micrel, Inc. 10 * Copyright (c) 2014 Johan Hovold <johan@kernel.org> 11 * 12 * Support : Micrel Phys: 13 * Giga phys: ksz9021, ksz9031, ksz9131 14 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041 15 * ksz8021, ksz8031, ksz8051, 16 * ksz8081, ksz8091, 17 * ksz8061, 18 * Switch : ksz8873, ksz886x 19 * ksz9477 20 */ 21 22 #include <linux/bitfield.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/phy.h> 26 #include <linux/micrel_phy.h> 27 #include <linux/of.h> 28 #include <linux/clk.h> 29 #include <linux/delay.h> 30 31 /* Operation Mode Strap Override */ 32 #define MII_KSZPHY_OMSO 0x16 33 #define KSZPHY_OMSO_FACTORY_TEST BIT(15) 34 #define KSZPHY_OMSO_B_CAST_OFF BIT(9) 35 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5) 36 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1) 37 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0) 38 39 /* general Interrupt control/status reg in vendor specific block. */ 40 #define MII_KSZPHY_INTCS 0x1B 41 #define KSZPHY_INTCS_JABBER BIT(15) 42 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14) 43 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13) 44 #define KSZPHY_INTCS_PARELLEL BIT(12) 45 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11) 46 #define KSZPHY_INTCS_LINK_DOWN BIT(10) 47 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9) 48 #define KSZPHY_INTCS_LINK_UP BIT(8) 49 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\ 50 KSZPHY_INTCS_LINK_DOWN) 51 52 /* PHY Control 1 */ 53 #define MII_KSZPHY_CTRL_1 0x1e 54 55 /* PHY Control 2 / PHY Control (if no PHY Control 1) */ 56 #define MII_KSZPHY_CTRL_2 0x1f 57 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2 58 /* bitmap of PHY register to set interrupt mode */ 59 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9) 60 #define KSZPHY_RMII_REF_CLK_SEL BIT(7) 61 62 /* Write/read to/from extended registers */ 63 #define MII_KSZPHY_EXTREG 0x0b 64 #define KSZPHY_EXTREG_WRITE 0x8000 65 66 #define MII_KSZPHY_EXTREG_WRITE 0x0c 67 #define MII_KSZPHY_EXTREG_READ 0x0d 68 69 /* Extended registers */ 70 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104 71 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105 72 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106 73 74 #define PS_TO_REG 200 75 76 struct kszphy_hw_stat { 77 const char *string; 78 u8 reg; 79 u8 bits; 80 }; 81 82 static struct kszphy_hw_stat kszphy_hw_stats[] = { 83 { "phy_receive_errors", 21, 16}, 84 { "phy_idle_errors", 10, 8 }, 85 }; 86 87 struct kszphy_type { 88 u32 led_mode_reg; 89 u16 interrupt_level_mask; 90 bool has_broadcast_disable; 91 bool has_nand_tree_disable; 92 bool has_rmii_ref_clk_sel; 93 }; 94 95 struct kszphy_priv { 96 const struct kszphy_type *type; 97 int led_mode; 98 bool rmii_ref_clk_sel; 99 bool rmii_ref_clk_sel_val; 100 u64 stats[ARRAY_SIZE(kszphy_hw_stats)]; 101 }; 102 103 static const struct kszphy_type ksz8021_type = { 104 .led_mode_reg = MII_KSZPHY_CTRL_2, 105 .has_broadcast_disable = true, 106 .has_nand_tree_disable = true, 107 .has_rmii_ref_clk_sel = true, 108 }; 109 110 static const struct kszphy_type ksz8041_type = { 111 .led_mode_reg = MII_KSZPHY_CTRL_1, 112 }; 113 114 static const struct kszphy_type ksz8051_type = { 115 .led_mode_reg = MII_KSZPHY_CTRL_2, 116 .has_nand_tree_disable = true, 117 }; 118 119 static const struct kszphy_type ksz8081_type = { 120 .led_mode_reg = MII_KSZPHY_CTRL_2, 121 .has_broadcast_disable = true, 122 .has_nand_tree_disable = true, 123 .has_rmii_ref_clk_sel = true, 124 }; 125 126 static const struct kszphy_type ks8737_type = { 127 .interrupt_level_mask = BIT(14), 128 }; 129 130 static const struct kszphy_type ksz9021_type = { 131 .interrupt_level_mask = BIT(14), 132 }; 133 134 static int kszphy_extended_write(struct phy_device *phydev, 135 u32 regnum, u16 val) 136 { 137 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum); 138 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); 139 } 140 141 static int kszphy_extended_read(struct phy_device *phydev, 142 u32 regnum) 143 { 144 phy_write(phydev, MII_KSZPHY_EXTREG, regnum); 145 return phy_read(phydev, MII_KSZPHY_EXTREG_READ); 146 } 147 148 static int kszphy_ack_interrupt(struct phy_device *phydev) 149 { 150 /* bit[7..0] int status, which is a read and clear register. */ 151 int rc; 152 153 rc = phy_read(phydev, MII_KSZPHY_INTCS); 154 155 return (rc < 0) ? rc : 0; 156 } 157 158 static int kszphy_config_intr(struct phy_device *phydev) 159 { 160 const struct kszphy_type *type = phydev->drv->driver_data; 161 int temp; 162 u16 mask; 163 164 if (type && type->interrupt_level_mask) 165 mask = type->interrupt_level_mask; 166 else 167 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH; 168 169 /* set the interrupt pin active low */ 170 temp = phy_read(phydev, MII_KSZPHY_CTRL); 171 if (temp < 0) 172 return temp; 173 temp &= ~mask; 174 phy_write(phydev, MII_KSZPHY_CTRL, temp); 175 176 /* enable / disable interrupts */ 177 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 178 temp = KSZPHY_INTCS_ALL; 179 else 180 temp = 0; 181 182 return phy_write(phydev, MII_KSZPHY_INTCS, temp); 183 } 184 185 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val) 186 { 187 int ctrl; 188 189 ctrl = phy_read(phydev, MII_KSZPHY_CTRL); 190 if (ctrl < 0) 191 return ctrl; 192 193 if (val) 194 ctrl |= KSZPHY_RMII_REF_CLK_SEL; 195 else 196 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL; 197 198 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl); 199 } 200 201 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val) 202 { 203 int rc, temp, shift; 204 205 switch (reg) { 206 case MII_KSZPHY_CTRL_1: 207 shift = 14; 208 break; 209 case MII_KSZPHY_CTRL_2: 210 shift = 4; 211 break; 212 default: 213 return -EINVAL; 214 } 215 216 temp = phy_read(phydev, reg); 217 if (temp < 0) { 218 rc = temp; 219 goto out; 220 } 221 222 temp &= ~(3 << shift); 223 temp |= val << shift; 224 rc = phy_write(phydev, reg, temp); 225 out: 226 if (rc < 0) 227 phydev_err(phydev, "failed to set led mode\n"); 228 229 return rc; 230 } 231 232 /* Disable PHY address 0 as the broadcast address, so that it can be used as a 233 * unique (non-broadcast) address on a shared bus. 234 */ 235 static int kszphy_broadcast_disable(struct phy_device *phydev) 236 { 237 int ret; 238 239 ret = phy_read(phydev, MII_KSZPHY_OMSO); 240 if (ret < 0) 241 goto out; 242 243 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF); 244 out: 245 if (ret) 246 phydev_err(phydev, "failed to disable broadcast address\n"); 247 248 return ret; 249 } 250 251 static int kszphy_nand_tree_disable(struct phy_device *phydev) 252 { 253 int ret; 254 255 ret = phy_read(phydev, MII_KSZPHY_OMSO); 256 if (ret < 0) 257 goto out; 258 259 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON)) 260 return 0; 261 262 ret = phy_write(phydev, MII_KSZPHY_OMSO, 263 ret & ~KSZPHY_OMSO_NAND_TREE_ON); 264 out: 265 if (ret) 266 phydev_err(phydev, "failed to disable NAND tree mode\n"); 267 268 return ret; 269 } 270 271 /* Some config bits need to be set again on resume, handle them here. */ 272 static int kszphy_config_reset(struct phy_device *phydev) 273 { 274 struct kszphy_priv *priv = phydev->priv; 275 int ret; 276 277 if (priv->rmii_ref_clk_sel) { 278 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val); 279 if (ret) { 280 phydev_err(phydev, 281 "failed to set rmii reference clock\n"); 282 return ret; 283 } 284 } 285 286 if (priv->led_mode >= 0) 287 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode); 288 289 return 0; 290 } 291 292 static int kszphy_config_init(struct phy_device *phydev) 293 { 294 struct kszphy_priv *priv = phydev->priv; 295 const struct kszphy_type *type; 296 297 if (!priv) 298 return 0; 299 300 type = priv->type; 301 302 if (type->has_broadcast_disable) 303 kszphy_broadcast_disable(phydev); 304 305 if (type->has_nand_tree_disable) 306 kszphy_nand_tree_disable(phydev); 307 308 return kszphy_config_reset(phydev); 309 } 310 311 static int ksz8041_fiber_mode(struct phy_device *phydev) 312 { 313 struct device_node *of_node = phydev->mdio.dev.of_node; 314 315 return of_property_read_bool(of_node, "micrel,fiber-mode"); 316 } 317 318 static int ksz8041_config_init(struct phy_device *phydev) 319 { 320 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 321 322 /* Limit supported and advertised modes in fiber mode */ 323 if (ksz8041_fiber_mode(phydev)) { 324 phydev->dev_flags |= MICREL_PHY_FXEN; 325 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask); 326 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask); 327 328 linkmode_and(phydev->supported, phydev->supported, mask); 329 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 330 phydev->supported); 331 linkmode_and(phydev->advertising, phydev->advertising, mask); 332 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 333 phydev->advertising); 334 phydev->autoneg = AUTONEG_DISABLE; 335 } 336 337 return kszphy_config_init(phydev); 338 } 339 340 static int ksz8041_config_aneg(struct phy_device *phydev) 341 { 342 /* Skip auto-negotiation in fiber mode */ 343 if (phydev->dev_flags & MICREL_PHY_FXEN) { 344 phydev->speed = SPEED_100; 345 return 0; 346 } 347 348 return genphy_config_aneg(phydev); 349 } 350 351 static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev, 352 const bool ksz_8051) 353 { 354 int ret; 355 356 if ((phydev->phy_id & MICREL_PHY_ID_MASK) != PHY_ID_KSZ8051) 357 return 0; 358 359 ret = phy_read(phydev, MII_BMSR); 360 if (ret < 0) 361 return ret; 362 363 /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same 364 * exact PHY ID. However, they can be told apart by the extended 365 * capability registers presence. The KSZ8051 PHY has them while 366 * the switch does not. 367 */ 368 ret &= BMSR_ERCAP; 369 if (ksz_8051) 370 return ret; 371 else 372 return !ret; 373 } 374 375 static int ksz8051_match_phy_device(struct phy_device *phydev) 376 { 377 return ksz8051_ksz8795_match_phy_device(phydev, true); 378 } 379 380 static int ksz8081_config_init(struct phy_device *phydev) 381 { 382 /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line 383 * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a 384 * pull-down is missing, the factory test mode should be cleared by 385 * manually writing a 0. 386 */ 387 phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST); 388 389 return kszphy_config_init(phydev); 390 } 391 392 static int ksz8061_config_init(struct phy_device *phydev) 393 { 394 int ret; 395 396 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A); 397 if (ret) 398 return ret; 399 400 return kszphy_config_init(phydev); 401 } 402 403 static int ksz8795_match_phy_device(struct phy_device *phydev) 404 { 405 return ksz8051_ksz8795_match_phy_device(phydev, false); 406 } 407 408 static int ksz9021_load_values_from_of(struct phy_device *phydev, 409 const struct device_node *of_node, 410 u16 reg, 411 const char *field1, const char *field2, 412 const char *field3, const char *field4) 413 { 414 int val1 = -1; 415 int val2 = -2; 416 int val3 = -3; 417 int val4 = -4; 418 int newval; 419 int matches = 0; 420 421 if (!of_property_read_u32(of_node, field1, &val1)) 422 matches++; 423 424 if (!of_property_read_u32(of_node, field2, &val2)) 425 matches++; 426 427 if (!of_property_read_u32(of_node, field3, &val3)) 428 matches++; 429 430 if (!of_property_read_u32(of_node, field4, &val4)) 431 matches++; 432 433 if (!matches) 434 return 0; 435 436 if (matches < 4) 437 newval = kszphy_extended_read(phydev, reg); 438 else 439 newval = 0; 440 441 if (val1 != -1) 442 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0); 443 444 if (val2 != -2) 445 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4); 446 447 if (val3 != -3) 448 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8); 449 450 if (val4 != -4) 451 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12); 452 453 return kszphy_extended_write(phydev, reg, newval); 454 } 455 456 static int ksz9021_config_init(struct phy_device *phydev) 457 { 458 const struct device *dev = &phydev->mdio.dev; 459 const struct device_node *of_node = dev->of_node; 460 const struct device *dev_walker; 461 462 /* The Micrel driver has a deprecated option to place phy OF 463 * properties in the MAC node. Walk up the tree of devices to 464 * find a device with an OF node. 465 */ 466 dev_walker = &phydev->mdio.dev; 467 do { 468 of_node = dev_walker->of_node; 469 dev_walker = dev_walker->parent; 470 471 } while (!of_node && dev_walker); 472 473 if (of_node) { 474 ksz9021_load_values_from_of(phydev, of_node, 475 MII_KSZPHY_CLK_CONTROL_PAD_SKEW, 476 "txen-skew-ps", "txc-skew-ps", 477 "rxdv-skew-ps", "rxc-skew-ps"); 478 ksz9021_load_values_from_of(phydev, of_node, 479 MII_KSZPHY_RX_DATA_PAD_SKEW, 480 "rxd0-skew-ps", "rxd1-skew-ps", 481 "rxd2-skew-ps", "rxd3-skew-ps"); 482 ksz9021_load_values_from_of(phydev, of_node, 483 MII_KSZPHY_TX_DATA_PAD_SKEW, 484 "txd0-skew-ps", "txd1-skew-ps", 485 "txd2-skew-ps", "txd3-skew-ps"); 486 } 487 return 0; 488 } 489 490 #define KSZ9031_PS_TO_REG 60 491 492 /* Extended registers */ 493 /* MMD Address 0x0 */ 494 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3 495 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4 496 497 /* MMD Address 0x2 */ 498 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4 499 #define MII_KSZ9031RN_RX_CTL_M GENMASK(7, 4) 500 #define MII_KSZ9031RN_TX_CTL_M GENMASK(3, 0) 501 502 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5 503 #define MII_KSZ9031RN_RXD3 GENMASK(15, 12) 504 #define MII_KSZ9031RN_RXD2 GENMASK(11, 8) 505 #define MII_KSZ9031RN_RXD1 GENMASK(7, 4) 506 #define MII_KSZ9031RN_RXD0 GENMASK(3, 0) 507 508 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6 509 #define MII_KSZ9031RN_TXD3 GENMASK(15, 12) 510 #define MII_KSZ9031RN_TXD2 GENMASK(11, 8) 511 #define MII_KSZ9031RN_TXD1 GENMASK(7, 4) 512 #define MII_KSZ9031RN_TXD0 GENMASK(3, 0) 513 514 #define MII_KSZ9031RN_CLK_PAD_SKEW 8 515 #define MII_KSZ9031RN_GTX_CLK GENMASK(9, 5) 516 #define MII_KSZ9031RN_RX_CLK GENMASK(4, 0) 517 518 /* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To 519 * provide different RGMII options we need to configure delay offset 520 * for each pad relative to build in delay. 521 */ 522 /* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of 523 * 1.80ns 524 */ 525 #define RX_ID 0x7 526 #define RX_CLK_ID 0x19 527 528 /* set rx to +0.30ns and rx_clk to -0.90ns to compensate the 529 * internal 1.2ns delay. 530 */ 531 #define RX_ND 0xc 532 #define RX_CLK_ND 0x0 533 534 /* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */ 535 #define TX_ID 0x0 536 #define TX_CLK_ID 0x1f 537 538 /* set tx and tx_clk to "No delay adjustment" to keep 0ns 539 * dealy 540 */ 541 #define TX_ND 0x7 542 #define TX_CLK_ND 0xf 543 544 /* MMD Address 0x1C */ 545 #define MII_KSZ9031RN_EDPD 0x23 546 #define MII_KSZ9031RN_EDPD_ENABLE BIT(0) 547 548 static int ksz9031_of_load_skew_values(struct phy_device *phydev, 549 const struct device_node *of_node, 550 u16 reg, size_t field_sz, 551 const char *field[], u8 numfields, 552 bool *update) 553 { 554 int val[4] = {-1, -2, -3, -4}; 555 int matches = 0; 556 u16 mask; 557 u16 maxval; 558 u16 newval; 559 int i; 560 561 for (i = 0; i < numfields; i++) 562 if (!of_property_read_u32(of_node, field[i], val + i)) 563 matches++; 564 565 if (!matches) 566 return 0; 567 568 *update |= true; 569 570 if (matches < numfields) 571 newval = phy_read_mmd(phydev, 2, reg); 572 else 573 newval = 0; 574 575 maxval = (field_sz == 4) ? 0xf : 0x1f; 576 for (i = 0; i < numfields; i++) 577 if (val[i] != -(i + 1)) { 578 mask = 0xffff; 579 mask ^= maxval << (field_sz * i); 580 newval = (newval & mask) | 581 (((val[i] / KSZ9031_PS_TO_REG) & maxval) 582 << (field_sz * i)); 583 } 584 585 return phy_write_mmd(phydev, 2, reg, newval); 586 } 587 588 /* Center KSZ9031RNX FLP timing at 16ms. */ 589 static int ksz9031_center_flp_timing(struct phy_device *phydev) 590 { 591 int result; 592 593 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI, 594 0x0006); 595 if (result) 596 return result; 597 598 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO, 599 0x1A80); 600 if (result) 601 return result; 602 603 return genphy_restart_aneg(phydev); 604 } 605 606 /* Enable energy-detect power-down mode */ 607 static int ksz9031_enable_edpd(struct phy_device *phydev) 608 { 609 int reg; 610 611 reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD); 612 if (reg < 0) 613 return reg; 614 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD, 615 reg | MII_KSZ9031RN_EDPD_ENABLE); 616 } 617 618 static int ksz9031_config_rgmii_delay(struct phy_device *phydev) 619 { 620 u16 rx, tx, rx_clk, tx_clk; 621 int ret; 622 623 switch (phydev->interface) { 624 case PHY_INTERFACE_MODE_RGMII: 625 tx = TX_ND; 626 tx_clk = TX_CLK_ND; 627 rx = RX_ND; 628 rx_clk = RX_CLK_ND; 629 break; 630 case PHY_INTERFACE_MODE_RGMII_ID: 631 tx = TX_ID; 632 tx_clk = TX_CLK_ID; 633 rx = RX_ID; 634 rx_clk = RX_CLK_ID; 635 break; 636 case PHY_INTERFACE_MODE_RGMII_RXID: 637 tx = TX_ND; 638 tx_clk = TX_CLK_ND; 639 rx = RX_ID; 640 rx_clk = RX_CLK_ID; 641 break; 642 case PHY_INTERFACE_MODE_RGMII_TXID: 643 tx = TX_ID; 644 tx_clk = TX_CLK_ID; 645 rx = RX_ND; 646 rx_clk = RX_CLK_ND; 647 break; 648 default: 649 return 0; 650 } 651 652 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW, 653 FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) | 654 FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx)); 655 if (ret < 0) 656 return ret; 657 658 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW, 659 FIELD_PREP(MII_KSZ9031RN_RXD3, rx) | 660 FIELD_PREP(MII_KSZ9031RN_RXD2, rx) | 661 FIELD_PREP(MII_KSZ9031RN_RXD1, rx) | 662 FIELD_PREP(MII_KSZ9031RN_RXD0, rx)); 663 if (ret < 0) 664 return ret; 665 666 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW, 667 FIELD_PREP(MII_KSZ9031RN_TXD3, tx) | 668 FIELD_PREP(MII_KSZ9031RN_TXD2, tx) | 669 FIELD_PREP(MII_KSZ9031RN_TXD1, tx) | 670 FIELD_PREP(MII_KSZ9031RN_TXD0, tx)); 671 if (ret < 0) 672 return ret; 673 674 return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW, 675 FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) | 676 FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk)); 677 } 678 679 static int ksz9031_config_init(struct phy_device *phydev) 680 { 681 const struct device *dev = &phydev->mdio.dev; 682 const struct device_node *of_node = dev->of_node; 683 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"}; 684 static const char *rx_data_skews[4] = { 685 "rxd0-skew-ps", "rxd1-skew-ps", 686 "rxd2-skew-ps", "rxd3-skew-ps" 687 }; 688 static const char *tx_data_skews[4] = { 689 "txd0-skew-ps", "txd1-skew-ps", 690 "txd2-skew-ps", "txd3-skew-ps" 691 }; 692 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"}; 693 const struct device *dev_walker; 694 int result; 695 696 result = ksz9031_enable_edpd(phydev); 697 if (result < 0) 698 return result; 699 700 /* The Micrel driver has a deprecated option to place phy OF 701 * properties in the MAC node. Walk up the tree of devices to 702 * find a device with an OF node. 703 */ 704 dev_walker = &phydev->mdio.dev; 705 do { 706 of_node = dev_walker->of_node; 707 dev_walker = dev_walker->parent; 708 } while (!of_node && dev_walker); 709 710 if (of_node) { 711 bool update = false; 712 713 if (phy_interface_is_rgmii(phydev)) { 714 result = ksz9031_config_rgmii_delay(phydev); 715 if (result < 0) 716 return result; 717 } 718 719 ksz9031_of_load_skew_values(phydev, of_node, 720 MII_KSZ9031RN_CLK_PAD_SKEW, 5, 721 clk_skews, 2, &update); 722 723 ksz9031_of_load_skew_values(phydev, of_node, 724 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, 725 control_skews, 2, &update); 726 727 ksz9031_of_load_skew_values(phydev, of_node, 728 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, 729 rx_data_skews, 4, &update); 730 731 ksz9031_of_load_skew_values(phydev, of_node, 732 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, 733 tx_data_skews, 4, &update); 734 735 if (update && phydev->interface != PHY_INTERFACE_MODE_RGMII) 736 phydev_warn(phydev, 737 "*-skew-ps values should be used only with phy-mode = \"rgmii\"\n"); 738 739 /* Silicon Errata Sheet (DS80000691D or DS80000692D): 740 * When the device links in the 1000BASE-T slave mode only, 741 * the optional 125MHz reference output clock (CLK125_NDO) 742 * has wide duty cycle variation. 743 * 744 * The optional CLK125_NDO clock does not meet the RGMII 745 * 45/55 percent (min/max) duty cycle requirement and therefore 746 * cannot be used directly by the MAC side for clocking 747 * applications that have setup/hold time requirements on 748 * rising and falling clock edges. 749 * 750 * Workaround: 751 * Force the phy to be the master to receive a stable clock 752 * which meets the duty cycle requirement. 753 */ 754 if (of_property_read_bool(of_node, "micrel,force-master")) { 755 result = phy_read(phydev, MII_CTRL1000); 756 if (result < 0) 757 goto err_force_master; 758 759 /* enable master mode, config & prefer master */ 760 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER; 761 result = phy_write(phydev, MII_CTRL1000, result); 762 if (result < 0) 763 goto err_force_master; 764 } 765 } 766 767 return ksz9031_center_flp_timing(phydev); 768 769 err_force_master: 770 phydev_err(phydev, "failed to force the phy to master mode\n"); 771 return result; 772 } 773 774 #define KSZ9131_SKEW_5BIT_MAX 2400 775 #define KSZ9131_SKEW_4BIT_MAX 800 776 #define KSZ9131_OFFSET 700 777 #define KSZ9131_STEP 100 778 779 static int ksz9131_of_load_skew_values(struct phy_device *phydev, 780 struct device_node *of_node, 781 u16 reg, size_t field_sz, 782 char *field[], u8 numfields) 783 { 784 int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET), 785 -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)}; 786 int skewval, skewmax = 0; 787 int matches = 0; 788 u16 maxval; 789 u16 newval; 790 u16 mask; 791 int i; 792 793 /* psec properties in dts should mean x pico seconds */ 794 if (field_sz == 5) 795 skewmax = KSZ9131_SKEW_5BIT_MAX; 796 else 797 skewmax = KSZ9131_SKEW_4BIT_MAX; 798 799 for (i = 0; i < numfields; i++) 800 if (!of_property_read_s32(of_node, field[i], &skewval)) { 801 if (skewval < -KSZ9131_OFFSET) 802 skewval = -KSZ9131_OFFSET; 803 else if (skewval > skewmax) 804 skewval = skewmax; 805 806 val[i] = skewval + KSZ9131_OFFSET; 807 matches++; 808 } 809 810 if (!matches) 811 return 0; 812 813 if (matches < numfields) 814 newval = phy_read_mmd(phydev, 2, reg); 815 else 816 newval = 0; 817 818 maxval = (field_sz == 4) ? 0xf : 0x1f; 819 for (i = 0; i < numfields; i++) 820 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) { 821 mask = 0xffff; 822 mask ^= maxval << (field_sz * i); 823 newval = (newval & mask) | 824 (((val[i] / KSZ9131_STEP) & maxval) 825 << (field_sz * i)); 826 } 827 828 return phy_write_mmd(phydev, 2, reg, newval); 829 } 830 831 #define KSZ9131RN_MMD_COMMON_CTRL_REG 2 832 #define KSZ9131RN_RXC_DLL_CTRL 76 833 #define KSZ9131RN_TXC_DLL_CTRL 77 834 #define KSZ9131RN_DLL_CTRL_BYPASS BIT_MASK(12) 835 #define KSZ9131RN_DLL_ENABLE_DELAY 0 836 #define KSZ9131RN_DLL_DISABLE_DELAY BIT(12) 837 838 static int ksz9131_config_rgmii_delay(struct phy_device *phydev) 839 { 840 u16 rxcdll_val, txcdll_val; 841 int ret; 842 843 switch (phydev->interface) { 844 case PHY_INTERFACE_MODE_RGMII: 845 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY; 846 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY; 847 break; 848 case PHY_INTERFACE_MODE_RGMII_ID: 849 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; 850 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; 851 break; 852 case PHY_INTERFACE_MODE_RGMII_RXID: 853 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; 854 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY; 855 break; 856 case PHY_INTERFACE_MODE_RGMII_TXID: 857 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY; 858 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; 859 break; 860 default: 861 return 0; 862 } 863 864 ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, 865 KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS, 866 rxcdll_val); 867 if (ret < 0) 868 return ret; 869 870 return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, 871 KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS, 872 txcdll_val); 873 } 874 875 static int ksz9131_config_init(struct phy_device *phydev) 876 { 877 const struct device *dev = &phydev->mdio.dev; 878 struct device_node *of_node = dev->of_node; 879 char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"}; 880 char *rx_data_skews[4] = { 881 "rxd0-skew-psec", "rxd1-skew-psec", 882 "rxd2-skew-psec", "rxd3-skew-psec" 883 }; 884 char *tx_data_skews[4] = { 885 "txd0-skew-psec", "txd1-skew-psec", 886 "txd2-skew-psec", "txd3-skew-psec" 887 }; 888 char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"}; 889 const struct device *dev_walker; 890 int ret; 891 892 dev_walker = &phydev->mdio.dev; 893 do { 894 of_node = dev_walker->of_node; 895 dev_walker = dev_walker->parent; 896 } while (!of_node && dev_walker); 897 898 if (!of_node) 899 return 0; 900 901 if (phy_interface_is_rgmii(phydev)) { 902 ret = ksz9131_config_rgmii_delay(phydev); 903 if (ret < 0) 904 return ret; 905 } 906 907 ret = ksz9131_of_load_skew_values(phydev, of_node, 908 MII_KSZ9031RN_CLK_PAD_SKEW, 5, 909 clk_skews, 2); 910 if (ret < 0) 911 return ret; 912 913 ret = ksz9131_of_load_skew_values(phydev, of_node, 914 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, 915 control_skews, 2); 916 if (ret < 0) 917 return ret; 918 919 ret = ksz9131_of_load_skew_values(phydev, of_node, 920 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, 921 rx_data_skews, 4); 922 if (ret < 0) 923 return ret; 924 925 ret = ksz9131_of_load_skew_values(phydev, of_node, 926 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, 927 tx_data_skews, 4); 928 if (ret < 0) 929 return ret; 930 931 return 0; 932 } 933 934 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06 935 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6) 936 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4) 937 static int ksz8873mll_read_status(struct phy_device *phydev) 938 { 939 int regval; 940 941 /* dummy read */ 942 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 943 944 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 945 946 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX) 947 phydev->duplex = DUPLEX_HALF; 948 else 949 phydev->duplex = DUPLEX_FULL; 950 951 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED) 952 phydev->speed = SPEED_10; 953 else 954 phydev->speed = SPEED_100; 955 956 phydev->link = 1; 957 phydev->pause = phydev->asym_pause = 0; 958 959 return 0; 960 } 961 962 static int ksz9031_get_features(struct phy_device *phydev) 963 { 964 int ret; 965 966 ret = genphy_read_abilities(phydev); 967 if (ret < 0) 968 return ret; 969 970 /* Silicon Errata Sheet (DS80000691D or DS80000692D): 971 * Whenever the device's Asymmetric Pause capability is set to 1, 972 * link-up may fail after a link-up to link-down transition. 973 * 974 * The Errata Sheet is for ksz9031, but ksz9021 has the same issue 975 * 976 * Workaround: 977 * Do not enable the Asymmetric Pause capability bit. 978 */ 979 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported); 980 981 /* We force setting the Pause capability as the core will force the 982 * Asymmetric Pause capability to 1 otherwise. 983 */ 984 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported); 985 986 return 0; 987 } 988 989 static int ksz9031_read_status(struct phy_device *phydev) 990 { 991 int err; 992 int regval; 993 994 err = genphy_read_status(phydev); 995 if (err) 996 return err; 997 998 /* Make sure the PHY is not broken. Read idle error count, 999 * and reset the PHY if it is maxed out. 1000 */ 1001 regval = phy_read(phydev, MII_STAT1000); 1002 if ((regval & 0xFF) == 0xFF) { 1003 phy_init_hw(phydev); 1004 phydev->link = 0; 1005 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev)) 1006 phydev->drv->config_intr(phydev); 1007 return genphy_config_aneg(phydev); 1008 } 1009 1010 return 0; 1011 } 1012 1013 static int ksz8873mll_config_aneg(struct phy_device *phydev) 1014 { 1015 return 0; 1016 } 1017 1018 static int kszphy_get_sset_count(struct phy_device *phydev) 1019 { 1020 return ARRAY_SIZE(kszphy_hw_stats); 1021 } 1022 1023 static void kszphy_get_strings(struct phy_device *phydev, u8 *data) 1024 { 1025 int i; 1026 1027 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) { 1028 strlcpy(data + i * ETH_GSTRING_LEN, 1029 kszphy_hw_stats[i].string, ETH_GSTRING_LEN); 1030 } 1031 } 1032 1033 static u64 kszphy_get_stat(struct phy_device *phydev, int i) 1034 { 1035 struct kszphy_hw_stat stat = kszphy_hw_stats[i]; 1036 struct kszphy_priv *priv = phydev->priv; 1037 int val; 1038 u64 ret; 1039 1040 val = phy_read(phydev, stat.reg); 1041 if (val < 0) { 1042 ret = U64_MAX; 1043 } else { 1044 val = val & ((1 << stat.bits) - 1); 1045 priv->stats[i] += val; 1046 ret = priv->stats[i]; 1047 } 1048 1049 return ret; 1050 } 1051 1052 static void kszphy_get_stats(struct phy_device *phydev, 1053 struct ethtool_stats *stats, u64 *data) 1054 { 1055 int i; 1056 1057 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) 1058 data[i] = kszphy_get_stat(phydev, i); 1059 } 1060 1061 static int kszphy_suspend(struct phy_device *phydev) 1062 { 1063 /* Disable PHY Interrupts */ 1064 if (phy_interrupt_is_valid(phydev)) { 1065 phydev->interrupts = PHY_INTERRUPT_DISABLED; 1066 if (phydev->drv->config_intr) 1067 phydev->drv->config_intr(phydev); 1068 } 1069 1070 return genphy_suspend(phydev); 1071 } 1072 1073 static int kszphy_resume(struct phy_device *phydev) 1074 { 1075 int ret; 1076 1077 genphy_resume(phydev); 1078 1079 /* After switching from power-down to normal mode, an internal global 1080 * reset is automatically generated. Wait a minimum of 1 ms before 1081 * read/write access to the PHY registers. 1082 */ 1083 usleep_range(1000, 2000); 1084 1085 ret = kszphy_config_reset(phydev); 1086 if (ret) 1087 return ret; 1088 1089 /* Enable PHY Interrupts */ 1090 if (phy_interrupt_is_valid(phydev)) { 1091 phydev->interrupts = PHY_INTERRUPT_ENABLED; 1092 if (phydev->drv->config_intr) 1093 phydev->drv->config_intr(phydev); 1094 } 1095 1096 return 0; 1097 } 1098 1099 static int kszphy_probe(struct phy_device *phydev) 1100 { 1101 const struct kszphy_type *type = phydev->drv->driver_data; 1102 const struct device_node *np = phydev->mdio.dev.of_node; 1103 struct kszphy_priv *priv; 1104 struct clk *clk; 1105 int ret; 1106 1107 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 1108 if (!priv) 1109 return -ENOMEM; 1110 1111 phydev->priv = priv; 1112 1113 priv->type = type; 1114 1115 if (type->led_mode_reg) { 1116 ret = of_property_read_u32(np, "micrel,led-mode", 1117 &priv->led_mode); 1118 if (ret) 1119 priv->led_mode = -1; 1120 1121 if (priv->led_mode > 3) { 1122 phydev_err(phydev, "invalid led mode: 0x%02x\n", 1123 priv->led_mode); 1124 priv->led_mode = -1; 1125 } 1126 } else { 1127 priv->led_mode = -1; 1128 } 1129 1130 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref"); 1131 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */ 1132 if (!IS_ERR_OR_NULL(clk)) { 1133 unsigned long rate = clk_get_rate(clk); 1134 bool rmii_ref_clk_sel_25_mhz; 1135 1136 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel; 1137 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np, 1138 "micrel,rmii-reference-clock-select-25-mhz"); 1139 1140 if (rate > 24500000 && rate < 25500000) { 1141 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz; 1142 } else if (rate > 49500000 && rate < 50500000) { 1143 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz; 1144 } else { 1145 phydev_err(phydev, "Clock rate out of range: %ld\n", 1146 rate); 1147 return -EINVAL; 1148 } 1149 } 1150 1151 if (ksz8041_fiber_mode(phydev)) 1152 phydev->port = PORT_FIBRE; 1153 1154 /* Support legacy board-file configuration */ 1155 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) { 1156 priv->rmii_ref_clk_sel = true; 1157 priv->rmii_ref_clk_sel_val = true; 1158 } 1159 1160 return 0; 1161 } 1162 1163 static struct phy_driver ksphy_driver[] = { 1164 { 1165 .phy_id = PHY_ID_KS8737, 1166 .phy_id_mask = MICREL_PHY_ID_MASK, 1167 .name = "Micrel KS8737", 1168 /* PHY_BASIC_FEATURES */ 1169 .driver_data = &ks8737_type, 1170 .config_init = kszphy_config_init, 1171 .ack_interrupt = kszphy_ack_interrupt, 1172 .config_intr = kszphy_config_intr, 1173 .suspend = genphy_suspend, 1174 .resume = genphy_resume, 1175 }, { 1176 .phy_id = PHY_ID_KSZ8021, 1177 .phy_id_mask = 0x00ffffff, 1178 .name = "Micrel KSZ8021 or KSZ8031", 1179 /* PHY_BASIC_FEATURES */ 1180 .driver_data = &ksz8021_type, 1181 .probe = kszphy_probe, 1182 .config_init = kszphy_config_init, 1183 .ack_interrupt = kszphy_ack_interrupt, 1184 .config_intr = kszphy_config_intr, 1185 .get_sset_count = kszphy_get_sset_count, 1186 .get_strings = kszphy_get_strings, 1187 .get_stats = kszphy_get_stats, 1188 .suspend = genphy_suspend, 1189 .resume = genphy_resume, 1190 }, { 1191 .phy_id = PHY_ID_KSZ8031, 1192 .phy_id_mask = 0x00ffffff, 1193 .name = "Micrel KSZ8031", 1194 /* PHY_BASIC_FEATURES */ 1195 .driver_data = &ksz8021_type, 1196 .probe = kszphy_probe, 1197 .config_init = kszphy_config_init, 1198 .ack_interrupt = kszphy_ack_interrupt, 1199 .config_intr = kszphy_config_intr, 1200 .get_sset_count = kszphy_get_sset_count, 1201 .get_strings = kszphy_get_strings, 1202 .get_stats = kszphy_get_stats, 1203 .suspend = genphy_suspend, 1204 .resume = genphy_resume, 1205 }, { 1206 .phy_id = PHY_ID_KSZ8041, 1207 .phy_id_mask = MICREL_PHY_ID_MASK, 1208 .name = "Micrel KSZ8041", 1209 /* PHY_BASIC_FEATURES */ 1210 .driver_data = &ksz8041_type, 1211 .probe = kszphy_probe, 1212 .config_init = ksz8041_config_init, 1213 .config_aneg = ksz8041_config_aneg, 1214 .ack_interrupt = kszphy_ack_interrupt, 1215 .config_intr = kszphy_config_intr, 1216 .get_sset_count = kszphy_get_sset_count, 1217 .get_strings = kszphy_get_strings, 1218 .get_stats = kszphy_get_stats, 1219 .suspend = genphy_suspend, 1220 .resume = genphy_resume, 1221 }, { 1222 .phy_id = PHY_ID_KSZ8041RNLI, 1223 .phy_id_mask = MICREL_PHY_ID_MASK, 1224 .name = "Micrel KSZ8041RNLI", 1225 /* PHY_BASIC_FEATURES */ 1226 .driver_data = &ksz8041_type, 1227 .probe = kszphy_probe, 1228 .config_init = kszphy_config_init, 1229 .ack_interrupt = kszphy_ack_interrupt, 1230 .config_intr = kszphy_config_intr, 1231 .get_sset_count = kszphy_get_sset_count, 1232 .get_strings = kszphy_get_strings, 1233 .get_stats = kszphy_get_stats, 1234 .suspend = genphy_suspend, 1235 .resume = genphy_resume, 1236 }, { 1237 .name = "Micrel KSZ8051", 1238 /* PHY_BASIC_FEATURES */ 1239 .driver_data = &ksz8051_type, 1240 .probe = kszphy_probe, 1241 .config_init = kszphy_config_init, 1242 .ack_interrupt = kszphy_ack_interrupt, 1243 .config_intr = kszphy_config_intr, 1244 .get_sset_count = kszphy_get_sset_count, 1245 .get_strings = kszphy_get_strings, 1246 .get_stats = kszphy_get_stats, 1247 .match_phy_device = ksz8051_match_phy_device, 1248 .suspend = genphy_suspend, 1249 .resume = genphy_resume, 1250 }, { 1251 .phy_id = PHY_ID_KSZ8001, 1252 .name = "Micrel KSZ8001 or KS8721", 1253 .phy_id_mask = 0x00fffffc, 1254 /* PHY_BASIC_FEATURES */ 1255 .driver_data = &ksz8041_type, 1256 .probe = kszphy_probe, 1257 .config_init = kszphy_config_init, 1258 .ack_interrupt = kszphy_ack_interrupt, 1259 .config_intr = kszphy_config_intr, 1260 .get_sset_count = kszphy_get_sset_count, 1261 .get_strings = kszphy_get_strings, 1262 .get_stats = kszphy_get_stats, 1263 .suspend = genphy_suspend, 1264 .resume = genphy_resume, 1265 }, { 1266 .phy_id = PHY_ID_KSZ8081, 1267 .name = "Micrel KSZ8081 or KSZ8091", 1268 .phy_id_mask = MICREL_PHY_ID_MASK, 1269 /* PHY_BASIC_FEATURES */ 1270 .driver_data = &ksz8081_type, 1271 .probe = kszphy_probe, 1272 .config_init = ksz8081_config_init, 1273 .ack_interrupt = kszphy_ack_interrupt, 1274 .soft_reset = genphy_soft_reset, 1275 .config_intr = kszphy_config_intr, 1276 .get_sset_count = kszphy_get_sset_count, 1277 .get_strings = kszphy_get_strings, 1278 .get_stats = kszphy_get_stats, 1279 .suspend = kszphy_suspend, 1280 .resume = kszphy_resume, 1281 }, { 1282 .phy_id = PHY_ID_KSZ8061, 1283 .name = "Micrel KSZ8061", 1284 .phy_id_mask = MICREL_PHY_ID_MASK, 1285 /* PHY_BASIC_FEATURES */ 1286 .config_init = ksz8061_config_init, 1287 .ack_interrupt = kszphy_ack_interrupt, 1288 .config_intr = kszphy_config_intr, 1289 .suspend = genphy_suspend, 1290 .resume = genphy_resume, 1291 }, { 1292 .phy_id = PHY_ID_KSZ9021, 1293 .phy_id_mask = 0x000ffffe, 1294 .name = "Micrel KSZ9021 Gigabit PHY", 1295 /* PHY_GBIT_FEATURES */ 1296 .driver_data = &ksz9021_type, 1297 .probe = kszphy_probe, 1298 .get_features = ksz9031_get_features, 1299 .config_init = ksz9021_config_init, 1300 .ack_interrupt = kszphy_ack_interrupt, 1301 .config_intr = kszphy_config_intr, 1302 .get_sset_count = kszphy_get_sset_count, 1303 .get_strings = kszphy_get_strings, 1304 .get_stats = kszphy_get_stats, 1305 .suspend = genphy_suspend, 1306 .resume = genphy_resume, 1307 .read_mmd = genphy_read_mmd_unsupported, 1308 .write_mmd = genphy_write_mmd_unsupported, 1309 }, { 1310 .phy_id = PHY_ID_KSZ9031, 1311 .phy_id_mask = MICREL_PHY_ID_MASK, 1312 .name = "Micrel KSZ9031 Gigabit PHY", 1313 .driver_data = &ksz9021_type, 1314 .probe = kszphy_probe, 1315 .get_features = ksz9031_get_features, 1316 .config_init = ksz9031_config_init, 1317 .soft_reset = genphy_soft_reset, 1318 .read_status = ksz9031_read_status, 1319 .ack_interrupt = kszphy_ack_interrupt, 1320 .config_intr = kszphy_config_intr, 1321 .get_sset_count = kszphy_get_sset_count, 1322 .get_strings = kszphy_get_strings, 1323 .get_stats = kszphy_get_stats, 1324 .suspend = genphy_suspend, 1325 .resume = kszphy_resume, 1326 }, { 1327 .phy_id = PHY_ID_LAN8814, 1328 .phy_id_mask = MICREL_PHY_ID_MASK, 1329 .name = "Microchip INDY Gigabit Quad PHY", 1330 .driver_data = &ksz9021_type, 1331 .probe = kszphy_probe, 1332 .soft_reset = genphy_soft_reset, 1333 .read_status = ksz9031_read_status, 1334 .get_sset_count = kszphy_get_sset_count, 1335 .get_strings = kszphy_get_strings, 1336 .get_stats = kszphy_get_stats, 1337 .suspend = genphy_suspend, 1338 .resume = kszphy_resume, 1339 }, { 1340 .phy_id = PHY_ID_KSZ9131, 1341 .phy_id_mask = MICREL_PHY_ID_MASK, 1342 .name = "Microchip KSZ9131 Gigabit PHY", 1343 /* PHY_GBIT_FEATURES */ 1344 .driver_data = &ksz9021_type, 1345 .probe = kszphy_probe, 1346 .config_init = ksz9131_config_init, 1347 .read_status = genphy_read_status, 1348 .ack_interrupt = kszphy_ack_interrupt, 1349 .config_intr = kszphy_config_intr, 1350 .get_sset_count = kszphy_get_sset_count, 1351 .get_strings = kszphy_get_strings, 1352 .get_stats = kszphy_get_stats, 1353 .suspend = genphy_suspend, 1354 .resume = kszphy_resume, 1355 }, { 1356 .phy_id = PHY_ID_KSZ8873MLL, 1357 .phy_id_mask = MICREL_PHY_ID_MASK, 1358 .name = "Micrel KSZ8873MLL Switch", 1359 /* PHY_BASIC_FEATURES */ 1360 .config_init = kszphy_config_init, 1361 .config_aneg = ksz8873mll_config_aneg, 1362 .read_status = ksz8873mll_read_status, 1363 .suspend = genphy_suspend, 1364 .resume = genphy_resume, 1365 }, { 1366 .phy_id = PHY_ID_KSZ886X, 1367 .phy_id_mask = MICREL_PHY_ID_MASK, 1368 .name = "Micrel KSZ886X Switch", 1369 /* PHY_BASIC_FEATURES */ 1370 .config_init = kszphy_config_init, 1371 .suspend = genphy_suspend, 1372 .resume = genphy_resume, 1373 }, { 1374 .name = "Micrel KSZ87XX Switch", 1375 /* PHY_BASIC_FEATURES */ 1376 .config_init = kszphy_config_init, 1377 .match_phy_device = ksz8795_match_phy_device, 1378 .suspend = genphy_suspend, 1379 .resume = genphy_resume, 1380 }, { 1381 .phy_id = PHY_ID_KSZ9477, 1382 .phy_id_mask = MICREL_PHY_ID_MASK, 1383 .name = "Microchip KSZ9477", 1384 /* PHY_GBIT_FEATURES */ 1385 .config_init = kszphy_config_init, 1386 .suspend = genphy_suspend, 1387 .resume = genphy_resume, 1388 } }; 1389 1390 module_phy_driver(ksphy_driver); 1391 1392 MODULE_DESCRIPTION("Micrel PHY driver"); 1393 MODULE_AUTHOR("David J. Choi"); 1394 MODULE_LICENSE("GPL"); 1395 1396 static struct mdio_device_id __maybe_unused micrel_tbl[] = { 1397 { PHY_ID_KSZ9021, 0x000ffffe }, 1398 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK }, 1399 { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK }, 1400 { PHY_ID_KSZ8001, 0x00fffffc }, 1401 { PHY_ID_KS8737, MICREL_PHY_ID_MASK }, 1402 { PHY_ID_KSZ8021, 0x00ffffff }, 1403 { PHY_ID_KSZ8031, 0x00ffffff }, 1404 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK }, 1405 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK }, 1406 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK }, 1407 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK }, 1408 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK }, 1409 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK }, 1410 { PHY_ID_LAN8814, MICREL_PHY_ID_MASK }, 1411 { } 1412 }; 1413 1414 MODULE_DEVICE_TABLE(mdio, micrel_tbl); 1415