1 /* 2 * drivers/net/phy/micrel.c 3 * 4 * Driver for Micrel PHYs 5 * 6 * Author: David J. Choi 7 * 8 * Copyright (c) 2010-2013 Micrel, Inc. 9 * Copyright (c) 2014 Johan Hovold <johan@kernel.org> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * Support : Micrel Phys: 17 * Giga phys: ksz9021, ksz9031 18 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041 19 * ksz8021, ksz8031, ksz8051, 20 * ksz8081, ksz8091, 21 * ksz8061, 22 * Switch : ksz8873, ksz886x 23 */ 24 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/phy.h> 28 #include <linux/micrel_phy.h> 29 #include <linux/of.h> 30 #include <linux/clk.h> 31 32 /* Operation Mode Strap Override */ 33 #define MII_KSZPHY_OMSO 0x16 34 #define KSZPHY_OMSO_B_CAST_OFF BIT(9) 35 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5) 36 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1) 37 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0) 38 39 /* general Interrupt control/status reg in vendor specific block. */ 40 #define MII_KSZPHY_INTCS 0x1B 41 #define KSZPHY_INTCS_JABBER BIT(15) 42 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14) 43 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13) 44 #define KSZPHY_INTCS_PARELLEL BIT(12) 45 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11) 46 #define KSZPHY_INTCS_LINK_DOWN BIT(10) 47 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9) 48 #define KSZPHY_INTCS_LINK_UP BIT(8) 49 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\ 50 KSZPHY_INTCS_LINK_DOWN) 51 52 /* PHY Control 1 */ 53 #define MII_KSZPHY_CTRL_1 0x1e 54 55 /* PHY Control 2 / PHY Control (if no PHY Control 1) */ 56 #define MII_KSZPHY_CTRL_2 0x1f 57 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2 58 /* bitmap of PHY register to set interrupt mode */ 59 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9) 60 #define KSZPHY_RMII_REF_CLK_SEL BIT(7) 61 62 /* Write/read to/from extended registers */ 63 #define MII_KSZPHY_EXTREG 0x0b 64 #define KSZPHY_EXTREG_WRITE 0x8000 65 66 #define MII_KSZPHY_EXTREG_WRITE 0x0c 67 #define MII_KSZPHY_EXTREG_READ 0x0d 68 69 /* Extended registers */ 70 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104 71 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105 72 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106 73 74 #define PS_TO_REG 200 75 76 struct kszphy_hw_stat { 77 const char *string; 78 u8 reg; 79 u8 bits; 80 }; 81 82 static struct kszphy_hw_stat kszphy_hw_stats[] = { 83 { "phy_receive_errors", 21, 16}, 84 { "phy_idle_errors", 10, 8 }, 85 }; 86 87 struct kszphy_type { 88 u32 led_mode_reg; 89 u16 interrupt_level_mask; 90 bool has_broadcast_disable; 91 bool has_nand_tree_disable; 92 bool has_rmii_ref_clk_sel; 93 }; 94 95 struct kszphy_priv { 96 const struct kszphy_type *type; 97 int led_mode; 98 bool rmii_ref_clk_sel; 99 bool rmii_ref_clk_sel_val; 100 u64 stats[ARRAY_SIZE(kszphy_hw_stats)]; 101 }; 102 103 static const struct kszphy_type ksz8021_type = { 104 .led_mode_reg = MII_KSZPHY_CTRL_2, 105 .has_broadcast_disable = true, 106 .has_nand_tree_disable = true, 107 .has_rmii_ref_clk_sel = true, 108 }; 109 110 static const struct kszphy_type ksz8041_type = { 111 .led_mode_reg = MII_KSZPHY_CTRL_1, 112 }; 113 114 static const struct kszphy_type ksz8051_type = { 115 .led_mode_reg = MII_KSZPHY_CTRL_2, 116 .has_nand_tree_disable = true, 117 }; 118 119 static const struct kszphy_type ksz8081_type = { 120 .led_mode_reg = MII_KSZPHY_CTRL_2, 121 .has_broadcast_disable = true, 122 .has_nand_tree_disable = true, 123 .has_rmii_ref_clk_sel = true, 124 }; 125 126 static const struct kszphy_type ks8737_type = { 127 .interrupt_level_mask = BIT(14), 128 }; 129 130 static const struct kszphy_type ksz9021_type = { 131 .interrupt_level_mask = BIT(14), 132 }; 133 134 static int kszphy_extended_write(struct phy_device *phydev, 135 u32 regnum, u16 val) 136 { 137 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum); 138 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); 139 } 140 141 static int kszphy_extended_read(struct phy_device *phydev, 142 u32 regnum) 143 { 144 phy_write(phydev, MII_KSZPHY_EXTREG, regnum); 145 return phy_read(phydev, MII_KSZPHY_EXTREG_READ); 146 } 147 148 static int kszphy_ack_interrupt(struct phy_device *phydev) 149 { 150 /* bit[7..0] int status, which is a read and clear register. */ 151 int rc; 152 153 rc = phy_read(phydev, MII_KSZPHY_INTCS); 154 155 return (rc < 0) ? rc : 0; 156 } 157 158 static int kszphy_config_intr(struct phy_device *phydev) 159 { 160 const struct kszphy_type *type = phydev->drv->driver_data; 161 int temp; 162 u16 mask; 163 164 if (type && type->interrupt_level_mask) 165 mask = type->interrupt_level_mask; 166 else 167 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH; 168 169 /* set the interrupt pin active low */ 170 temp = phy_read(phydev, MII_KSZPHY_CTRL); 171 if (temp < 0) 172 return temp; 173 temp &= ~mask; 174 phy_write(phydev, MII_KSZPHY_CTRL, temp); 175 176 /* enable / disable interrupts */ 177 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 178 temp = KSZPHY_INTCS_ALL; 179 else 180 temp = 0; 181 182 return phy_write(phydev, MII_KSZPHY_INTCS, temp); 183 } 184 185 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val) 186 { 187 int ctrl; 188 189 ctrl = phy_read(phydev, MII_KSZPHY_CTRL); 190 if (ctrl < 0) 191 return ctrl; 192 193 if (val) 194 ctrl |= KSZPHY_RMII_REF_CLK_SEL; 195 else 196 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL; 197 198 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl); 199 } 200 201 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val) 202 { 203 int rc, temp, shift; 204 205 switch (reg) { 206 case MII_KSZPHY_CTRL_1: 207 shift = 14; 208 break; 209 case MII_KSZPHY_CTRL_2: 210 shift = 4; 211 break; 212 default: 213 return -EINVAL; 214 } 215 216 temp = phy_read(phydev, reg); 217 if (temp < 0) { 218 rc = temp; 219 goto out; 220 } 221 222 temp &= ~(3 << shift); 223 temp |= val << shift; 224 rc = phy_write(phydev, reg, temp); 225 out: 226 if (rc < 0) 227 phydev_err(phydev, "failed to set led mode\n"); 228 229 return rc; 230 } 231 232 /* Disable PHY address 0 as the broadcast address, so that it can be used as a 233 * unique (non-broadcast) address on a shared bus. 234 */ 235 static int kszphy_broadcast_disable(struct phy_device *phydev) 236 { 237 int ret; 238 239 ret = phy_read(phydev, MII_KSZPHY_OMSO); 240 if (ret < 0) 241 goto out; 242 243 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF); 244 out: 245 if (ret) 246 phydev_err(phydev, "failed to disable broadcast address\n"); 247 248 return ret; 249 } 250 251 static int kszphy_nand_tree_disable(struct phy_device *phydev) 252 { 253 int ret; 254 255 ret = phy_read(phydev, MII_KSZPHY_OMSO); 256 if (ret < 0) 257 goto out; 258 259 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON)) 260 return 0; 261 262 ret = phy_write(phydev, MII_KSZPHY_OMSO, 263 ret & ~KSZPHY_OMSO_NAND_TREE_ON); 264 out: 265 if (ret) 266 phydev_err(phydev, "failed to disable NAND tree mode\n"); 267 268 return ret; 269 } 270 271 static int kszphy_config_init(struct phy_device *phydev) 272 { 273 struct kszphy_priv *priv = phydev->priv; 274 const struct kszphy_type *type; 275 int ret; 276 277 if (!priv) 278 return 0; 279 280 type = priv->type; 281 282 if (type->has_broadcast_disable) 283 kszphy_broadcast_disable(phydev); 284 285 if (type->has_nand_tree_disable) 286 kszphy_nand_tree_disable(phydev); 287 288 if (priv->rmii_ref_clk_sel) { 289 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val); 290 if (ret) { 291 phydev_err(phydev, 292 "failed to set rmii reference clock\n"); 293 return ret; 294 } 295 } 296 297 if (priv->led_mode >= 0) 298 kszphy_setup_led(phydev, type->led_mode_reg, priv->led_mode); 299 300 if (phy_interrupt_is_valid(phydev)) { 301 int ctl = phy_read(phydev, MII_BMCR); 302 303 if (ctl < 0) 304 return ctl; 305 306 ret = phy_write(phydev, MII_BMCR, ctl & ~BMCR_ANENABLE); 307 if (ret < 0) 308 return ret; 309 } 310 311 return 0; 312 } 313 314 static int ksz8041_config_init(struct phy_device *phydev) 315 { 316 struct device_node *of_node = phydev->mdio.dev.of_node; 317 318 /* Limit supported and advertised modes in fiber mode */ 319 if (of_property_read_bool(of_node, "micrel,fiber-mode")) { 320 phydev->dev_flags |= MICREL_PHY_FXEN; 321 phydev->supported &= SUPPORTED_FIBRE | 322 SUPPORTED_100baseT_Full | 323 SUPPORTED_100baseT_Half; 324 phydev->advertising &= ADVERTISED_FIBRE | 325 ADVERTISED_100baseT_Full | 326 ADVERTISED_100baseT_Half; 327 phydev->autoneg = AUTONEG_DISABLE; 328 } 329 330 return kszphy_config_init(phydev); 331 } 332 333 static int ksz8041_config_aneg(struct phy_device *phydev) 334 { 335 /* Skip auto-negotiation in fiber mode */ 336 if (phydev->dev_flags & MICREL_PHY_FXEN) { 337 phydev->speed = SPEED_100; 338 return 0; 339 } 340 341 return genphy_config_aneg(phydev); 342 } 343 344 static int ksz9021_load_values_from_of(struct phy_device *phydev, 345 const struct device_node *of_node, 346 u16 reg, 347 const char *field1, const char *field2, 348 const char *field3, const char *field4) 349 { 350 int val1 = -1; 351 int val2 = -2; 352 int val3 = -3; 353 int val4 = -4; 354 int newval; 355 int matches = 0; 356 357 if (!of_property_read_u32(of_node, field1, &val1)) 358 matches++; 359 360 if (!of_property_read_u32(of_node, field2, &val2)) 361 matches++; 362 363 if (!of_property_read_u32(of_node, field3, &val3)) 364 matches++; 365 366 if (!of_property_read_u32(of_node, field4, &val4)) 367 matches++; 368 369 if (!matches) 370 return 0; 371 372 if (matches < 4) 373 newval = kszphy_extended_read(phydev, reg); 374 else 375 newval = 0; 376 377 if (val1 != -1) 378 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0); 379 380 if (val2 != -2) 381 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4); 382 383 if (val3 != -3) 384 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8); 385 386 if (val4 != -4) 387 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12); 388 389 return kszphy_extended_write(phydev, reg, newval); 390 } 391 392 static int ksz9021_config_init(struct phy_device *phydev) 393 { 394 const struct device *dev = &phydev->mdio.dev; 395 const struct device_node *of_node = dev->of_node; 396 const struct device *dev_walker; 397 398 /* The Micrel driver has a deprecated option to place phy OF 399 * properties in the MAC node. Walk up the tree of devices to 400 * find a device with an OF node. 401 */ 402 dev_walker = &phydev->mdio.dev; 403 do { 404 of_node = dev_walker->of_node; 405 dev_walker = dev_walker->parent; 406 407 } while (!of_node && dev_walker); 408 409 if (of_node) { 410 ksz9021_load_values_from_of(phydev, of_node, 411 MII_KSZPHY_CLK_CONTROL_PAD_SKEW, 412 "txen-skew-ps", "txc-skew-ps", 413 "rxdv-skew-ps", "rxc-skew-ps"); 414 ksz9021_load_values_from_of(phydev, of_node, 415 MII_KSZPHY_RX_DATA_PAD_SKEW, 416 "rxd0-skew-ps", "rxd1-skew-ps", 417 "rxd2-skew-ps", "rxd3-skew-ps"); 418 ksz9021_load_values_from_of(phydev, of_node, 419 MII_KSZPHY_TX_DATA_PAD_SKEW, 420 "txd0-skew-ps", "txd1-skew-ps", 421 "txd2-skew-ps", "txd3-skew-ps"); 422 } 423 return 0; 424 } 425 426 #define MII_KSZ9031RN_MMD_CTRL_REG 0x0d 427 #define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e 428 #define OP_DATA 1 429 #define KSZ9031_PS_TO_REG 60 430 431 /* Extended registers */ 432 /* MMD Address 0x0 */ 433 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3 434 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4 435 436 /* MMD Address 0x2 */ 437 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4 438 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5 439 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6 440 #define MII_KSZ9031RN_CLK_PAD_SKEW 8 441 442 static int ksz9031_extended_write(struct phy_device *phydev, 443 u8 mode, u32 dev_addr, u32 regnum, u16 val) 444 { 445 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr); 446 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum); 447 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr); 448 return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val); 449 } 450 451 static int ksz9031_extended_read(struct phy_device *phydev, 452 u8 mode, u32 dev_addr, u32 regnum) 453 { 454 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr); 455 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum); 456 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr); 457 return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG); 458 } 459 460 static int ksz9031_of_load_skew_values(struct phy_device *phydev, 461 const struct device_node *of_node, 462 u16 reg, size_t field_sz, 463 const char *field[], u8 numfields) 464 { 465 int val[4] = {-1, -2, -3, -4}; 466 int matches = 0; 467 u16 mask; 468 u16 maxval; 469 u16 newval; 470 int i; 471 472 for (i = 0; i < numfields; i++) 473 if (!of_property_read_u32(of_node, field[i], val + i)) 474 matches++; 475 476 if (!matches) 477 return 0; 478 479 if (matches < numfields) 480 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg); 481 else 482 newval = 0; 483 484 maxval = (field_sz == 4) ? 0xf : 0x1f; 485 for (i = 0; i < numfields; i++) 486 if (val[i] != -(i + 1)) { 487 mask = 0xffff; 488 mask ^= maxval << (field_sz * i); 489 newval = (newval & mask) | 490 (((val[i] / KSZ9031_PS_TO_REG) & maxval) 491 << (field_sz * i)); 492 } 493 494 return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval); 495 } 496 497 static int ksz9031_center_flp_timing(struct phy_device *phydev) 498 { 499 int result; 500 501 /* Center KSZ9031RNX FLP timing at 16ms. */ 502 result = ksz9031_extended_write(phydev, OP_DATA, 0, 503 MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006); 504 result = ksz9031_extended_write(phydev, OP_DATA, 0, 505 MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80); 506 507 if (result) 508 return result; 509 510 return genphy_restart_aneg(phydev); 511 } 512 513 static int ksz9031_config_init(struct phy_device *phydev) 514 { 515 const struct device *dev = &phydev->mdio.dev; 516 const struct device_node *of_node = dev->of_node; 517 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"}; 518 static const char *rx_data_skews[4] = { 519 "rxd0-skew-ps", "rxd1-skew-ps", 520 "rxd2-skew-ps", "rxd3-skew-ps" 521 }; 522 static const char *tx_data_skews[4] = { 523 "txd0-skew-ps", "txd1-skew-ps", 524 "txd2-skew-ps", "txd3-skew-ps" 525 }; 526 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"}; 527 const struct device *dev_walker; 528 529 /* The Micrel driver has a deprecated option to place phy OF 530 * properties in the MAC node. Walk up the tree of devices to 531 * find a device with an OF node. 532 */ 533 dev_walker = &phydev->mdio.dev; 534 do { 535 of_node = dev_walker->of_node; 536 dev_walker = dev_walker->parent; 537 } while (!of_node && dev_walker); 538 539 if (of_node) { 540 ksz9031_of_load_skew_values(phydev, of_node, 541 MII_KSZ9031RN_CLK_PAD_SKEW, 5, 542 clk_skews, 2); 543 544 ksz9031_of_load_skew_values(phydev, of_node, 545 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, 546 control_skews, 2); 547 548 ksz9031_of_load_skew_values(phydev, of_node, 549 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, 550 rx_data_skews, 4); 551 552 ksz9031_of_load_skew_values(phydev, of_node, 553 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, 554 tx_data_skews, 4); 555 } 556 557 return ksz9031_center_flp_timing(phydev); 558 } 559 560 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06 561 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6) 562 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4) 563 static int ksz8873mll_read_status(struct phy_device *phydev) 564 { 565 int regval; 566 567 /* dummy read */ 568 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 569 570 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 571 572 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX) 573 phydev->duplex = DUPLEX_HALF; 574 else 575 phydev->duplex = DUPLEX_FULL; 576 577 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED) 578 phydev->speed = SPEED_10; 579 else 580 phydev->speed = SPEED_100; 581 582 phydev->link = 1; 583 phydev->pause = phydev->asym_pause = 0; 584 585 return 0; 586 } 587 588 static int ksz9031_read_status(struct phy_device *phydev) 589 { 590 int err; 591 int regval; 592 593 err = genphy_read_status(phydev); 594 if (err) 595 return err; 596 597 /* Make sure the PHY is not broken. Read idle error count, 598 * and reset the PHY if it is maxed out. 599 */ 600 regval = phy_read(phydev, MII_STAT1000); 601 if ((regval & 0xFF) == 0xFF) { 602 phy_init_hw(phydev); 603 phydev->link = 0; 604 } 605 606 return 0; 607 } 608 609 static int ksz8873mll_config_aneg(struct phy_device *phydev) 610 { 611 return 0; 612 } 613 614 /* This routine returns -1 as an indication to the caller that the 615 * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE 616 * MMD extended PHY registers. 617 */ 618 static int 619 ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum, 620 int regnum) 621 { 622 return -1; 623 } 624 625 /* This routine does nothing since the Micrel ksz9021 does not support 626 * standard IEEE MMD extended PHY registers. 627 */ 628 static void 629 ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum, 630 int regnum, u32 val) 631 { 632 } 633 634 static int kszphy_get_sset_count(struct phy_device *phydev) 635 { 636 return ARRAY_SIZE(kszphy_hw_stats); 637 } 638 639 static void kszphy_get_strings(struct phy_device *phydev, u8 *data) 640 { 641 int i; 642 643 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) { 644 memcpy(data + i * ETH_GSTRING_LEN, 645 kszphy_hw_stats[i].string, ETH_GSTRING_LEN); 646 } 647 } 648 649 #ifndef UINT64_MAX 650 #define UINT64_MAX (u64)(~((u64)0)) 651 #endif 652 static u64 kszphy_get_stat(struct phy_device *phydev, int i) 653 { 654 struct kszphy_hw_stat stat = kszphy_hw_stats[i]; 655 struct kszphy_priv *priv = phydev->priv; 656 int val; 657 u64 ret; 658 659 val = phy_read(phydev, stat.reg); 660 if (val < 0) { 661 ret = UINT64_MAX; 662 } else { 663 val = val & ((1 << stat.bits) - 1); 664 priv->stats[i] += val; 665 ret = priv->stats[i]; 666 } 667 668 return ret; 669 } 670 671 static void kszphy_get_stats(struct phy_device *phydev, 672 struct ethtool_stats *stats, u64 *data) 673 { 674 int i; 675 676 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) 677 data[i] = kszphy_get_stat(phydev, i); 678 } 679 680 static int kszphy_resume(struct phy_device *phydev) 681 { 682 int value; 683 684 mutex_lock(&phydev->lock); 685 686 value = phy_read(phydev, MII_BMCR); 687 phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN); 688 689 kszphy_config_intr(phydev); 690 mutex_unlock(&phydev->lock); 691 692 return 0; 693 } 694 695 static int kszphy_probe(struct phy_device *phydev) 696 { 697 const struct kszphy_type *type = phydev->drv->driver_data; 698 const struct device_node *np = phydev->mdio.dev.of_node; 699 struct kszphy_priv *priv; 700 struct clk *clk; 701 int ret; 702 703 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 704 if (!priv) 705 return -ENOMEM; 706 707 phydev->priv = priv; 708 709 priv->type = type; 710 711 if (type->led_mode_reg) { 712 ret = of_property_read_u32(np, "micrel,led-mode", 713 &priv->led_mode); 714 if (ret) 715 priv->led_mode = -1; 716 717 if (priv->led_mode > 3) { 718 phydev_err(phydev, "invalid led mode: 0x%02x\n", 719 priv->led_mode); 720 priv->led_mode = -1; 721 } 722 } else { 723 priv->led_mode = -1; 724 } 725 726 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref"); 727 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */ 728 if (!IS_ERR_OR_NULL(clk)) { 729 unsigned long rate = clk_get_rate(clk); 730 bool rmii_ref_clk_sel_25_mhz; 731 732 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel; 733 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np, 734 "micrel,rmii-reference-clock-select-25-mhz"); 735 736 if (rate > 24500000 && rate < 25500000) { 737 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz; 738 } else if (rate > 49500000 && rate < 50500000) { 739 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz; 740 } else { 741 phydev_err(phydev, "Clock rate out of range: %ld\n", 742 rate); 743 return -EINVAL; 744 } 745 } 746 747 /* Support legacy board-file configuration */ 748 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) { 749 priv->rmii_ref_clk_sel = true; 750 priv->rmii_ref_clk_sel_val = true; 751 } 752 753 return 0; 754 } 755 756 static struct phy_driver ksphy_driver[] = { 757 { 758 .phy_id = PHY_ID_KS8737, 759 .phy_id_mask = MICREL_PHY_ID_MASK, 760 .name = "Micrel KS8737", 761 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), 762 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 763 .driver_data = &ks8737_type, 764 .config_init = kszphy_config_init, 765 .config_aneg = genphy_config_aneg, 766 .read_status = genphy_read_status, 767 .ack_interrupt = kszphy_ack_interrupt, 768 .config_intr = kszphy_config_intr, 769 .get_sset_count = kszphy_get_sset_count, 770 .get_strings = kszphy_get_strings, 771 .get_stats = kszphy_get_stats, 772 .suspend = genphy_suspend, 773 .resume = genphy_resume, 774 }, { 775 .phy_id = PHY_ID_KSZ8021, 776 .phy_id_mask = 0x00ffffff, 777 .name = "Micrel KSZ8021 or KSZ8031", 778 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause | 779 SUPPORTED_Asym_Pause), 780 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 781 .driver_data = &ksz8021_type, 782 .probe = kszphy_probe, 783 .config_init = kszphy_config_init, 784 .config_aneg = genphy_config_aneg, 785 .read_status = genphy_read_status, 786 .ack_interrupt = kszphy_ack_interrupt, 787 .config_intr = kszphy_config_intr, 788 .get_sset_count = kszphy_get_sset_count, 789 .get_strings = kszphy_get_strings, 790 .get_stats = kszphy_get_stats, 791 .suspend = genphy_suspend, 792 .resume = genphy_resume, 793 }, { 794 .phy_id = PHY_ID_KSZ8031, 795 .phy_id_mask = 0x00ffffff, 796 .name = "Micrel KSZ8031", 797 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause | 798 SUPPORTED_Asym_Pause), 799 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 800 .driver_data = &ksz8021_type, 801 .probe = kszphy_probe, 802 .config_init = kszphy_config_init, 803 .config_aneg = genphy_config_aneg, 804 .read_status = genphy_read_status, 805 .ack_interrupt = kszphy_ack_interrupt, 806 .config_intr = kszphy_config_intr, 807 .get_sset_count = kszphy_get_sset_count, 808 .get_strings = kszphy_get_strings, 809 .get_stats = kszphy_get_stats, 810 .suspend = genphy_suspend, 811 .resume = genphy_resume, 812 }, { 813 .phy_id = PHY_ID_KSZ8041, 814 .phy_id_mask = MICREL_PHY_ID_MASK, 815 .name = "Micrel KSZ8041", 816 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause 817 | SUPPORTED_Asym_Pause), 818 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 819 .driver_data = &ksz8041_type, 820 .probe = kszphy_probe, 821 .config_init = ksz8041_config_init, 822 .config_aneg = ksz8041_config_aneg, 823 .read_status = genphy_read_status, 824 .ack_interrupt = kszphy_ack_interrupt, 825 .config_intr = kszphy_config_intr, 826 .get_sset_count = kszphy_get_sset_count, 827 .get_strings = kszphy_get_strings, 828 .get_stats = kszphy_get_stats, 829 .suspend = genphy_suspend, 830 .resume = genphy_resume, 831 }, { 832 .phy_id = PHY_ID_KSZ8041RNLI, 833 .phy_id_mask = MICREL_PHY_ID_MASK, 834 .name = "Micrel KSZ8041RNLI", 835 .features = PHY_BASIC_FEATURES | 836 SUPPORTED_Pause | SUPPORTED_Asym_Pause, 837 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 838 .driver_data = &ksz8041_type, 839 .probe = kszphy_probe, 840 .config_init = kszphy_config_init, 841 .config_aneg = genphy_config_aneg, 842 .read_status = genphy_read_status, 843 .ack_interrupt = kszphy_ack_interrupt, 844 .config_intr = kszphy_config_intr, 845 .get_sset_count = kszphy_get_sset_count, 846 .get_strings = kszphy_get_strings, 847 .get_stats = kszphy_get_stats, 848 .suspend = genphy_suspend, 849 .resume = genphy_resume, 850 }, { 851 .phy_id = PHY_ID_KSZ8051, 852 .phy_id_mask = MICREL_PHY_ID_MASK, 853 .name = "Micrel KSZ8051", 854 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause 855 | SUPPORTED_Asym_Pause), 856 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 857 .driver_data = &ksz8051_type, 858 .probe = kszphy_probe, 859 .config_init = kszphy_config_init, 860 .config_aneg = genphy_config_aneg, 861 .read_status = genphy_read_status, 862 .ack_interrupt = kszphy_ack_interrupt, 863 .config_intr = kszphy_config_intr, 864 .get_sset_count = kszphy_get_sset_count, 865 .get_strings = kszphy_get_strings, 866 .get_stats = kszphy_get_stats, 867 .suspend = genphy_suspend, 868 .resume = genphy_resume, 869 }, { 870 .phy_id = PHY_ID_KSZ8001, 871 .name = "Micrel KSZ8001 or KS8721", 872 .phy_id_mask = 0x00fffffc, 873 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), 874 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 875 .driver_data = &ksz8041_type, 876 .probe = kszphy_probe, 877 .config_init = kszphy_config_init, 878 .config_aneg = genphy_config_aneg, 879 .read_status = genphy_read_status, 880 .ack_interrupt = kszphy_ack_interrupt, 881 .config_intr = kszphy_config_intr, 882 .get_sset_count = kszphy_get_sset_count, 883 .get_strings = kszphy_get_strings, 884 .get_stats = kszphy_get_stats, 885 .suspend = genphy_suspend, 886 .resume = genphy_resume, 887 }, { 888 .phy_id = PHY_ID_KSZ8081, 889 .name = "Micrel KSZ8081 or KSZ8091", 890 .phy_id_mask = MICREL_PHY_ID_MASK, 891 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), 892 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 893 .driver_data = &ksz8081_type, 894 .probe = kszphy_probe, 895 .config_init = kszphy_config_init, 896 .config_aneg = genphy_config_aneg, 897 .read_status = genphy_read_status, 898 .ack_interrupt = kszphy_ack_interrupt, 899 .config_intr = kszphy_config_intr, 900 .get_sset_count = kszphy_get_sset_count, 901 .get_strings = kszphy_get_strings, 902 .get_stats = kszphy_get_stats, 903 .suspend = genphy_suspend, 904 .resume = kszphy_resume, 905 }, { 906 .phy_id = PHY_ID_KSZ8061, 907 .name = "Micrel KSZ8061", 908 .phy_id_mask = MICREL_PHY_ID_MASK, 909 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), 910 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 911 .config_init = kszphy_config_init, 912 .config_aneg = genphy_config_aneg, 913 .read_status = genphy_read_status, 914 .ack_interrupt = kszphy_ack_interrupt, 915 .config_intr = kszphy_config_intr, 916 .get_sset_count = kszphy_get_sset_count, 917 .get_strings = kszphy_get_strings, 918 .get_stats = kszphy_get_stats, 919 .suspend = genphy_suspend, 920 .resume = genphy_resume, 921 }, { 922 .phy_id = PHY_ID_KSZ9021, 923 .phy_id_mask = 0x000ffffe, 924 .name = "Micrel KSZ9021 Gigabit PHY", 925 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause), 926 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 927 .driver_data = &ksz9021_type, 928 .config_init = ksz9021_config_init, 929 .config_aneg = genphy_config_aneg, 930 .read_status = genphy_read_status, 931 .ack_interrupt = kszphy_ack_interrupt, 932 .config_intr = kszphy_config_intr, 933 .get_sset_count = kszphy_get_sset_count, 934 .get_strings = kszphy_get_strings, 935 .get_stats = kszphy_get_stats, 936 .suspend = genphy_suspend, 937 .resume = genphy_resume, 938 .read_mmd_indirect = ksz9021_rd_mmd_phyreg, 939 .write_mmd_indirect = ksz9021_wr_mmd_phyreg, 940 }, { 941 .phy_id = PHY_ID_KSZ9031, 942 .phy_id_mask = MICREL_PHY_ID_MASK, 943 .name = "Micrel KSZ9031 Gigabit PHY", 944 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause), 945 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 946 .driver_data = &ksz9021_type, 947 .config_init = ksz9031_config_init, 948 .config_aneg = genphy_config_aneg, 949 .read_status = ksz9031_read_status, 950 .ack_interrupt = kszphy_ack_interrupt, 951 .config_intr = kszphy_config_intr, 952 .get_sset_count = kszphy_get_sset_count, 953 .get_strings = kszphy_get_strings, 954 .get_stats = kszphy_get_stats, 955 .suspend = genphy_suspend, 956 .resume = genphy_resume, 957 }, { 958 .phy_id = PHY_ID_KSZ8873MLL, 959 .phy_id_mask = MICREL_PHY_ID_MASK, 960 .name = "Micrel KSZ8873MLL Switch", 961 .features = (SUPPORTED_Pause | SUPPORTED_Asym_Pause), 962 .flags = PHY_HAS_MAGICANEG, 963 .config_init = kszphy_config_init, 964 .config_aneg = ksz8873mll_config_aneg, 965 .read_status = ksz8873mll_read_status, 966 .get_sset_count = kszphy_get_sset_count, 967 .get_strings = kszphy_get_strings, 968 .get_stats = kszphy_get_stats, 969 .suspend = genphy_suspend, 970 .resume = genphy_resume, 971 }, { 972 .phy_id = PHY_ID_KSZ886X, 973 .phy_id_mask = MICREL_PHY_ID_MASK, 974 .name = "Micrel KSZ886X Switch", 975 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), 976 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 977 .config_init = kszphy_config_init, 978 .config_aneg = genphy_config_aneg, 979 .read_status = genphy_read_status, 980 .get_sset_count = kszphy_get_sset_count, 981 .get_strings = kszphy_get_strings, 982 .get_stats = kszphy_get_stats, 983 .suspend = genphy_suspend, 984 .resume = genphy_resume, 985 } }; 986 987 module_phy_driver(ksphy_driver); 988 989 MODULE_DESCRIPTION("Micrel PHY driver"); 990 MODULE_AUTHOR("David J. Choi"); 991 MODULE_LICENSE("GPL"); 992 993 static struct mdio_device_id __maybe_unused micrel_tbl[] = { 994 { PHY_ID_KSZ9021, 0x000ffffe }, 995 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK }, 996 { PHY_ID_KSZ8001, 0x00fffffc }, 997 { PHY_ID_KS8737, MICREL_PHY_ID_MASK }, 998 { PHY_ID_KSZ8021, 0x00ffffff }, 999 { PHY_ID_KSZ8031, 0x00ffffff }, 1000 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK }, 1001 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK }, 1002 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK }, 1003 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK }, 1004 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK }, 1005 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK }, 1006 { } 1007 }; 1008 1009 MODULE_DEVICE_TABLE(mdio, micrel_tbl); 1010