1a2443fd1SAndrew Lunn // SPDX-License-Identifier: GPL-2.0+ 2d0507009SDavid J. Choi /* 3d0507009SDavid J. Choi * drivers/net/phy/micrel.c 4d0507009SDavid J. Choi * 5d0507009SDavid J. Choi * Driver for Micrel PHYs 6d0507009SDavid J. Choi * 7d0507009SDavid J. Choi * Author: David J. Choi 8d0507009SDavid J. Choi * 97ab59dc1SDavid J. Choi * Copyright (c) 2010-2013 Micrel, Inc. 10ee0dc2fbSJohan Hovold * Copyright (c) 2014 Johan Hovold <johan@kernel.org> 11d0507009SDavid J. Choi * 127ab59dc1SDavid J. Choi * Support : Micrel Phys: 13bff5b4b3SYuiko Oshino * Giga phys: ksz9021, ksz9031, ksz9131 147ab59dc1SDavid J. Choi * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041 157ab59dc1SDavid J. Choi * ksz8021, ksz8031, ksz8051, 167ab59dc1SDavid J. Choi * ksz8081, ksz8091, 177ab59dc1SDavid J. Choi * ksz8061, 187ab59dc1SDavid J. Choi * Switch : ksz8873, ksz886x 19fc3973a1SWoojung Huh * ksz9477 20d0507009SDavid J. Choi */ 21d0507009SDavid J. Choi 22bcf3440cSOleksij Rempel #include <linux/bitfield.h> 2349011e0cSOleksij Rempel #include <linux/ethtool_netlink.h> 24d0507009SDavid J. Choi #include <linux/kernel.h> 25d0507009SDavid J. Choi #include <linux/module.h> 26d0507009SDavid J. Choi #include <linux/phy.h> 27d606ef3fSBaruch Siach #include <linux/micrel_phy.h> 28954c3967SSean Cross #include <linux/of.h> 291fadee0cSSascha Hauer #include <linux/clk.h> 306110dff7SOleksij Rempel #include <linux/delay.h> 31ece19502SDivya Koppera #include <linux/ptp_clock_kernel.h> 32ece19502SDivya Koppera #include <linux/ptp_clock.h> 33ece19502SDivya Koppera #include <linux/ptp_classify.h> 34ece19502SDivya Koppera #include <linux/net_tstamp.h> 35738871b0SMichael Walle #include <linux/gpio/consumer.h> 36d0507009SDavid J. Choi 37212ea99aSMarek Vasut /* Operation Mode Strap Override */ 38212ea99aSMarek Vasut #define MII_KSZPHY_OMSO 0x16 397a1d8390SAntoine Tenart #define KSZPHY_OMSO_FACTORY_TEST BIT(15) 4000aee095SJohan Hovold #define KSZPHY_OMSO_B_CAST_OFF BIT(9) 412b0ba96cSSylvain Rochet #define KSZPHY_OMSO_NAND_TREE_ON BIT(5) 4200aee095SJohan Hovold #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1) 4300aee095SJohan Hovold #define KSZPHY_OMSO_MII_OVERRIDE BIT(0) 44212ea99aSMarek Vasut 4551f932c4SChoi, David /* general Interrupt control/status reg in vendor specific block. */ 4651f932c4SChoi, David #define MII_KSZPHY_INTCS 0x1B 4700aee095SJohan Hovold #define KSZPHY_INTCS_JABBER BIT(15) 4800aee095SJohan Hovold #define KSZPHY_INTCS_RECEIVE_ERR BIT(14) 4900aee095SJohan Hovold #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13) 5000aee095SJohan Hovold #define KSZPHY_INTCS_PARELLEL BIT(12) 5100aee095SJohan Hovold #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11) 5200aee095SJohan Hovold #define KSZPHY_INTCS_LINK_DOWN BIT(10) 5300aee095SJohan Hovold #define KSZPHY_INTCS_REMOTE_FAULT BIT(9) 5400aee095SJohan Hovold #define KSZPHY_INTCS_LINK_UP BIT(8) 5551f932c4SChoi, David #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\ 5651f932c4SChoi, David KSZPHY_INTCS_LINK_DOWN) 5759ca4e58SIoana Ciornei #define KSZPHY_INTCS_LINK_DOWN_STATUS BIT(2) 5859ca4e58SIoana Ciornei #define KSZPHY_INTCS_LINK_UP_STATUS BIT(0) 5959ca4e58SIoana Ciornei #define KSZPHY_INTCS_STATUS (KSZPHY_INTCS_LINK_DOWN_STATUS |\ 6059ca4e58SIoana Ciornei KSZPHY_INTCS_LINK_UP_STATUS) 6151f932c4SChoi, David 6249011e0cSOleksij Rempel /* LinkMD Control/Status */ 6349011e0cSOleksij Rempel #define KSZ8081_LMD 0x1d 6449011e0cSOleksij Rempel #define KSZ8081_LMD_ENABLE_TEST BIT(15) 6549011e0cSOleksij Rempel #define KSZ8081_LMD_STAT_NORMAL 0 6649011e0cSOleksij Rempel #define KSZ8081_LMD_STAT_OPEN 1 6749011e0cSOleksij Rempel #define KSZ8081_LMD_STAT_SHORT 2 6849011e0cSOleksij Rempel #define KSZ8081_LMD_STAT_FAIL 3 6949011e0cSOleksij Rempel #define KSZ8081_LMD_STAT_MASK GENMASK(14, 13) 7049011e0cSOleksij Rempel /* Short cable (<10 meter) has been detected by LinkMD */ 7149011e0cSOleksij Rempel #define KSZ8081_LMD_SHORT_INDICATOR BIT(12) 7249011e0cSOleksij Rempel #define KSZ8081_LMD_DELTA_TIME_MASK GENMASK(8, 0) 7349011e0cSOleksij Rempel 7458389c00SMarek Vasut #define KSZ9x31_LMD 0x12 7558389c00SMarek Vasut #define KSZ9x31_LMD_VCT_EN BIT(15) 7658389c00SMarek Vasut #define KSZ9x31_LMD_VCT_DIS_TX BIT(14) 7758389c00SMarek Vasut #define KSZ9x31_LMD_VCT_PAIR(n) (((n) & 0x3) << 12) 7858389c00SMarek Vasut #define KSZ9x31_LMD_VCT_SEL_RESULT 0 7958389c00SMarek Vasut #define KSZ9x31_LMD_VCT_SEL_THRES_HI BIT(10) 8058389c00SMarek Vasut #define KSZ9x31_LMD_VCT_SEL_THRES_LO BIT(11) 8158389c00SMarek Vasut #define KSZ9x31_LMD_VCT_SEL_MASK GENMASK(11, 10) 8258389c00SMarek Vasut #define KSZ9x31_LMD_VCT_ST_NORMAL 0 8358389c00SMarek Vasut #define KSZ9x31_LMD_VCT_ST_OPEN 1 8458389c00SMarek Vasut #define KSZ9x31_LMD_VCT_ST_SHORT 2 8558389c00SMarek Vasut #define KSZ9x31_LMD_VCT_ST_FAIL 3 8658389c00SMarek Vasut #define KSZ9x31_LMD_VCT_ST_MASK GENMASK(9, 8) 8758389c00SMarek Vasut #define KSZ9x31_LMD_VCT_DATA_REFLECTED_INVALID BIT(7) 8858389c00SMarek Vasut #define KSZ9x31_LMD_VCT_DATA_SIG_WAIT_TOO_LONG BIT(6) 8958389c00SMarek Vasut #define KSZ9x31_LMD_VCT_DATA_MASK100 BIT(5) 9058389c00SMarek Vasut #define KSZ9x31_LMD_VCT_DATA_NLP_FLP BIT(4) 9158389c00SMarek Vasut #define KSZ9x31_LMD_VCT_DATA_LO_PULSE_MASK GENMASK(3, 2) 9258389c00SMarek Vasut #define KSZ9x31_LMD_VCT_DATA_HI_PULSE_MASK GENMASK(1, 0) 9358389c00SMarek Vasut #define KSZ9x31_LMD_VCT_DATA_MASK GENMASK(7, 0) 9458389c00SMarek Vasut 9521b688daSDivya Koppera #define KSZPHY_WIRE_PAIR_MASK 0x3 9621b688daSDivya Koppera 9721b688daSDivya Koppera #define LAN8814_CABLE_DIAG 0x12 9821b688daSDivya Koppera #define LAN8814_CABLE_DIAG_STAT_MASK GENMASK(9, 8) 9921b688daSDivya Koppera #define LAN8814_CABLE_DIAG_VCT_DATA_MASK GENMASK(7, 0) 10021b688daSDivya Koppera #define LAN8814_PAIR_BIT_SHIFT 12 10121b688daSDivya Koppera 10221b688daSDivya Koppera #define LAN8814_WIRE_PAIR_MASK 0xF 10321b688daSDivya Koppera 104b3ec7248SDivya Koppera /* Lan8814 general Interrupt control/status reg in GPHY specific block. */ 105b3ec7248SDivya Koppera #define LAN8814_INTC 0x18 106b3ec7248SDivya Koppera #define LAN8814_INTS 0x1B 107b3ec7248SDivya Koppera 108b3ec7248SDivya Koppera #define LAN8814_INT_LINK_DOWN BIT(2) 109b3ec7248SDivya Koppera #define LAN8814_INT_LINK_UP BIT(0) 110b3ec7248SDivya Koppera #define LAN8814_INT_LINK (LAN8814_INT_LINK_UP |\ 111b3ec7248SDivya Koppera LAN8814_INT_LINK_DOWN) 112b3ec7248SDivya Koppera 113b3ec7248SDivya Koppera #define LAN8814_INTR_CTRL_REG 0x34 114b3ec7248SDivya Koppera #define LAN8814_INTR_CTRL_REG_POLARITY BIT(1) 115b3ec7248SDivya Koppera #define LAN8814_INTR_CTRL_REG_INTR_ENABLE BIT(0) 116b3ec7248SDivya Koppera 117ece19502SDivya Koppera /* Represents 1ppm adjustment in 2^32 format with 118ece19502SDivya Koppera * each nsec contains 4 clock cycles. 119ece19502SDivya Koppera * The value is calculated as following: (1/1000000)/((2^-32)/4) 120ece19502SDivya Koppera */ 121ece19502SDivya Koppera #define LAN8814_1PPM_FORMAT 17179 122ece19502SDivya Koppera 123ece19502SDivya Koppera #define PTP_RX_MOD 0x024F 124ece19502SDivya Koppera #define PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3) 125ece19502SDivya Koppera #define PTP_RX_TIMESTAMP_EN 0x024D 126ece19502SDivya Koppera #define PTP_TX_TIMESTAMP_EN 0x028D 127ece19502SDivya Koppera 128ece19502SDivya Koppera #define PTP_TIMESTAMP_EN_SYNC_ BIT(0) 129ece19502SDivya Koppera #define PTP_TIMESTAMP_EN_DREQ_ BIT(1) 130ece19502SDivya Koppera #define PTP_TIMESTAMP_EN_PDREQ_ BIT(2) 131ece19502SDivya Koppera #define PTP_TIMESTAMP_EN_PDRES_ BIT(3) 132ece19502SDivya Koppera 133ece19502SDivya Koppera #define PTP_TX_PARSE_L2_ADDR_EN 0x0284 134ece19502SDivya Koppera #define PTP_RX_PARSE_L2_ADDR_EN 0x0244 135ece19502SDivya Koppera 136ece19502SDivya Koppera #define PTP_TX_PARSE_IP_ADDR_EN 0x0285 137ece19502SDivya Koppera #define PTP_RX_PARSE_IP_ADDR_EN 0x0245 138ece19502SDivya Koppera #define LTC_HARD_RESET 0x023F 139ece19502SDivya Koppera #define LTC_HARD_RESET_ BIT(0) 140ece19502SDivya Koppera 141ece19502SDivya Koppera #define TSU_HARD_RESET 0x02C1 142ece19502SDivya Koppera #define TSU_HARD_RESET_ BIT(0) 143ece19502SDivya Koppera 144ece19502SDivya Koppera #define PTP_CMD_CTL 0x0200 145ece19502SDivya Koppera #define PTP_CMD_CTL_PTP_DISABLE_ BIT(0) 146ece19502SDivya Koppera #define PTP_CMD_CTL_PTP_ENABLE_ BIT(1) 147ece19502SDivya Koppera #define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3) 148ece19502SDivya Koppera #define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4) 149ece19502SDivya Koppera #define PTP_CMD_CTL_PTP_LTC_STEP_SEC_ BIT(5) 150ece19502SDivya Koppera #define PTP_CMD_CTL_PTP_LTC_STEP_NSEC_ BIT(6) 151ece19502SDivya Koppera 152ece19502SDivya Koppera #define PTP_CLOCK_SET_SEC_MID 0x0206 153ece19502SDivya Koppera #define PTP_CLOCK_SET_SEC_LO 0x0207 154ece19502SDivya Koppera #define PTP_CLOCK_SET_NS_HI 0x0208 155ece19502SDivya Koppera #define PTP_CLOCK_SET_NS_LO 0x0209 156ece19502SDivya Koppera 157ece19502SDivya Koppera #define PTP_CLOCK_READ_SEC_MID 0x022A 158ece19502SDivya Koppera #define PTP_CLOCK_READ_SEC_LO 0x022B 159ece19502SDivya Koppera #define PTP_CLOCK_READ_NS_HI 0x022C 160ece19502SDivya Koppera #define PTP_CLOCK_READ_NS_LO 0x022D 161ece19502SDivya Koppera 162ece19502SDivya Koppera #define PTP_OPERATING_MODE 0x0241 163ece19502SDivya Koppera #define PTP_OPERATING_MODE_STANDALONE_ BIT(0) 164ece19502SDivya Koppera 165ece19502SDivya Koppera #define PTP_TX_MOD 0x028F 166ece19502SDivya Koppera #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ BIT(12) 167ece19502SDivya Koppera #define PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3) 168ece19502SDivya Koppera 169ece19502SDivya Koppera #define PTP_RX_PARSE_CONFIG 0x0242 170ece19502SDivya Koppera #define PTP_RX_PARSE_CONFIG_LAYER2_EN_ BIT(0) 171ece19502SDivya Koppera #define PTP_RX_PARSE_CONFIG_IPV4_EN_ BIT(1) 172ece19502SDivya Koppera #define PTP_RX_PARSE_CONFIG_IPV6_EN_ BIT(2) 173ece19502SDivya Koppera 174ece19502SDivya Koppera #define PTP_TX_PARSE_CONFIG 0x0282 175ece19502SDivya Koppera #define PTP_TX_PARSE_CONFIG_LAYER2_EN_ BIT(0) 176ece19502SDivya Koppera #define PTP_TX_PARSE_CONFIG_IPV4_EN_ BIT(1) 177ece19502SDivya Koppera #define PTP_TX_PARSE_CONFIG_IPV6_EN_ BIT(2) 178ece19502SDivya Koppera 179ece19502SDivya Koppera #define PTP_CLOCK_RATE_ADJ_HI 0x020C 180ece19502SDivya Koppera #define PTP_CLOCK_RATE_ADJ_LO 0x020D 181ece19502SDivya Koppera #define PTP_CLOCK_RATE_ADJ_DIR_ BIT(15) 182ece19502SDivya Koppera 183ece19502SDivya Koppera #define PTP_LTC_STEP_ADJ_HI 0x0212 184ece19502SDivya Koppera #define PTP_LTC_STEP_ADJ_LO 0x0213 185ece19502SDivya Koppera #define PTP_LTC_STEP_ADJ_DIR_ BIT(15) 186ece19502SDivya Koppera 187ece19502SDivya Koppera #define LAN8814_INTR_STS_REG 0x0033 188ece19502SDivya Koppera #define LAN8814_INTR_STS_REG_1588_TSU0_ BIT(0) 189ece19502SDivya Koppera #define LAN8814_INTR_STS_REG_1588_TSU1_ BIT(1) 190ece19502SDivya Koppera #define LAN8814_INTR_STS_REG_1588_TSU2_ BIT(2) 191ece19502SDivya Koppera #define LAN8814_INTR_STS_REG_1588_TSU3_ BIT(3) 192ece19502SDivya Koppera 193ece19502SDivya Koppera #define PTP_CAP_INFO 0x022A 194ece19502SDivya Koppera #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x0f00) >> 8) 195ece19502SDivya Koppera #define PTP_CAP_INFO_RX_TS_CNT_GET_(reg_val) ((reg_val) & 0x000f) 196ece19502SDivya Koppera 197ece19502SDivya Koppera #define PTP_TX_EGRESS_SEC_HI 0x0296 198ece19502SDivya Koppera #define PTP_TX_EGRESS_SEC_LO 0x0297 199ece19502SDivya Koppera #define PTP_TX_EGRESS_NS_HI 0x0294 200ece19502SDivya Koppera #define PTP_TX_EGRESS_NS_LO 0x0295 201ece19502SDivya Koppera #define PTP_TX_MSG_HEADER2 0x0299 202ece19502SDivya Koppera 203ece19502SDivya Koppera #define PTP_RX_INGRESS_SEC_HI 0x0256 204ece19502SDivya Koppera #define PTP_RX_INGRESS_SEC_LO 0x0257 205ece19502SDivya Koppera #define PTP_RX_INGRESS_NS_HI 0x0254 206ece19502SDivya Koppera #define PTP_RX_INGRESS_NS_LO 0x0255 207ece19502SDivya Koppera #define PTP_RX_MSG_HEADER2 0x0259 208ece19502SDivya Koppera 209ece19502SDivya Koppera #define PTP_TSU_INT_EN 0x0200 210ece19502SDivya Koppera #define PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ BIT(3) 211ece19502SDivya Koppera #define PTP_TSU_INT_EN_PTP_TX_TS_EN_ BIT(2) 212ece19502SDivya Koppera #define PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_ BIT(1) 213ece19502SDivya Koppera #define PTP_TSU_INT_EN_PTP_RX_TS_EN_ BIT(0) 214ece19502SDivya Koppera 215ece19502SDivya Koppera #define PTP_TSU_INT_STS 0x0201 216ece19502SDivya Koppera #define PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_ BIT(3) 217ece19502SDivya Koppera #define PTP_TSU_INT_STS_PTP_TX_TS_EN_ BIT(2) 218ece19502SDivya Koppera #define PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_ BIT(1) 219ece19502SDivya Koppera #define PTP_TSU_INT_STS_PTP_RX_TS_EN_ BIT(0) 220ece19502SDivya Koppera 221a516b7f7SDivya Koppera #define LAN8814_LED_CTRL_1 0x0 222a516b7f7SDivya Koppera #define LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_ BIT(6) 223a516b7f7SDivya Koppera 2245a16778eSJohan Hovold /* PHY Control 1 */ 2255a16778eSJohan Hovold #define MII_KSZPHY_CTRL_1 0x1e 226f873f112SOleksij Rempel #define KSZ8081_CTRL1_MDIX_STAT BIT(4) 2275a16778eSJohan Hovold 2285a16778eSJohan Hovold /* PHY Control 2 / PHY Control (if no PHY Control 1) */ 2295a16778eSJohan Hovold #define MII_KSZPHY_CTRL_2 0x1f 2305a16778eSJohan Hovold #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2 23151f932c4SChoi, David /* bitmap of PHY register to set interrupt mode */ 232f873f112SOleksij Rempel #define KSZ8081_CTRL2_HP_MDIX BIT(15) 233f873f112SOleksij Rempel #define KSZ8081_CTRL2_MDI_MDI_X_SELECT BIT(14) 234f873f112SOleksij Rempel #define KSZ8081_CTRL2_DISABLE_AUTO_MDIX BIT(13) 235f873f112SOleksij Rempel #define KSZ8081_CTRL2_FORCE_LINK BIT(11) 236f873f112SOleksij Rempel #define KSZ8081_CTRL2_POWER_SAVING BIT(10) 23700aee095SJohan Hovold #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9) 23863f44b2bSJohan Hovold #define KSZPHY_RMII_REF_CLK_SEL BIT(7) 23951f932c4SChoi, David 240954c3967SSean Cross /* Write/read to/from extended registers */ 241954c3967SSean Cross #define MII_KSZPHY_EXTREG 0x0b 242954c3967SSean Cross #define KSZPHY_EXTREG_WRITE 0x8000 243954c3967SSean Cross 244954c3967SSean Cross #define MII_KSZPHY_EXTREG_WRITE 0x0c 245954c3967SSean Cross #define MII_KSZPHY_EXTREG_READ 0x0d 246954c3967SSean Cross 247954c3967SSean Cross /* Extended registers */ 248954c3967SSean Cross #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104 249954c3967SSean Cross #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105 250954c3967SSean Cross #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106 251954c3967SSean Cross 252954c3967SSean Cross #define PS_TO_REG 200 253ece19502SDivya Koppera #define FIFO_SIZE 8 254954c3967SSean Cross 2552b2427d0SAndrew Lunn struct kszphy_hw_stat { 2562b2427d0SAndrew Lunn const char *string; 2572b2427d0SAndrew Lunn u8 reg; 2582b2427d0SAndrew Lunn u8 bits; 2592b2427d0SAndrew Lunn }; 2602b2427d0SAndrew Lunn 2612b2427d0SAndrew Lunn static struct kszphy_hw_stat kszphy_hw_stats[] = { 2622b2427d0SAndrew Lunn { "phy_receive_errors", 21, 16}, 2632b2427d0SAndrew Lunn { "phy_idle_errors", 10, 8 }, 2642b2427d0SAndrew Lunn }; 2652b2427d0SAndrew Lunn 266e6a423a8SJohan Hovold struct kszphy_type { 267e6a423a8SJohan Hovold u32 led_mode_reg; 268c6f9575cSJohan Hovold u16 interrupt_level_mask; 26921b688daSDivya Koppera u16 cable_diag_reg; 27021b688daSDivya Koppera unsigned long pair_mask; 271a8f1a19dSHoratiu Vultur u16 disable_dll_tx_bit; 272a8f1a19dSHoratiu Vultur u16 disable_dll_rx_bit; 273a8f1a19dSHoratiu Vultur u16 disable_dll_mask; 2740f95903eSJohan Hovold bool has_broadcast_disable; 2752b0ba96cSSylvain Rochet bool has_nand_tree_disable; 27663f44b2bSJohan Hovold bool has_rmii_ref_clk_sel; 277e6a423a8SJohan Hovold }; 278e6a423a8SJohan Hovold 279ece19502SDivya Koppera /* Shared structure between the PHYs of the same package. */ 280ece19502SDivya Koppera struct lan8814_shared_priv { 281ece19502SDivya Koppera struct phy_device *phydev; 282ece19502SDivya Koppera struct ptp_clock *ptp_clock; 283ece19502SDivya Koppera struct ptp_clock_info ptp_clock_info; 284ece19502SDivya Koppera 285ece19502SDivya Koppera /* Reference counter to how many ports in the package are enabling the 286ece19502SDivya Koppera * timestamping 287ece19502SDivya Koppera */ 288ece19502SDivya Koppera u8 ref; 289ece19502SDivya Koppera 290ece19502SDivya Koppera /* Lock for ptp_clock and ref */ 291ece19502SDivya Koppera struct mutex shared_lock; 292ece19502SDivya Koppera }; 293ece19502SDivya Koppera 294ece19502SDivya Koppera struct lan8814_ptp_rx_ts { 295ece19502SDivya Koppera struct list_head list; 296ece19502SDivya Koppera u32 seconds; 297ece19502SDivya Koppera u32 nsec; 298ece19502SDivya Koppera u16 seq_id; 299ece19502SDivya Koppera }; 300ece19502SDivya Koppera 301ece19502SDivya Koppera struct kszphy_ptp_priv { 302ece19502SDivya Koppera struct mii_timestamper mii_ts; 303ece19502SDivya Koppera struct phy_device *phydev; 304ece19502SDivya Koppera 305ece19502SDivya Koppera struct sk_buff_head tx_queue; 306ece19502SDivya Koppera struct sk_buff_head rx_queue; 307ece19502SDivya Koppera 308ece19502SDivya Koppera struct list_head rx_ts_list; 309ece19502SDivya Koppera /* Lock for Rx ts fifo */ 310ece19502SDivya Koppera spinlock_t rx_ts_lock; 311ece19502SDivya Koppera 312ece19502SDivya Koppera int hwts_tx_type; 313ece19502SDivya Koppera enum hwtstamp_rx_filters rx_filter; 314ece19502SDivya Koppera int layer; 315ece19502SDivya Koppera int version; 316ece19502SDivya Koppera }; 317ece19502SDivya Koppera 318e6a423a8SJohan Hovold struct kszphy_priv { 319ece19502SDivya Koppera struct kszphy_ptp_priv ptp_priv; 320e6a423a8SJohan Hovold const struct kszphy_type *type; 321e7a792e9SJohan Hovold int led_mode; 32258389c00SMarek Vasut u16 vct_ctrl1000; 32363f44b2bSJohan Hovold bool rmii_ref_clk_sel; 32463f44b2bSJohan Hovold bool rmii_ref_clk_sel_val; 3252b2427d0SAndrew Lunn u64 stats[ARRAY_SIZE(kszphy_hw_stats)]; 326e6a423a8SJohan Hovold }; 327e6a423a8SJohan Hovold 328a516b7f7SDivya Koppera static const struct kszphy_type lan8814_type = { 329a516b7f7SDivya Koppera .led_mode_reg = ~LAN8814_LED_CTRL_1, 33021b688daSDivya Koppera .cable_diag_reg = LAN8814_CABLE_DIAG, 33121b688daSDivya Koppera .pair_mask = LAN8814_WIRE_PAIR_MASK, 33221b688daSDivya Koppera }; 33321b688daSDivya Koppera 33421b688daSDivya Koppera static const struct kszphy_type ksz886x_type = { 33521b688daSDivya Koppera .cable_diag_reg = KSZ8081_LMD, 33621b688daSDivya Koppera .pair_mask = KSZPHY_WIRE_PAIR_MASK, 337a516b7f7SDivya Koppera }; 338a516b7f7SDivya Koppera 339e6a423a8SJohan Hovold static const struct kszphy_type ksz8021_type = { 340e6a423a8SJohan Hovold .led_mode_reg = MII_KSZPHY_CTRL_2, 341d0e1df9cSJohan Hovold .has_broadcast_disable = true, 3422b0ba96cSSylvain Rochet .has_nand_tree_disable = true, 34363f44b2bSJohan Hovold .has_rmii_ref_clk_sel = true, 344e6a423a8SJohan Hovold }; 345e6a423a8SJohan Hovold 346e6a423a8SJohan Hovold static const struct kszphy_type ksz8041_type = { 347e6a423a8SJohan Hovold .led_mode_reg = MII_KSZPHY_CTRL_1, 348e6a423a8SJohan Hovold }; 349e6a423a8SJohan Hovold 350e6a423a8SJohan Hovold static const struct kszphy_type ksz8051_type = { 351e6a423a8SJohan Hovold .led_mode_reg = MII_KSZPHY_CTRL_2, 3522b0ba96cSSylvain Rochet .has_nand_tree_disable = true, 353e6a423a8SJohan Hovold }; 354e6a423a8SJohan Hovold 355e6a423a8SJohan Hovold static const struct kszphy_type ksz8081_type = { 356e6a423a8SJohan Hovold .led_mode_reg = MII_KSZPHY_CTRL_2, 3570f95903eSJohan Hovold .has_broadcast_disable = true, 3582b0ba96cSSylvain Rochet .has_nand_tree_disable = true, 35986dc1342SJohan Hovold .has_rmii_ref_clk_sel = true, 360e6a423a8SJohan Hovold }; 361e6a423a8SJohan Hovold 362c6f9575cSJohan Hovold static const struct kszphy_type ks8737_type = { 363c6f9575cSJohan Hovold .interrupt_level_mask = BIT(14), 364c6f9575cSJohan Hovold }; 365c6f9575cSJohan Hovold 366c6f9575cSJohan Hovold static const struct kszphy_type ksz9021_type = { 367c6f9575cSJohan Hovold .interrupt_level_mask = BIT(14), 368c6f9575cSJohan Hovold }; 369c6f9575cSJohan Hovold 370a8f1a19dSHoratiu Vultur static const struct kszphy_type ksz9131_type = { 371a8f1a19dSHoratiu Vultur .interrupt_level_mask = BIT(14), 372a8f1a19dSHoratiu Vultur .disable_dll_tx_bit = BIT(12), 373a8f1a19dSHoratiu Vultur .disable_dll_rx_bit = BIT(12), 374a8f1a19dSHoratiu Vultur .disable_dll_mask = BIT_MASK(12), 375a8f1a19dSHoratiu Vultur }; 376a8f1a19dSHoratiu Vultur 377a8f1a19dSHoratiu Vultur static const struct kszphy_type lan8841_type = { 378a8f1a19dSHoratiu Vultur .disable_dll_tx_bit = BIT(14), 379a8f1a19dSHoratiu Vultur .disable_dll_rx_bit = BIT(14), 380a8f1a19dSHoratiu Vultur .disable_dll_mask = BIT_MASK(14), 381*a136391aSHoratiu Vultur .cable_diag_reg = LAN8814_CABLE_DIAG, 382*a136391aSHoratiu Vultur .pair_mask = LAN8814_WIRE_PAIR_MASK, 383a8f1a19dSHoratiu Vultur }; 384a8f1a19dSHoratiu Vultur 385954c3967SSean Cross static int kszphy_extended_write(struct phy_device *phydev, 386954c3967SSean Cross u32 regnum, u16 val) 387954c3967SSean Cross { 388954c3967SSean Cross phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum); 389954c3967SSean Cross return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); 390954c3967SSean Cross } 391954c3967SSean Cross 392954c3967SSean Cross static int kszphy_extended_read(struct phy_device *phydev, 393954c3967SSean Cross u32 regnum) 394954c3967SSean Cross { 395954c3967SSean Cross phy_write(phydev, MII_KSZPHY_EXTREG, regnum); 396954c3967SSean Cross return phy_read(phydev, MII_KSZPHY_EXTREG_READ); 397954c3967SSean Cross } 398954c3967SSean Cross 39951f932c4SChoi, David static int kszphy_ack_interrupt(struct phy_device *phydev) 40051f932c4SChoi, David { 40151f932c4SChoi, David /* bit[7..0] int status, which is a read and clear register. */ 40251f932c4SChoi, David int rc; 40351f932c4SChoi, David 40451f932c4SChoi, David rc = phy_read(phydev, MII_KSZPHY_INTCS); 40551f932c4SChoi, David 40651f932c4SChoi, David return (rc < 0) ? rc : 0; 40751f932c4SChoi, David } 40851f932c4SChoi, David 40951f932c4SChoi, David static int kszphy_config_intr(struct phy_device *phydev) 41051f932c4SChoi, David { 411c6f9575cSJohan Hovold const struct kszphy_type *type = phydev->drv->driver_data; 412c0c99d0cSIoana Ciornei int temp, err; 413c6f9575cSJohan Hovold u16 mask; 414c6f9575cSJohan Hovold 415c6f9575cSJohan Hovold if (type && type->interrupt_level_mask) 416c6f9575cSJohan Hovold mask = type->interrupt_level_mask; 417c6f9575cSJohan Hovold else 418c6f9575cSJohan Hovold mask = KSZPHY_CTRL_INT_ACTIVE_HIGH; 41951f932c4SChoi, David 42051f932c4SChoi, David /* set the interrupt pin active low */ 42151f932c4SChoi, David temp = phy_read(phydev, MII_KSZPHY_CTRL); 4225bb8fc0dSJohan Hovold if (temp < 0) 4235bb8fc0dSJohan Hovold return temp; 424c6f9575cSJohan Hovold temp &= ~mask; 42551f932c4SChoi, David phy_write(phydev, MII_KSZPHY_CTRL, temp); 42651f932c4SChoi, David 427c6f9575cSJohan Hovold /* enable / disable interrupts */ 428c0c99d0cSIoana Ciornei if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 429c0c99d0cSIoana Ciornei err = kszphy_ack_interrupt(phydev); 430c0c99d0cSIoana Ciornei if (err) 431c0c99d0cSIoana Ciornei return err; 43251f932c4SChoi, David 433c0c99d0cSIoana Ciornei temp = KSZPHY_INTCS_ALL; 434c0c99d0cSIoana Ciornei err = phy_write(phydev, MII_KSZPHY_INTCS, temp); 435c0c99d0cSIoana Ciornei } else { 436c0c99d0cSIoana Ciornei temp = 0; 437c0c99d0cSIoana Ciornei err = phy_write(phydev, MII_KSZPHY_INTCS, temp); 438c0c99d0cSIoana Ciornei if (err) 439c0c99d0cSIoana Ciornei return err; 440c0c99d0cSIoana Ciornei 441c0c99d0cSIoana Ciornei err = kszphy_ack_interrupt(phydev); 442c0c99d0cSIoana Ciornei } 443c0c99d0cSIoana Ciornei 444c0c99d0cSIoana Ciornei return err; 44551f932c4SChoi, David } 446d0507009SDavid J. Choi 44759ca4e58SIoana Ciornei static irqreturn_t kszphy_handle_interrupt(struct phy_device *phydev) 44859ca4e58SIoana Ciornei { 44959ca4e58SIoana Ciornei int irq_status; 45059ca4e58SIoana Ciornei 45159ca4e58SIoana Ciornei irq_status = phy_read(phydev, MII_KSZPHY_INTCS); 45259ca4e58SIoana Ciornei if (irq_status < 0) { 45359ca4e58SIoana Ciornei phy_error(phydev); 45459ca4e58SIoana Ciornei return IRQ_NONE; 45559ca4e58SIoana Ciornei } 45659ca4e58SIoana Ciornei 457fff4c746SOleksij Rempel if (!(irq_status & KSZPHY_INTCS_STATUS)) 45859ca4e58SIoana Ciornei return IRQ_NONE; 45959ca4e58SIoana Ciornei 46059ca4e58SIoana Ciornei phy_trigger_machine(phydev); 46159ca4e58SIoana Ciornei 46259ca4e58SIoana Ciornei return IRQ_HANDLED; 46359ca4e58SIoana Ciornei } 46459ca4e58SIoana Ciornei 46563f44b2bSJohan Hovold static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val) 46663f44b2bSJohan Hovold { 46763f44b2bSJohan Hovold int ctrl; 46863f44b2bSJohan Hovold 46963f44b2bSJohan Hovold ctrl = phy_read(phydev, MII_KSZPHY_CTRL); 47063f44b2bSJohan Hovold if (ctrl < 0) 47163f44b2bSJohan Hovold return ctrl; 47263f44b2bSJohan Hovold 47363f44b2bSJohan Hovold if (val) 47463f44b2bSJohan Hovold ctrl |= KSZPHY_RMII_REF_CLK_SEL; 47563f44b2bSJohan Hovold else 47663f44b2bSJohan Hovold ctrl &= ~KSZPHY_RMII_REF_CLK_SEL; 47763f44b2bSJohan Hovold 47863f44b2bSJohan Hovold return phy_write(phydev, MII_KSZPHY_CTRL, ctrl); 47963f44b2bSJohan Hovold } 48063f44b2bSJohan Hovold 481e7a792e9SJohan Hovold static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val) 48220d8435aSBen Dooks { 4835a16778eSJohan Hovold int rc, temp, shift; 4848620546cSJohan Hovold 4855a16778eSJohan Hovold switch (reg) { 4865a16778eSJohan Hovold case MII_KSZPHY_CTRL_1: 4875a16778eSJohan Hovold shift = 14; 4885a16778eSJohan Hovold break; 4895a16778eSJohan Hovold case MII_KSZPHY_CTRL_2: 4905a16778eSJohan Hovold shift = 4; 4915a16778eSJohan Hovold break; 4925a16778eSJohan Hovold default: 4935a16778eSJohan Hovold return -EINVAL; 4945a16778eSJohan Hovold } 4955a16778eSJohan Hovold 49620d8435aSBen Dooks temp = phy_read(phydev, reg); 497b7035860SJohan Hovold if (temp < 0) { 498b7035860SJohan Hovold rc = temp; 499b7035860SJohan Hovold goto out; 500b7035860SJohan Hovold } 50120d8435aSBen Dooks 50228bdc499SSergei Shtylyov temp &= ~(3 << shift); 50320d8435aSBen Dooks temp |= val << shift; 50420d8435aSBen Dooks rc = phy_write(phydev, reg, temp); 505b7035860SJohan Hovold out: 506b7035860SJohan Hovold if (rc < 0) 50772ba48beSAndrew Lunn phydev_err(phydev, "failed to set led mode\n"); 50820d8435aSBen Dooks 509b7035860SJohan Hovold return rc; 51020d8435aSBen Dooks } 51120d8435aSBen Dooks 512bde15129SJohan Hovold /* Disable PHY address 0 as the broadcast address, so that it can be used as a 513bde15129SJohan Hovold * unique (non-broadcast) address on a shared bus. 514bde15129SJohan Hovold */ 515bde15129SJohan Hovold static int kszphy_broadcast_disable(struct phy_device *phydev) 516bde15129SJohan Hovold { 517bde15129SJohan Hovold int ret; 518bde15129SJohan Hovold 519bde15129SJohan Hovold ret = phy_read(phydev, MII_KSZPHY_OMSO); 520bde15129SJohan Hovold if (ret < 0) 521bde15129SJohan Hovold goto out; 522bde15129SJohan Hovold 523bde15129SJohan Hovold ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF); 524bde15129SJohan Hovold out: 525bde15129SJohan Hovold if (ret) 52672ba48beSAndrew Lunn phydev_err(phydev, "failed to disable broadcast address\n"); 527bde15129SJohan Hovold 528bde15129SJohan Hovold return ret; 529bde15129SJohan Hovold } 530bde15129SJohan Hovold 5312b0ba96cSSylvain Rochet static int kszphy_nand_tree_disable(struct phy_device *phydev) 5322b0ba96cSSylvain Rochet { 5332b0ba96cSSylvain Rochet int ret; 5342b0ba96cSSylvain Rochet 5352b0ba96cSSylvain Rochet ret = phy_read(phydev, MII_KSZPHY_OMSO); 5362b0ba96cSSylvain Rochet if (ret < 0) 5372b0ba96cSSylvain Rochet goto out; 5382b0ba96cSSylvain Rochet 5392b0ba96cSSylvain Rochet if (!(ret & KSZPHY_OMSO_NAND_TREE_ON)) 5402b0ba96cSSylvain Rochet return 0; 5412b0ba96cSSylvain Rochet 5422b0ba96cSSylvain Rochet ret = phy_write(phydev, MII_KSZPHY_OMSO, 5432b0ba96cSSylvain Rochet ret & ~KSZPHY_OMSO_NAND_TREE_ON); 5442b0ba96cSSylvain Rochet out: 5452b0ba96cSSylvain Rochet if (ret) 54672ba48beSAndrew Lunn phydev_err(phydev, "failed to disable NAND tree mode\n"); 5472b0ba96cSSylvain Rochet 5482b0ba96cSSylvain Rochet return ret; 5492b0ba96cSSylvain Rochet } 5502b0ba96cSSylvain Rochet 55179e498a9SLeonard Crestez /* Some config bits need to be set again on resume, handle them here. */ 55279e498a9SLeonard Crestez static int kszphy_config_reset(struct phy_device *phydev) 55379e498a9SLeonard Crestez { 55479e498a9SLeonard Crestez struct kszphy_priv *priv = phydev->priv; 55579e498a9SLeonard Crestez int ret; 55679e498a9SLeonard Crestez 55779e498a9SLeonard Crestez if (priv->rmii_ref_clk_sel) { 55879e498a9SLeonard Crestez ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val); 55979e498a9SLeonard Crestez if (ret) { 56079e498a9SLeonard Crestez phydev_err(phydev, 56179e498a9SLeonard Crestez "failed to set rmii reference clock\n"); 56279e498a9SLeonard Crestez return ret; 56379e498a9SLeonard Crestez } 56479e498a9SLeonard Crestez } 56579e498a9SLeonard Crestez 566f2ef6f75SFabio Estevam if (priv->type && priv->led_mode >= 0) 56779e498a9SLeonard Crestez kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode); 56879e498a9SLeonard Crestez 56979e498a9SLeonard Crestez return 0; 57079e498a9SLeonard Crestez } 57179e498a9SLeonard Crestez 572d0507009SDavid J. Choi static int kszphy_config_init(struct phy_device *phydev) 573d0507009SDavid J. Choi { 574e6a423a8SJohan Hovold struct kszphy_priv *priv = phydev->priv; 575e6a423a8SJohan Hovold const struct kszphy_type *type; 576d0507009SDavid J. Choi 577e6a423a8SJohan Hovold if (!priv) 578e6a423a8SJohan Hovold return 0; 579e6a423a8SJohan Hovold 580e6a423a8SJohan Hovold type = priv->type; 581e6a423a8SJohan Hovold 582f2ef6f75SFabio Estevam if (type && type->has_broadcast_disable) 5830f95903eSJohan Hovold kszphy_broadcast_disable(phydev); 5840f95903eSJohan Hovold 585f2ef6f75SFabio Estevam if (type && type->has_nand_tree_disable) 5862b0ba96cSSylvain Rochet kszphy_nand_tree_disable(phydev); 5872b0ba96cSSylvain Rochet 58879e498a9SLeonard Crestez return kszphy_config_reset(phydev); 58920d8435aSBen Dooks } 59020d8435aSBen Dooks 5914217a64eSMichael Walle static int ksz8041_fiber_mode(struct phy_device *phydev) 5924217a64eSMichael Walle { 5934217a64eSMichael Walle struct device_node *of_node = phydev->mdio.dev.of_node; 5944217a64eSMichael Walle 5954217a64eSMichael Walle return of_property_read_bool(of_node, "micrel,fiber-mode"); 5964217a64eSMichael Walle } 5974217a64eSMichael Walle 59877501a79SPhilipp Zabel static int ksz8041_config_init(struct phy_device *phydev) 59977501a79SPhilipp Zabel { 6003c1bcc86SAndrew Lunn __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 6013c1bcc86SAndrew Lunn 60277501a79SPhilipp Zabel /* Limit supported and advertised modes in fiber mode */ 6034217a64eSMichael Walle if (ksz8041_fiber_mode(phydev)) { 60477501a79SPhilipp Zabel phydev->dev_flags |= MICREL_PHY_FXEN; 6053c1bcc86SAndrew Lunn linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask); 6063c1bcc86SAndrew Lunn linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask); 6073c1bcc86SAndrew Lunn 6083c1bcc86SAndrew Lunn linkmode_and(phydev->supported, phydev->supported, mask); 6093c1bcc86SAndrew Lunn linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 6103c1bcc86SAndrew Lunn phydev->supported); 6113c1bcc86SAndrew Lunn linkmode_and(phydev->advertising, phydev->advertising, mask); 6123c1bcc86SAndrew Lunn linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 6133c1bcc86SAndrew Lunn phydev->advertising); 61477501a79SPhilipp Zabel phydev->autoneg = AUTONEG_DISABLE; 61577501a79SPhilipp Zabel } 61677501a79SPhilipp Zabel 61777501a79SPhilipp Zabel return kszphy_config_init(phydev); 61877501a79SPhilipp Zabel } 61977501a79SPhilipp Zabel 62077501a79SPhilipp Zabel static int ksz8041_config_aneg(struct phy_device *phydev) 62177501a79SPhilipp Zabel { 62277501a79SPhilipp Zabel /* Skip auto-negotiation in fiber mode */ 62377501a79SPhilipp Zabel if (phydev->dev_flags & MICREL_PHY_FXEN) { 62477501a79SPhilipp Zabel phydev->speed = SPEED_100; 62577501a79SPhilipp Zabel return 0; 62677501a79SPhilipp Zabel } 62777501a79SPhilipp Zabel 62877501a79SPhilipp Zabel return genphy_config_aneg(phydev); 62977501a79SPhilipp Zabel } 63077501a79SPhilipp Zabel 6318b95599cSMarek Vasut static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev, 632a5e63c7dSSteve Bennett const bool ksz_8051) 6338b95599cSMarek Vasut { 6348b95599cSMarek Vasut int ret; 6358b95599cSMarek Vasut 636a5e63c7dSSteve Bennett if ((phydev->phy_id & MICREL_PHY_ID_MASK) != PHY_ID_KSZ8051) 6378b95599cSMarek Vasut return 0; 6388b95599cSMarek Vasut 6398b95599cSMarek Vasut ret = phy_read(phydev, MII_BMSR); 6408b95599cSMarek Vasut if (ret < 0) 6418b95599cSMarek Vasut return ret; 6428b95599cSMarek Vasut 6438b95599cSMarek Vasut /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same 6448b95599cSMarek Vasut * exact PHY ID. However, they can be told apart by the extended 6458b95599cSMarek Vasut * capability registers presence. The KSZ8051 PHY has them while 6468b95599cSMarek Vasut * the switch does not. 6478b95599cSMarek Vasut */ 6488b95599cSMarek Vasut ret &= BMSR_ERCAP; 649a5e63c7dSSteve Bennett if (ksz_8051) 6508b95599cSMarek Vasut return ret; 6518b95599cSMarek Vasut else 6528b95599cSMarek Vasut return !ret; 6538b95599cSMarek Vasut } 6548b95599cSMarek Vasut 6558b95599cSMarek Vasut static int ksz8051_match_phy_device(struct phy_device *phydev) 6568b95599cSMarek Vasut { 657a5e63c7dSSteve Bennett return ksz8051_ksz8795_match_phy_device(phydev, true); 6588b95599cSMarek Vasut } 6598b95599cSMarek Vasut 6607a1d8390SAntoine Tenart static int ksz8081_config_init(struct phy_device *phydev) 6617a1d8390SAntoine Tenart { 6627a1d8390SAntoine Tenart /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line 6637a1d8390SAntoine Tenart * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a 6647a1d8390SAntoine Tenart * pull-down is missing, the factory test mode should be cleared by 6657a1d8390SAntoine Tenart * manually writing a 0. 6667a1d8390SAntoine Tenart */ 6677a1d8390SAntoine Tenart phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST); 6687a1d8390SAntoine Tenart 6697a1d8390SAntoine Tenart return kszphy_config_init(phydev); 6707a1d8390SAntoine Tenart } 6717a1d8390SAntoine Tenart 672f873f112SOleksij Rempel static int ksz8081_config_mdix(struct phy_device *phydev, u8 ctrl) 673f873f112SOleksij Rempel { 674f873f112SOleksij Rempel u16 val; 675f873f112SOleksij Rempel 676f873f112SOleksij Rempel switch (ctrl) { 677f873f112SOleksij Rempel case ETH_TP_MDI: 678f873f112SOleksij Rempel val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX; 679f873f112SOleksij Rempel break; 680f873f112SOleksij Rempel case ETH_TP_MDI_X: 681f873f112SOleksij Rempel val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX | 682f873f112SOleksij Rempel KSZ8081_CTRL2_MDI_MDI_X_SELECT; 683f873f112SOleksij Rempel break; 684f873f112SOleksij Rempel case ETH_TP_MDI_AUTO: 685f873f112SOleksij Rempel val = 0; 686f873f112SOleksij Rempel break; 687f873f112SOleksij Rempel default: 688f873f112SOleksij Rempel return 0; 689f873f112SOleksij Rempel } 690f873f112SOleksij Rempel 691f873f112SOleksij Rempel return phy_modify(phydev, MII_KSZPHY_CTRL_2, 692f873f112SOleksij Rempel KSZ8081_CTRL2_HP_MDIX | 693f873f112SOleksij Rempel KSZ8081_CTRL2_MDI_MDI_X_SELECT | 694f873f112SOleksij Rempel KSZ8081_CTRL2_DISABLE_AUTO_MDIX, 695f873f112SOleksij Rempel KSZ8081_CTRL2_HP_MDIX | val); 696f873f112SOleksij Rempel } 697f873f112SOleksij Rempel 698f873f112SOleksij Rempel static int ksz8081_config_aneg(struct phy_device *phydev) 699f873f112SOleksij Rempel { 700f873f112SOleksij Rempel int ret; 701f873f112SOleksij Rempel 702f873f112SOleksij Rempel ret = genphy_config_aneg(phydev); 703f873f112SOleksij Rempel if (ret) 704f873f112SOleksij Rempel return ret; 705f873f112SOleksij Rempel 706f873f112SOleksij Rempel /* The MDI-X configuration is automatically changed by the PHY after 707f873f112SOleksij Rempel * switching from autoneg off to on. So, take MDI-X configuration under 708f873f112SOleksij Rempel * own control and set it after autoneg configuration was done. 709f873f112SOleksij Rempel */ 710f873f112SOleksij Rempel return ksz8081_config_mdix(phydev, phydev->mdix_ctrl); 711f873f112SOleksij Rempel } 712f873f112SOleksij Rempel 713f873f112SOleksij Rempel static int ksz8081_mdix_update(struct phy_device *phydev) 714f873f112SOleksij Rempel { 715f873f112SOleksij Rempel int ret; 716f873f112SOleksij Rempel 717f873f112SOleksij Rempel ret = phy_read(phydev, MII_KSZPHY_CTRL_2); 718f873f112SOleksij Rempel if (ret < 0) 719f873f112SOleksij Rempel return ret; 720f873f112SOleksij Rempel 721f873f112SOleksij Rempel if (ret & KSZ8081_CTRL2_DISABLE_AUTO_MDIX) { 722f873f112SOleksij Rempel if (ret & KSZ8081_CTRL2_MDI_MDI_X_SELECT) 723f873f112SOleksij Rempel phydev->mdix_ctrl = ETH_TP_MDI_X; 724f873f112SOleksij Rempel else 725f873f112SOleksij Rempel phydev->mdix_ctrl = ETH_TP_MDI; 726f873f112SOleksij Rempel } else { 727f873f112SOleksij Rempel phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 728f873f112SOleksij Rempel } 729f873f112SOleksij Rempel 730f873f112SOleksij Rempel ret = phy_read(phydev, MII_KSZPHY_CTRL_1); 731f873f112SOleksij Rempel if (ret < 0) 732f873f112SOleksij Rempel return ret; 733f873f112SOleksij Rempel 734f873f112SOleksij Rempel if (ret & KSZ8081_CTRL1_MDIX_STAT) 735f873f112SOleksij Rempel phydev->mdix = ETH_TP_MDI; 736f873f112SOleksij Rempel else 737f873f112SOleksij Rempel phydev->mdix = ETH_TP_MDI_X; 738f873f112SOleksij Rempel 739f873f112SOleksij Rempel return 0; 740f873f112SOleksij Rempel } 741f873f112SOleksij Rempel 742f873f112SOleksij Rempel static int ksz8081_read_status(struct phy_device *phydev) 743f873f112SOleksij Rempel { 744f873f112SOleksij Rempel int ret; 745f873f112SOleksij Rempel 746f873f112SOleksij Rempel ret = ksz8081_mdix_update(phydev); 747f873f112SOleksij Rempel if (ret < 0) 748f873f112SOleksij Rempel return ret; 749f873f112SOleksij Rempel 750f873f112SOleksij Rempel return genphy_read_status(phydev); 751f873f112SOleksij Rempel } 752f873f112SOleksij Rempel 753232ba3a5SRajasingh Thavamani static int ksz8061_config_init(struct phy_device *phydev) 754232ba3a5SRajasingh Thavamani { 755232ba3a5SRajasingh Thavamani int ret; 756232ba3a5SRajasingh Thavamani 757232ba3a5SRajasingh Thavamani ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A); 758232ba3a5SRajasingh Thavamani if (ret) 759232ba3a5SRajasingh Thavamani return ret; 760232ba3a5SRajasingh Thavamani 761232ba3a5SRajasingh Thavamani return kszphy_config_init(phydev); 762232ba3a5SRajasingh Thavamani } 763232ba3a5SRajasingh Thavamani 7648b95599cSMarek Vasut static int ksz8795_match_phy_device(struct phy_device *phydev) 7658b95599cSMarek Vasut { 766a5e63c7dSSteve Bennett return ksz8051_ksz8795_match_phy_device(phydev, false); 7678b95599cSMarek Vasut } 7688b95599cSMarek Vasut 769954c3967SSean Cross static int ksz9021_load_values_from_of(struct phy_device *phydev, 7703c9a9f7fSJaeden Amero const struct device_node *of_node, 7713c9a9f7fSJaeden Amero u16 reg, 7723c9a9f7fSJaeden Amero const char *field1, const char *field2, 7733c9a9f7fSJaeden Amero const char *field3, const char *field4) 774954c3967SSean Cross { 775954c3967SSean Cross int val1 = -1; 776954c3967SSean Cross int val2 = -2; 777954c3967SSean Cross int val3 = -3; 778954c3967SSean Cross int val4 = -4; 779954c3967SSean Cross int newval; 780954c3967SSean Cross int matches = 0; 781954c3967SSean Cross 782954c3967SSean Cross if (!of_property_read_u32(of_node, field1, &val1)) 783954c3967SSean Cross matches++; 784954c3967SSean Cross 785954c3967SSean Cross if (!of_property_read_u32(of_node, field2, &val2)) 786954c3967SSean Cross matches++; 787954c3967SSean Cross 788954c3967SSean Cross if (!of_property_read_u32(of_node, field3, &val3)) 789954c3967SSean Cross matches++; 790954c3967SSean Cross 791954c3967SSean Cross if (!of_property_read_u32(of_node, field4, &val4)) 792954c3967SSean Cross matches++; 793954c3967SSean Cross 794954c3967SSean Cross if (!matches) 795954c3967SSean Cross return 0; 796954c3967SSean Cross 797954c3967SSean Cross if (matches < 4) 798954c3967SSean Cross newval = kszphy_extended_read(phydev, reg); 799954c3967SSean Cross else 800954c3967SSean Cross newval = 0; 801954c3967SSean Cross 802954c3967SSean Cross if (val1 != -1) 803954c3967SSean Cross newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0); 804954c3967SSean Cross 8056a119745SHubert Chaumette if (val2 != -2) 806954c3967SSean Cross newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4); 807954c3967SSean Cross 8086a119745SHubert Chaumette if (val3 != -3) 809954c3967SSean Cross newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8); 810954c3967SSean Cross 8116a119745SHubert Chaumette if (val4 != -4) 812954c3967SSean Cross newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12); 813954c3967SSean Cross 814954c3967SSean Cross return kszphy_extended_write(phydev, reg, newval); 815954c3967SSean Cross } 816954c3967SSean Cross 817954c3967SSean Cross static int ksz9021_config_init(struct phy_device *phydev) 818954c3967SSean Cross { 819ce4f8afdSColin Ian King const struct device_node *of_node; 820651df218SAndrew Lunn const struct device *dev_walker; 821954c3967SSean Cross 822651df218SAndrew Lunn /* The Micrel driver has a deprecated option to place phy OF 823651df218SAndrew Lunn * properties in the MAC node. Walk up the tree of devices to 824651df218SAndrew Lunn * find a device with an OF node. 825651df218SAndrew Lunn */ 826e5a03bfdSAndrew Lunn dev_walker = &phydev->mdio.dev; 827651df218SAndrew Lunn do { 828651df218SAndrew Lunn of_node = dev_walker->of_node; 829651df218SAndrew Lunn dev_walker = dev_walker->parent; 830651df218SAndrew Lunn 831651df218SAndrew Lunn } while (!of_node && dev_walker); 832954c3967SSean Cross 833954c3967SSean Cross if (of_node) { 834954c3967SSean Cross ksz9021_load_values_from_of(phydev, of_node, 835954c3967SSean Cross MII_KSZPHY_CLK_CONTROL_PAD_SKEW, 836954c3967SSean Cross "txen-skew-ps", "txc-skew-ps", 837954c3967SSean Cross "rxdv-skew-ps", "rxc-skew-ps"); 838954c3967SSean Cross ksz9021_load_values_from_of(phydev, of_node, 839954c3967SSean Cross MII_KSZPHY_RX_DATA_PAD_SKEW, 840954c3967SSean Cross "rxd0-skew-ps", "rxd1-skew-ps", 841954c3967SSean Cross "rxd2-skew-ps", "rxd3-skew-ps"); 842954c3967SSean Cross ksz9021_load_values_from_of(phydev, of_node, 843954c3967SSean Cross MII_KSZPHY_TX_DATA_PAD_SKEW, 844954c3967SSean Cross "txd0-skew-ps", "txd1-skew-ps", 845954c3967SSean Cross "txd2-skew-ps", "txd3-skew-ps"); 846954c3967SSean Cross } 847954c3967SSean Cross return 0; 848954c3967SSean Cross } 849954c3967SSean Cross 8506e4b8273SHubert Chaumette #define KSZ9031_PS_TO_REG 60 8516e4b8273SHubert Chaumette 8526e4b8273SHubert Chaumette /* Extended registers */ 8536270e1aeSJaeden Amero /* MMD Address 0x0 */ 8546270e1aeSJaeden Amero #define MII_KSZ9031RN_FLP_BURST_TX_LO 3 8556270e1aeSJaeden Amero #define MII_KSZ9031RN_FLP_BURST_TX_HI 4 8566270e1aeSJaeden Amero 857ae6c97bbSJaeden Amero /* MMD Address 0x2 */ 8586e4b8273SHubert Chaumette #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4 859bcf3440cSOleksij Rempel #define MII_KSZ9031RN_RX_CTL_M GENMASK(7, 4) 860bcf3440cSOleksij Rempel #define MII_KSZ9031RN_TX_CTL_M GENMASK(3, 0) 861bcf3440cSOleksij Rempel 8626e4b8273SHubert Chaumette #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5 863bcf3440cSOleksij Rempel #define MII_KSZ9031RN_RXD3 GENMASK(15, 12) 864bcf3440cSOleksij Rempel #define MII_KSZ9031RN_RXD2 GENMASK(11, 8) 865bcf3440cSOleksij Rempel #define MII_KSZ9031RN_RXD1 GENMASK(7, 4) 866bcf3440cSOleksij Rempel #define MII_KSZ9031RN_RXD0 GENMASK(3, 0) 867bcf3440cSOleksij Rempel 8686e4b8273SHubert Chaumette #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6 869bcf3440cSOleksij Rempel #define MII_KSZ9031RN_TXD3 GENMASK(15, 12) 870bcf3440cSOleksij Rempel #define MII_KSZ9031RN_TXD2 GENMASK(11, 8) 871bcf3440cSOleksij Rempel #define MII_KSZ9031RN_TXD1 GENMASK(7, 4) 872bcf3440cSOleksij Rempel #define MII_KSZ9031RN_TXD0 GENMASK(3, 0) 873bcf3440cSOleksij Rempel 8746e4b8273SHubert Chaumette #define MII_KSZ9031RN_CLK_PAD_SKEW 8 875bcf3440cSOleksij Rempel #define MII_KSZ9031RN_GTX_CLK GENMASK(9, 5) 876bcf3440cSOleksij Rempel #define MII_KSZ9031RN_RX_CLK GENMASK(4, 0) 877bcf3440cSOleksij Rempel 878bcf3440cSOleksij Rempel /* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To 879bcf3440cSOleksij Rempel * provide different RGMII options we need to configure delay offset 880bcf3440cSOleksij Rempel * for each pad relative to build in delay. 881bcf3440cSOleksij Rempel */ 882bcf3440cSOleksij Rempel /* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of 883bcf3440cSOleksij Rempel * 1.80ns 884bcf3440cSOleksij Rempel */ 885bcf3440cSOleksij Rempel #define RX_ID 0x7 886bcf3440cSOleksij Rempel #define RX_CLK_ID 0x19 887bcf3440cSOleksij Rempel 888bcf3440cSOleksij Rempel /* set rx to +0.30ns and rx_clk to -0.90ns to compensate the 889bcf3440cSOleksij Rempel * internal 1.2ns delay. 890bcf3440cSOleksij Rempel */ 891bcf3440cSOleksij Rempel #define RX_ND 0xc 892bcf3440cSOleksij Rempel #define RX_CLK_ND 0x0 893bcf3440cSOleksij Rempel 894bcf3440cSOleksij Rempel /* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */ 895bcf3440cSOleksij Rempel #define TX_ID 0x0 896bcf3440cSOleksij Rempel #define TX_CLK_ID 0x1f 897bcf3440cSOleksij Rempel 898bcf3440cSOleksij Rempel /* set tx and tx_clk to "No delay adjustment" to keep 0ns 899bcf3440cSOleksij Rempel * dealy 900bcf3440cSOleksij Rempel */ 901bcf3440cSOleksij Rempel #define TX_ND 0x7 902bcf3440cSOleksij Rempel #define TX_CLK_ND 0xf 9036e4b8273SHubert Chaumette 904af70c1f9SMike Looijmans /* MMD Address 0x1C */ 905af70c1f9SMike Looijmans #define MII_KSZ9031RN_EDPD 0x23 906af70c1f9SMike Looijmans #define MII_KSZ9031RN_EDPD_ENABLE BIT(0) 907af70c1f9SMike Looijmans 9086e4b8273SHubert Chaumette static int ksz9031_of_load_skew_values(struct phy_device *phydev, 9093c9a9f7fSJaeden Amero const struct device_node *of_node, 9106e4b8273SHubert Chaumette u16 reg, size_t field_sz, 911bcf3440cSOleksij Rempel const char *field[], u8 numfields, 912bcf3440cSOleksij Rempel bool *update) 9136e4b8273SHubert Chaumette { 9146e4b8273SHubert Chaumette int val[4] = {-1, -2, -3, -4}; 9156e4b8273SHubert Chaumette int matches = 0; 9166e4b8273SHubert Chaumette u16 mask; 9176e4b8273SHubert Chaumette u16 maxval; 9186e4b8273SHubert Chaumette u16 newval; 9196e4b8273SHubert Chaumette int i; 9206e4b8273SHubert Chaumette 9216e4b8273SHubert Chaumette for (i = 0; i < numfields; i++) 9226e4b8273SHubert Chaumette if (!of_property_read_u32(of_node, field[i], val + i)) 9236e4b8273SHubert Chaumette matches++; 9246e4b8273SHubert Chaumette 9256e4b8273SHubert Chaumette if (!matches) 9266e4b8273SHubert Chaumette return 0; 9276e4b8273SHubert Chaumette 928bcf3440cSOleksij Rempel *update |= true; 929bcf3440cSOleksij Rempel 9306e4b8273SHubert Chaumette if (matches < numfields) 9319b420effSHeiner Kallweit newval = phy_read_mmd(phydev, 2, reg); 9326e4b8273SHubert Chaumette else 9336e4b8273SHubert Chaumette newval = 0; 9346e4b8273SHubert Chaumette 9356e4b8273SHubert Chaumette maxval = (field_sz == 4) ? 0xf : 0x1f; 9366e4b8273SHubert Chaumette for (i = 0; i < numfields; i++) 9376e4b8273SHubert Chaumette if (val[i] != -(i + 1)) { 9386e4b8273SHubert Chaumette mask = 0xffff; 9396e4b8273SHubert Chaumette mask ^= maxval << (field_sz * i); 9406e4b8273SHubert Chaumette newval = (newval & mask) | 9416e4b8273SHubert Chaumette (((val[i] / KSZ9031_PS_TO_REG) & maxval) 9426e4b8273SHubert Chaumette << (field_sz * i)); 9436e4b8273SHubert Chaumette } 9446e4b8273SHubert Chaumette 9459b420effSHeiner Kallweit return phy_write_mmd(phydev, 2, reg, newval); 9466e4b8273SHubert Chaumette } 9476e4b8273SHubert Chaumette 948a0da456bSMax Uvarov /* Center KSZ9031RNX FLP timing at 16ms. */ 9496270e1aeSJaeden Amero static int ksz9031_center_flp_timing(struct phy_device *phydev) 9506270e1aeSJaeden Amero { 9516270e1aeSJaeden Amero int result; 9526270e1aeSJaeden Amero 9539b420effSHeiner Kallweit result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI, 9549b420effSHeiner Kallweit 0x0006); 955a0da456bSMax Uvarov if (result) 956a0da456bSMax Uvarov return result; 957a0da456bSMax Uvarov 9589b420effSHeiner Kallweit result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO, 9599b420effSHeiner Kallweit 0x1A80); 9606270e1aeSJaeden Amero if (result) 9616270e1aeSJaeden Amero return result; 9626270e1aeSJaeden Amero 9636270e1aeSJaeden Amero return genphy_restart_aneg(phydev); 9646270e1aeSJaeden Amero } 9656270e1aeSJaeden Amero 966af70c1f9SMike Looijmans /* Enable energy-detect power-down mode */ 967af70c1f9SMike Looijmans static int ksz9031_enable_edpd(struct phy_device *phydev) 968af70c1f9SMike Looijmans { 969af70c1f9SMike Looijmans int reg; 970af70c1f9SMike Looijmans 9719b420effSHeiner Kallweit reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD); 972af70c1f9SMike Looijmans if (reg < 0) 973af70c1f9SMike Looijmans return reg; 9749b420effSHeiner Kallweit return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD, 975af70c1f9SMike Looijmans reg | MII_KSZ9031RN_EDPD_ENABLE); 976af70c1f9SMike Looijmans } 977af70c1f9SMike Looijmans 978bcf3440cSOleksij Rempel static int ksz9031_config_rgmii_delay(struct phy_device *phydev) 979bcf3440cSOleksij Rempel { 980bcf3440cSOleksij Rempel u16 rx, tx, rx_clk, tx_clk; 981bcf3440cSOleksij Rempel int ret; 982bcf3440cSOleksij Rempel 983bcf3440cSOleksij Rempel switch (phydev->interface) { 984bcf3440cSOleksij Rempel case PHY_INTERFACE_MODE_RGMII: 985bcf3440cSOleksij Rempel tx = TX_ND; 986bcf3440cSOleksij Rempel tx_clk = TX_CLK_ND; 987bcf3440cSOleksij Rempel rx = RX_ND; 988bcf3440cSOleksij Rempel rx_clk = RX_CLK_ND; 989bcf3440cSOleksij Rempel break; 990bcf3440cSOleksij Rempel case PHY_INTERFACE_MODE_RGMII_ID: 991bcf3440cSOleksij Rempel tx = TX_ID; 992bcf3440cSOleksij Rempel tx_clk = TX_CLK_ID; 993bcf3440cSOleksij Rempel rx = RX_ID; 994bcf3440cSOleksij Rempel rx_clk = RX_CLK_ID; 995bcf3440cSOleksij Rempel break; 996bcf3440cSOleksij Rempel case PHY_INTERFACE_MODE_RGMII_RXID: 997bcf3440cSOleksij Rempel tx = TX_ND; 998bcf3440cSOleksij Rempel tx_clk = TX_CLK_ND; 999bcf3440cSOleksij Rempel rx = RX_ID; 1000bcf3440cSOleksij Rempel rx_clk = RX_CLK_ID; 1001bcf3440cSOleksij Rempel break; 1002bcf3440cSOleksij Rempel case PHY_INTERFACE_MODE_RGMII_TXID: 1003bcf3440cSOleksij Rempel tx = TX_ID; 1004bcf3440cSOleksij Rempel tx_clk = TX_CLK_ID; 1005bcf3440cSOleksij Rempel rx = RX_ND; 1006bcf3440cSOleksij Rempel rx_clk = RX_CLK_ND; 1007bcf3440cSOleksij Rempel break; 1008bcf3440cSOleksij Rempel default: 1009bcf3440cSOleksij Rempel return 0; 1010bcf3440cSOleksij Rempel } 1011bcf3440cSOleksij Rempel 1012bcf3440cSOleksij Rempel ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW, 1013bcf3440cSOleksij Rempel FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) | 1014bcf3440cSOleksij Rempel FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx)); 1015bcf3440cSOleksij Rempel if (ret < 0) 1016bcf3440cSOleksij Rempel return ret; 1017bcf3440cSOleksij Rempel 1018bcf3440cSOleksij Rempel ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW, 1019bcf3440cSOleksij Rempel FIELD_PREP(MII_KSZ9031RN_RXD3, rx) | 1020bcf3440cSOleksij Rempel FIELD_PREP(MII_KSZ9031RN_RXD2, rx) | 1021bcf3440cSOleksij Rempel FIELD_PREP(MII_KSZ9031RN_RXD1, rx) | 1022bcf3440cSOleksij Rempel FIELD_PREP(MII_KSZ9031RN_RXD0, rx)); 1023bcf3440cSOleksij Rempel if (ret < 0) 1024bcf3440cSOleksij Rempel return ret; 1025bcf3440cSOleksij Rempel 1026bcf3440cSOleksij Rempel ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW, 1027bcf3440cSOleksij Rempel FIELD_PREP(MII_KSZ9031RN_TXD3, tx) | 1028bcf3440cSOleksij Rempel FIELD_PREP(MII_KSZ9031RN_TXD2, tx) | 1029bcf3440cSOleksij Rempel FIELD_PREP(MII_KSZ9031RN_TXD1, tx) | 1030bcf3440cSOleksij Rempel FIELD_PREP(MII_KSZ9031RN_TXD0, tx)); 1031bcf3440cSOleksij Rempel if (ret < 0) 1032bcf3440cSOleksij Rempel return ret; 1033bcf3440cSOleksij Rempel 1034bcf3440cSOleksij Rempel return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW, 1035bcf3440cSOleksij Rempel FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) | 1036bcf3440cSOleksij Rempel FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk)); 1037bcf3440cSOleksij Rempel } 1038bcf3440cSOleksij Rempel 10396e4b8273SHubert Chaumette static int ksz9031_config_init(struct phy_device *phydev) 10406e4b8273SHubert Chaumette { 1041ce4f8afdSColin Ian King const struct device_node *of_node; 10423c9a9f7fSJaeden Amero static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"}; 10433c9a9f7fSJaeden Amero static const char *rx_data_skews[4] = { 10446e4b8273SHubert Chaumette "rxd0-skew-ps", "rxd1-skew-ps", 10456e4b8273SHubert Chaumette "rxd2-skew-ps", "rxd3-skew-ps" 10466e4b8273SHubert Chaumette }; 10473c9a9f7fSJaeden Amero static const char *tx_data_skews[4] = { 10486e4b8273SHubert Chaumette "txd0-skew-ps", "txd1-skew-ps", 10496e4b8273SHubert Chaumette "txd2-skew-ps", "txd3-skew-ps" 10506e4b8273SHubert Chaumette }; 10513c9a9f7fSJaeden Amero static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"}; 1052b4c19f71SRoosen Henri const struct device *dev_walker; 1053af70c1f9SMike Looijmans int result; 1054af70c1f9SMike Looijmans 1055af70c1f9SMike Looijmans result = ksz9031_enable_edpd(phydev); 1056af70c1f9SMike Looijmans if (result < 0) 1057af70c1f9SMike Looijmans return result; 10586e4b8273SHubert Chaumette 1059b4c19f71SRoosen Henri /* The Micrel driver has a deprecated option to place phy OF 1060b4c19f71SRoosen Henri * properties in the MAC node. Walk up the tree of devices to 1061b4c19f71SRoosen Henri * find a device with an OF node. 1062b4c19f71SRoosen Henri */ 10639d367eddSDavid S. Miller dev_walker = &phydev->mdio.dev; 1064b4c19f71SRoosen Henri do { 1065b4c19f71SRoosen Henri of_node = dev_walker->of_node; 1066b4c19f71SRoosen Henri dev_walker = dev_walker->parent; 1067b4c19f71SRoosen Henri } while (!of_node && dev_walker); 10686e4b8273SHubert Chaumette 10696e4b8273SHubert Chaumette if (of_node) { 1070bcf3440cSOleksij Rempel bool update = false; 1071bcf3440cSOleksij Rempel 1072bcf3440cSOleksij Rempel if (phy_interface_is_rgmii(phydev)) { 1073bcf3440cSOleksij Rempel result = ksz9031_config_rgmii_delay(phydev); 1074bcf3440cSOleksij Rempel if (result < 0) 1075bcf3440cSOleksij Rempel return result; 1076bcf3440cSOleksij Rempel } 1077bcf3440cSOleksij Rempel 10786e4b8273SHubert Chaumette ksz9031_of_load_skew_values(phydev, of_node, 10796e4b8273SHubert Chaumette MII_KSZ9031RN_CLK_PAD_SKEW, 5, 1080bcf3440cSOleksij Rempel clk_skews, 2, &update); 10816e4b8273SHubert Chaumette 10826e4b8273SHubert Chaumette ksz9031_of_load_skew_values(phydev, of_node, 10836e4b8273SHubert Chaumette MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, 1084bcf3440cSOleksij Rempel control_skews, 2, &update); 10856e4b8273SHubert Chaumette 10866e4b8273SHubert Chaumette ksz9031_of_load_skew_values(phydev, of_node, 10876e4b8273SHubert Chaumette MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, 1088bcf3440cSOleksij Rempel rx_data_skews, 4, &update); 10896e4b8273SHubert Chaumette 10906e4b8273SHubert Chaumette ksz9031_of_load_skew_values(phydev, of_node, 10916e4b8273SHubert Chaumette MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, 1092bcf3440cSOleksij Rempel tx_data_skews, 4, &update); 1093bcf3440cSOleksij Rempel 109467ca5159SMatthias Schiffer if (update && !phy_interface_is_rgmii(phydev)) 1095bcf3440cSOleksij Rempel phydev_warn(phydev, 109667ca5159SMatthias Schiffer "*-skew-ps values should be used only with RGMII PHY modes\n"); 1097e1b505a6SMarkus Niebel 1098e1b505a6SMarkus Niebel /* Silicon Errata Sheet (DS80000691D or DS80000692D): 1099e1b505a6SMarkus Niebel * When the device links in the 1000BASE-T slave mode only, 1100e1b505a6SMarkus Niebel * the optional 125MHz reference output clock (CLK125_NDO) 1101e1b505a6SMarkus Niebel * has wide duty cycle variation. 1102e1b505a6SMarkus Niebel * 1103e1b505a6SMarkus Niebel * The optional CLK125_NDO clock does not meet the RGMII 1104e1b505a6SMarkus Niebel * 45/55 percent (min/max) duty cycle requirement and therefore 1105e1b505a6SMarkus Niebel * cannot be used directly by the MAC side for clocking 1106e1b505a6SMarkus Niebel * applications that have setup/hold time requirements on 1107e1b505a6SMarkus Niebel * rising and falling clock edges. 1108e1b505a6SMarkus Niebel * 1109e1b505a6SMarkus Niebel * Workaround: 1110e1b505a6SMarkus Niebel * Force the phy to be the master to receive a stable clock 1111e1b505a6SMarkus Niebel * which meets the duty cycle requirement. 1112e1b505a6SMarkus Niebel */ 1113e1b505a6SMarkus Niebel if (of_property_read_bool(of_node, "micrel,force-master")) { 1114e1b505a6SMarkus Niebel result = phy_read(phydev, MII_CTRL1000); 1115e1b505a6SMarkus Niebel if (result < 0) 1116e1b505a6SMarkus Niebel goto err_force_master; 1117e1b505a6SMarkus Niebel 1118e1b505a6SMarkus Niebel /* enable master mode, config & prefer master */ 1119e1b505a6SMarkus Niebel result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER; 1120e1b505a6SMarkus Niebel result = phy_write(phydev, MII_CTRL1000, result); 1121e1b505a6SMarkus Niebel if (result < 0) 1122e1b505a6SMarkus Niebel goto err_force_master; 1123e1b505a6SMarkus Niebel } 11246e4b8273SHubert Chaumette } 11256270e1aeSJaeden Amero 11266270e1aeSJaeden Amero return ksz9031_center_flp_timing(phydev); 1127e1b505a6SMarkus Niebel 1128e1b505a6SMarkus Niebel err_force_master: 1129e1b505a6SMarkus Niebel phydev_err(phydev, "failed to force the phy to master mode\n"); 1130e1b505a6SMarkus Niebel return result; 11316e4b8273SHubert Chaumette } 11326e4b8273SHubert Chaumette 1133bff5b4b3SYuiko Oshino #define KSZ9131_SKEW_5BIT_MAX 2400 1134bff5b4b3SYuiko Oshino #define KSZ9131_SKEW_4BIT_MAX 800 1135bff5b4b3SYuiko Oshino #define KSZ9131_OFFSET 700 1136bff5b4b3SYuiko Oshino #define KSZ9131_STEP 100 1137bff5b4b3SYuiko Oshino 1138bff5b4b3SYuiko Oshino static int ksz9131_of_load_skew_values(struct phy_device *phydev, 1139bff5b4b3SYuiko Oshino struct device_node *of_node, 1140bff5b4b3SYuiko Oshino u16 reg, size_t field_sz, 1141bff5b4b3SYuiko Oshino char *field[], u8 numfields) 1142bff5b4b3SYuiko Oshino { 1143bff5b4b3SYuiko Oshino int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET), 1144bff5b4b3SYuiko Oshino -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)}; 1145bff5b4b3SYuiko Oshino int skewval, skewmax = 0; 1146bff5b4b3SYuiko Oshino int matches = 0; 1147bff5b4b3SYuiko Oshino u16 maxval; 1148bff5b4b3SYuiko Oshino u16 newval; 1149bff5b4b3SYuiko Oshino u16 mask; 1150bff5b4b3SYuiko Oshino int i; 1151bff5b4b3SYuiko Oshino 1152bff5b4b3SYuiko Oshino /* psec properties in dts should mean x pico seconds */ 1153bff5b4b3SYuiko Oshino if (field_sz == 5) 1154bff5b4b3SYuiko Oshino skewmax = KSZ9131_SKEW_5BIT_MAX; 1155bff5b4b3SYuiko Oshino else 1156bff5b4b3SYuiko Oshino skewmax = KSZ9131_SKEW_4BIT_MAX; 1157bff5b4b3SYuiko Oshino 1158bff5b4b3SYuiko Oshino for (i = 0; i < numfields; i++) 1159bff5b4b3SYuiko Oshino if (!of_property_read_s32(of_node, field[i], &skewval)) { 1160bff5b4b3SYuiko Oshino if (skewval < -KSZ9131_OFFSET) 1161bff5b4b3SYuiko Oshino skewval = -KSZ9131_OFFSET; 1162bff5b4b3SYuiko Oshino else if (skewval > skewmax) 1163bff5b4b3SYuiko Oshino skewval = skewmax; 1164bff5b4b3SYuiko Oshino 1165bff5b4b3SYuiko Oshino val[i] = skewval + KSZ9131_OFFSET; 1166bff5b4b3SYuiko Oshino matches++; 1167bff5b4b3SYuiko Oshino } 1168bff5b4b3SYuiko Oshino 1169bff5b4b3SYuiko Oshino if (!matches) 1170bff5b4b3SYuiko Oshino return 0; 1171bff5b4b3SYuiko Oshino 1172bff5b4b3SYuiko Oshino if (matches < numfields) 11739b420effSHeiner Kallweit newval = phy_read_mmd(phydev, 2, reg); 1174bff5b4b3SYuiko Oshino else 1175bff5b4b3SYuiko Oshino newval = 0; 1176bff5b4b3SYuiko Oshino 1177bff5b4b3SYuiko Oshino maxval = (field_sz == 4) ? 0xf : 0x1f; 1178bff5b4b3SYuiko Oshino for (i = 0; i < numfields; i++) 1179bff5b4b3SYuiko Oshino if (val[i] != -(i + 1 + KSZ9131_OFFSET)) { 1180bff5b4b3SYuiko Oshino mask = 0xffff; 1181bff5b4b3SYuiko Oshino mask ^= maxval << (field_sz * i); 1182bff5b4b3SYuiko Oshino newval = (newval & mask) | 1183bff5b4b3SYuiko Oshino (((val[i] / KSZ9131_STEP) & maxval) 1184bff5b4b3SYuiko Oshino << (field_sz * i)); 1185bff5b4b3SYuiko Oshino } 1186bff5b4b3SYuiko Oshino 11879b420effSHeiner Kallweit return phy_write_mmd(phydev, 2, reg, newval); 1188bff5b4b3SYuiko Oshino } 1189bff5b4b3SYuiko Oshino 1190bd734a74SPhilippe Schenker #define KSZ9131RN_MMD_COMMON_CTRL_REG 2 1191bd734a74SPhilippe Schenker #define KSZ9131RN_RXC_DLL_CTRL 76 1192bd734a74SPhilippe Schenker #define KSZ9131RN_TXC_DLL_CTRL 77 1193bd734a74SPhilippe Schenker #define KSZ9131RN_DLL_ENABLE_DELAY 0 1194bd734a74SPhilippe Schenker 1195bd734a74SPhilippe Schenker static int ksz9131_config_rgmii_delay(struct phy_device *phydev) 1196bd734a74SPhilippe Schenker { 1197a8f1a19dSHoratiu Vultur const struct kszphy_type *type = phydev->drv->driver_data; 1198bd734a74SPhilippe Schenker u16 rxcdll_val, txcdll_val; 1199bd734a74SPhilippe Schenker int ret; 1200bd734a74SPhilippe Schenker 1201bd734a74SPhilippe Schenker switch (phydev->interface) { 1202bd734a74SPhilippe Schenker case PHY_INTERFACE_MODE_RGMII: 1203a8f1a19dSHoratiu Vultur rxcdll_val = type->disable_dll_rx_bit; 1204a8f1a19dSHoratiu Vultur txcdll_val = type->disable_dll_tx_bit; 1205bd734a74SPhilippe Schenker break; 1206bd734a74SPhilippe Schenker case PHY_INTERFACE_MODE_RGMII_ID: 1207bd734a74SPhilippe Schenker rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; 1208bd734a74SPhilippe Schenker txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; 1209bd734a74SPhilippe Schenker break; 1210bd734a74SPhilippe Schenker case PHY_INTERFACE_MODE_RGMII_RXID: 1211bd734a74SPhilippe Schenker rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; 1212a8f1a19dSHoratiu Vultur txcdll_val = type->disable_dll_tx_bit; 1213bd734a74SPhilippe Schenker break; 1214bd734a74SPhilippe Schenker case PHY_INTERFACE_MODE_RGMII_TXID: 1215a8f1a19dSHoratiu Vultur rxcdll_val = type->disable_dll_rx_bit; 1216bd734a74SPhilippe Schenker txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; 1217bd734a74SPhilippe Schenker break; 1218bd734a74SPhilippe Schenker default: 1219bd734a74SPhilippe Schenker return 0; 1220bd734a74SPhilippe Schenker } 1221bd734a74SPhilippe Schenker 1222bd734a74SPhilippe Schenker ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, 1223a8f1a19dSHoratiu Vultur KSZ9131RN_RXC_DLL_CTRL, type->disable_dll_mask, 1224bd734a74SPhilippe Schenker rxcdll_val); 1225bd734a74SPhilippe Schenker if (ret < 0) 1226bd734a74SPhilippe Schenker return ret; 1227bd734a74SPhilippe Schenker 1228bd734a74SPhilippe Schenker return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, 1229a8f1a19dSHoratiu Vultur KSZ9131RN_TXC_DLL_CTRL, type->disable_dll_mask, 1230bd734a74SPhilippe Schenker txcdll_val); 1231bd734a74SPhilippe Schenker } 1232bd734a74SPhilippe Schenker 12330316c7e6SFrancesco Dolcini /* Silicon Errata DS80000693B 12340316c7e6SFrancesco Dolcini * 12350316c7e6SFrancesco Dolcini * When LEDs are configured in Individual Mode, LED1 is ON in a no-link 12360316c7e6SFrancesco Dolcini * condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves 12370316c7e6SFrancesco Dolcini * according to the datasheet (off if there is no link). 12380316c7e6SFrancesco Dolcini */ 12390316c7e6SFrancesco Dolcini static int ksz9131_led_errata(struct phy_device *phydev) 12400316c7e6SFrancesco Dolcini { 12410316c7e6SFrancesco Dolcini int reg; 12420316c7e6SFrancesco Dolcini 12430316c7e6SFrancesco Dolcini reg = phy_read_mmd(phydev, 2, 0); 12440316c7e6SFrancesco Dolcini if (reg < 0) 12450316c7e6SFrancesco Dolcini return reg; 12460316c7e6SFrancesco Dolcini 12470316c7e6SFrancesco Dolcini if (!(reg & BIT(4))) 12480316c7e6SFrancesco Dolcini return 0; 12490316c7e6SFrancesco Dolcini 12500316c7e6SFrancesco Dolcini return phy_set_bits(phydev, 0x1e, BIT(9)); 12510316c7e6SFrancesco Dolcini } 12520316c7e6SFrancesco Dolcini 1253bff5b4b3SYuiko Oshino static int ksz9131_config_init(struct phy_device *phydev) 1254bff5b4b3SYuiko Oshino { 1255ce4f8afdSColin Ian King struct device_node *of_node; 1256bff5b4b3SYuiko Oshino char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"}; 1257bff5b4b3SYuiko Oshino char *rx_data_skews[4] = { 1258bff5b4b3SYuiko Oshino "rxd0-skew-psec", "rxd1-skew-psec", 1259bff5b4b3SYuiko Oshino "rxd2-skew-psec", "rxd3-skew-psec" 1260bff5b4b3SYuiko Oshino }; 1261bff5b4b3SYuiko Oshino char *tx_data_skews[4] = { 1262bff5b4b3SYuiko Oshino "txd0-skew-psec", "txd1-skew-psec", 1263bff5b4b3SYuiko Oshino "txd2-skew-psec", "txd3-skew-psec" 1264bff5b4b3SYuiko Oshino }; 1265bff5b4b3SYuiko Oshino char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"}; 1266bff5b4b3SYuiko Oshino const struct device *dev_walker; 1267bff5b4b3SYuiko Oshino int ret; 1268bff5b4b3SYuiko Oshino 1269bff5b4b3SYuiko Oshino dev_walker = &phydev->mdio.dev; 1270bff5b4b3SYuiko Oshino do { 1271bff5b4b3SYuiko Oshino of_node = dev_walker->of_node; 1272bff5b4b3SYuiko Oshino dev_walker = dev_walker->parent; 1273bff5b4b3SYuiko Oshino } while (!of_node && dev_walker); 1274bff5b4b3SYuiko Oshino 1275bff5b4b3SYuiko Oshino if (!of_node) 1276bff5b4b3SYuiko Oshino return 0; 1277bff5b4b3SYuiko Oshino 1278bd734a74SPhilippe Schenker if (phy_interface_is_rgmii(phydev)) { 1279bd734a74SPhilippe Schenker ret = ksz9131_config_rgmii_delay(phydev); 1280bd734a74SPhilippe Schenker if (ret < 0) 1281bd734a74SPhilippe Schenker return ret; 1282bd734a74SPhilippe Schenker } 1283bd734a74SPhilippe Schenker 1284bff5b4b3SYuiko Oshino ret = ksz9131_of_load_skew_values(phydev, of_node, 1285bff5b4b3SYuiko Oshino MII_KSZ9031RN_CLK_PAD_SKEW, 5, 1286bff5b4b3SYuiko Oshino clk_skews, 2); 1287bff5b4b3SYuiko Oshino if (ret < 0) 1288bff5b4b3SYuiko Oshino return ret; 1289bff5b4b3SYuiko Oshino 1290bff5b4b3SYuiko Oshino ret = ksz9131_of_load_skew_values(phydev, of_node, 1291bff5b4b3SYuiko Oshino MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, 1292bff5b4b3SYuiko Oshino control_skews, 2); 1293bff5b4b3SYuiko Oshino if (ret < 0) 1294bff5b4b3SYuiko Oshino return ret; 1295bff5b4b3SYuiko Oshino 1296bff5b4b3SYuiko Oshino ret = ksz9131_of_load_skew_values(phydev, of_node, 1297bff5b4b3SYuiko Oshino MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, 1298bff5b4b3SYuiko Oshino rx_data_skews, 4); 1299bff5b4b3SYuiko Oshino if (ret < 0) 1300bff5b4b3SYuiko Oshino return ret; 1301bff5b4b3SYuiko Oshino 1302bff5b4b3SYuiko Oshino ret = ksz9131_of_load_skew_values(phydev, of_node, 1303bff5b4b3SYuiko Oshino MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, 1304bff5b4b3SYuiko Oshino tx_data_skews, 4); 1305bff5b4b3SYuiko Oshino if (ret < 0) 1306bff5b4b3SYuiko Oshino return ret; 1307bff5b4b3SYuiko Oshino 13080316c7e6SFrancesco Dolcini ret = ksz9131_led_errata(phydev); 13090316c7e6SFrancesco Dolcini if (ret < 0) 13100316c7e6SFrancesco Dolcini return ret; 13110316c7e6SFrancesco Dolcini 1312bff5b4b3SYuiko Oshino return 0; 1313bff5b4b3SYuiko Oshino } 1314bff5b4b3SYuiko Oshino 1315b64e6a87SRaju Lakkaraju #define MII_KSZ9131_AUTO_MDIX 0x1C 1316b64e6a87SRaju Lakkaraju #define MII_KSZ9131_AUTO_MDI_SET BIT(7) 1317b64e6a87SRaju Lakkaraju #define MII_KSZ9131_AUTO_MDIX_SWAP_OFF BIT(6) 1318b64e6a87SRaju Lakkaraju 1319b64e6a87SRaju Lakkaraju static int ksz9131_mdix_update(struct phy_device *phydev) 1320b64e6a87SRaju Lakkaraju { 1321b64e6a87SRaju Lakkaraju int ret; 1322b64e6a87SRaju Lakkaraju 1323b64e6a87SRaju Lakkaraju ret = phy_read(phydev, MII_KSZ9131_AUTO_MDIX); 1324b64e6a87SRaju Lakkaraju if (ret < 0) 1325b64e6a87SRaju Lakkaraju return ret; 1326b64e6a87SRaju Lakkaraju 1327b64e6a87SRaju Lakkaraju if (ret & MII_KSZ9131_AUTO_MDIX_SWAP_OFF) { 1328b64e6a87SRaju Lakkaraju if (ret & MII_KSZ9131_AUTO_MDI_SET) 1329b64e6a87SRaju Lakkaraju phydev->mdix_ctrl = ETH_TP_MDI; 1330b64e6a87SRaju Lakkaraju else 1331b64e6a87SRaju Lakkaraju phydev->mdix_ctrl = ETH_TP_MDI_X; 1332b64e6a87SRaju Lakkaraju } else { 1333b64e6a87SRaju Lakkaraju phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 1334b64e6a87SRaju Lakkaraju } 1335b64e6a87SRaju Lakkaraju 1336b64e6a87SRaju Lakkaraju if (ret & MII_KSZ9131_AUTO_MDI_SET) 1337b64e6a87SRaju Lakkaraju phydev->mdix = ETH_TP_MDI; 1338b64e6a87SRaju Lakkaraju else 1339b64e6a87SRaju Lakkaraju phydev->mdix = ETH_TP_MDI_X; 1340b64e6a87SRaju Lakkaraju 1341b64e6a87SRaju Lakkaraju return 0; 1342b64e6a87SRaju Lakkaraju } 1343b64e6a87SRaju Lakkaraju 1344b64e6a87SRaju Lakkaraju static int ksz9131_config_mdix(struct phy_device *phydev, u8 ctrl) 1345b64e6a87SRaju Lakkaraju { 1346b64e6a87SRaju Lakkaraju u16 val; 1347b64e6a87SRaju Lakkaraju 1348b64e6a87SRaju Lakkaraju switch (ctrl) { 1349b64e6a87SRaju Lakkaraju case ETH_TP_MDI: 1350b64e6a87SRaju Lakkaraju val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF | 1351b64e6a87SRaju Lakkaraju MII_KSZ9131_AUTO_MDI_SET; 1352b64e6a87SRaju Lakkaraju break; 1353b64e6a87SRaju Lakkaraju case ETH_TP_MDI_X: 1354b64e6a87SRaju Lakkaraju val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF; 1355b64e6a87SRaju Lakkaraju break; 1356b64e6a87SRaju Lakkaraju case ETH_TP_MDI_AUTO: 1357b64e6a87SRaju Lakkaraju val = 0; 1358b64e6a87SRaju Lakkaraju break; 1359b64e6a87SRaju Lakkaraju default: 1360b64e6a87SRaju Lakkaraju return 0; 1361b64e6a87SRaju Lakkaraju } 1362b64e6a87SRaju Lakkaraju 1363b64e6a87SRaju Lakkaraju return phy_modify(phydev, MII_KSZ9131_AUTO_MDIX, 1364b64e6a87SRaju Lakkaraju MII_KSZ9131_AUTO_MDIX_SWAP_OFF | 1365b64e6a87SRaju Lakkaraju MII_KSZ9131_AUTO_MDI_SET, val); 1366b64e6a87SRaju Lakkaraju } 1367b64e6a87SRaju Lakkaraju 1368b64e6a87SRaju Lakkaraju static int ksz9131_read_status(struct phy_device *phydev) 1369b64e6a87SRaju Lakkaraju { 1370b64e6a87SRaju Lakkaraju int ret; 1371b64e6a87SRaju Lakkaraju 1372b64e6a87SRaju Lakkaraju ret = ksz9131_mdix_update(phydev); 1373b64e6a87SRaju Lakkaraju if (ret < 0) 1374b64e6a87SRaju Lakkaraju return ret; 1375b64e6a87SRaju Lakkaraju 1376b64e6a87SRaju Lakkaraju return genphy_read_status(phydev); 1377b64e6a87SRaju Lakkaraju } 1378b64e6a87SRaju Lakkaraju 1379b64e6a87SRaju Lakkaraju static int ksz9131_config_aneg(struct phy_device *phydev) 1380b64e6a87SRaju Lakkaraju { 1381b64e6a87SRaju Lakkaraju int ret; 1382b64e6a87SRaju Lakkaraju 1383b64e6a87SRaju Lakkaraju ret = ksz9131_config_mdix(phydev, phydev->mdix_ctrl); 1384b64e6a87SRaju Lakkaraju if (ret) 1385b64e6a87SRaju Lakkaraju return ret; 1386b64e6a87SRaju Lakkaraju 1387b64e6a87SRaju Lakkaraju return genphy_config_aneg(phydev); 1388b64e6a87SRaju Lakkaraju } 1389b64e6a87SRaju Lakkaraju 139093272e07SJean-Christophe PLAGNIOL-VILLARD #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06 139100aee095SJohan Hovold #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6) 139200aee095SJohan Hovold #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4) 139332d73b14SJingoo Han static int ksz8873mll_read_status(struct phy_device *phydev) 139493272e07SJean-Christophe PLAGNIOL-VILLARD { 139593272e07SJean-Christophe PLAGNIOL-VILLARD int regval; 139693272e07SJean-Christophe PLAGNIOL-VILLARD 139793272e07SJean-Christophe PLAGNIOL-VILLARD /* dummy read */ 139893272e07SJean-Christophe PLAGNIOL-VILLARD regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 139993272e07SJean-Christophe PLAGNIOL-VILLARD 140093272e07SJean-Christophe PLAGNIOL-VILLARD regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 140193272e07SJean-Christophe PLAGNIOL-VILLARD 140293272e07SJean-Christophe PLAGNIOL-VILLARD if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX) 140393272e07SJean-Christophe PLAGNIOL-VILLARD phydev->duplex = DUPLEX_HALF; 140493272e07SJean-Christophe PLAGNIOL-VILLARD else 140593272e07SJean-Christophe PLAGNIOL-VILLARD phydev->duplex = DUPLEX_FULL; 140693272e07SJean-Christophe PLAGNIOL-VILLARD 140793272e07SJean-Christophe PLAGNIOL-VILLARD if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED) 140893272e07SJean-Christophe PLAGNIOL-VILLARD phydev->speed = SPEED_10; 140993272e07SJean-Christophe PLAGNIOL-VILLARD else 141093272e07SJean-Christophe PLAGNIOL-VILLARD phydev->speed = SPEED_100; 141193272e07SJean-Christophe PLAGNIOL-VILLARD 141293272e07SJean-Christophe PLAGNIOL-VILLARD phydev->link = 1; 141393272e07SJean-Christophe PLAGNIOL-VILLARD phydev->pause = phydev->asym_pause = 0; 141493272e07SJean-Christophe PLAGNIOL-VILLARD 141593272e07SJean-Christophe PLAGNIOL-VILLARD return 0; 141693272e07SJean-Christophe PLAGNIOL-VILLARD } 141793272e07SJean-Christophe PLAGNIOL-VILLARD 14183aed3e2aSAntoine Tenart static int ksz9031_get_features(struct phy_device *phydev) 14193aed3e2aSAntoine Tenart { 14203aed3e2aSAntoine Tenart int ret; 14213aed3e2aSAntoine Tenart 14223aed3e2aSAntoine Tenart ret = genphy_read_abilities(phydev); 14233aed3e2aSAntoine Tenart if (ret < 0) 14243aed3e2aSAntoine Tenart return ret; 14253aed3e2aSAntoine Tenart 14263aed3e2aSAntoine Tenart /* Silicon Errata Sheet (DS80000691D or DS80000692D): 14273aed3e2aSAntoine Tenart * Whenever the device's Asymmetric Pause capability is set to 1, 14283aed3e2aSAntoine Tenart * link-up may fail after a link-up to link-down transition. 14293aed3e2aSAntoine Tenart * 1430407d8098SHans Andersson * The Errata Sheet is for ksz9031, but ksz9021 has the same issue 1431407d8098SHans Andersson * 14323aed3e2aSAntoine Tenart * Workaround: 14333aed3e2aSAntoine Tenart * Do not enable the Asymmetric Pause capability bit. 14343aed3e2aSAntoine Tenart */ 14353aed3e2aSAntoine Tenart linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported); 14363aed3e2aSAntoine Tenart 14373aed3e2aSAntoine Tenart /* We force setting the Pause capability as the core will force the 14383aed3e2aSAntoine Tenart * Asymmetric Pause capability to 1 otherwise. 14393aed3e2aSAntoine Tenart */ 14403aed3e2aSAntoine Tenart linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported); 14413aed3e2aSAntoine Tenart 14423aed3e2aSAntoine Tenart return 0; 14433aed3e2aSAntoine Tenart } 14443aed3e2aSAntoine Tenart 1445d2fd719bSNathan Sullivan static int ksz9031_read_status(struct phy_device *phydev) 1446d2fd719bSNathan Sullivan { 1447d2fd719bSNathan Sullivan int err; 1448d2fd719bSNathan Sullivan int regval; 1449d2fd719bSNathan Sullivan 1450d2fd719bSNathan Sullivan err = genphy_read_status(phydev); 1451d2fd719bSNathan Sullivan if (err) 1452d2fd719bSNathan Sullivan return err; 1453d2fd719bSNathan Sullivan 1454d2fd719bSNathan Sullivan /* Make sure the PHY is not broken. Read idle error count, 1455d2fd719bSNathan Sullivan * and reset the PHY if it is maxed out. 1456d2fd719bSNathan Sullivan */ 1457d2fd719bSNathan Sullivan regval = phy_read(phydev, MII_STAT1000); 1458d2fd719bSNathan Sullivan if ((regval & 0xFF) == 0xFF) { 1459d2fd719bSNathan Sullivan phy_init_hw(phydev); 1460d2fd719bSNathan Sullivan phydev->link = 0; 1461b866203dSZach Brown if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev)) 1462b866203dSZach Brown phydev->drv->config_intr(phydev); 1463c1a8d0a3SGrygorii Strashko return genphy_config_aneg(phydev); 1464d2fd719bSNathan Sullivan } 1465d2fd719bSNathan Sullivan 1466d2fd719bSNathan Sullivan return 0; 1467d2fd719bSNathan Sullivan } 1468d2fd719bSNathan Sullivan 146958389c00SMarek Vasut static int ksz9x31_cable_test_start(struct phy_device *phydev) 147058389c00SMarek Vasut { 147158389c00SMarek Vasut struct kszphy_priv *priv = phydev->priv; 147258389c00SMarek Vasut int ret; 147358389c00SMarek Vasut 147458389c00SMarek Vasut /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic 147558389c00SMarek Vasut * Prior to running the cable diagnostics, Auto-negotiation should 147658389c00SMarek Vasut * be disabled, full duplex set and the link speed set to 1000Mbps 147758389c00SMarek Vasut * via the Basic Control Register. 147858389c00SMarek Vasut */ 147958389c00SMarek Vasut ret = phy_modify(phydev, MII_BMCR, 148058389c00SMarek Vasut BMCR_SPEED1000 | BMCR_FULLDPLX | 148158389c00SMarek Vasut BMCR_ANENABLE | BMCR_SPEED100, 148258389c00SMarek Vasut BMCR_SPEED1000 | BMCR_FULLDPLX); 148358389c00SMarek Vasut if (ret) 148458389c00SMarek Vasut return ret; 148558389c00SMarek Vasut 148658389c00SMarek Vasut /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic 148758389c00SMarek Vasut * The Master-Slave configuration should be set to Slave by writing 148858389c00SMarek Vasut * a value of 0x1000 to the Auto-Negotiation Master Slave Control 148958389c00SMarek Vasut * Register. 149058389c00SMarek Vasut */ 149158389c00SMarek Vasut ret = phy_read(phydev, MII_CTRL1000); 149258389c00SMarek Vasut if (ret < 0) 149358389c00SMarek Vasut return ret; 149458389c00SMarek Vasut 149558389c00SMarek Vasut /* Cache these bits, they need to be restored once LinkMD finishes. */ 149658389c00SMarek Vasut priv->vct_ctrl1000 = ret & (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 149758389c00SMarek Vasut ret &= ~(CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 149858389c00SMarek Vasut ret |= CTL1000_ENABLE_MASTER; 149958389c00SMarek Vasut 150058389c00SMarek Vasut return phy_write(phydev, MII_CTRL1000, ret); 150158389c00SMarek Vasut } 150258389c00SMarek Vasut 150358389c00SMarek Vasut static int ksz9x31_cable_test_result_trans(u16 status) 150458389c00SMarek Vasut { 150558389c00SMarek Vasut switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) { 150658389c00SMarek Vasut case KSZ9x31_LMD_VCT_ST_NORMAL: 150758389c00SMarek Vasut return ETHTOOL_A_CABLE_RESULT_CODE_OK; 150858389c00SMarek Vasut case KSZ9x31_LMD_VCT_ST_OPEN: 150958389c00SMarek Vasut return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 151058389c00SMarek Vasut case KSZ9x31_LMD_VCT_ST_SHORT: 151158389c00SMarek Vasut return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 151258389c00SMarek Vasut case KSZ9x31_LMD_VCT_ST_FAIL: 151358389c00SMarek Vasut fallthrough; 151458389c00SMarek Vasut default: 151558389c00SMarek Vasut return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 151658389c00SMarek Vasut } 151758389c00SMarek Vasut } 151858389c00SMarek Vasut 151958389c00SMarek Vasut static bool ksz9x31_cable_test_failed(u16 status) 152058389c00SMarek Vasut { 152158389c00SMarek Vasut int stat = FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status); 152258389c00SMarek Vasut 152358389c00SMarek Vasut return stat == KSZ9x31_LMD_VCT_ST_FAIL; 152458389c00SMarek Vasut } 152558389c00SMarek Vasut 152658389c00SMarek Vasut static bool ksz9x31_cable_test_fault_length_valid(u16 status) 152758389c00SMarek Vasut { 152858389c00SMarek Vasut switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) { 152958389c00SMarek Vasut case KSZ9x31_LMD_VCT_ST_OPEN: 153058389c00SMarek Vasut fallthrough; 153158389c00SMarek Vasut case KSZ9x31_LMD_VCT_ST_SHORT: 153258389c00SMarek Vasut return true; 153358389c00SMarek Vasut } 153458389c00SMarek Vasut return false; 153558389c00SMarek Vasut } 153658389c00SMarek Vasut 153758389c00SMarek Vasut static int ksz9x31_cable_test_fault_length(struct phy_device *phydev, u16 stat) 153858389c00SMarek Vasut { 153958389c00SMarek Vasut int dt = FIELD_GET(KSZ9x31_LMD_VCT_DATA_MASK, stat); 154058389c00SMarek Vasut 154158389c00SMarek Vasut /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic 154258389c00SMarek Vasut * 154358389c00SMarek Vasut * distance to fault = (VCT_DATA - 22) * 4 / cable propagation velocity 154458389c00SMarek Vasut */ 154558389c00SMarek Vasut if ((phydev->phy_id & MICREL_PHY_ID_MASK) == PHY_ID_KSZ9131) 154658389c00SMarek Vasut dt = clamp(dt - 22, 0, 255); 154758389c00SMarek Vasut 154858389c00SMarek Vasut return (dt * 400) / 10; 154958389c00SMarek Vasut } 155058389c00SMarek Vasut 155158389c00SMarek Vasut static int ksz9x31_cable_test_wait_for_completion(struct phy_device *phydev) 155258389c00SMarek Vasut { 155358389c00SMarek Vasut int val, ret; 155458389c00SMarek Vasut 155558389c00SMarek Vasut ret = phy_read_poll_timeout(phydev, KSZ9x31_LMD, val, 155658389c00SMarek Vasut !(val & KSZ9x31_LMD_VCT_EN), 155758389c00SMarek Vasut 30000, 100000, true); 155858389c00SMarek Vasut 155958389c00SMarek Vasut return ret < 0 ? ret : 0; 156058389c00SMarek Vasut } 156158389c00SMarek Vasut 156258389c00SMarek Vasut static int ksz9x31_cable_test_get_pair(int pair) 156358389c00SMarek Vasut { 156458389c00SMarek Vasut static const int ethtool_pair[] = { 156558389c00SMarek Vasut ETHTOOL_A_CABLE_PAIR_A, 156658389c00SMarek Vasut ETHTOOL_A_CABLE_PAIR_B, 156758389c00SMarek Vasut ETHTOOL_A_CABLE_PAIR_C, 156858389c00SMarek Vasut ETHTOOL_A_CABLE_PAIR_D, 156958389c00SMarek Vasut }; 157058389c00SMarek Vasut 157158389c00SMarek Vasut return ethtool_pair[pair]; 157258389c00SMarek Vasut } 157358389c00SMarek Vasut 157458389c00SMarek Vasut static int ksz9x31_cable_test_one_pair(struct phy_device *phydev, int pair) 157558389c00SMarek Vasut { 157658389c00SMarek Vasut int ret, val; 157758389c00SMarek Vasut 157858389c00SMarek Vasut /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic 157958389c00SMarek Vasut * To test each individual cable pair, set the cable pair in the Cable 158058389c00SMarek Vasut * Diagnostics Test Pair (VCT_PAIR[1:0]) field of the LinkMD Cable 158158389c00SMarek Vasut * Diagnostic Register, along with setting the Cable Diagnostics Test 158258389c00SMarek Vasut * Enable (VCT_EN) bit. The Cable Diagnostics Test Enable (VCT_EN) bit 158358389c00SMarek Vasut * will self clear when the test is concluded. 158458389c00SMarek Vasut */ 158558389c00SMarek Vasut ret = phy_write(phydev, KSZ9x31_LMD, 158658389c00SMarek Vasut KSZ9x31_LMD_VCT_EN | KSZ9x31_LMD_VCT_PAIR(pair)); 158758389c00SMarek Vasut if (ret) 158858389c00SMarek Vasut return ret; 158958389c00SMarek Vasut 159058389c00SMarek Vasut ret = ksz9x31_cable_test_wait_for_completion(phydev); 159158389c00SMarek Vasut if (ret) 159258389c00SMarek Vasut return ret; 159358389c00SMarek Vasut 159458389c00SMarek Vasut val = phy_read(phydev, KSZ9x31_LMD); 159558389c00SMarek Vasut if (val < 0) 159658389c00SMarek Vasut return val; 159758389c00SMarek Vasut 159858389c00SMarek Vasut if (ksz9x31_cable_test_failed(val)) 159958389c00SMarek Vasut return -EAGAIN; 160058389c00SMarek Vasut 160158389c00SMarek Vasut ret = ethnl_cable_test_result(phydev, 160258389c00SMarek Vasut ksz9x31_cable_test_get_pair(pair), 160358389c00SMarek Vasut ksz9x31_cable_test_result_trans(val)); 160458389c00SMarek Vasut if (ret) 160558389c00SMarek Vasut return ret; 160658389c00SMarek Vasut 160758389c00SMarek Vasut if (!ksz9x31_cable_test_fault_length_valid(val)) 160858389c00SMarek Vasut return 0; 160958389c00SMarek Vasut 161058389c00SMarek Vasut return ethnl_cable_test_fault_length(phydev, 161158389c00SMarek Vasut ksz9x31_cable_test_get_pair(pair), 161258389c00SMarek Vasut ksz9x31_cable_test_fault_length(phydev, val)); 161358389c00SMarek Vasut } 161458389c00SMarek Vasut 161558389c00SMarek Vasut static int ksz9x31_cable_test_get_status(struct phy_device *phydev, 161658389c00SMarek Vasut bool *finished) 161758389c00SMarek Vasut { 161858389c00SMarek Vasut struct kszphy_priv *priv = phydev->priv; 161958389c00SMarek Vasut unsigned long pair_mask = 0xf; 162058389c00SMarek Vasut int retries = 20; 162158389c00SMarek Vasut int pair, ret, rv; 162258389c00SMarek Vasut 162358389c00SMarek Vasut *finished = false; 162458389c00SMarek Vasut 162558389c00SMarek Vasut /* Try harder if link partner is active */ 162658389c00SMarek Vasut while (pair_mask && retries--) { 162758389c00SMarek Vasut for_each_set_bit(pair, &pair_mask, 4) { 162858389c00SMarek Vasut ret = ksz9x31_cable_test_one_pair(phydev, pair); 162958389c00SMarek Vasut if (ret == -EAGAIN) 163058389c00SMarek Vasut continue; 163158389c00SMarek Vasut if (ret < 0) 163258389c00SMarek Vasut return ret; 163358389c00SMarek Vasut clear_bit(pair, &pair_mask); 163458389c00SMarek Vasut } 163558389c00SMarek Vasut /* If link partner is in autonegotiation mode it will send 2ms 163658389c00SMarek Vasut * of FLPs with at least 6ms of silence. 163758389c00SMarek Vasut * Add 2ms sleep to have better chances to hit this silence. 163858389c00SMarek Vasut */ 163958389c00SMarek Vasut if (pair_mask) 164058389c00SMarek Vasut usleep_range(2000, 3000); 164158389c00SMarek Vasut } 164258389c00SMarek Vasut 164358389c00SMarek Vasut /* Report remaining unfinished pair result as unknown. */ 164458389c00SMarek Vasut for_each_set_bit(pair, &pair_mask, 4) { 164558389c00SMarek Vasut ret = ethnl_cable_test_result(phydev, 164658389c00SMarek Vasut ksz9x31_cable_test_get_pair(pair), 164758389c00SMarek Vasut ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC); 164858389c00SMarek Vasut } 164958389c00SMarek Vasut 165058389c00SMarek Vasut *finished = true; 165158389c00SMarek Vasut 165258389c00SMarek Vasut /* Restore cached bits from before LinkMD got started. */ 165358389c00SMarek Vasut rv = phy_modify(phydev, MII_CTRL1000, 165458389c00SMarek Vasut CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER, 165558389c00SMarek Vasut priv->vct_ctrl1000); 165658389c00SMarek Vasut if (rv) 165758389c00SMarek Vasut return rv; 165858389c00SMarek Vasut 165958389c00SMarek Vasut return ret; 166058389c00SMarek Vasut } 166158389c00SMarek Vasut 166293272e07SJean-Christophe PLAGNIOL-VILLARD static int ksz8873mll_config_aneg(struct phy_device *phydev) 166393272e07SJean-Christophe PLAGNIOL-VILLARD { 166493272e07SJean-Christophe PLAGNIOL-VILLARD return 0; 166593272e07SJean-Christophe PLAGNIOL-VILLARD } 166693272e07SJean-Christophe PLAGNIOL-VILLARD 166752939393SOleksij Rempel static int ksz886x_config_mdix(struct phy_device *phydev, u8 ctrl) 166852939393SOleksij Rempel { 166952939393SOleksij Rempel u16 val; 167052939393SOleksij Rempel 167152939393SOleksij Rempel switch (ctrl) { 167252939393SOleksij Rempel case ETH_TP_MDI: 167352939393SOleksij Rempel val = KSZ886X_BMCR_DISABLE_AUTO_MDIX; 167452939393SOleksij Rempel break; 167552939393SOleksij Rempel case ETH_TP_MDI_X: 167652939393SOleksij Rempel /* Note: The naming of the bit KSZ886X_BMCR_FORCE_MDI is bit 167752939393SOleksij Rempel * counter intuitive, the "-X" in "1 = Force MDI" in the data 167852939393SOleksij Rempel * sheet seems to be missing: 167952939393SOleksij Rempel * 1 = Force MDI (sic!) (transmit on RX+/RX- pins) 168052939393SOleksij Rempel * 0 = Normal operation (transmit on TX+/TX- pins) 168152939393SOleksij Rempel */ 168252939393SOleksij Rempel val = KSZ886X_BMCR_DISABLE_AUTO_MDIX | KSZ886X_BMCR_FORCE_MDI; 168352939393SOleksij Rempel break; 168452939393SOleksij Rempel case ETH_TP_MDI_AUTO: 168552939393SOleksij Rempel val = 0; 168652939393SOleksij Rempel break; 168752939393SOleksij Rempel default: 168852939393SOleksij Rempel return 0; 168952939393SOleksij Rempel } 169052939393SOleksij Rempel 169152939393SOleksij Rempel return phy_modify(phydev, MII_BMCR, 169252939393SOleksij Rempel KSZ886X_BMCR_HP_MDIX | KSZ886X_BMCR_FORCE_MDI | 169352939393SOleksij Rempel KSZ886X_BMCR_DISABLE_AUTO_MDIX, 169452939393SOleksij Rempel KSZ886X_BMCR_HP_MDIX | val); 169552939393SOleksij Rempel } 169652939393SOleksij Rempel 169752939393SOleksij Rempel static int ksz886x_config_aneg(struct phy_device *phydev) 169852939393SOleksij Rempel { 169952939393SOleksij Rempel int ret; 170052939393SOleksij Rempel 170152939393SOleksij Rempel ret = genphy_config_aneg(phydev); 170252939393SOleksij Rempel if (ret) 170352939393SOleksij Rempel return ret; 170452939393SOleksij Rempel 170552939393SOleksij Rempel /* The MDI-X configuration is automatically changed by the PHY after 170652939393SOleksij Rempel * switching from autoneg off to on. So, take MDI-X configuration under 170752939393SOleksij Rempel * own control and set it after autoneg configuration was done. 170852939393SOleksij Rempel */ 170952939393SOleksij Rempel return ksz886x_config_mdix(phydev, phydev->mdix_ctrl); 171052939393SOleksij Rempel } 171152939393SOleksij Rempel 171252939393SOleksij Rempel static int ksz886x_mdix_update(struct phy_device *phydev) 171352939393SOleksij Rempel { 171452939393SOleksij Rempel int ret; 171552939393SOleksij Rempel 171652939393SOleksij Rempel ret = phy_read(phydev, MII_BMCR); 171752939393SOleksij Rempel if (ret < 0) 171852939393SOleksij Rempel return ret; 171952939393SOleksij Rempel 172052939393SOleksij Rempel if (ret & KSZ886X_BMCR_DISABLE_AUTO_MDIX) { 172152939393SOleksij Rempel if (ret & KSZ886X_BMCR_FORCE_MDI) 172252939393SOleksij Rempel phydev->mdix_ctrl = ETH_TP_MDI_X; 172352939393SOleksij Rempel else 172452939393SOleksij Rempel phydev->mdix_ctrl = ETH_TP_MDI; 172552939393SOleksij Rempel } else { 172652939393SOleksij Rempel phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 172752939393SOleksij Rempel } 172852939393SOleksij Rempel 172952939393SOleksij Rempel ret = phy_read(phydev, MII_KSZPHY_CTRL); 173052939393SOleksij Rempel if (ret < 0) 173152939393SOleksij Rempel return ret; 173252939393SOleksij Rempel 173352939393SOleksij Rempel /* Same reverse logic as KSZ886X_BMCR_FORCE_MDI */ 173452939393SOleksij Rempel if (ret & KSZ886X_CTRL_MDIX_STAT) 173552939393SOleksij Rempel phydev->mdix = ETH_TP_MDI_X; 173652939393SOleksij Rempel else 173752939393SOleksij Rempel phydev->mdix = ETH_TP_MDI; 173852939393SOleksij Rempel 173952939393SOleksij Rempel return 0; 174052939393SOleksij Rempel } 174152939393SOleksij Rempel 174252939393SOleksij Rempel static int ksz886x_read_status(struct phy_device *phydev) 174352939393SOleksij Rempel { 174452939393SOleksij Rempel int ret; 174552939393SOleksij Rempel 174652939393SOleksij Rempel ret = ksz886x_mdix_update(phydev); 174752939393SOleksij Rempel if (ret < 0) 174852939393SOleksij Rempel return ret; 174952939393SOleksij Rempel 175052939393SOleksij Rempel return genphy_read_status(phydev); 175152939393SOleksij Rempel } 175252939393SOleksij Rempel 17532b2427d0SAndrew Lunn static int kszphy_get_sset_count(struct phy_device *phydev) 17542b2427d0SAndrew Lunn { 17552b2427d0SAndrew Lunn return ARRAY_SIZE(kszphy_hw_stats); 17562b2427d0SAndrew Lunn } 17572b2427d0SAndrew Lunn 17582b2427d0SAndrew Lunn static void kszphy_get_strings(struct phy_device *phydev, u8 *data) 17592b2427d0SAndrew Lunn { 17602b2427d0SAndrew Lunn int i; 17612b2427d0SAndrew Lunn 17622b2427d0SAndrew Lunn for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) { 1763fb3ceec1SWolfram Sang strscpy(data + i * ETH_GSTRING_LEN, 17642b2427d0SAndrew Lunn kszphy_hw_stats[i].string, ETH_GSTRING_LEN); 17652b2427d0SAndrew Lunn } 17662b2427d0SAndrew Lunn } 17672b2427d0SAndrew Lunn 17682b2427d0SAndrew Lunn static u64 kszphy_get_stat(struct phy_device *phydev, int i) 17692b2427d0SAndrew Lunn { 17702b2427d0SAndrew Lunn struct kszphy_hw_stat stat = kszphy_hw_stats[i]; 17712b2427d0SAndrew Lunn struct kszphy_priv *priv = phydev->priv; 1772321b4d4bSAndrew Lunn int val; 1773321b4d4bSAndrew Lunn u64 ret; 17742b2427d0SAndrew Lunn 17752b2427d0SAndrew Lunn val = phy_read(phydev, stat.reg); 17762b2427d0SAndrew Lunn if (val < 0) { 17776c3442f5SJisheng Zhang ret = U64_MAX; 17782b2427d0SAndrew Lunn } else { 17792b2427d0SAndrew Lunn val = val & ((1 << stat.bits) - 1); 17802b2427d0SAndrew Lunn priv->stats[i] += val; 1781321b4d4bSAndrew Lunn ret = priv->stats[i]; 17822b2427d0SAndrew Lunn } 17832b2427d0SAndrew Lunn 1784321b4d4bSAndrew Lunn return ret; 17852b2427d0SAndrew Lunn } 17862b2427d0SAndrew Lunn 17872b2427d0SAndrew Lunn static void kszphy_get_stats(struct phy_device *phydev, 17882b2427d0SAndrew Lunn struct ethtool_stats *stats, u64 *data) 17892b2427d0SAndrew Lunn { 17902b2427d0SAndrew Lunn int i; 17912b2427d0SAndrew Lunn 17922b2427d0SAndrew Lunn for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) 17932b2427d0SAndrew Lunn data[i] = kszphy_get_stat(phydev, i); 17942b2427d0SAndrew Lunn } 17952b2427d0SAndrew Lunn 1796836384d2SWenyou Yang static int kszphy_suspend(struct phy_device *phydev) 1797836384d2SWenyou Yang { 1798836384d2SWenyou Yang /* Disable PHY Interrupts */ 1799836384d2SWenyou Yang if (phy_interrupt_is_valid(phydev)) { 1800836384d2SWenyou Yang phydev->interrupts = PHY_INTERRUPT_DISABLED; 1801836384d2SWenyou Yang if (phydev->drv->config_intr) 1802836384d2SWenyou Yang phydev->drv->config_intr(phydev); 1803836384d2SWenyou Yang } 1804836384d2SWenyou Yang 1805836384d2SWenyou Yang return genphy_suspend(phydev); 1806836384d2SWenyou Yang } 1807836384d2SWenyou Yang 1808a516b7f7SDivya Koppera static void kszphy_parse_led_mode(struct phy_device *phydev) 1809a516b7f7SDivya Koppera { 1810a516b7f7SDivya Koppera const struct kszphy_type *type = phydev->drv->driver_data; 1811a516b7f7SDivya Koppera const struct device_node *np = phydev->mdio.dev.of_node; 1812a516b7f7SDivya Koppera struct kszphy_priv *priv = phydev->priv; 1813a516b7f7SDivya Koppera int ret; 1814a516b7f7SDivya Koppera 1815a516b7f7SDivya Koppera if (type && type->led_mode_reg) { 1816a516b7f7SDivya Koppera ret = of_property_read_u32(np, "micrel,led-mode", 1817a516b7f7SDivya Koppera &priv->led_mode); 1818a516b7f7SDivya Koppera 1819a516b7f7SDivya Koppera if (ret) 1820a516b7f7SDivya Koppera priv->led_mode = -1; 1821a516b7f7SDivya Koppera 1822a516b7f7SDivya Koppera if (priv->led_mode > 3) { 1823a516b7f7SDivya Koppera phydev_err(phydev, "invalid led mode: 0x%02x\n", 1824a516b7f7SDivya Koppera priv->led_mode); 1825a516b7f7SDivya Koppera priv->led_mode = -1; 1826a516b7f7SDivya Koppera } 1827a516b7f7SDivya Koppera } else { 1828a516b7f7SDivya Koppera priv->led_mode = -1; 1829a516b7f7SDivya Koppera } 1830a516b7f7SDivya Koppera } 1831a516b7f7SDivya Koppera 1832f5aba91dSAlexandre Belloni static int kszphy_resume(struct phy_device *phydev) 1833f5aba91dSAlexandre Belloni { 183479e498a9SLeonard Crestez int ret; 183579e498a9SLeonard Crestez 1836836384d2SWenyou Yang genphy_resume(phydev); 1837f5aba91dSAlexandre Belloni 18386110dff7SOleksij Rempel /* After switching from power-down to normal mode, an internal global 18396110dff7SOleksij Rempel * reset is automatically generated. Wait a minimum of 1 ms before 18406110dff7SOleksij Rempel * read/write access to the PHY registers. 18416110dff7SOleksij Rempel */ 18426110dff7SOleksij Rempel usleep_range(1000, 2000); 18436110dff7SOleksij Rempel 184479e498a9SLeonard Crestez ret = kszphy_config_reset(phydev); 184579e498a9SLeonard Crestez if (ret) 184679e498a9SLeonard Crestez return ret; 184779e498a9SLeonard Crestez 1848836384d2SWenyou Yang /* Enable PHY Interrupts */ 1849836384d2SWenyou Yang if (phy_interrupt_is_valid(phydev)) { 1850836384d2SWenyou Yang phydev->interrupts = PHY_INTERRUPT_ENABLED; 1851836384d2SWenyou Yang if (phydev->drv->config_intr) 1852836384d2SWenyou Yang phydev->drv->config_intr(phydev); 1853836384d2SWenyou Yang } 1854f5aba91dSAlexandre Belloni 1855f5aba91dSAlexandre Belloni return 0; 1856f5aba91dSAlexandre Belloni } 1857f5aba91dSAlexandre Belloni 1858e6a423a8SJohan Hovold static int kszphy_probe(struct phy_device *phydev) 1859e6a423a8SJohan Hovold { 1860e6a423a8SJohan Hovold const struct kszphy_type *type = phydev->drv->driver_data; 1861e5a03bfdSAndrew Lunn const struct device_node *np = phydev->mdio.dev.of_node; 1862e6a423a8SJohan Hovold struct kszphy_priv *priv; 186363f44b2bSJohan Hovold struct clk *clk; 1864e6a423a8SJohan Hovold 1865e5a03bfdSAndrew Lunn priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 1866e6a423a8SJohan Hovold if (!priv) 1867e6a423a8SJohan Hovold return -ENOMEM; 1868e6a423a8SJohan Hovold 1869e6a423a8SJohan Hovold phydev->priv = priv; 1870e6a423a8SJohan Hovold 1871e6a423a8SJohan Hovold priv->type = type; 1872e6a423a8SJohan Hovold 1873a516b7f7SDivya Koppera kszphy_parse_led_mode(phydev); 1874e7a792e9SJohan Hovold 1875e5a03bfdSAndrew Lunn clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref"); 1876bced8701SNiklas Cassel /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */ 1877bced8701SNiklas Cassel if (!IS_ERR_OR_NULL(clk)) { 18781fadee0cSSascha Hauer unsigned long rate = clk_get_rate(clk); 187986dc1342SJohan Hovold bool rmii_ref_clk_sel_25_mhz; 18801fadee0cSSascha Hauer 1881f2ef6f75SFabio Estevam if (type) 188263f44b2bSJohan Hovold priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel; 188386dc1342SJohan Hovold rmii_ref_clk_sel_25_mhz = of_property_read_bool(np, 188486dc1342SJohan Hovold "micrel,rmii-reference-clock-select-25-mhz"); 188563f44b2bSJohan Hovold 18861fadee0cSSascha Hauer if (rate > 24500000 && rate < 25500000) { 188786dc1342SJohan Hovold priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz; 18881fadee0cSSascha Hauer } else if (rate > 49500000 && rate < 50500000) { 188986dc1342SJohan Hovold priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz; 18901fadee0cSSascha Hauer } else { 189172ba48beSAndrew Lunn phydev_err(phydev, "Clock rate out of range: %ld\n", 189272ba48beSAndrew Lunn rate); 18931fadee0cSSascha Hauer return -EINVAL; 18941fadee0cSSascha Hauer } 18951fadee0cSSascha Hauer } 18961fadee0cSSascha Hauer 18974217a64eSMichael Walle if (ksz8041_fiber_mode(phydev)) 18984217a64eSMichael Walle phydev->port = PORT_FIBRE; 18994217a64eSMichael Walle 190063f44b2bSJohan Hovold /* Support legacy board-file configuration */ 190163f44b2bSJohan Hovold if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) { 190263f44b2bSJohan Hovold priv->rmii_ref_clk_sel = true; 190363f44b2bSJohan Hovold priv->rmii_ref_clk_sel_val = true; 190463f44b2bSJohan Hovold } 190563f44b2bSJohan Hovold 190663f44b2bSJohan Hovold return 0; 19071fadee0cSSascha Hauer } 19081fadee0cSSascha Hauer 190921b688daSDivya Koppera static int lan8814_cable_test_start(struct phy_device *phydev) 191021b688daSDivya Koppera { 191121b688daSDivya Koppera /* If autoneg is enabled, we won't be able to test cross pair 191221b688daSDivya Koppera * short. In this case, the PHY will "detect" a link and 191321b688daSDivya Koppera * confuse the internal state machine - disable auto neg here. 191421b688daSDivya Koppera * Set the speed to 1000mbit and full duplex. 191521b688daSDivya Koppera */ 191621b688daSDivya Koppera return phy_modify(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100, 191721b688daSDivya Koppera BMCR_SPEED1000 | BMCR_FULLDPLX); 191821b688daSDivya Koppera } 191921b688daSDivya Koppera 192049011e0cSOleksij Rempel static int ksz886x_cable_test_start(struct phy_device *phydev) 192149011e0cSOleksij Rempel { 192249011e0cSOleksij Rempel if (phydev->dev_flags & MICREL_KSZ8_P1_ERRATA) 192349011e0cSOleksij Rempel return -EOPNOTSUPP; 192449011e0cSOleksij Rempel 192549011e0cSOleksij Rempel /* If autoneg is enabled, we won't be able to test cross pair 192649011e0cSOleksij Rempel * short. In this case, the PHY will "detect" a link and 192749011e0cSOleksij Rempel * confuse the internal state machine - disable auto neg here. 192849011e0cSOleksij Rempel * If autoneg is disabled, we should set the speed to 10mbit. 192949011e0cSOleksij Rempel */ 193049011e0cSOleksij Rempel return phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100); 193149011e0cSOleksij Rempel } 193249011e0cSOleksij Rempel 1933fa182ea2SDivya Koppera static __always_inline int ksz886x_cable_test_result_trans(u16 status, u16 mask) 193449011e0cSOleksij Rempel { 193521b688daSDivya Koppera switch (FIELD_GET(mask, status)) { 193649011e0cSOleksij Rempel case KSZ8081_LMD_STAT_NORMAL: 193749011e0cSOleksij Rempel return ETHTOOL_A_CABLE_RESULT_CODE_OK; 193849011e0cSOleksij Rempel case KSZ8081_LMD_STAT_SHORT: 193949011e0cSOleksij Rempel return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 194049011e0cSOleksij Rempel case KSZ8081_LMD_STAT_OPEN: 194149011e0cSOleksij Rempel return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 194249011e0cSOleksij Rempel case KSZ8081_LMD_STAT_FAIL: 194349011e0cSOleksij Rempel fallthrough; 194449011e0cSOleksij Rempel default: 194549011e0cSOleksij Rempel return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 194649011e0cSOleksij Rempel } 194749011e0cSOleksij Rempel } 194849011e0cSOleksij Rempel 1949fa182ea2SDivya Koppera static __always_inline bool ksz886x_cable_test_failed(u16 status, u16 mask) 195049011e0cSOleksij Rempel { 195121b688daSDivya Koppera return FIELD_GET(mask, status) == 195249011e0cSOleksij Rempel KSZ8081_LMD_STAT_FAIL; 195349011e0cSOleksij Rempel } 195449011e0cSOleksij Rempel 1955fa182ea2SDivya Koppera static __always_inline bool ksz886x_cable_test_fault_length_valid(u16 status, u16 mask) 195649011e0cSOleksij Rempel { 195721b688daSDivya Koppera switch (FIELD_GET(mask, status)) { 195849011e0cSOleksij Rempel case KSZ8081_LMD_STAT_OPEN: 195949011e0cSOleksij Rempel fallthrough; 196049011e0cSOleksij Rempel case KSZ8081_LMD_STAT_SHORT: 196149011e0cSOleksij Rempel return true; 196249011e0cSOleksij Rempel } 196349011e0cSOleksij Rempel return false; 196449011e0cSOleksij Rempel } 196549011e0cSOleksij Rempel 1966fa182ea2SDivya Koppera static __always_inline int ksz886x_cable_test_fault_length(struct phy_device *phydev, 1967fa182ea2SDivya Koppera u16 status, u16 data_mask) 196849011e0cSOleksij Rempel { 196949011e0cSOleksij Rempel int dt; 197049011e0cSOleksij Rempel 197149011e0cSOleksij Rempel /* According to the data sheet the distance to the fault is 197221b688daSDivya Koppera * DELTA_TIME * 0.4 meters for ksz phys. 197321b688daSDivya Koppera * (DELTA_TIME - 22) * 0.8 for lan8814 phy. 197449011e0cSOleksij Rempel */ 197521b688daSDivya Koppera dt = FIELD_GET(data_mask, status); 197649011e0cSOleksij Rempel 197721b688daSDivya Koppera if ((phydev->phy_id & MICREL_PHY_ID_MASK) == PHY_ID_LAN8814) 197821b688daSDivya Koppera return ((dt - 22) * 800) / 10; 197921b688daSDivya Koppera else 198049011e0cSOleksij Rempel return (dt * 400) / 10; 198149011e0cSOleksij Rempel } 198249011e0cSOleksij Rempel 198349011e0cSOleksij Rempel static int ksz886x_cable_test_wait_for_completion(struct phy_device *phydev) 198449011e0cSOleksij Rempel { 198521b688daSDivya Koppera const struct kszphy_type *type = phydev->drv->driver_data; 198649011e0cSOleksij Rempel int val, ret; 198749011e0cSOleksij Rempel 198821b688daSDivya Koppera ret = phy_read_poll_timeout(phydev, type->cable_diag_reg, val, 198949011e0cSOleksij Rempel !(val & KSZ8081_LMD_ENABLE_TEST), 199049011e0cSOleksij Rempel 30000, 100000, true); 199149011e0cSOleksij Rempel 199249011e0cSOleksij Rempel return ret < 0 ? ret : 0; 199349011e0cSOleksij Rempel } 199449011e0cSOleksij Rempel 199521b688daSDivya Koppera static int lan8814_cable_test_one_pair(struct phy_device *phydev, int pair) 199621b688daSDivya Koppera { 199721b688daSDivya Koppera static const int ethtool_pair[] = { ETHTOOL_A_CABLE_PAIR_A, 199821b688daSDivya Koppera ETHTOOL_A_CABLE_PAIR_B, 199921b688daSDivya Koppera ETHTOOL_A_CABLE_PAIR_C, 200021b688daSDivya Koppera ETHTOOL_A_CABLE_PAIR_D, 200121b688daSDivya Koppera }; 200221b688daSDivya Koppera u32 fault_length; 200321b688daSDivya Koppera int ret; 200421b688daSDivya Koppera int val; 200521b688daSDivya Koppera 200621b688daSDivya Koppera val = KSZ8081_LMD_ENABLE_TEST; 200721b688daSDivya Koppera val = val | (pair << LAN8814_PAIR_BIT_SHIFT); 200821b688daSDivya Koppera 200921b688daSDivya Koppera ret = phy_write(phydev, LAN8814_CABLE_DIAG, val); 201021b688daSDivya Koppera if (ret < 0) 201121b688daSDivya Koppera return ret; 201221b688daSDivya Koppera 201321b688daSDivya Koppera ret = ksz886x_cable_test_wait_for_completion(phydev); 201421b688daSDivya Koppera if (ret) 201521b688daSDivya Koppera return ret; 201621b688daSDivya Koppera 201721b688daSDivya Koppera val = phy_read(phydev, LAN8814_CABLE_DIAG); 201821b688daSDivya Koppera if (val < 0) 201921b688daSDivya Koppera return val; 202021b688daSDivya Koppera 202121b688daSDivya Koppera if (ksz886x_cable_test_failed(val, LAN8814_CABLE_DIAG_STAT_MASK)) 202221b688daSDivya Koppera return -EAGAIN; 202321b688daSDivya Koppera 202421b688daSDivya Koppera ret = ethnl_cable_test_result(phydev, ethtool_pair[pair], 202521b688daSDivya Koppera ksz886x_cable_test_result_trans(val, 202621b688daSDivya Koppera LAN8814_CABLE_DIAG_STAT_MASK 202721b688daSDivya Koppera )); 202821b688daSDivya Koppera if (ret) 202921b688daSDivya Koppera return ret; 203021b688daSDivya Koppera 203121b688daSDivya Koppera if (!ksz886x_cable_test_fault_length_valid(val, LAN8814_CABLE_DIAG_STAT_MASK)) 203221b688daSDivya Koppera return 0; 203321b688daSDivya Koppera 203421b688daSDivya Koppera fault_length = ksz886x_cable_test_fault_length(phydev, val, 203521b688daSDivya Koppera LAN8814_CABLE_DIAG_VCT_DATA_MASK); 203621b688daSDivya Koppera 203721b688daSDivya Koppera return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], fault_length); 203821b688daSDivya Koppera } 203921b688daSDivya Koppera 204049011e0cSOleksij Rempel static int ksz886x_cable_test_one_pair(struct phy_device *phydev, int pair) 204149011e0cSOleksij Rempel { 204249011e0cSOleksij Rempel static const int ethtool_pair[] = { 204349011e0cSOleksij Rempel ETHTOOL_A_CABLE_PAIR_A, 204449011e0cSOleksij Rempel ETHTOOL_A_CABLE_PAIR_B, 204549011e0cSOleksij Rempel }; 204649011e0cSOleksij Rempel int ret, val, mdix; 204721b688daSDivya Koppera u32 fault_length; 204849011e0cSOleksij Rempel 204949011e0cSOleksij Rempel /* There is no way to choice the pair, like we do one ksz9031. 205049011e0cSOleksij Rempel * We can workaround this limitation by using the MDI-X functionality. 205149011e0cSOleksij Rempel */ 205249011e0cSOleksij Rempel if (pair == 0) 205349011e0cSOleksij Rempel mdix = ETH_TP_MDI; 205449011e0cSOleksij Rempel else 205549011e0cSOleksij Rempel mdix = ETH_TP_MDI_X; 205649011e0cSOleksij Rempel 205749011e0cSOleksij Rempel switch (phydev->phy_id & MICREL_PHY_ID_MASK) { 205849011e0cSOleksij Rempel case PHY_ID_KSZ8081: 205949011e0cSOleksij Rempel ret = ksz8081_config_mdix(phydev, mdix); 206049011e0cSOleksij Rempel break; 206149011e0cSOleksij Rempel case PHY_ID_KSZ886X: 206249011e0cSOleksij Rempel ret = ksz886x_config_mdix(phydev, mdix); 206349011e0cSOleksij Rempel break; 206449011e0cSOleksij Rempel default: 206549011e0cSOleksij Rempel ret = -ENODEV; 206649011e0cSOleksij Rempel } 206749011e0cSOleksij Rempel 206849011e0cSOleksij Rempel if (ret) 206949011e0cSOleksij Rempel return ret; 207049011e0cSOleksij Rempel 207149011e0cSOleksij Rempel /* Now we are ready to fire. This command will send a 100ns pulse 207249011e0cSOleksij Rempel * to the pair. 207349011e0cSOleksij Rempel */ 207449011e0cSOleksij Rempel ret = phy_write(phydev, KSZ8081_LMD, KSZ8081_LMD_ENABLE_TEST); 207549011e0cSOleksij Rempel if (ret) 207649011e0cSOleksij Rempel return ret; 207749011e0cSOleksij Rempel 207849011e0cSOleksij Rempel ret = ksz886x_cable_test_wait_for_completion(phydev); 207949011e0cSOleksij Rempel if (ret) 208049011e0cSOleksij Rempel return ret; 208149011e0cSOleksij Rempel 208249011e0cSOleksij Rempel val = phy_read(phydev, KSZ8081_LMD); 208349011e0cSOleksij Rempel if (val < 0) 208449011e0cSOleksij Rempel return val; 208549011e0cSOleksij Rempel 208621b688daSDivya Koppera if (ksz886x_cable_test_failed(val, KSZ8081_LMD_STAT_MASK)) 208749011e0cSOleksij Rempel return -EAGAIN; 208849011e0cSOleksij Rempel 208949011e0cSOleksij Rempel ret = ethnl_cable_test_result(phydev, ethtool_pair[pair], 209021b688daSDivya Koppera ksz886x_cable_test_result_trans(val, KSZ8081_LMD_STAT_MASK)); 209149011e0cSOleksij Rempel if (ret) 209249011e0cSOleksij Rempel return ret; 209349011e0cSOleksij Rempel 209421b688daSDivya Koppera if (!ksz886x_cable_test_fault_length_valid(val, KSZ8081_LMD_STAT_MASK)) 209549011e0cSOleksij Rempel return 0; 209649011e0cSOleksij Rempel 209721b688daSDivya Koppera fault_length = ksz886x_cable_test_fault_length(phydev, val, KSZ8081_LMD_DELTA_TIME_MASK); 209821b688daSDivya Koppera 209921b688daSDivya Koppera return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], fault_length); 210049011e0cSOleksij Rempel } 210149011e0cSOleksij Rempel 210249011e0cSOleksij Rempel static int ksz886x_cable_test_get_status(struct phy_device *phydev, 210349011e0cSOleksij Rempel bool *finished) 210449011e0cSOleksij Rempel { 210521b688daSDivya Koppera const struct kszphy_type *type = phydev->drv->driver_data; 210621b688daSDivya Koppera unsigned long pair_mask = type->pair_mask; 210749011e0cSOleksij Rempel int retries = 20; 2108d50ede4fSDivya Koppera int ret = 0; 2109d50ede4fSDivya Koppera int pair; 211049011e0cSOleksij Rempel 211149011e0cSOleksij Rempel *finished = false; 211249011e0cSOleksij Rempel 211349011e0cSOleksij Rempel /* Try harder if link partner is active */ 211449011e0cSOleksij Rempel while (pair_mask && retries--) { 211549011e0cSOleksij Rempel for_each_set_bit(pair, &pair_mask, 4) { 211621b688daSDivya Koppera if (type->cable_diag_reg == LAN8814_CABLE_DIAG) 211721b688daSDivya Koppera ret = lan8814_cable_test_one_pair(phydev, pair); 211821b688daSDivya Koppera else 211949011e0cSOleksij Rempel ret = ksz886x_cable_test_one_pair(phydev, pair); 212049011e0cSOleksij Rempel if (ret == -EAGAIN) 212149011e0cSOleksij Rempel continue; 212249011e0cSOleksij Rempel if (ret < 0) 212349011e0cSOleksij Rempel return ret; 212449011e0cSOleksij Rempel clear_bit(pair, &pair_mask); 212549011e0cSOleksij Rempel } 212649011e0cSOleksij Rempel /* If link partner is in autonegotiation mode it will send 2ms 212749011e0cSOleksij Rempel * of FLPs with at least 6ms of silence. 212849011e0cSOleksij Rempel * Add 2ms sleep to have better chances to hit this silence. 212949011e0cSOleksij Rempel */ 213049011e0cSOleksij Rempel if (pair_mask) 213149011e0cSOleksij Rempel msleep(2); 213249011e0cSOleksij Rempel } 213349011e0cSOleksij Rempel 213449011e0cSOleksij Rempel *finished = true; 213549011e0cSOleksij Rempel 213649011e0cSOleksij Rempel return ret; 213749011e0cSOleksij Rempel } 213849011e0cSOleksij Rempel 21397c2dcfa2SHoratiu Vultur #define LAN_EXT_PAGE_ACCESS_CONTROL 0x16 21407c2dcfa2SHoratiu Vultur #define LAN_EXT_PAGE_ACCESS_ADDRESS_DATA 0x17 21417c2dcfa2SHoratiu Vultur #define LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC 0x4000 21427c2dcfa2SHoratiu Vultur 21437467d716SHoratiu Vultur #define LAN8814_QSGMII_SOFT_RESET 0x43 21447467d716SHoratiu Vultur #define LAN8814_QSGMII_SOFT_RESET_BIT BIT(0) 21457467d716SHoratiu Vultur #define LAN8814_QSGMII_PCS1G_ANEG_CONFIG 0x13 21467467d716SHoratiu Vultur #define LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA BIT(3) 21477467d716SHoratiu Vultur #define LAN8814_ALIGN_SWAP 0x4a 21487467d716SHoratiu Vultur #define LAN8814_ALIGN_TX_A_B_SWAP 0x1 21497467d716SHoratiu Vultur #define LAN8814_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0) 21507467d716SHoratiu Vultur 21517c2dcfa2SHoratiu Vultur #define LAN8804_ALIGN_SWAP 0x4a 21527c2dcfa2SHoratiu Vultur #define LAN8804_ALIGN_TX_A_B_SWAP 0x1 21537c2dcfa2SHoratiu Vultur #define LAN8804_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0) 21547c2dcfa2SHoratiu Vultur #define LAN8814_CLOCK_MANAGEMENT 0xd 21557c2dcfa2SHoratiu Vultur #define LAN8814_LINK_QUALITY 0x8e 21567c2dcfa2SHoratiu Vultur 21577c2dcfa2SHoratiu Vultur static int lanphy_read_page_reg(struct phy_device *phydev, int page, u32 addr) 21587c2dcfa2SHoratiu Vultur { 215912a4d677SWan Jiabing int data; 21607c2dcfa2SHoratiu Vultur 21614488f6b6SDivya Koppera phy_lock_mdio_bus(phydev); 21624488f6b6SDivya Koppera __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page); 21634488f6b6SDivya Koppera __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr); 21644488f6b6SDivya Koppera __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, 21657c2dcfa2SHoratiu Vultur (page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC)); 21664488f6b6SDivya Koppera data = __phy_read(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA); 21674488f6b6SDivya Koppera phy_unlock_mdio_bus(phydev); 21687c2dcfa2SHoratiu Vultur 21697c2dcfa2SHoratiu Vultur return data; 21707c2dcfa2SHoratiu Vultur } 21717c2dcfa2SHoratiu Vultur 21727c2dcfa2SHoratiu Vultur static int lanphy_write_page_reg(struct phy_device *phydev, int page, u16 addr, 21737c2dcfa2SHoratiu Vultur u16 val) 21747c2dcfa2SHoratiu Vultur { 21754488f6b6SDivya Koppera phy_lock_mdio_bus(phydev); 21764488f6b6SDivya Koppera __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page); 21774488f6b6SDivya Koppera __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr); 21784488f6b6SDivya Koppera __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, 21794488f6b6SDivya Koppera page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC); 21807c2dcfa2SHoratiu Vultur 21814488f6b6SDivya Koppera val = __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val); 21824488f6b6SDivya Koppera if (val != 0) 21837c2dcfa2SHoratiu Vultur phydev_err(phydev, "Error: phy_write has returned error %d\n", 21847c2dcfa2SHoratiu Vultur val); 21854488f6b6SDivya Koppera phy_unlock_mdio_bus(phydev); 21867c2dcfa2SHoratiu Vultur return val; 21877c2dcfa2SHoratiu Vultur } 21887c2dcfa2SHoratiu Vultur 2189ece19502SDivya Koppera static int lan8814_config_ts_intr(struct phy_device *phydev, bool enable) 21907467d716SHoratiu Vultur { 2191ece19502SDivya Koppera u16 val = 0; 21927467d716SHoratiu Vultur 2193ece19502SDivya Koppera if (enable) 2194ece19502SDivya Koppera val = PTP_TSU_INT_EN_PTP_TX_TS_EN_ | 2195ece19502SDivya Koppera PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ | 2196ece19502SDivya Koppera PTP_TSU_INT_EN_PTP_RX_TS_EN_ | 2197ece19502SDivya Koppera PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_; 21987467d716SHoratiu Vultur 2199ece19502SDivya Koppera return lanphy_write_page_reg(phydev, 5, PTP_TSU_INT_EN, val); 2200ece19502SDivya Koppera } 22017467d716SHoratiu Vultur 2202ece19502SDivya Koppera static void lan8814_ptp_rx_ts_get(struct phy_device *phydev, 2203ece19502SDivya Koppera u32 *seconds, u32 *nano_seconds, u16 *seq_id) 2204ece19502SDivya Koppera { 2205ece19502SDivya Koppera *seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_HI); 2206ece19502SDivya Koppera *seconds = (*seconds << 16) | 2207ece19502SDivya Koppera lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_LO); 2208ece19502SDivya Koppera 2209ece19502SDivya Koppera *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_HI); 2210ece19502SDivya Koppera *nano_seconds = ((*nano_seconds & 0x3fff) << 16) | 2211ece19502SDivya Koppera lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_LO); 2212ece19502SDivya Koppera 2213ece19502SDivya Koppera *seq_id = lanphy_read_page_reg(phydev, 5, PTP_RX_MSG_HEADER2); 2214ece19502SDivya Koppera } 2215ece19502SDivya Koppera 2216ece19502SDivya Koppera static void lan8814_ptp_tx_ts_get(struct phy_device *phydev, 2217ece19502SDivya Koppera u32 *seconds, u32 *nano_seconds, u16 *seq_id) 2218ece19502SDivya Koppera { 2219ece19502SDivya Koppera *seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_HI); 2220ece19502SDivya Koppera *seconds = *seconds << 16 | 2221ece19502SDivya Koppera lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_LO); 2222ece19502SDivya Koppera 2223ece19502SDivya Koppera *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_HI); 2224ece19502SDivya Koppera *nano_seconds = ((*nano_seconds & 0x3fff) << 16) | 2225ece19502SDivya Koppera lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_LO); 2226ece19502SDivya Koppera 2227ece19502SDivya Koppera *seq_id = lanphy_read_page_reg(phydev, 5, PTP_TX_MSG_HEADER2); 2228ece19502SDivya Koppera } 2229ece19502SDivya Koppera 2230ece19502SDivya Koppera static int lan8814_ts_info(struct mii_timestamper *mii_ts, struct ethtool_ts_info *info) 2231ece19502SDivya Koppera { 2232ece19502SDivya Koppera struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts); 2233ece19502SDivya Koppera struct phy_device *phydev = ptp_priv->phydev; 2234ece19502SDivya Koppera struct lan8814_shared_priv *shared = phydev->shared->priv; 2235ece19502SDivya Koppera 2236ece19502SDivya Koppera info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE | 2237ece19502SDivya Koppera SOF_TIMESTAMPING_RX_HARDWARE | 2238ece19502SDivya Koppera SOF_TIMESTAMPING_RAW_HARDWARE; 2239ece19502SDivya Koppera 2240ece19502SDivya Koppera info->phc_index = ptp_clock_index(shared->ptp_clock); 2241ece19502SDivya Koppera 2242ece19502SDivya Koppera info->tx_types = 2243ece19502SDivya Koppera (1 << HWTSTAMP_TX_OFF) | 2244ece19502SDivya Koppera (1 << HWTSTAMP_TX_ON) | 2245ece19502SDivya Koppera (1 << HWTSTAMP_TX_ONESTEP_SYNC); 2246ece19502SDivya Koppera 2247ece19502SDivya Koppera info->rx_filters = 2248ece19502SDivya Koppera (1 << HWTSTAMP_FILTER_NONE) | 2249ece19502SDivya Koppera (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 2250ece19502SDivya Koppera (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 2251ece19502SDivya Koppera (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 2252ece19502SDivya Koppera (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 22537467d716SHoratiu Vultur 22547467d716SHoratiu Vultur return 0; 22557467d716SHoratiu Vultur } 22567467d716SHoratiu Vultur 2257ece19502SDivya Koppera static void lan8814_flush_fifo(struct phy_device *phydev, bool egress) 2258ece19502SDivya Koppera { 2259ece19502SDivya Koppera int i; 2260ece19502SDivya Koppera 2261ece19502SDivya Koppera for (i = 0; i < FIFO_SIZE; ++i) 2262ece19502SDivya Koppera lanphy_read_page_reg(phydev, 5, 2263ece19502SDivya Koppera egress ? PTP_TX_MSG_HEADER2 : PTP_RX_MSG_HEADER2); 2264ece19502SDivya Koppera 2265ece19502SDivya Koppera /* Read to clear overflow status bit */ 2266ece19502SDivya Koppera lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS); 2267ece19502SDivya Koppera } 2268ece19502SDivya Koppera 2269ece19502SDivya Koppera static int lan8814_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr) 2270ece19502SDivya Koppera { 2271ece19502SDivya Koppera struct kszphy_ptp_priv *ptp_priv = 2272ece19502SDivya Koppera container_of(mii_ts, struct kszphy_ptp_priv, mii_ts); 2273ece19502SDivya Koppera struct phy_device *phydev = ptp_priv->phydev; 2274ece19502SDivya Koppera struct lan8814_shared_priv *shared = phydev->shared->priv; 2275ece19502SDivya Koppera struct lan8814_ptp_rx_ts *rx_ts, *tmp; 2276ece19502SDivya Koppera struct hwtstamp_config config; 2277ece19502SDivya Koppera int txcfg = 0, rxcfg = 0; 2278ece19502SDivya Koppera int pkt_ts_enable; 2279ece19502SDivya Koppera 2280ece19502SDivya Koppera if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 2281ece19502SDivya Koppera return -EFAULT; 2282ece19502SDivya Koppera 2283ece19502SDivya Koppera ptp_priv->hwts_tx_type = config.tx_type; 2284ece19502SDivya Koppera ptp_priv->rx_filter = config.rx_filter; 2285ece19502SDivya Koppera 2286ece19502SDivya Koppera switch (config.rx_filter) { 2287ece19502SDivya Koppera case HWTSTAMP_FILTER_NONE: 2288ece19502SDivya Koppera ptp_priv->layer = 0; 2289ece19502SDivya Koppera ptp_priv->version = 0; 2290ece19502SDivya Koppera break; 2291ece19502SDivya Koppera case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 2292ece19502SDivya Koppera case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 2293ece19502SDivya Koppera case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 2294ece19502SDivya Koppera ptp_priv->layer = PTP_CLASS_L4; 2295ece19502SDivya Koppera ptp_priv->version = PTP_CLASS_V2; 2296ece19502SDivya Koppera break; 2297ece19502SDivya Koppera case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2298ece19502SDivya Koppera case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 2299ece19502SDivya Koppera case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 2300ece19502SDivya Koppera ptp_priv->layer = PTP_CLASS_L2; 2301ece19502SDivya Koppera ptp_priv->version = PTP_CLASS_V2; 2302ece19502SDivya Koppera break; 2303ece19502SDivya Koppera case HWTSTAMP_FILTER_PTP_V2_EVENT: 2304ece19502SDivya Koppera case HWTSTAMP_FILTER_PTP_V2_SYNC: 2305ece19502SDivya Koppera case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 2306ece19502SDivya Koppera ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2; 2307ece19502SDivya Koppera ptp_priv->version = PTP_CLASS_V2; 2308ece19502SDivya Koppera break; 2309ece19502SDivya Koppera default: 2310ece19502SDivya Koppera return -ERANGE; 2311ece19502SDivya Koppera } 2312ece19502SDivya Koppera 2313ece19502SDivya Koppera if (ptp_priv->layer & PTP_CLASS_L2) { 2314ece19502SDivya Koppera rxcfg = PTP_RX_PARSE_CONFIG_LAYER2_EN_; 2315ece19502SDivya Koppera txcfg = PTP_TX_PARSE_CONFIG_LAYER2_EN_; 2316ece19502SDivya Koppera } else if (ptp_priv->layer & PTP_CLASS_L4) { 2317ece19502SDivya Koppera rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_; 2318ece19502SDivya Koppera txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_; 2319ece19502SDivya Koppera } 2320ece19502SDivya Koppera lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_PARSE_CONFIG, rxcfg); 2321ece19502SDivya Koppera lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_PARSE_CONFIG, txcfg); 2322ece19502SDivya Koppera 2323ece19502SDivya Koppera pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ | 2324ece19502SDivya Koppera PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_; 2325ece19502SDivya Koppera lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_TIMESTAMP_EN, pkt_ts_enable); 2326ece19502SDivya Koppera lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_TIMESTAMP_EN, pkt_ts_enable); 2327ece19502SDivya Koppera 2328ece19502SDivya Koppera if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC) 2329ece19502SDivya Koppera lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD, 2330ece19502SDivya Koppera PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_); 2331ece19502SDivya Koppera 2332ece19502SDivya Koppera if (config.rx_filter != HWTSTAMP_FILTER_NONE) 2333ece19502SDivya Koppera lan8814_config_ts_intr(ptp_priv->phydev, true); 2334ece19502SDivya Koppera else 2335ece19502SDivya Koppera lan8814_config_ts_intr(ptp_priv->phydev, false); 2336ece19502SDivya Koppera 2337ece19502SDivya Koppera mutex_lock(&shared->shared_lock); 2338ece19502SDivya Koppera if (config.rx_filter != HWTSTAMP_FILTER_NONE) 2339ece19502SDivya Koppera shared->ref++; 2340ece19502SDivya Koppera else 2341ece19502SDivya Koppera shared->ref--; 2342ece19502SDivya Koppera 2343ece19502SDivya Koppera if (shared->ref) 2344ece19502SDivya Koppera lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL, 2345ece19502SDivya Koppera PTP_CMD_CTL_PTP_ENABLE_); 2346ece19502SDivya Koppera else 2347ece19502SDivya Koppera lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL, 2348ece19502SDivya Koppera PTP_CMD_CTL_PTP_DISABLE_); 2349ece19502SDivya Koppera mutex_unlock(&shared->shared_lock); 2350ece19502SDivya Koppera 2351ece19502SDivya Koppera /* In case of multiple starts and stops, these needs to be cleared */ 2352ece19502SDivya Koppera list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) { 2353ece19502SDivya Koppera list_del(&rx_ts->list); 2354ece19502SDivya Koppera kfree(rx_ts); 2355ece19502SDivya Koppera } 2356ece19502SDivya Koppera skb_queue_purge(&ptp_priv->rx_queue); 2357ece19502SDivya Koppera skb_queue_purge(&ptp_priv->tx_queue); 2358ece19502SDivya Koppera 2359ece19502SDivya Koppera lan8814_flush_fifo(ptp_priv->phydev, false); 2360ece19502SDivya Koppera lan8814_flush_fifo(ptp_priv->phydev, true); 2361ece19502SDivya Koppera 2362ece19502SDivya Koppera return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? -EFAULT : 0; 2363ece19502SDivya Koppera } 2364ece19502SDivya Koppera 2365ece19502SDivya Koppera static void lan8814_txtstamp(struct mii_timestamper *mii_ts, 2366ece19502SDivya Koppera struct sk_buff *skb, int type) 2367ece19502SDivya Koppera { 2368ece19502SDivya Koppera struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts); 2369ece19502SDivya Koppera 2370ece19502SDivya Koppera switch (ptp_priv->hwts_tx_type) { 2371ece19502SDivya Koppera case HWTSTAMP_TX_ONESTEP_SYNC: 23723914a9c0SKurt Kanzenbach if (ptp_msg_is_sync(skb, type)) { 2373ece19502SDivya Koppera kfree_skb(skb); 2374ece19502SDivya Koppera return; 2375ece19502SDivya Koppera } 2376ece19502SDivya Koppera fallthrough; 2377ece19502SDivya Koppera case HWTSTAMP_TX_ON: 2378ece19502SDivya Koppera skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2379ece19502SDivya Koppera skb_queue_tail(&ptp_priv->tx_queue, skb); 2380ece19502SDivya Koppera break; 2381ece19502SDivya Koppera case HWTSTAMP_TX_OFF: 2382ece19502SDivya Koppera default: 2383ece19502SDivya Koppera kfree_skb(skb); 2384ece19502SDivya Koppera break; 2385ece19502SDivya Koppera } 2386ece19502SDivya Koppera } 2387ece19502SDivya Koppera 2388ece19502SDivya Koppera static void lan8814_get_sig_rx(struct sk_buff *skb, u16 *sig) 2389ece19502SDivya Koppera { 2390ece19502SDivya Koppera struct ptp_header *ptp_header; 2391ece19502SDivya Koppera u32 type; 2392ece19502SDivya Koppera 2393ece19502SDivya Koppera skb_push(skb, ETH_HLEN); 2394ece19502SDivya Koppera type = ptp_classify_raw(skb); 2395ece19502SDivya Koppera ptp_header = ptp_parse_header(skb, type); 2396ece19502SDivya Koppera skb_pull_inline(skb, ETH_HLEN); 2397ece19502SDivya Koppera 2398ece19502SDivya Koppera *sig = (__force u16)(ntohs(ptp_header->sequence_id)); 2399ece19502SDivya Koppera } 2400ece19502SDivya Koppera 2401ece19502SDivya Koppera static bool lan8814_match_rx_ts(struct kszphy_ptp_priv *ptp_priv, 2402ece19502SDivya Koppera struct sk_buff *skb) 2403ece19502SDivya Koppera { 2404ece19502SDivya Koppera struct skb_shared_hwtstamps *shhwtstamps; 2405ece19502SDivya Koppera struct lan8814_ptp_rx_ts *rx_ts, *tmp; 2406ece19502SDivya Koppera unsigned long flags; 2407ece19502SDivya Koppera bool ret = false; 2408ece19502SDivya Koppera u16 skb_sig; 2409ece19502SDivya Koppera 2410ece19502SDivya Koppera lan8814_get_sig_rx(skb, &skb_sig); 2411ece19502SDivya Koppera 2412ece19502SDivya Koppera /* Iterate over all RX timestamps and match it with the received skbs */ 2413ece19502SDivya Koppera spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags); 2414ece19502SDivya Koppera list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) { 2415ece19502SDivya Koppera /* Check if we found the signature we were looking for. */ 2416ece19502SDivya Koppera if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id))) 2417ece19502SDivya Koppera continue; 2418ece19502SDivya Koppera 2419ece19502SDivya Koppera shhwtstamps = skb_hwtstamps(skb); 2420ece19502SDivya Koppera memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 2421ece19502SDivya Koppera shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds, 2422ece19502SDivya Koppera rx_ts->nsec); 2423ece19502SDivya Koppera list_del(&rx_ts->list); 2424ece19502SDivya Koppera kfree(rx_ts); 2425ece19502SDivya Koppera 2426ece19502SDivya Koppera ret = true; 2427ece19502SDivya Koppera break; 2428ece19502SDivya Koppera } 2429ece19502SDivya Koppera spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags); 2430ece19502SDivya Koppera 243167dbd6c0SSebastian Andrzej Siewior if (ret) 243267dbd6c0SSebastian Andrzej Siewior netif_rx(skb); 2433ece19502SDivya Koppera return ret; 2434ece19502SDivya Koppera } 2435ece19502SDivya Koppera 2436ece19502SDivya Koppera static bool lan8814_rxtstamp(struct mii_timestamper *mii_ts, struct sk_buff *skb, int type) 2437ece19502SDivya Koppera { 2438ece19502SDivya Koppera struct kszphy_ptp_priv *ptp_priv = 2439ece19502SDivya Koppera container_of(mii_ts, struct kszphy_ptp_priv, mii_ts); 2440ece19502SDivya Koppera 2441ece19502SDivya Koppera if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE || 2442ece19502SDivya Koppera type == PTP_CLASS_NONE) 2443ece19502SDivya Koppera return false; 2444ece19502SDivya Koppera 2445ece19502SDivya Koppera if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0) 2446ece19502SDivya Koppera return false; 2447ece19502SDivya Koppera 2448ece19502SDivya Koppera /* If we failed to match then add it to the queue for when the timestamp 2449ece19502SDivya Koppera * will come 2450ece19502SDivya Koppera */ 2451ece19502SDivya Koppera if (!lan8814_match_rx_ts(ptp_priv, skb)) 2452ece19502SDivya Koppera skb_queue_tail(&ptp_priv->rx_queue, skb); 2453ece19502SDivya Koppera 2454ece19502SDivya Koppera return true; 2455ece19502SDivya Koppera } 2456ece19502SDivya Koppera 2457ece19502SDivya Koppera static void lan8814_ptp_clock_set(struct phy_device *phydev, 2458ece19502SDivya Koppera u32 seconds, u32 nano_seconds) 2459ece19502SDivya Koppera { 2460ece19502SDivya Koppera u32 sec_low, sec_high, nsec_low, nsec_high; 2461ece19502SDivya Koppera 2462ece19502SDivya Koppera sec_low = seconds & 0xffff; 2463ece19502SDivya Koppera sec_high = (seconds >> 16) & 0xffff; 2464ece19502SDivya Koppera nsec_low = nano_seconds & 0xffff; 2465ece19502SDivya Koppera nsec_high = (nano_seconds >> 16) & 0x3fff; 2466ece19502SDivya Koppera 2467ece19502SDivya Koppera lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_LO, sec_low); 2468ece19502SDivya Koppera lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_MID, sec_high); 2469ece19502SDivya Koppera lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_LO, nsec_low); 2470ece19502SDivya Koppera lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_HI, nsec_high); 2471ece19502SDivya Koppera 2472ece19502SDivya Koppera lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_LOAD_); 2473ece19502SDivya Koppera } 2474ece19502SDivya Koppera 2475ece19502SDivya Koppera static void lan8814_ptp_clock_get(struct phy_device *phydev, 2476ece19502SDivya Koppera u32 *seconds, u32 *nano_seconds) 2477ece19502SDivya Koppera { 2478ece19502SDivya Koppera lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_READ_); 2479ece19502SDivya Koppera 2480ece19502SDivya Koppera *seconds = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_MID); 2481ece19502SDivya Koppera *seconds = (*seconds << 16) | 2482ece19502SDivya Koppera lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_LO); 2483ece19502SDivya Koppera 2484ece19502SDivya Koppera *nano_seconds = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_HI); 2485ece19502SDivya Koppera *nano_seconds = ((*nano_seconds & 0x3fff) << 16) | 2486ece19502SDivya Koppera lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_LO); 2487ece19502SDivya Koppera } 2488ece19502SDivya Koppera 2489ece19502SDivya Koppera static int lan8814_ptpci_gettime64(struct ptp_clock_info *ptpci, 2490ece19502SDivya Koppera struct timespec64 *ts) 2491ece19502SDivya Koppera { 2492ece19502SDivya Koppera struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv, 2493ece19502SDivya Koppera ptp_clock_info); 2494ece19502SDivya Koppera struct phy_device *phydev = shared->phydev; 2495ece19502SDivya Koppera u32 nano_seconds; 2496ece19502SDivya Koppera u32 seconds; 2497ece19502SDivya Koppera 2498ece19502SDivya Koppera mutex_lock(&shared->shared_lock); 2499ece19502SDivya Koppera lan8814_ptp_clock_get(phydev, &seconds, &nano_seconds); 2500ece19502SDivya Koppera mutex_unlock(&shared->shared_lock); 2501ece19502SDivya Koppera ts->tv_sec = seconds; 2502ece19502SDivya Koppera ts->tv_nsec = nano_seconds; 2503ece19502SDivya Koppera 2504ece19502SDivya Koppera return 0; 2505ece19502SDivya Koppera } 2506ece19502SDivya Koppera 2507ece19502SDivya Koppera static int lan8814_ptpci_settime64(struct ptp_clock_info *ptpci, 2508ece19502SDivya Koppera const struct timespec64 *ts) 2509ece19502SDivya Koppera { 2510ece19502SDivya Koppera struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv, 2511ece19502SDivya Koppera ptp_clock_info); 2512ece19502SDivya Koppera struct phy_device *phydev = shared->phydev; 2513ece19502SDivya Koppera 2514ece19502SDivya Koppera mutex_lock(&shared->shared_lock); 2515ece19502SDivya Koppera lan8814_ptp_clock_set(phydev, ts->tv_sec, ts->tv_nsec); 2516ece19502SDivya Koppera mutex_unlock(&shared->shared_lock); 2517ece19502SDivya Koppera 2518ece19502SDivya Koppera return 0; 2519ece19502SDivya Koppera } 2520ece19502SDivya Koppera 2521ece19502SDivya Koppera static void lan8814_ptp_clock_step(struct phy_device *phydev, 2522ece19502SDivya Koppera s64 time_step_ns) 2523ece19502SDivya Koppera { 2524ece19502SDivya Koppera u32 nano_seconds_step; 2525ece19502SDivya Koppera u64 abs_time_step_ns; 2526ece19502SDivya Koppera u32 unsigned_seconds; 2527ece19502SDivya Koppera u32 nano_seconds; 2528ece19502SDivya Koppera u32 remainder; 2529ece19502SDivya Koppera s32 seconds; 2530ece19502SDivya Koppera 2531ece19502SDivya Koppera if (time_step_ns > 15000000000LL) { 2532ece19502SDivya Koppera /* convert to clock set */ 2533ece19502SDivya Koppera lan8814_ptp_clock_get(phydev, &unsigned_seconds, &nano_seconds); 2534ece19502SDivya Koppera unsigned_seconds += div_u64_rem(time_step_ns, 1000000000LL, 2535ece19502SDivya Koppera &remainder); 2536ece19502SDivya Koppera nano_seconds += remainder; 2537ece19502SDivya Koppera if (nano_seconds >= 1000000000) { 2538ece19502SDivya Koppera unsigned_seconds++; 2539ece19502SDivya Koppera nano_seconds -= 1000000000; 2540ece19502SDivya Koppera } 2541ece19502SDivya Koppera lan8814_ptp_clock_set(phydev, unsigned_seconds, nano_seconds); 2542ece19502SDivya Koppera return; 2543ece19502SDivya Koppera } else if (time_step_ns < -15000000000LL) { 2544ece19502SDivya Koppera /* convert to clock set */ 2545ece19502SDivya Koppera time_step_ns = -time_step_ns; 2546ece19502SDivya Koppera 2547ece19502SDivya Koppera lan8814_ptp_clock_get(phydev, &unsigned_seconds, &nano_seconds); 2548ece19502SDivya Koppera unsigned_seconds -= div_u64_rem(time_step_ns, 1000000000LL, 2549ece19502SDivya Koppera &remainder); 2550ece19502SDivya Koppera nano_seconds_step = remainder; 2551ece19502SDivya Koppera if (nano_seconds < nano_seconds_step) { 2552ece19502SDivya Koppera unsigned_seconds--; 2553ece19502SDivya Koppera nano_seconds += 1000000000; 2554ece19502SDivya Koppera } 2555ece19502SDivya Koppera nano_seconds -= nano_seconds_step; 2556ece19502SDivya Koppera lan8814_ptp_clock_set(phydev, unsigned_seconds, 2557ece19502SDivya Koppera nano_seconds); 2558ece19502SDivya Koppera return; 2559ece19502SDivya Koppera } 2560ece19502SDivya Koppera 2561ece19502SDivya Koppera /* do clock step */ 2562ece19502SDivya Koppera if (time_step_ns >= 0) { 2563ece19502SDivya Koppera abs_time_step_ns = (u64)time_step_ns; 2564ece19502SDivya Koppera seconds = (s32)div_u64_rem(abs_time_step_ns, 1000000000, 2565ece19502SDivya Koppera &remainder); 2566ece19502SDivya Koppera nano_seconds = remainder; 2567ece19502SDivya Koppera } else { 2568ece19502SDivya Koppera abs_time_step_ns = (u64)(-time_step_ns); 2569ece19502SDivya Koppera seconds = -((s32)div_u64_rem(abs_time_step_ns, 1000000000, 2570ece19502SDivya Koppera &remainder)); 2571ece19502SDivya Koppera nano_seconds = remainder; 2572ece19502SDivya Koppera if (nano_seconds > 0) { 2573ece19502SDivya Koppera /* subtracting nano seconds is not allowed 2574ece19502SDivya Koppera * convert to subtracting from seconds, 2575ece19502SDivya Koppera * and adding to nanoseconds 2576ece19502SDivya Koppera */ 2577ece19502SDivya Koppera seconds--; 2578ece19502SDivya Koppera nano_seconds = (1000000000 - nano_seconds); 2579ece19502SDivya Koppera } 2580ece19502SDivya Koppera } 2581ece19502SDivya Koppera 2582ece19502SDivya Koppera if (nano_seconds > 0) { 2583ece19502SDivya Koppera /* add 8 ns to cover the likely normal increment */ 2584ece19502SDivya Koppera nano_seconds += 8; 2585ece19502SDivya Koppera } 2586ece19502SDivya Koppera 2587ece19502SDivya Koppera if (nano_seconds >= 1000000000) { 2588ece19502SDivya Koppera /* carry into seconds */ 2589ece19502SDivya Koppera seconds++; 2590ece19502SDivya Koppera nano_seconds -= 1000000000; 2591ece19502SDivya Koppera } 2592ece19502SDivya Koppera 2593ece19502SDivya Koppera while (seconds) { 2594ece19502SDivya Koppera if (seconds > 0) { 2595ece19502SDivya Koppera u32 adjustment_value = (u32)seconds; 2596ece19502SDivya Koppera u16 adjustment_value_lo, adjustment_value_hi; 2597ece19502SDivya Koppera 2598ece19502SDivya Koppera if (adjustment_value > 0xF) 2599ece19502SDivya Koppera adjustment_value = 0xF; 2600ece19502SDivya Koppera 2601ece19502SDivya Koppera adjustment_value_lo = adjustment_value & 0xffff; 2602ece19502SDivya Koppera adjustment_value_hi = (adjustment_value >> 16) & 0x3fff; 2603ece19502SDivya Koppera 2604ece19502SDivya Koppera lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO, 2605ece19502SDivya Koppera adjustment_value_lo); 2606ece19502SDivya Koppera lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI, 2607ece19502SDivya Koppera PTP_LTC_STEP_ADJ_DIR_ | 2608ece19502SDivya Koppera adjustment_value_hi); 2609ece19502SDivya Koppera seconds -= ((s32)adjustment_value); 2610ece19502SDivya Koppera } else { 2611ece19502SDivya Koppera u32 adjustment_value = (u32)(-seconds); 2612ece19502SDivya Koppera u16 adjustment_value_lo, adjustment_value_hi; 2613ece19502SDivya Koppera 2614ece19502SDivya Koppera if (adjustment_value > 0xF) 2615ece19502SDivya Koppera adjustment_value = 0xF; 2616ece19502SDivya Koppera 2617ece19502SDivya Koppera adjustment_value_lo = adjustment_value & 0xffff; 2618ece19502SDivya Koppera adjustment_value_hi = (adjustment_value >> 16) & 0x3fff; 2619ece19502SDivya Koppera 2620ece19502SDivya Koppera lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO, 2621ece19502SDivya Koppera adjustment_value_lo); 2622ece19502SDivya Koppera lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI, 2623ece19502SDivya Koppera adjustment_value_hi); 2624ece19502SDivya Koppera seconds += ((s32)adjustment_value); 2625ece19502SDivya Koppera } 2626ece19502SDivya Koppera lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, 2627ece19502SDivya Koppera PTP_CMD_CTL_PTP_LTC_STEP_SEC_); 2628ece19502SDivya Koppera } 2629ece19502SDivya Koppera if (nano_seconds) { 2630ece19502SDivya Koppera u16 nano_seconds_lo; 2631ece19502SDivya Koppera u16 nano_seconds_hi; 2632ece19502SDivya Koppera 2633ece19502SDivya Koppera nano_seconds_lo = nano_seconds & 0xffff; 2634ece19502SDivya Koppera nano_seconds_hi = (nano_seconds >> 16) & 0x3fff; 2635ece19502SDivya Koppera 2636ece19502SDivya Koppera lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO, 2637ece19502SDivya Koppera nano_seconds_lo); 2638ece19502SDivya Koppera lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI, 2639ece19502SDivya Koppera PTP_LTC_STEP_ADJ_DIR_ | 2640ece19502SDivya Koppera nano_seconds_hi); 2641ece19502SDivya Koppera lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, 2642ece19502SDivya Koppera PTP_CMD_CTL_PTP_LTC_STEP_NSEC_); 2643ece19502SDivya Koppera } 2644ece19502SDivya Koppera } 2645ece19502SDivya Koppera 2646ece19502SDivya Koppera static int lan8814_ptpci_adjtime(struct ptp_clock_info *ptpci, s64 delta) 2647ece19502SDivya Koppera { 2648ece19502SDivya Koppera struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv, 2649ece19502SDivya Koppera ptp_clock_info); 2650ece19502SDivya Koppera struct phy_device *phydev = shared->phydev; 2651ece19502SDivya Koppera 2652ece19502SDivya Koppera mutex_lock(&shared->shared_lock); 2653ece19502SDivya Koppera lan8814_ptp_clock_step(phydev, delta); 2654ece19502SDivya Koppera mutex_unlock(&shared->shared_lock); 2655ece19502SDivya Koppera 2656ece19502SDivya Koppera return 0; 2657ece19502SDivya Koppera } 2658ece19502SDivya Koppera 2659ece19502SDivya Koppera static int lan8814_ptpci_adjfine(struct ptp_clock_info *ptpci, long scaled_ppm) 2660ece19502SDivya Koppera { 2661ece19502SDivya Koppera struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv, 2662ece19502SDivya Koppera ptp_clock_info); 2663ece19502SDivya Koppera struct phy_device *phydev = shared->phydev; 2664ece19502SDivya Koppera u16 kszphy_rate_adj_lo, kszphy_rate_adj_hi; 2665ece19502SDivya Koppera bool positive = true; 2666ece19502SDivya Koppera u32 kszphy_rate_adj; 2667ece19502SDivya Koppera 2668ece19502SDivya Koppera if (scaled_ppm < 0) { 2669ece19502SDivya Koppera scaled_ppm = -scaled_ppm; 2670ece19502SDivya Koppera positive = false; 2671ece19502SDivya Koppera } 2672ece19502SDivya Koppera 2673ece19502SDivya Koppera kszphy_rate_adj = LAN8814_1PPM_FORMAT * (scaled_ppm >> 16); 2674ece19502SDivya Koppera kszphy_rate_adj += (LAN8814_1PPM_FORMAT * (0xffff & scaled_ppm)) >> 16; 2675ece19502SDivya Koppera 2676ece19502SDivya Koppera kszphy_rate_adj_lo = kszphy_rate_adj & 0xffff; 2677ece19502SDivya Koppera kszphy_rate_adj_hi = (kszphy_rate_adj >> 16) & 0x3fff; 2678ece19502SDivya Koppera 2679ece19502SDivya Koppera if (positive) 2680ece19502SDivya Koppera kszphy_rate_adj_hi |= PTP_CLOCK_RATE_ADJ_DIR_; 2681ece19502SDivya Koppera 2682ece19502SDivya Koppera mutex_lock(&shared->shared_lock); 2683ece19502SDivya Koppera lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_HI, kszphy_rate_adj_hi); 2684ece19502SDivya Koppera lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_LO, kszphy_rate_adj_lo); 2685ece19502SDivya Koppera mutex_unlock(&shared->shared_lock); 2686ece19502SDivya Koppera 2687ece19502SDivya Koppera return 0; 2688ece19502SDivya Koppera } 2689ece19502SDivya Koppera 2690ece19502SDivya Koppera static void lan8814_get_sig_tx(struct sk_buff *skb, u16 *sig) 2691ece19502SDivya Koppera { 2692ece19502SDivya Koppera struct ptp_header *ptp_header; 2693ece19502SDivya Koppera u32 type; 2694ece19502SDivya Koppera 2695ece19502SDivya Koppera type = ptp_classify_raw(skb); 2696ece19502SDivya Koppera ptp_header = ptp_parse_header(skb, type); 2697ece19502SDivya Koppera 2698ece19502SDivya Koppera *sig = (__force u16)(ntohs(ptp_header->sequence_id)); 2699ece19502SDivya Koppera } 2700ece19502SDivya Koppera 2701ece19502SDivya Koppera static void lan8814_dequeue_tx_skb(struct kszphy_ptp_priv *ptp_priv) 2702ece19502SDivya Koppera { 2703ece19502SDivya Koppera struct phy_device *phydev = ptp_priv->phydev; 2704ece19502SDivya Koppera struct skb_shared_hwtstamps shhwtstamps; 2705ece19502SDivya Koppera struct sk_buff *skb, *skb_tmp; 2706ece19502SDivya Koppera unsigned long flags; 2707ece19502SDivya Koppera u32 seconds, nsec; 2708ece19502SDivya Koppera bool ret = false; 2709ece19502SDivya Koppera u16 skb_sig; 2710ece19502SDivya Koppera u16 seq_id; 2711ece19502SDivya Koppera 2712ece19502SDivya Koppera lan8814_ptp_tx_ts_get(phydev, &seconds, &nsec, &seq_id); 2713ece19502SDivya Koppera 2714ece19502SDivya Koppera spin_lock_irqsave(&ptp_priv->tx_queue.lock, flags); 2715ece19502SDivya Koppera skb_queue_walk_safe(&ptp_priv->tx_queue, skb, skb_tmp) { 2716ece19502SDivya Koppera lan8814_get_sig_tx(skb, &skb_sig); 2717ece19502SDivya Koppera 2718ece19502SDivya Koppera if (memcmp(&skb_sig, &seq_id, sizeof(seq_id))) 2719ece19502SDivya Koppera continue; 2720ece19502SDivya Koppera 2721ece19502SDivya Koppera __skb_unlink(skb, &ptp_priv->tx_queue); 2722ece19502SDivya Koppera ret = true; 2723ece19502SDivya Koppera break; 2724ece19502SDivya Koppera } 2725ece19502SDivya Koppera spin_unlock_irqrestore(&ptp_priv->tx_queue.lock, flags); 2726ece19502SDivya Koppera 2727ece19502SDivya Koppera if (ret) { 2728ece19502SDivya Koppera memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 2729ece19502SDivya Koppera shhwtstamps.hwtstamp = ktime_set(seconds, nsec); 2730ece19502SDivya Koppera skb_complete_tx_timestamp(skb, &shhwtstamps); 2731ece19502SDivya Koppera } 2732ece19502SDivya Koppera } 2733ece19502SDivya Koppera 2734ece19502SDivya Koppera static void lan8814_get_tx_ts(struct kszphy_ptp_priv *ptp_priv) 2735ece19502SDivya Koppera { 2736ece19502SDivya Koppera struct phy_device *phydev = ptp_priv->phydev; 2737ece19502SDivya Koppera u32 reg; 2738ece19502SDivya Koppera 2739ece19502SDivya Koppera do { 2740ece19502SDivya Koppera lan8814_dequeue_tx_skb(ptp_priv); 2741ece19502SDivya Koppera 2742ece19502SDivya Koppera /* If other timestamps are available in the FIFO, 2743ece19502SDivya Koppera * process them. 2744ece19502SDivya Koppera */ 2745ece19502SDivya Koppera reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO); 2746ece19502SDivya Koppera } while (PTP_CAP_INFO_TX_TS_CNT_GET_(reg) > 0); 2747ece19502SDivya Koppera } 2748ece19502SDivya Koppera 2749ece19502SDivya Koppera static bool lan8814_match_skb(struct kszphy_ptp_priv *ptp_priv, 2750ece19502SDivya Koppera struct lan8814_ptp_rx_ts *rx_ts) 2751ece19502SDivya Koppera { 2752ece19502SDivya Koppera struct skb_shared_hwtstamps *shhwtstamps; 2753ece19502SDivya Koppera struct sk_buff *skb, *skb_tmp; 2754ece19502SDivya Koppera unsigned long flags; 2755ece19502SDivya Koppera bool ret = false; 2756ece19502SDivya Koppera u16 skb_sig; 2757ece19502SDivya Koppera 2758ece19502SDivya Koppera spin_lock_irqsave(&ptp_priv->rx_queue.lock, flags); 2759ece19502SDivya Koppera skb_queue_walk_safe(&ptp_priv->rx_queue, skb, skb_tmp) { 2760ece19502SDivya Koppera lan8814_get_sig_rx(skb, &skb_sig); 2761ece19502SDivya Koppera 2762ece19502SDivya Koppera if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id))) 2763ece19502SDivya Koppera continue; 2764ece19502SDivya Koppera 2765ece19502SDivya Koppera __skb_unlink(skb, &ptp_priv->rx_queue); 2766ece19502SDivya Koppera 2767ece19502SDivya Koppera ret = true; 2768ece19502SDivya Koppera break; 2769ece19502SDivya Koppera } 2770ece19502SDivya Koppera spin_unlock_irqrestore(&ptp_priv->rx_queue.lock, flags); 2771ece19502SDivya Koppera 2772ece19502SDivya Koppera if (ret) { 2773ece19502SDivya Koppera shhwtstamps = skb_hwtstamps(skb); 2774ece19502SDivya Koppera memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 2775ece19502SDivya Koppera shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds, rx_ts->nsec); 2776e1f9e434SSebastian Andrzej Siewior netif_rx(skb); 2777ece19502SDivya Koppera } 2778ece19502SDivya Koppera 2779ece19502SDivya Koppera return ret; 2780ece19502SDivya Koppera } 2781ece19502SDivya Koppera 2782ece19502SDivya Koppera static void lan8814_get_rx_ts(struct kszphy_ptp_priv *ptp_priv) 2783ece19502SDivya Koppera { 2784ece19502SDivya Koppera struct phy_device *phydev = ptp_priv->phydev; 2785ece19502SDivya Koppera struct lan8814_ptp_rx_ts *rx_ts; 2786ece19502SDivya Koppera unsigned long flags; 2787ece19502SDivya Koppera u32 reg; 2788ece19502SDivya Koppera 2789ece19502SDivya Koppera do { 2790ece19502SDivya Koppera rx_ts = kzalloc(sizeof(*rx_ts), GFP_KERNEL); 2791ece19502SDivya Koppera if (!rx_ts) 2792ece19502SDivya Koppera return; 2793ece19502SDivya Koppera 2794ece19502SDivya Koppera lan8814_ptp_rx_ts_get(phydev, &rx_ts->seconds, &rx_ts->nsec, 2795ece19502SDivya Koppera &rx_ts->seq_id); 2796ece19502SDivya Koppera 2797ece19502SDivya Koppera /* If we failed to match the skb add it to the queue for when 2798ece19502SDivya Koppera * the frame will come 2799ece19502SDivya Koppera */ 2800ece19502SDivya Koppera if (!lan8814_match_skb(ptp_priv, rx_ts)) { 2801ece19502SDivya Koppera spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags); 2802ece19502SDivya Koppera list_add(&rx_ts->list, &ptp_priv->rx_ts_list); 2803ece19502SDivya Koppera spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags); 2804ece19502SDivya Koppera } else { 2805ece19502SDivya Koppera kfree(rx_ts); 2806ece19502SDivya Koppera } 2807ece19502SDivya Koppera 2808ece19502SDivya Koppera /* If other timestamps are available in the FIFO, 2809ece19502SDivya Koppera * process them. 2810ece19502SDivya Koppera */ 2811ece19502SDivya Koppera reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO); 2812ece19502SDivya Koppera } while (PTP_CAP_INFO_RX_TS_CNT_GET_(reg) > 0); 2813ece19502SDivya Koppera } 2814ece19502SDivya Koppera 28157abd92a5SHoratiu Vultur static void lan8814_handle_ptp_interrupt(struct phy_device *phydev, u16 status) 2816ece19502SDivya Koppera { 2817ece19502SDivya Koppera struct kszphy_priv *priv = phydev->priv; 2818ece19502SDivya Koppera struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv; 2819ece19502SDivya Koppera 2820ece19502SDivya Koppera if (status & PTP_TSU_INT_STS_PTP_TX_TS_EN_) 2821ece19502SDivya Koppera lan8814_get_tx_ts(ptp_priv); 2822ece19502SDivya Koppera 2823ece19502SDivya Koppera if (status & PTP_TSU_INT_STS_PTP_RX_TS_EN_) 2824ece19502SDivya Koppera lan8814_get_rx_ts(ptp_priv); 2825ece19502SDivya Koppera 2826ece19502SDivya Koppera if (status & PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_) { 2827ece19502SDivya Koppera lan8814_flush_fifo(phydev, true); 2828ece19502SDivya Koppera skb_queue_purge(&ptp_priv->tx_queue); 2829ece19502SDivya Koppera } 2830ece19502SDivya Koppera 2831ece19502SDivya Koppera if (status & PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_) { 2832ece19502SDivya Koppera lan8814_flush_fifo(phydev, false); 2833ece19502SDivya Koppera skb_queue_purge(&ptp_priv->rx_queue); 2834ece19502SDivya Koppera } 2835ece19502SDivya Koppera } 2836ece19502SDivya Koppera 28377c2dcfa2SHoratiu Vultur static int lan8804_config_init(struct phy_device *phydev) 28387c2dcfa2SHoratiu Vultur { 28397c2dcfa2SHoratiu Vultur int val; 28407c2dcfa2SHoratiu Vultur 28417c2dcfa2SHoratiu Vultur /* MDI-X setting for swap A,B transmit */ 28427c2dcfa2SHoratiu Vultur val = lanphy_read_page_reg(phydev, 2, LAN8804_ALIGN_SWAP); 28437c2dcfa2SHoratiu Vultur val &= ~LAN8804_ALIGN_TX_A_B_SWAP_MASK; 28447c2dcfa2SHoratiu Vultur val |= LAN8804_ALIGN_TX_A_B_SWAP; 28457c2dcfa2SHoratiu Vultur lanphy_write_page_reg(phydev, 2, LAN8804_ALIGN_SWAP, val); 28467c2dcfa2SHoratiu Vultur 28477c2dcfa2SHoratiu Vultur /* Make sure that the PHY will not stop generating the clock when the 28487c2dcfa2SHoratiu Vultur * link partner goes down 28497c2dcfa2SHoratiu Vultur */ 28507c2dcfa2SHoratiu Vultur lanphy_write_page_reg(phydev, 31, LAN8814_CLOCK_MANAGEMENT, 0x27e); 28517c2dcfa2SHoratiu Vultur lanphy_read_page_reg(phydev, 1, LAN8814_LINK_QUALITY); 28527c2dcfa2SHoratiu Vultur 28537c2dcfa2SHoratiu Vultur return 0; 28547c2dcfa2SHoratiu Vultur } 28557c2dcfa2SHoratiu Vultur 2856b324c6e5SHoratiu Vultur static irqreturn_t lan8804_handle_interrupt(struct phy_device *phydev) 2857b324c6e5SHoratiu Vultur { 2858b324c6e5SHoratiu Vultur int status; 2859b324c6e5SHoratiu Vultur 2860b324c6e5SHoratiu Vultur status = phy_read(phydev, LAN8814_INTS); 2861b324c6e5SHoratiu Vultur if (status < 0) { 2862b324c6e5SHoratiu Vultur phy_error(phydev); 2863b324c6e5SHoratiu Vultur return IRQ_NONE; 2864b324c6e5SHoratiu Vultur } 2865b324c6e5SHoratiu Vultur 2866b324c6e5SHoratiu Vultur if (status > 0) 2867b324c6e5SHoratiu Vultur phy_trigger_machine(phydev); 2868b324c6e5SHoratiu Vultur 2869b324c6e5SHoratiu Vultur return IRQ_HANDLED; 2870b324c6e5SHoratiu Vultur } 2871b324c6e5SHoratiu Vultur 2872b324c6e5SHoratiu Vultur #define LAN8804_OUTPUT_CONTROL 25 2873b324c6e5SHoratiu Vultur #define LAN8804_OUTPUT_CONTROL_INTR_BUFFER BIT(14) 2874b324c6e5SHoratiu Vultur #define LAN8804_CONTROL 31 2875b324c6e5SHoratiu Vultur #define LAN8804_CONTROL_INTR_POLARITY BIT(14) 2876b324c6e5SHoratiu Vultur 2877b324c6e5SHoratiu Vultur static int lan8804_config_intr(struct phy_device *phydev) 2878b324c6e5SHoratiu Vultur { 2879b324c6e5SHoratiu Vultur int err; 2880b324c6e5SHoratiu Vultur 2881b324c6e5SHoratiu Vultur /* This is an internal PHY of lan966x and is not possible to change the 2882b324c6e5SHoratiu Vultur * polarity on the GIC found in lan966x, therefore change the polarity 2883b324c6e5SHoratiu Vultur * of the interrupt in the PHY from being active low instead of active 2884b324c6e5SHoratiu Vultur * high. 2885b324c6e5SHoratiu Vultur */ 2886b324c6e5SHoratiu Vultur phy_write(phydev, LAN8804_CONTROL, LAN8804_CONTROL_INTR_POLARITY); 2887b324c6e5SHoratiu Vultur 2888b324c6e5SHoratiu Vultur /* By default interrupt buffer is open-drain in which case the interrupt 2889b324c6e5SHoratiu Vultur * can be active only low. Therefore change the interrupt buffer to be 2890b324c6e5SHoratiu Vultur * push-pull to be able to change interrupt polarity 2891b324c6e5SHoratiu Vultur */ 2892b324c6e5SHoratiu Vultur phy_write(phydev, LAN8804_OUTPUT_CONTROL, 2893b324c6e5SHoratiu Vultur LAN8804_OUTPUT_CONTROL_INTR_BUFFER); 2894b324c6e5SHoratiu Vultur 2895b324c6e5SHoratiu Vultur if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 2896b324c6e5SHoratiu Vultur err = phy_read(phydev, LAN8814_INTS); 2897b324c6e5SHoratiu Vultur if (err < 0) 2898b324c6e5SHoratiu Vultur return err; 2899b324c6e5SHoratiu Vultur 2900b324c6e5SHoratiu Vultur err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK); 2901b324c6e5SHoratiu Vultur if (err) 2902b324c6e5SHoratiu Vultur return err; 2903b324c6e5SHoratiu Vultur } else { 2904b324c6e5SHoratiu Vultur err = phy_write(phydev, LAN8814_INTC, 0); 2905b324c6e5SHoratiu Vultur if (err) 2906b324c6e5SHoratiu Vultur return err; 2907b324c6e5SHoratiu Vultur 2908b324c6e5SHoratiu Vultur err = phy_read(phydev, LAN8814_INTS); 2909b324c6e5SHoratiu Vultur if (err < 0) 2910b324c6e5SHoratiu Vultur return err; 2911b324c6e5SHoratiu Vultur } 2912b324c6e5SHoratiu Vultur 2913b324c6e5SHoratiu Vultur return 0; 2914b324c6e5SHoratiu Vultur } 2915b324c6e5SHoratiu Vultur 2916b3ec7248SDivya Koppera static irqreturn_t lan8814_handle_interrupt(struct phy_device *phydev) 2917b3ec7248SDivya Koppera { 29182002fbacSMichael Walle int ret = IRQ_NONE; 29197abd92a5SHoratiu Vultur int irq_status; 2920b3ec7248SDivya Koppera 2921b3ec7248SDivya Koppera irq_status = phy_read(phydev, LAN8814_INTS); 2922ece19502SDivya Koppera if (irq_status < 0) { 2923ece19502SDivya Koppera phy_error(phydev); 2924ece19502SDivya Koppera return IRQ_NONE; 2925ece19502SDivya Koppera } 2926ece19502SDivya Koppera 29272002fbacSMichael Walle if (irq_status & LAN8814_INT_LINK) { 29282002fbacSMichael Walle phy_trigger_machine(phydev); 29292002fbacSMichael Walle ret = IRQ_HANDLED; 29302002fbacSMichael Walle } 29312002fbacSMichael Walle 29327abd92a5SHoratiu Vultur while (true) { 29337abd92a5SHoratiu Vultur irq_status = lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS); 29347abd92a5SHoratiu Vultur if (!irq_status) 2935ece19502SDivya Koppera break; 29367abd92a5SHoratiu Vultur 29377abd92a5SHoratiu Vultur lan8814_handle_ptp_interrupt(phydev, irq_status); 29387abd92a5SHoratiu Vultur ret = IRQ_HANDLED; 29392002fbacSMichael Walle } 29402002fbacSMichael Walle 29412002fbacSMichael Walle return ret; 2942b3ec7248SDivya Koppera } 2943b3ec7248SDivya Koppera 2944b3ec7248SDivya Koppera static int lan8814_ack_interrupt(struct phy_device *phydev) 2945b3ec7248SDivya Koppera { 2946b3ec7248SDivya Koppera /* bit[12..0] int status, which is a read and clear register. */ 2947b3ec7248SDivya Koppera int rc; 2948b3ec7248SDivya Koppera 2949b3ec7248SDivya Koppera rc = phy_read(phydev, LAN8814_INTS); 2950b3ec7248SDivya Koppera 2951b3ec7248SDivya Koppera return (rc < 0) ? rc : 0; 2952b3ec7248SDivya Koppera } 2953b3ec7248SDivya Koppera 2954b3ec7248SDivya Koppera static int lan8814_config_intr(struct phy_device *phydev) 2955b3ec7248SDivya Koppera { 2956b3ec7248SDivya Koppera int err; 2957b3ec7248SDivya Koppera 2958b3ec7248SDivya Koppera lanphy_write_page_reg(phydev, 4, LAN8814_INTR_CTRL_REG, 2959b3ec7248SDivya Koppera LAN8814_INTR_CTRL_REG_POLARITY | 2960b3ec7248SDivya Koppera LAN8814_INTR_CTRL_REG_INTR_ENABLE); 2961b3ec7248SDivya Koppera 2962b3ec7248SDivya Koppera /* enable / disable interrupts */ 2963b3ec7248SDivya Koppera if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 2964b3ec7248SDivya Koppera err = lan8814_ack_interrupt(phydev); 2965b3ec7248SDivya Koppera if (err) 2966b3ec7248SDivya Koppera return err; 2967b3ec7248SDivya Koppera 2968b3ec7248SDivya Koppera err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK); 2969b3ec7248SDivya Koppera } else { 2970b3ec7248SDivya Koppera err = phy_write(phydev, LAN8814_INTC, 0); 2971b3ec7248SDivya Koppera if (err) 2972b3ec7248SDivya Koppera return err; 2973b3ec7248SDivya Koppera 2974b3ec7248SDivya Koppera err = lan8814_ack_interrupt(phydev); 2975b3ec7248SDivya Koppera } 2976b3ec7248SDivya Koppera 2977b3ec7248SDivya Koppera return err; 2978b3ec7248SDivya Koppera } 2979b3ec7248SDivya Koppera 2980ece19502SDivya Koppera static void lan8814_ptp_init(struct phy_device *phydev) 2981ece19502SDivya Koppera { 2982ece19502SDivya Koppera struct kszphy_priv *priv = phydev->priv; 2983ece19502SDivya Koppera struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv; 2984ece19502SDivya Koppera u32 temp; 2985ece19502SDivya Koppera 298631d00ca4SMichael Walle if (!IS_ENABLED(CONFIG_PTP_1588_CLOCK) || 298731d00ca4SMichael Walle !IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING)) 298831d00ca4SMichael Walle return; 298931d00ca4SMichael Walle 2990ece19502SDivya Koppera lanphy_write_page_reg(phydev, 5, TSU_HARD_RESET, TSU_HARD_RESET_); 2991ece19502SDivya Koppera 2992ece19502SDivya Koppera temp = lanphy_read_page_reg(phydev, 5, PTP_TX_MOD); 2993ece19502SDivya Koppera temp |= PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_; 2994ece19502SDivya Koppera lanphy_write_page_reg(phydev, 5, PTP_TX_MOD, temp); 2995ece19502SDivya Koppera 2996ece19502SDivya Koppera temp = lanphy_read_page_reg(phydev, 5, PTP_RX_MOD); 2997ece19502SDivya Koppera temp |= PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_; 2998ece19502SDivya Koppera lanphy_write_page_reg(phydev, 5, PTP_RX_MOD, temp); 2999ece19502SDivya Koppera 3000ece19502SDivya Koppera lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_CONFIG, 0); 3001ece19502SDivya Koppera lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_CONFIG, 0); 3002ece19502SDivya Koppera 3003ece19502SDivya Koppera /* Removing default registers configs related to L2 and IP */ 3004ece19502SDivya Koppera lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_L2_ADDR_EN, 0); 3005ece19502SDivya Koppera lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_L2_ADDR_EN, 0); 3006ece19502SDivya Koppera lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_IP_ADDR_EN, 0); 3007ece19502SDivya Koppera lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_IP_ADDR_EN, 0); 3008ece19502SDivya Koppera 3009ece19502SDivya Koppera skb_queue_head_init(&ptp_priv->tx_queue); 3010ece19502SDivya Koppera skb_queue_head_init(&ptp_priv->rx_queue); 3011ece19502SDivya Koppera INIT_LIST_HEAD(&ptp_priv->rx_ts_list); 3012ece19502SDivya Koppera spin_lock_init(&ptp_priv->rx_ts_lock); 3013ece19502SDivya Koppera 3014ece19502SDivya Koppera ptp_priv->phydev = phydev; 3015ece19502SDivya Koppera 3016ece19502SDivya Koppera ptp_priv->mii_ts.rxtstamp = lan8814_rxtstamp; 3017ece19502SDivya Koppera ptp_priv->mii_ts.txtstamp = lan8814_txtstamp; 3018ece19502SDivya Koppera ptp_priv->mii_ts.hwtstamp = lan8814_hwtstamp; 3019ece19502SDivya Koppera ptp_priv->mii_ts.ts_info = lan8814_ts_info; 3020ece19502SDivya Koppera 3021ece19502SDivya Koppera phydev->mii_ts = &ptp_priv->mii_ts; 3022ece19502SDivya Koppera } 3023ece19502SDivya Koppera 3024ece19502SDivya Koppera static int lan8814_ptp_probe_once(struct phy_device *phydev) 3025ece19502SDivya Koppera { 3026ece19502SDivya Koppera struct lan8814_shared_priv *shared = phydev->shared->priv; 3027ece19502SDivya Koppera 3028ece19502SDivya Koppera /* Initialise shared lock for clock*/ 3029ece19502SDivya Koppera mutex_init(&shared->shared_lock); 3030ece19502SDivya Koppera 3031ece19502SDivya Koppera shared->ptp_clock_info.owner = THIS_MODULE; 3032ece19502SDivya Koppera snprintf(shared->ptp_clock_info.name, 30, "%s", phydev->drv->name); 3033ece19502SDivya Koppera shared->ptp_clock_info.max_adj = 31249999; 3034ece19502SDivya Koppera shared->ptp_clock_info.n_alarm = 0; 3035ece19502SDivya Koppera shared->ptp_clock_info.n_ext_ts = 0; 3036ece19502SDivya Koppera shared->ptp_clock_info.n_pins = 0; 3037ece19502SDivya Koppera shared->ptp_clock_info.pps = 0; 3038ece19502SDivya Koppera shared->ptp_clock_info.pin_config = NULL; 3039ece19502SDivya Koppera shared->ptp_clock_info.adjfine = lan8814_ptpci_adjfine; 3040ece19502SDivya Koppera shared->ptp_clock_info.adjtime = lan8814_ptpci_adjtime; 3041ece19502SDivya Koppera shared->ptp_clock_info.gettime64 = lan8814_ptpci_gettime64; 3042ece19502SDivya Koppera shared->ptp_clock_info.settime64 = lan8814_ptpci_settime64; 3043ece19502SDivya Koppera shared->ptp_clock_info.getcrosststamp = NULL; 3044ece19502SDivya Koppera 3045ece19502SDivya Koppera shared->ptp_clock = ptp_clock_register(&shared->ptp_clock_info, 3046ece19502SDivya Koppera &phydev->mdio.dev); 30473f88d7d1SDivya Koppera if (IS_ERR(shared->ptp_clock)) { 3048ece19502SDivya Koppera phydev_err(phydev, "ptp_clock_register failed %lu\n", 3049ece19502SDivya Koppera PTR_ERR(shared->ptp_clock)); 3050ece19502SDivya Koppera return -EINVAL; 3051ece19502SDivya Koppera } 3052ece19502SDivya Koppera 30533f88d7d1SDivya Koppera /* Check if PHC support is missing at the configuration level */ 30543f88d7d1SDivya Koppera if (!shared->ptp_clock) 30553f88d7d1SDivya Koppera return 0; 30563f88d7d1SDivya Koppera 3057ece19502SDivya Koppera phydev_dbg(phydev, "successfully registered ptp clock\n"); 3058ece19502SDivya Koppera 3059ece19502SDivya Koppera shared->phydev = phydev; 3060ece19502SDivya Koppera 3061ece19502SDivya Koppera /* The EP.4 is shared between all the PHYs in the package and also it 3062ece19502SDivya Koppera * can be accessed by any of the PHYs 3063ece19502SDivya Koppera */ 3064ece19502SDivya Koppera lanphy_write_page_reg(phydev, 4, LTC_HARD_RESET, LTC_HARD_RESET_); 3065ece19502SDivya Koppera lanphy_write_page_reg(phydev, 4, PTP_OPERATING_MODE, 3066ece19502SDivya Koppera PTP_OPERATING_MODE_STANDALONE_); 3067ece19502SDivya Koppera 3068ece19502SDivya Koppera return 0; 3069ece19502SDivya Koppera } 3070ece19502SDivya Koppera 3071a516b7f7SDivya Koppera static void lan8814_setup_led(struct phy_device *phydev, int val) 3072a516b7f7SDivya Koppera { 3073a516b7f7SDivya Koppera int temp; 3074a516b7f7SDivya Koppera 3075a516b7f7SDivya Koppera temp = lanphy_read_page_reg(phydev, 5, LAN8814_LED_CTRL_1); 3076a516b7f7SDivya Koppera 3077a516b7f7SDivya Koppera if (val) 3078a516b7f7SDivya Koppera temp |= LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_; 3079a516b7f7SDivya Koppera else 3080a516b7f7SDivya Koppera temp &= ~LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_; 3081a516b7f7SDivya Koppera 3082a516b7f7SDivya Koppera lanphy_write_page_reg(phydev, 5, LAN8814_LED_CTRL_1, temp); 3083a516b7f7SDivya Koppera } 3084a516b7f7SDivya Koppera 3085ece19502SDivya Koppera static int lan8814_config_init(struct phy_device *phydev) 3086ece19502SDivya Koppera { 3087a516b7f7SDivya Koppera struct kszphy_priv *lan8814 = phydev->priv; 3088ece19502SDivya Koppera int val; 3089ece19502SDivya Koppera 3090ece19502SDivya Koppera /* Reset the PHY */ 3091ece19502SDivya Koppera val = lanphy_read_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET); 3092ece19502SDivya Koppera val |= LAN8814_QSGMII_SOFT_RESET_BIT; 3093ece19502SDivya Koppera lanphy_write_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET, val); 3094ece19502SDivya Koppera 3095ece19502SDivya Koppera /* Disable ANEG with QSGMII PCS Host side */ 3096ece19502SDivya Koppera val = lanphy_read_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG); 3097ece19502SDivya Koppera val &= ~LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA; 3098ece19502SDivya Koppera lanphy_write_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG, val); 3099ece19502SDivya Koppera 3100ece19502SDivya Koppera /* MDI-X setting for swap A,B transmit */ 3101ece19502SDivya Koppera val = lanphy_read_page_reg(phydev, 2, LAN8814_ALIGN_SWAP); 3102ece19502SDivya Koppera val &= ~LAN8814_ALIGN_TX_A_B_SWAP_MASK; 3103ece19502SDivya Koppera val |= LAN8814_ALIGN_TX_A_B_SWAP; 3104ece19502SDivya Koppera lanphy_write_page_reg(phydev, 2, LAN8814_ALIGN_SWAP, val); 3105ece19502SDivya Koppera 3106a516b7f7SDivya Koppera if (lan8814->led_mode >= 0) 3107a516b7f7SDivya Koppera lan8814_setup_led(phydev, lan8814->led_mode); 3108a516b7f7SDivya Koppera 3109ece19502SDivya Koppera return 0; 3110ece19502SDivya Koppera } 3111ece19502SDivya Koppera 31124a4ce822SHoratiu Vultur /* It is expected that there will not be any 'lan8814_take_coma_mode' 31134a4ce822SHoratiu Vultur * function called in suspend. Because the GPIO line can be shared, so if one of 31144a4ce822SHoratiu Vultur * the phys goes back in coma mode, then all the other PHYs will go, which is 31154a4ce822SHoratiu Vultur * wrong. 31164a4ce822SHoratiu Vultur */ 3117738871b0SMichael Walle static int lan8814_release_coma_mode(struct phy_device *phydev) 3118738871b0SMichael Walle { 3119738871b0SMichael Walle struct gpio_desc *gpiod; 3120738871b0SMichael Walle 3121738871b0SMichael Walle gpiod = devm_gpiod_get_optional(&phydev->mdio.dev, "coma-mode", 31224a4ce822SHoratiu Vultur GPIOD_OUT_HIGH_OPEN_DRAIN | 31234a4ce822SHoratiu Vultur GPIOD_FLAGS_BIT_NONEXCLUSIVE); 3124738871b0SMichael Walle if (IS_ERR(gpiod)) 3125738871b0SMichael Walle return PTR_ERR(gpiod); 3126738871b0SMichael Walle 3127738871b0SMichael Walle gpiod_set_consumer_name(gpiod, "LAN8814 coma mode"); 3128738871b0SMichael Walle gpiod_set_value_cansleep(gpiod, 0); 3129738871b0SMichael Walle 3130738871b0SMichael Walle return 0; 3131738871b0SMichael Walle } 3132738871b0SMichael Walle 3133ece19502SDivya Koppera static int lan8814_probe(struct phy_device *phydev) 3134ece19502SDivya Koppera { 3135a516b7f7SDivya Koppera const struct kszphy_type *type = phydev->drv->driver_data; 3136ece19502SDivya Koppera struct kszphy_priv *priv; 3137ece19502SDivya Koppera u16 addr; 3138ece19502SDivya Koppera int err; 3139ece19502SDivya Koppera 3140ece19502SDivya Koppera priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 3141ece19502SDivya Koppera if (!priv) 3142ece19502SDivya Koppera return -ENOMEM; 3143ece19502SDivya Koppera 3144ece19502SDivya Koppera phydev->priv = priv; 3145ece19502SDivya Koppera 3146a516b7f7SDivya Koppera priv->type = type; 3147a516b7f7SDivya Koppera 3148a516b7f7SDivya Koppera kszphy_parse_led_mode(phydev); 3149a516b7f7SDivya Koppera 3150ece19502SDivya Koppera /* Strap-in value for PHY address, below register read gives starting 3151ece19502SDivya Koppera * phy address value 3152ece19502SDivya Koppera */ 3153ece19502SDivya Koppera addr = lanphy_read_page_reg(phydev, 4, 0) & 0x1F; 3154ece19502SDivya Koppera devm_phy_package_join(&phydev->mdio.dev, phydev, 3155ece19502SDivya Koppera addr, sizeof(struct lan8814_shared_priv)); 3156ece19502SDivya Koppera 3157ece19502SDivya Koppera if (phy_package_init_once(phydev)) { 3158738871b0SMichael Walle err = lan8814_release_coma_mode(phydev); 3159738871b0SMichael Walle if (err) 3160738871b0SMichael Walle return err; 3161738871b0SMichael Walle 3162ece19502SDivya Koppera err = lan8814_ptp_probe_once(phydev); 3163ece19502SDivya Koppera if (err) 3164ece19502SDivya Koppera return err; 3165ece19502SDivya Koppera } 3166ece19502SDivya Koppera 3167ece19502SDivya Koppera lan8814_ptp_init(phydev); 3168ece19502SDivya Koppera 3169ece19502SDivya Koppera return 0; 3170ece19502SDivya Koppera } 3171ece19502SDivya Koppera 3172a8f1a19dSHoratiu Vultur #define LAN8841_MMD_TIMER_REG 0 3173a8f1a19dSHoratiu Vultur #define LAN8841_MMD0_REGISTER_17 17 3174a8f1a19dSHoratiu Vultur #define LAN8841_MMD0_REGISTER_17_DROP_OPT(x) ((x) & 0x3) 3175a8f1a19dSHoratiu Vultur #define LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS BIT(3) 3176a8f1a19dSHoratiu Vultur #define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG 2 3177a8f1a19dSHoratiu Vultur #define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK BIT(14) 3178a8f1a19dSHoratiu Vultur #define LAN8841_MMD_ANALOG_REG 28 3179a8f1a19dSHoratiu Vultur #define LAN8841_ANALOG_CONTROL_1 1 3180a8f1a19dSHoratiu Vultur #define LAN8841_ANALOG_CONTROL_1_PLL_TRIM(x) (((x) & 0x3) << 5) 3181a8f1a19dSHoratiu Vultur #define LAN8841_ANALOG_CONTROL_10 13 3182a8f1a19dSHoratiu Vultur #define LAN8841_ANALOG_CONTROL_10_PLL_DIV(x) ((x) & 0x3) 3183a8f1a19dSHoratiu Vultur #define LAN8841_ANALOG_CONTROL_11 14 3184a8f1a19dSHoratiu Vultur #define LAN8841_ANALOG_CONTROL_11_LDO_REF(x) (((x) & 0x7) << 12) 3185a8f1a19dSHoratiu Vultur #define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT 69 3186a8f1a19dSHoratiu Vultur #define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL 0xbffc 3187a8f1a19dSHoratiu Vultur #define LAN8841_BTRX_POWER_DOWN 70 3188a8f1a19dSHoratiu Vultur #define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A BIT(0) 3189a8f1a19dSHoratiu Vultur #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_A BIT(1) 3190a8f1a19dSHoratiu Vultur #define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B BIT(2) 3191a8f1a19dSHoratiu Vultur #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_B BIT(3) 3192a8f1a19dSHoratiu Vultur #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_C BIT(5) 3193a8f1a19dSHoratiu Vultur #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_D BIT(7) 3194a8f1a19dSHoratiu Vultur #define LAN8841_ADC_CHANNEL_MASK 198 3195a8f1a19dSHoratiu Vultur 3196a8f1a19dSHoratiu Vultur static int lan8841_config_init(struct phy_device *phydev) 3197a8f1a19dSHoratiu Vultur { 3198a8f1a19dSHoratiu Vultur int ret; 3199a8f1a19dSHoratiu Vultur 3200a8f1a19dSHoratiu Vultur ret = ksz9131_config_init(phydev); 3201a8f1a19dSHoratiu Vultur if (ret) 3202a8f1a19dSHoratiu Vultur return ret; 3203a8f1a19dSHoratiu Vultur 3204a8f1a19dSHoratiu Vultur /* 100BT Clause 40 improvenent errata */ 3205a8f1a19dSHoratiu Vultur phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, 3206a8f1a19dSHoratiu Vultur LAN8841_ANALOG_CONTROL_1, 3207a8f1a19dSHoratiu Vultur LAN8841_ANALOG_CONTROL_1_PLL_TRIM(0x2)); 3208a8f1a19dSHoratiu Vultur phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, 3209a8f1a19dSHoratiu Vultur LAN8841_ANALOG_CONTROL_10, 3210a8f1a19dSHoratiu Vultur LAN8841_ANALOG_CONTROL_10_PLL_DIV(0x1)); 3211a8f1a19dSHoratiu Vultur 3212a8f1a19dSHoratiu Vultur /* 10M/100M Ethernet Signal Tuning Errata for Shorted-Center Tap 3213a8f1a19dSHoratiu Vultur * Magnetics 3214a8f1a19dSHoratiu Vultur */ 3215a8f1a19dSHoratiu Vultur ret = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, 3216a8f1a19dSHoratiu Vultur LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG); 3217a8f1a19dSHoratiu Vultur if (ret & LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK) { 3218a8f1a19dSHoratiu Vultur phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, 3219a8f1a19dSHoratiu Vultur LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT, 3220a8f1a19dSHoratiu Vultur LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL); 3221a8f1a19dSHoratiu Vultur phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, 3222a8f1a19dSHoratiu Vultur LAN8841_BTRX_POWER_DOWN, 3223a8f1a19dSHoratiu Vultur LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A | 3224a8f1a19dSHoratiu Vultur LAN8841_BTRX_POWER_DOWN_BTRX_CH_A | 3225a8f1a19dSHoratiu Vultur LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B | 3226a8f1a19dSHoratiu Vultur LAN8841_BTRX_POWER_DOWN_BTRX_CH_B | 3227a8f1a19dSHoratiu Vultur LAN8841_BTRX_POWER_DOWN_BTRX_CH_C | 3228a8f1a19dSHoratiu Vultur LAN8841_BTRX_POWER_DOWN_BTRX_CH_D); 3229a8f1a19dSHoratiu Vultur } 3230a8f1a19dSHoratiu Vultur 3231a8f1a19dSHoratiu Vultur /* LDO Adjustment errata */ 3232a8f1a19dSHoratiu Vultur phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, 3233a8f1a19dSHoratiu Vultur LAN8841_ANALOG_CONTROL_11, 3234a8f1a19dSHoratiu Vultur LAN8841_ANALOG_CONTROL_11_LDO_REF(1)); 3235a8f1a19dSHoratiu Vultur 3236a8f1a19dSHoratiu Vultur /* 100BT RGMII latency tuning errata */ 3237a8f1a19dSHoratiu Vultur phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 3238a8f1a19dSHoratiu Vultur LAN8841_ADC_CHANNEL_MASK, 0x0); 3239a8f1a19dSHoratiu Vultur phy_write_mmd(phydev, LAN8841_MMD_TIMER_REG, 3240a8f1a19dSHoratiu Vultur LAN8841_MMD0_REGISTER_17, 3241a8f1a19dSHoratiu Vultur LAN8841_MMD0_REGISTER_17_DROP_OPT(2) | 3242a8f1a19dSHoratiu Vultur LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS); 3243a8f1a19dSHoratiu Vultur 3244a8f1a19dSHoratiu Vultur return 0; 3245a8f1a19dSHoratiu Vultur } 3246a8f1a19dSHoratiu Vultur 3247a8f1a19dSHoratiu Vultur #define LAN8841_OUTPUT_CTRL 25 3248a8f1a19dSHoratiu Vultur #define LAN8841_OUTPUT_CTRL_INT_BUFFER BIT(14) 3249a8f1a19dSHoratiu Vultur 3250a8f1a19dSHoratiu Vultur static int lan8841_config_intr(struct phy_device *phydev) 3251a8f1a19dSHoratiu Vultur { 3252a8f1a19dSHoratiu Vultur int err; 3253a8f1a19dSHoratiu Vultur 3254a8f1a19dSHoratiu Vultur phy_modify(phydev, LAN8841_OUTPUT_CTRL, 3255a8f1a19dSHoratiu Vultur LAN8841_OUTPUT_CTRL_INT_BUFFER, 0); 3256a8f1a19dSHoratiu Vultur 3257a8f1a19dSHoratiu Vultur if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 3258a8f1a19dSHoratiu Vultur err = phy_read(phydev, LAN8814_INTS); 3259a8f1a19dSHoratiu Vultur if (err) 3260a8f1a19dSHoratiu Vultur return err; 3261a8f1a19dSHoratiu Vultur 3262a8f1a19dSHoratiu Vultur err = phy_write(phydev, LAN8814_INTC, 3263a8f1a19dSHoratiu Vultur LAN8814_INT_LINK); 3264a8f1a19dSHoratiu Vultur } else { 3265a8f1a19dSHoratiu Vultur err = phy_write(phydev, LAN8814_INTC, 0); 3266a8f1a19dSHoratiu Vultur if (err) 3267a8f1a19dSHoratiu Vultur return err; 3268a8f1a19dSHoratiu Vultur 3269a8f1a19dSHoratiu Vultur err = phy_read(phydev, LAN8814_INTS); 3270a8f1a19dSHoratiu Vultur } 3271a8f1a19dSHoratiu Vultur 3272a8f1a19dSHoratiu Vultur return err; 3273a8f1a19dSHoratiu Vultur } 3274a8f1a19dSHoratiu Vultur 3275a8f1a19dSHoratiu Vultur static irqreturn_t lan8841_handle_interrupt(struct phy_device *phydev) 3276a8f1a19dSHoratiu Vultur { 3277a8f1a19dSHoratiu Vultur int irq_status; 3278a8f1a19dSHoratiu Vultur 3279a8f1a19dSHoratiu Vultur irq_status = phy_read(phydev, LAN8814_INTS); 3280a8f1a19dSHoratiu Vultur if (irq_status < 0) { 3281a8f1a19dSHoratiu Vultur phy_error(phydev); 3282a8f1a19dSHoratiu Vultur return IRQ_NONE; 3283a8f1a19dSHoratiu Vultur } 3284a8f1a19dSHoratiu Vultur 3285a8f1a19dSHoratiu Vultur if (irq_status & LAN8814_INT_LINK) { 3286a8f1a19dSHoratiu Vultur phy_trigger_machine(phydev); 3287a8f1a19dSHoratiu Vultur return IRQ_HANDLED; 3288a8f1a19dSHoratiu Vultur } 3289a8f1a19dSHoratiu Vultur 3290a8f1a19dSHoratiu Vultur return IRQ_NONE; 3291a8f1a19dSHoratiu Vultur } 3292a8f1a19dSHoratiu Vultur 3293a8f1a19dSHoratiu Vultur #define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER 3 3294a8f1a19dSHoratiu Vultur #define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN BIT(0) 3295a8f1a19dSHoratiu Vultur 3296a8f1a19dSHoratiu Vultur static int lan8841_probe(struct phy_device *phydev) 3297a8f1a19dSHoratiu Vultur { 3298a8f1a19dSHoratiu Vultur int err; 3299a8f1a19dSHoratiu Vultur 3300a8f1a19dSHoratiu Vultur err = kszphy_probe(phydev); 3301a8f1a19dSHoratiu Vultur if (err) 3302a8f1a19dSHoratiu Vultur return err; 3303a8f1a19dSHoratiu Vultur 3304a8f1a19dSHoratiu Vultur if (phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, 3305a8f1a19dSHoratiu Vultur LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER) & 3306a8f1a19dSHoratiu Vultur LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN) 3307a8f1a19dSHoratiu Vultur phydev->interface = PHY_INTERFACE_MODE_RGMII_RXID; 3308a8f1a19dSHoratiu Vultur 3309a8f1a19dSHoratiu Vultur return 0; 3310a8f1a19dSHoratiu Vultur } 3311a8f1a19dSHoratiu Vultur 3312d5bf9071SChristian Hohnstaedt static struct phy_driver ksphy_driver[] = { 3313d5bf9071SChristian Hohnstaedt { 331451f932c4SChoi, David .phy_id = PHY_ID_KS8737, 3315f893a99eSFabio Estevam .phy_id_mask = MICREL_PHY_ID_MASK, 331651f932c4SChoi, David .name = "Micrel KS8737", 3317dcdecdcfSHeiner Kallweit /* PHY_BASIC_FEATURES */ 3318c6f9575cSJohan Hovold .driver_data = &ks8737_type, 331915f03ffeSFabio Estevam .probe = kszphy_probe, 3320d0507009SDavid J. Choi .config_init = kszphy_config_init, 3321c6f9575cSJohan Hovold .config_intr = kszphy_config_intr, 332259ca4e58SIoana Ciornei .handle_interrupt = kszphy_handle_interrupt, 3323f1131b9cSClaudiu Beznea .suspend = kszphy_suspend, 3324f1131b9cSClaudiu Beznea .resume = kszphy_resume, 3325d5bf9071SChristian Hohnstaedt }, { 3326212ea99aSMarek Vasut .phy_id = PHY_ID_KSZ8021, 3327212ea99aSMarek Vasut .phy_id_mask = 0x00ffffff, 33287ab59dc1SDavid J. Choi .name = "Micrel KSZ8021 or KSZ8031", 3329dcdecdcfSHeiner Kallweit /* PHY_BASIC_FEATURES */ 3330e6a423a8SJohan Hovold .driver_data = &ksz8021_type, 333163f44b2bSJohan Hovold .probe = kszphy_probe, 3332d0e1df9cSJohan Hovold .config_init = kszphy_config_init, 3333212ea99aSMarek Vasut .config_intr = kszphy_config_intr, 333459ca4e58SIoana Ciornei .handle_interrupt = kszphy_handle_interrupt, 33352b2427d0SAndrew Lunn .get_sset_count = kszphy_get_sset_count, 33362b2427d0SAndrew Lunn .get_strings = kszphy_get_strings, 33372b2427d0SAndrew Lunn .get_stats = kszphy_get_stats, 3338f1131b9cSClaudiu Beznea .suspend = kszphy_suspend, 3339f1131b9cSClaudiu Beznea .resume = kszphy_resume, 3340212ea99aSMarek Vasut }, { 3341b818d1a7SHector Palacios .phy_id = PHY_ID_KSZ8031, 3342b818d1a7SHector Palacios .phy_id_mask = 0x00ffffff, 3343b818d1a7SHector Palacios .name = "Micrel KSZ8031", 3344dcdecdcfSHeiner Kallweit /* PHY_BASIC_FEATURES */ 3345e6a423a8SJohan Hovold .driver_data = &ksz8021_type, 334663f44b2bSJohan Hovold .probe = kszphy_probe, 3347d0e1df9cSJohan Hovold .config_init = kszphy_config_init, 3348b818d1a7SHector Palacios .config_intr = kszphy_config_intr, 334959ca4e58SIoana Ciornei .handle_interrupt = kszphy_handle_interrupt, 33502b2427d0SAndrew Lunn .get_sset_count = kszphy_get_sset_count, 33512b2427d0SAndrew Lunn .get_strings = kszphy_get_strings, 33522b2427d0SAndrew Lunn .get_stats = kszphy_get_stats, 3353f1131b9cSClaudiu Beznea .suspend = kszphy_suspend, 3354f1131b9cSClaudiu Beznea .resume = kszphy_resume, 3355b818d1a7SHector Palacios }, { 3356510d573fSMarek Vasut .phy_id = PHY_ID_KSZ8041, 3357f893a99eSFabio Estevam .phy_id_mask = MICREL_PHY_ID_MASK, 3358510d573fSMarek Vasut .name = "Micrel KSZ8041", 3359dcdecdcfSHeiner Kallweit /* PHY_BASIC_FEATURES */ 3360e6a423a8SJohan Hovold .driver_data = &ksz8041_type, 3361e6a423a8SJohan Hovold .probe = kszphy_probe, 336277501a79SPhilipp Zabel .config_init = ksz8041_config_init, 336377501a79SPhilipp Zabel .config_aneg = ksz8041_config_aneg, 336451f932c4SChoi, David .config_intr = kszphy_config_intr, 336559ca4e58SIoana Ciornei .handle_interrupt = kszphy_handle_interrupt, 33662b2427d0SAndrew Lunn .get_sset_count = kszphy_get_sset_count, 33672b2427d0SAndrew Lunn .get_strings = kszphy_get_strings, 33682b2427d0SAndrew Lunn .get_stats = kszphy_get_stats, 33692641b62dSStefan Agner /* No suspend/resume callbacks because of errata DS80000700A, 33702641b62dSStefan Agner * receiver error following software power down. 33712641b62dSStefan Agner */ 3372d5bf9071SChristian Hohnstaedt }, { 33734bd7b512SSergei Shtylyov .phy_id = PHY_ID_KSZ8041RNLI, 3374f893a99eSFabio Estevam .phy_id_mask = MICREL_PHY_ID_MASK, 33754bd7b512SSergei Shtylyov .name = "Micrel KSZ8041RNLI", 3376dcdecdcfSHeiner Kallweit /* PHY_BASIC_FEATURES */ 3377e6a423a8SJohan Hovold .driver_data = &ksz8041_type, 3378e6a423a8SJohan Hovold .probe = kszphy_probe, 3379e6a423a8SJohan Hovold .config_init = kszphy_config_init, 33804bd7b512SSergei Shtylyov .config_intr = kszphy_config_intr, 338159ca4e58SIoana Ciornei .handle_interrupt = kszphy_handle_interrupt, 33822b2427d0SAndrew Lunn .get_sset_count = kszphy_get_sset_count, 33832b2427d0SAndrew Lunn .get_strings = kszphy_get_strings, 33842b2427d0SAndrew Lunn .get_stats = kszphy_get_stats, 3385f1131b9cSClaudiu Beznea .suspend = kszphy_suspend, 3386f1131b9cSClaudiu Beznea .resume = kszphy_resume, 33874bd7b512SSergei Shtylyov }, { 3388510d573fSMarek Vasut .name = "Micrel KSZ8051", 3389dcdecdcfSHeiner Kallweit /* PHY_BASIC_FEATURES */ 3390e6a423a8SJohan Hovold .driver_data = &ksz8051_type, 3391e6a423a8SJohan Hovold .probe = kszphy_probe, 339263f44b2bSJohan Hovold .config_init = kszphy_config_init, 339351f932c4SChoi, David .config_intr = kszphy_config_intr, 339459ca4e58SIoana Ciornei .handle_interrupt = kszphy_handle_interrupt, 33952b2427d0SAndrew Lunn .get_sset_count = kszphy_get_sset_count, 33962b2427d0SAndrew Lunn .get_strings = kszphy_get_strings, 33972b2427d0SAndrew Lunn .get_stats = kszphy_get_stats, 33988b95599cSMarek Vasut .match_phy_device = ksz8051_match_phy_device, 3399f1131b9cSClaudiu Beznea .suspend = kszphy_suspend, 3400f1131b9cSClaudiu Beznea .resume = kszphy_resume, 3401d5bf9071SChristian Hohnstaedt }, { 3402510d573fSMarek Vasut .phy_id = PHY_ID_KSZ8001, 3403510d573fSMarek Vasut .name = "Micrel KSZ8001 or KS8721", 3404ecd5a323SAlexander Stein .phy_id_mask = 0x00fffffc, 3405dcdecdcfSHeiner Kallweit /* PHY_BASIC_FEATURES */ 3406e6a423a8SJohan Hovold .driver_data = &ksz8041_type, 3407e6a423a8SJohan Hovold .probe = kszphy_probe, 3408e6a423a8SJohan Hovold .config_init = kszphy_config_init, 340951f932c4SChoi, David .config_intr = kszphy_config_intr, 341059ca4e58SIoana Ciornei .handle_interrupt = kszphy_handle_interrupt, 34112b2427d0SAndrew Lunn .get_sset_count = kszphy_get_sset_count, 34122b2427d0SAndrew Lunn .get_strings = kszphy_get_strings, 34132b2427d0SAndrew Lunn .get_stats = kszphy_get_stats, 3414f1131b9cSClaudiu Beznea .suspend = kszphy_suspend, 3415f1131b9cSClaudiu Beznea .resume = kszphy_resume, 3416d5bf9071SChristian Hohnstaedt }, { 34177ab59dc1SDavid J. Choi .phy_id = PHY_ID_KSZ8081, 34187ab59dc1SDavid J. Choi .name = "Micrel KSZ8081 or KSZ8091", 3419f893a99eSFabio Estevam .phy_id_mask = MICREL_PHY_ID_MASK, 342049011e0cSOleksij Rempel .flags = PHY_POLL_CABLE_TEST, 3421dcdecdcfSHeiner Kallweit /* PHY_BASIC_FEATURES */ 3422e6a423a8SJohan Hovold .driver_data = &ksz8081_type, 3423e6a423a8SJohan Hovold .probe = kszphy_probe, 34247a1d8390SAntoine Tenart .config_init = ksz8081_config_init, 3425764d31caSChristian Melki .soft_reset = genphy_soft_reset, 3426f873f112SOleksij Rempel .config_aneg = ksz8081_config_aneg, 3427f873f112SOleksij Rempel .read_status = ksz8081_read_status, 34287ab59dc1SDavid J. Choi .config_intr = kszphy_config_intr, 342959ca4e58SIoana Ciornei .handle_interrupt = kszphy_handle_interrupt, 34302b2427d0SAndrew Lunn .get_sset_count = kszphy_get_sset_count, 34312b2427d0SAndrew Lunn .get_strings = kszphy_get_strings, 34322b2427d0SAndrew Lunn .get_stats = kszphy_get_stats, 3433836384d2SWenyou Yang .suspend = kszphy_suspend, 3434f5aba91dSAlexandre Belloni .resume = kszphy_resume, 343549011e0cSOleksij Rempel .cable_test_start = ksz886x_cable_test_start, 343649011e0cSOleksij Rempel .cable_test_get_status = ksz886x_cable_test_get_status, 34377ab59dc1SDavid J. Choi }, { 34387ab59dc1SDavid J. Choi .phy_id = PHY_ID_KSZ8061, 34397ab59dc1SDavid J. Choi .name = "Micrel KSZ8061", 3440f893a99eSFabio Estevam .phy_id_mask = MICREL_PHY_ID_MASK, 3441dcdecdcfSHeiner Kallweit /* PHY_BASIC_FEATURES */ 34428e6004dfSFabio Estevam .probe = kszphy_probe, 3443232ba3a5SRajasingh Thavamani .config_init = ksz8061_config_init, 34447ab59dc1SDavid J. Choi .config_intr = kszphy_config_intr, 344559ca4e58SIoana Ciornei .handle_interrupt = kszphy_handle_interrupt, 34468e6004dfSFabio Estevam .suspend = kszphy_suspend, 34478e6004dfSFabio Estevam .resume = kszphy_resume, 34487ab59dc1SDavid J. Choi }, { 3449d0507009SDavid J. Choi .phy_id = PHY_ID_KSZ9021, 345048d7d0adSJason Wang .phy_id_mask = 0x000ffffe, 3451d0507009SDavid J. Choi .name = "Micrel KSZ9021 Gigabit PHY", 3452dcdecdcfSHeiner Kallweit /* PHY_GBIT_FEATURES */ 3453c6f9575cSJohan Hovold .driver_data = &ksz9021_type, 3454bfe72442SGrygorii Strashko .probe = kszphy_probe, 3455407d8098SHans Andersson .get_features = ksz9031_get_features, 3456954c3967SSean Cross .config_init = ksz9021_config_init, 3457c6f9575cSJohan Hovold .config_intr = kszphy_config_intr, 345859ca4e58SIoana Ciornei .handle_interrupt = kszphy_handle_interrupt, 34592b2427d0SAndrew Lunn .get_sset_count = kszphy_get_sset_count, 34602b2427d0SAndrew Lunn .get_strings = kszphy_get_strings, 34612b2427d0SAndrew Lunn .get_stats = kszphy_get_stats, 3462f1131b9cSClaudiu Beznea .suspend = kszphy_suspend, 3463f1131b9cSClaudiu Beznea .resume = kszphy_resume, 3464c846a2b7SKevin Hao .read_mmd = genphy_read_mmd_unsupported, 3465c846a2b7SKevin Hao .write_mmd = genphy_write_mmd_unsupported, 346693272e07SJean-Christophe PLAGNIOL-VILLARD }, { 34677ab59dc1SDavid J. Choi .phy_id = PHY_ID_KSZ9031, 3468f893a99eSFabio Estevam .phy_id_mask = MICREL_PHY_ID_MASK, 34697ab59dc1SDavid J. Choi .name = "Micrel KSZ9031 Gigabit PHY", 347058389c00SMarek Vasut .flags = PHY_POLL_CABLE_TEST, 3471c6f9575cSJohan Hovold .driver_data = &ksz9021_type, 3472bfe72442SGrygorii Strashko .probe = kszphy_probe, 34733aed3e2aSAntoine Tenart .get_features = ksz9031_get_features, 34746e4b8273SHubert Chaumette .config_init = ksz9031_config_init, 34751d16073aSHeiner Kallweit .soft_reset = genphy_soft_reset, 3476d2fd719bSNathan Sullivan .read_status = ksz9031_read_status, 3477c6f9575cSJohan Hovold .config_intr = kszphy_config_intr, 347859ca4e58SIoana Ciornei .handle_interrupt = kszphy_handle_interrupt, 34792b2427d0SAndrew Lunn .get_sset_count = kszphy_get_sset_count, 34802b2427d0SAndrew Lunn .get_strings = kszphy_get_strings, 34812b2427d0SAndrew Lunn .get_stats = kszphy_get_stats, 3482f1131b9cSClaudiu Beznea .suspend = kszphy_suspend, 3483f64f1482SXander Huff .resume = kszphy_resume, 348458389c00SMarek Vasut .cable_test_start = ksz9x31_cable_test_start, 348558389c00SMarek Vasut .cable_test_get_status = ksz9x31_cable_test_get_status, 34867ab59dc1SDavid J. Choi }, { 34871623ad8eSDivya Koppera .phy_id = PHY_ID_LAN8814, 34881623ad8eSDivya Koppera .phy_id_mask = MICREL_PHY_ID_MASK, 34891623ad8eSDivya Koppera .name = "Microchip INDY Gigabit Quad PHY", 349021b688daSDivya Koppera .flags = PHY_POLL_CABLE_TEST, 34917467d716SHoratiu Vultur .config_init = lan8814_config_init, 3492a516b7f7SDivya Koppera .driver_data = &lan8814_type, 3493ece19502SDivya Koppera .probe = lan8814_probe, 34941623ad8eSDivya Koppera .soft_reset = genphy_soft_reset, 3495b814403aSHoratiu Vultur .read_status = ksz9031_read_status, 34961623ad8eSDivya Koppera .get_sset_count = kszphy_get_sset_count, 34971623ad8eSDivya Koppera .get_strings = kszphy_get_strings, 34981623ad8eSDivya Koppera .get_stats = kszphy_get_stats, 34991623ad8eSDivya Koppera .suspend = genphy_suspend, 35001623ad8eSDivya Koppera .resume = kszphy_resume, 3501b3ec7248SDivya Koppera .config_intr = lan8814_config_intr, 3502b3ec7248SDivya Koppera .handle_interrupt = lan8814_handle_interrupt, 350321b688daSDivya Koppera .cable_test_start = lan8814_cable_test_start, 350421b688daSDivya Koppera .cable_test_get_status = ksz886x_cable_test_get_status, 35051623ad8eSDivya Koppera }, { 35067c2dcfa2SHoratiu Vultur .phy_id = PHY_ID_LAN8804, 35077c2dcfa2SHoratiu Vultur .phy_id_mask = MICREL_PHY_ID_MASK, 35087c2dcfa2SHoratiu Vultur .name = "Microchip LAN966X Gigabit PHY", 35097c2dcfa2SHoratiu Vultur .config_init = lan8804_config_init, 35107c2dcfa2SHoratiu Vultur .driver_data = &ksz9021_type, 35117c2dcfa2SHoratiu Vultur .probe = kszphy_probe, 35127c2dcfa2SHoratiu Vultur .soft_reset = genphy_soft_reset, 35137c2dcfa2SHoratiu Vultur .read_status = ksz9031_read_status, 35147c2dcfa2SHoratiu Vultur .get_sset_count = kszphy_get_sset_count, 35157c2dcfa2SHoratiu Vultur .get_strings = kszphy_get_strings, 35167c2dcfa2SHoratiu Vultur .get_stats = kszphy_get_stats, 35177c2dcfa2SHoratiu Vultur .suspend = genphy_suspend, 35187c2dcfa2SHoratiu Vultur .resume = kszphy_resume, 3519b324c6e5SHoratiu Vultur .config_intr = lan8804_config_intr, 3520b324c6e5SHoratiu Vultur .handle_interrupt = lan8804_handle_interrupt, 35217c2dcfa2SHoratiu Vultur }, { 3522a8f1a19dSHoratiu Vultur .phy_id = PHY_ID_LAN8841, 3523a8f1a19dSHoratiu Vultur .phy_id_mask = MICREL_PHY_ID_MASK, 3524a8f1a19dSHoratiu Vultur .name = "Microchip LAN8841 Gigabit PHY", 3525*a136391aSHoratiu Vultur .flags = PHY_POLL_CABLE_TEST, 3526a8f1a19dSHoratiu Vultur .driver_data = &lan8841_type, 3527a8f1a19dSHoratiu Vultur .config_init = lan8841_config_init, 3528a8f1a19dSHoratiu Vultur .probe = lan8841_probe, 3529a8f1a19dSHoratiu Vultur .soft_reset = genphy_soft_reset, 3530a8f1a19dSHoratiu Vultur .config_intr = lan8841_config_intr, 3531a8f1a19dSHoratiu Vultur .handle_interrupt = lan8841_handle_interrupt, 3532a8f1a19dSHoratiu Vultur .get_sset_count = kszphy_get_sset_count, 3533a8f1a19dSHoratiu Vultur .get_strings = kszphy_get_strings, 3534a8f1a19dSHoratiu Vultur .get_stats = kszphy_get_stats, 3535a8f1a19dSHoratiu Vultur .suspend = genphy_suspend, 3536a8f1a19dSHoratiu Vultur .resume = genphy_resume, 3537*a136391aSHoratiu Vultur .cable_test_start = lan8814_cable_test_start, 3538*a136391aSHoratiu Vultur .cable_test_get_status = ksz886x_cable_test_get_status, 3539a8f1a19dSHoratiu Vultur }, { 3540bff5b4b3SYuiko Oshino .phy_id = PHY_ID_KSZ9131, 3541bff5b4b3SYuiko Oshino .phy_id_mask = MICREL_PHY_ID_MASK, 3542bff5b4b3SYuiko Oshino .name = "Microchip KSZ9131 Gigabit PHY", 3543dcdecdcfSHeiner Kallweit /* PHY_GBIT_FEATURES */ 354458389c00SMarek Vasut .flags = PHY_POLL_CABLE_TEST, 3545a8f1a19dSHoratiu Vultur .driver_data = &ksz9131_type, 3546bff5b4b3SYuiko Oshino .probe = kszphy_probe, 3547bff5b4b3SYuiko Oshino .config_init = ksz9131_config_init, 3548bff5b4b3SYuiko Oshino .config_intr = kszphy_config_intr, 3549b64e6a87SRaju Lakkaraju .config_aneg = ksz9131_config_aneg, 3550b64e6a87SRaju Lakkaraju .read_status = ksz9131_read_status, 355159ca4e58SIoana Ciornei .handle_interrupt = kszphy_handle_interrupt, 3552bff5b4b3SYuiko Oshino .get_sset_count = kszphy_get_sset_count, 3553bff5b4b3SYuiko Oshino .get_strings = kszphy_get_strings, 3554bff5b4b3SYuiko Oshino .get_stats = kszphy_get_stats, 3555f1131b9cSClaudiu Beznea .suspend = kszphy_suspend, 3556bff5b4b3SYuiko Oshino .resume = kszphy_resume, 355758389c00SMarek Vasut .cable_test_start = ksz9x31_cable_test_start, 355858389c00SMarek Vasut .cable_test_get_status = ksz9x31_cable_test_get_status, 3559bff5b4b3SYuiko Oshino }, { 356093272e07SJean-Christophe PLAGNIOL-VILLARD .phy_id = PHY_ID_KSZ8873MLL, 3561f893a99eSFabio Estevam .phy_id_mask = MICREL_PHY_ID_MASK, 356293272e07SJean-Christophe PLAGNIOL-VILLARD .name = "Micrel KSZ8873MLL Switch", 3563dcdecdcfSHeiner Kallweit /* PHY_BASIC_FEATURES */ 356493272e07SJean-Christophe PLAGNIOL-VILLARD .config_init = kszphy_config_init, 356593272e07SJean-Christophe PLAGNIOL-VILLARD .config_aneg = ksz8873mll_config_aneg, 356693272e07SJean-Christophe PLAGNIOL-VILLARD .read_status = ksz8873mll_read_status, 35671a5465f5SPatrice Vilchez .suspend = genphy_suspend, 35681a5465f5SPatrice Vilchez .resume = genphy_resume, 35697ab59dc1SDavid J. Choi }, { 35707ab59dc1SDavid J. Choi .phy_id = PHY_ID_KSZ886X, 3571f893a99eSFabio Estevam .phy_id_mask = MICREL_PHY_ID_MASK, 3572ab36a3a2SMarek Vasut .name = "Micrel KSZ8851 Ethernet MAC or KSZ886X Switch", 357321b688daSDivya Koppera .driver_data = &ksz886x_type, 3574dcdecdcfSHeiner Kallweit /* PHY_BASIC_FEATURES */ 357549011e0cSOleksij Rempel .flags = PHY_POLL_CABLE_TEST, 35767ab59dc1SDavid J. Choi .config_init = kszphy_config_init, 357752939393SOleksij Rempel .config_aneg = ksz886x_config_aneg, 357852939393SOleksij Rempel .read_status = ksz886x_read_status, 35791a5465f5SPatrice Vilchez .suspend = genphy_suspend, 35801a5465f5SPatrice Vilchez .resume = genphy_resume, 358149011e0cSOleksij Rempel .cable_test_start = ksz886x_cable_test_start, 358249011e0cSOleksij Rempel .cable_test_get_status = ksz886x_cable_test_get_status, 35839d162ed6SSean Nyekjaer }, { 35841d951ba3SMarek Vasut .name = "Micrel KSZ87XX Switch", 3585dcdecdcfSHeiner Kallweit /* PHY_BASIC_FEATURES */ 35869d162ed6SSean Nyekjaer .config_init = kszphy_config_init, 35878b95599cSMarek Vasut .match_phy_device = ksz8795_match_phy_device, 35889d162ed6SSean Nyekjaer .suspend = genphy_suspend, 35899d162ed6SSean Nyekjaer .resume = genphy_resume, 3590fc3973a1SWoojung Huh }, { 3591fc3973a1SWoojung Huh .phy_id = PHY_ID_KSZ9477, 3592fc3973a1SWoojung Huh .phy_id_mask = MICREL_PHY_ID_MASK, 3593fc3973a1SWoojung Huh .name = "Microchip KSZ9477", 3594dcdecdcfSHeiner Kallweit /* PHY_GBIT_FEATURES */ 3595fc3973a1SWoojung Huh .config_init = kszphy_config_init, 3596db45c76bSArun Ramadoss .config_intr = kszphy_config_intr, 3597db45c76bSArun Ramadoss .handle_interrupt = kszphy_handle_interrupt, 3598fc3973a1SWoojung Huh .suspend = genphy_suspend, 3599fc3973a1SWoojung Huh .resume = genphy_resume, 3600d5bf9071SChristian Hohnstaedt } }; 3601d0507009SDavid J. Choi 360250fd7150SJohan Hovold module_phy_driver(ksphy_driver); 3603d0507009SDavid J. Choi 3604d0507009SDavid J. Choi MODULE_DESCRIPTION("Micrel PHY driver"); 3605d0507009SDavid J. Choi MODULE_AUTHOR("David J. Choi"); 3606d0507009SDavid J. Choi MODULE_LICENSE("GPL"); 360752a60ed2SDavid S. Miller 3608cf93c945SUwe Kleine-König static struct mdio_device_id __maybe_unused micrel_tbl[] = { 360948d7d0adSJason Wang { PHY_ID_KSZ9021, 0x000ffffe }, 3610f893a99eSFabio Estevam { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK }, 3611bff5b4b3SYuiko Oshino { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK }, 3612ecd5a323SAlexander Stein { PHY_ID_KSZ8001, 0x00fffffc }, 3613f893a99eSFabio Estevam { PHY_ID_KS8737, MICREL_PHY_ID_MASK }, 3614212ea99aSMarek Vasut { PHY_ID_KSZ8021, 0x00ffffff }, 3615b818d1a7SHector Palacios { PHY_ID_KSZ8031, 0x00ffffff }, 3616f893a99eSFabio Estevam { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK }, 3617f893a99eSFabio Estevam { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK }, 3618f893a99eSFabio Estevam { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK }, 3619f893a99eSFabio Estevam { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK }, 3620f893a99eSFabio Estevam { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK }, 3621f893a99eSFabio Estevam { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK }, 36221623ad8eSDivya Koppera { PHY_ID_LAN8814, MICREL_PHY_ID_MASK }, 36237c2dcfa2SHoratiu Vultur { PHY_ID_LAN8804, MICREL_PHY_ID_MASK }, 3624a8f1a19dSHoratiu Vultur { PHY_ID_LAN8841, MICREL_PHY_ID_MASK }, 362552a60ed2SDavid S. Miller { } 362652a60ed2SDavid S. Miller }; 362752a60ed2SDavid S. Miller 362852a60ed2SDavid S. Miller MODULE_DEVICE_TABLE(mdio, micrel_tbl); 3629