1 // SPDX-License-Identifier: GPL-2.0 2 /* Driver for the Texas Instruments DP83867 PHY 3 * 4 * Copyright (C) 2015 Texas Instruments Inc. 5 */ 6 7 #include <linux/ethtool.h> 8 #include <linux/kernel.h> 9 #include <linux/mii.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/phy.h> 13 #include <linux/delay.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/bitfield.h> 17 #include <linux/nvmem-consumer.h> 18 19 #include <dt-bindings/net/ti-dp83867.h> 20 21 #define DP83867_PHY_ID 0x2000a231 22 #define DP83867_DEVADDR 0x1f 23 24 #define MII_DP83867_PHYCTRL 0x10 25 #define MII_DP83867_PHYSTS 0x11 26 #define MII_DP83867_MICR 0x12 27 #define MII_DP83867_ISR 0x13 28 #define DP83867_CFG2 0x14 29 #define DP83867_LEDCR1 0x18 30 #define DP83867_LEDCR2 0x19 31 #define DP83867_CFG3 0x1e 32 #define DP83867_CTRL 0x1f 33 34 /* Extended Registers */ 35 #define DP83867_FLD_THR_CFG 0x002e 36 #define DP83867_CFG4 0x0031 37 #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6)) 38 #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5) 39 #define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5) 40 #define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5) 41 #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5) 42 43 #define DP83867_RGMIICTL 0x0032 44 #define DP83867_STRAP_STS1 0x006E 45 #define DP83867_STRAP_STS2 0x006f 46 #define DP83867_RGMIIDCTL 0x0086 47 #define DP83867_DSP_FFE_CFG 0x012c 48 #define DP83867_RXFCFG 0x0134 49 #define DP83867_RXFPMD1 0x0136 50 #define DP83867_RXFPMD2 0x0137 51 #define DP83867_RXFPMD3 0x0138 52 #define DP83867_RXFSOP1 0x0139 53 #define DP83867_RXFSOP2 0x013A 54 #define DP83867_RXFSOP3 0x013B 55 #define DP83867_IO_MUX_CFG 0x0170 56 #define DP83867_SGMIICTL 0x00D3 57 #define DP83867_10M_SGMII_CFG 0x016F 58 #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7) 59 60 #define DP83867_SW_RESET BIT(15) 61 #define DP83867_SW_RESTART BIT(14) 62 63 /* MICR Interrupt bits */ 64 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) 65 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) 66 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) 67 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) 68 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) 69 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) 70 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) 71 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) 72 #define MII_DP83867_MICR_WOL_INT_EN BIT(3) 73 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) 74 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) 75 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0) 76 77 /* RGMIICTL bits */ 78 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) 79 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) 80 81 /* SGMIICTL bits */ 82 #define DP83867_SGMII_TYPE BIT(14) 83 84 /* RXFCFG bits*/ 85 #define DP83867_WOL_MAGIC_EN BIT(0) 86 #define DP83867_WOL_BCAST_EN BIT(2) 87 #define DP83867_WOL_UCAST_EN BIT(4) 88 #define DP83867_WOL_SEC_EN BIT(5) 89 #define DP83867_WOL_ENH_MAC BIT(7) 90 91 /* STRAP_STS1 bits */ 92 #define DP83867_STRAP_STS1_RESERVED BIT(11) 93 94 /* STRAP_STS2 bits */ 95 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4) 96 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4 97 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0) 98 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0 99 #define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2) 100 #define DP83867_STRAP_STS2_STRAP_FLD BIT(10) 101 102 /* PHY CTRL bits */ 103 #define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT 14 104 #define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT 12 105 #define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03 106 #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14) 107 #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12) 108 #define DP83867_PHYCR_RESERVED_MASK BIT(11) 109 #define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10) 110 111 /* RGMIIDCTL bits */ 112 #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf 113 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 114 #define DP83867_RGMII_TX_CLK_DELAY_INV (DP83867_RGMII_TX_CLK_DELAY_MAX + 1) 115 #define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf 116 #define DP83867_RGMII_RX_CLK_DELAY_SHIFT 0 117 #define DP83867_RGMII_RX_CLK_DELAY_INV (DP83867_RGMII_RX_CLK_DELAY_MAX + 1) 118 119 /* IO_MUX_CFG bits */ 120 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK 0x1f 121 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 122 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f 123 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6) 124 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8) 125 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 126 127 /* PHY STS bits */ 128 #define DP83867_PHYSTS_1000 BIT(15) 129 #define DP83867_PHYSTS_100 BIT(14) 130 #define DP83867_PHYSTS_DUPLEX BIT(13) 131 #define DP83867_PHYSTS_LINK BIT(10) 132 133 /* CFG2 bits */ 134 #define DP83867_DOWNSHIFT_EN (BIT(8) | BIT(9)) 135 #define DP83867_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11)) 136 #define DP83867_DOWNSHIFT_1_COUNT_VAL 0 137 #define DP83867_DOWNSHIFT_2_COUNT_VAL 1 138 #define DP83867_DOWNSHIFT_4_COUNT_VAL 2 139 #define DP83867_DOWNSHIFT_8_COUNT_VAL 3 140 #define DP83867_DOWNSHIFT_1_COUNT 1 141 #define DP83867_DOWNSHIFT_2_COUNT 2 142 #define DP83867_DOWNSHIFT_4_COUNT 4 143 #define DP83867_DOWNSHIFT_8_COUNT 8 144 #define DP83867_SGMII_AUTONEG_EN BIT(7) 145 146 /* CFG3 bits */ 147 #define DP83867_CFG3_INT_OE BIT(7) 148 #define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9) 149 150 /* CFG4 bits */ 151 #define DP83867_CFG4_PORT_MIRROR_EN BIT(0) 152 153 /* FLD_THR_CFG */ 154 #define DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK 0x7 155 156 #define DP83867_LED_COUNT 4 157 158 /* LED_DRV bits */ 159 #define DP83867_LED_DRV_EN(x) BIT((x) * 4) 160 #define DP83867_LED_DRV_VAL(x) BIT((x) * 4 + 1) 161 162 enum { 163 DP83867_PORT_MIRROING_KEEP, 164 DP83867_PORT_MIRROING_EN, 165 DP83867_PORT_MIRROING_DIS, 166 }; 167 168 struct dp83867_private { 169 u32 rx_id_delay; 170 u32 tx_id_delay; 171 u32 tx_fifo_depth; 172 u32 rx_fifo_depth; 173 int io_impedance; 174 int port_mirroring; 175 bool rxctrl_strap_quirk; 176 bool set_clk_output; 177 u32 clk_output_sel; 178 bool sgmii_ref_clk_en; 179 }; 180 181 static int dp83867_ack_interrupt(struct phy_device *phydev) 182 { 183 int err = phy_read(phydev, MII_DP83867_ISR); 184 185 if (err < 0) 186 return err; 187 188 return 0; 189 } 190 191 static int dp83867_set_wol(struct phy_device *phydev, 192 struct ethtool_wolinfo *wol) 193 { 194 struct net_device *ndev = phydev->attached_dev; 195 u16 val_rxcfg, val_micr; 196 const u8 *mac; 197 198 val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG); 199 val_micr = phy_read(phydev, MII_DP83867_MICR); 200 201 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | 202 WAKE_BCAST)) { 203 val_rxcfg |= DP83867_WOL_ENH_MAC; 204 val_micr |= MII_DP83867_MICR_WOL_INT_EN; 205 206 if (wol->wolopts & WAKE_MAGIC) { 207 mac = (const u8 *)ndev->dev_addr; 208 209 if (!is_valid_ether_addr(mac)) 210 return -EINVAL; 211 212 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1, 213 (mac[1] << 8 | mac[0])); 214 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2, 215 (mac[3] << 8 | mac[2])); 216 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3, 217 (mac[5] << 8 | mac[4])); 218 219 val_rxcfg |= DP83867_WOL_MAGIC_EN; 220 } else { 221 val_rxcfg &= ~DP83867_WOL_MAGIC_EN; 222 } 223 224 if (wol->wolopts & WAKE_MAGICSECURE) { 225 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1, 226 (wol->sopass[1] << 8) | wol->sopass[0]); 227 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2, 228 (wol->sopass[3] << 8) | wol->sopass[2]); 229 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3, 230 (wol->sopass[5] << 8) | wol->sopass[4]); 231 232 val_rxcfg |= DP83867_WOL_SEC_EN; 233 } else { 234 val_rxcfg &= ~DP83867_WOL_SEC_EN; 235 } 236 237 if (wol->wolopts & WAKE_UCAST) 238 val_rxcfg |= DP83867_WOL_UCAST_EN; 239 else 240 val_rxcfg &= ~DP83867_WOL_UCAST_EN; 241 242 if (wol->wolopts & WAKE_BCAST) 243 val_rxcfg |= DP83867_WOL_BCAST_EN; 244 else 245 val_rxcfg &= ~DP83867_WOL_BCAST_EN; 246 } else { 247 val_rxcfg &= ~DP83867_WOL_ENH_MAC; 248 val_micr &= ~MII_DP83867_MICR_WOL_INT_EN; 249 } 250 251 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg); 252 phy_write(phydev, MII_DP83867_MICR, val_micr); 253 254 return 0; 255 } 256 257 static void dp83867_get_wol(struct phy_device *phydev, 258 struct ethtool_wolinfo *wol) 259 { 260 u16 value, sopass_val; 261 262 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC | 263 WAKE_MAGICSECURE); 264 wol->wolopts = 0; 265 266 value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG); 267 268 if (value & DP83867_WOL_UCAST_EN) 269 wol->wolopts |= WAKE_UCAST; 270 271 if (value & DP83867_WOL_BCAST_EN) 272 wol->wolopts |= WAKE_BCAST; 273 274 if (value & DP83867_WOL_MAGIC_EN) 275 wol->wolopts |= WAKE_MAGIC; 276 277 if (value & DP83867_WOL_SEC_EN) { 278 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR, 279 DP83867_RXFSOP1); 280 wol->sopass[0] = (sopass_val & 0xff); 281 wol->sopass[1] = (sopass_val >> 8); 282 283 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR, 284 DP83867_RXFSOP2); 285 wol->sopass[2] = (sopass_val & 0xff); 286 wol->sopass[3] = (sopass_val >> 8); 287 288 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR, 289 DP83867_RXFSOP3); 290 wol->sopass[4] = (sopass_val & 0xff); 291 wol->sopass[5] = (sopass_val >> 8); 292 293 wol->wolopts |= WAKE_MAGICSECURE; 294 } 295 296 if (!(value & DP83867_WOL_ENH_MAC)) 297 wol->wolopts = 0; 298 } 299 300 static int dp83867_config_intr(struct phy_device *phydev) 301 { 302 int micr_status, err; 303 304 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 305 err = dp83867_ack_interrupt(phydev); 306 if (err) 307 return err; 308 309 micr_status = phy_read(phydev, MII_DP83867_MICR); 310 if (micr_status < 0) 311 return micr_status; 312 313 micr_status |= 314 (MII_DP83867_MICR_AN_ERR_INT_EN | 315 MII_DP83867_MICR_SPEED_CHNG_INT_EN | 316 MII_DP83867_MICR_AUTONEG_COMP_INT_EN | 317 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN | 318 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN | 319 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN); 320 321 err = phy_write(phydev, MII_DP83867_MICR, micr_status); 322 } else { 323 micr_status = 0x0; 324 err = phy_write(phydev, MII_DP83867_MICR, micr_status); 325 if (err) 326 return err; 327 328 err = dp83867_ack_interrupt(phydev); 329 } 330 331 return err; 332 } 333 334 static irqreturn_t dp83867_handle_interrupt(struct phy_device *phydev) 335 { 336 int irq_status, irq_enabled; 337 338 irq_status = phy_read(phydev, MII_DP83867_ISR); 339 if (irq_status < 0) { 340 phy_error(phydev); 341 return IRQ_NONE; 342 } 343 344 irq_enabled = phy_read(phydev, MII_DP83867_MICR); 345 if (irq_enabled < 0) { 346 phy_error(phydev); 347 return IRQ_NONE; 348 } 349 350 if (!(irq_status & irq_enabled)) 351 return IRQ_NONE; 352 353 phy_trigger_machine(phydev); 354 355 return IRQ_HANDLED; 356 } 357 358 static int dp83867_read_status(struct phy_device *phydev) 359 { 360 int status = phy_read(phydev, MII_DP83867_PHYSTS); 361 int ret; 362 363 ret = genphy_read_status(phydev); 364 if (ret) 365 return ret; 366 367 if (status < 0) 368 return status; 369 370 if (status & DP83867_PHYSTS_DUPLEX) 371 phydev->duplex = DUPLEX_FULL; 372 else 373 phydev->duplex = DUPLEX_HALF; 374 375 if (status & DP83867_PHYSTS_1000) 376 phydev->speed = SPEED_1000; 377 else if (status & DP83867_PHYSTS_100) 378 phydev->speed = SPEED_100; 379 else 380 phydev->speed = SPEED_10; 381 382 return 0; 383 } 384 385 static int dp83867_get_downshift(struct phy_device *phydev, u8 *data) 386 { 387 int val, cnt, enable, count; 388 389 val = phy_read(phydev, DP83867_CFG2); 390 if (val < 0) 391 return val; 392 393 enable = FIELD_GET(DP83867_DOWNSHIFT_EN, val); 394 cnt = FIELD_GET(DP83867_DOWNSHIFT_ATTEMPT_MASK, val); 395 396 switch (cnt) { 397 case DP83867_DOWNSHIFT_1_COUNT_VAL: 398 count = DP83867_DOWNSHIFT_1_COUNT; 399 break; 400 case DP83867_DOWNSHIFT_2_COUNT_VAL: 401 count = DP83867_DOWNSHIFT_2_COUNT; 402 break; 403 case DP83867_DOWNSHIFT_4_COUNT_VAL: 404 count = DP83867_DOWNSHIFT_4_COUNT; 405 break; 406 case DP83867_DOWNSHIFT_8_COUNT_VAL: 407 count = DP83867_DOWNSHIFT_8_COUNT; 408 break; 409 default: 410 return -EINVAL; 411 } 412 413 *data = enable ? count : DOWNSHIFT_DEV_DISABLE; 414 415 return 0; 416 } 417 418 static int dp83867_set_downshift(struct phy_device *phydev, u8 cnt) 419 { 420 int val, count; 421 422 if (cnt > DP83867_DOWNSHIFT_8_COUNT) 423 return -E2BIG; 424 425 if (!cnt) 426 return phy_clear_bits(phydev, DP83867_CFG2, 427 DP83867_DOWNSHIFT_EN); 428 429 switch (cnt) { 430 case DP83867_DOWNSHIFT_1_COUNT: 431 count = DP83867_DOWNSHIFT_1_COUNT_VAL; 432 break; 433 case DP83867_DOWNSHIFT_2_COUNT: 434 count = DP83867_DOWNSHIFT_2_COUNT_VAL; 435 break; 436 case DP83867_DOWNSHIFT_4_COUNT: 437 count = DP83867_DOWNSHIFT_4_COUNT_VAL; 438 break; 439 case DP83867_DOWNSHIFT_8_COUNT: 440 count = DP83867_DOWNSHIFT_8_COUNT_VAL; 441 break; 442 default: 443 phydev_err(phydev, 444 "Downshift count must be 1, 2, 4 or 8\n"); 445 return -EINVAL; 446 } 447 448 val = DP83867_DOWNSHIFT_EN; 449 val |= FIELD_PREP(DP83867_DOWNSHIFT_ATTEMPT_MASK, count); 450 451 return phy_modify(phydev, DP83867_CFG2, 452 DP83867_DOWNSHIFT_EN | DP83867_DOWNSHIFT_ATTEMPT_MASK, 453 val); 454 } 455 456 static int dp83867_get_tunable(struct phy_device *phydev, 457 struct ethtool_tunable *tuna, void *data) 458 { 459 switch (tuna->id) { 460 case ETHTOOL_PHY_DOWNSHIFT: 461 return dp83867_get_downshift(phydev, data); 462 default: 463 return -EOPNOTSUPP; 464 } 465 } 466 467 static int dp83867_set_tunable(struct phy_device *phydev, 468 struct ethtool_tunable *tuna, const void *data) 469 { 470 switch (tuna->id) { 471 case ETHTOOL_PHY_DOWNSHIFT: 472 return dp83867_set_downshift(phydev, *(const u8 *)data); 473 default: 474 return -EOPNOTSUPP; 475 } 476 } 477 478 static int dp83867_config_port_mirroring(struct phy_device *phydev) 479 { 480 struct dp83867_private *dp83867 = phydev->priv; 481 482 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN) 483 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 484 DP83867_CFG4_PORT_MIRROR_EN); 485 else 486 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 487 DP83867_CFG4_PORT_MIRROR_EN); 488 return 0; 489 } 490 491 static int dp83867_verify_rgmii_cfg(struct phy_device *phydev) 492 { 493 struct dp83867_private *dp83867 = phydev->priv; 494 495 /* Existing behavior was to use default pin strapping delay in rgmii 496 * mode, but rgmii should have meant no delay. Warn existing users. 497 */ 498 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { 499 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR, 500 DP83867_STRAP_STS2); 501 const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >> 502 DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT; 503 const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >> 504 DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT; 505 506 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE || 507 rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE) 508 phydev_warn(phydev, 509 "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n" 510 "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n", 511 txskew, rxskew); 512 } 513 514 /* RX delay *must* be specified if internal delay of RX is used. */ 515 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 516 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) && 517 dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) { 518 phydev_err(phydev, "ti,rx-internal-delay must be specified\n"); 519 return -EINVAL; 520 } 521 522 /* TX delay *must* be specified if internal delay of TX is used. */ 523 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 524 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) && 525 dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) { 526 phydev_err(phydev, "ti,tx-internal-delay must be specified\n"); 527 return -EINVAL; 528 } 529 530 return 0; 531 } 532 533 #if IS_ENABLED(CONFIG_OF_MDIO) 534 static int dp83867_of_init_io_impedance(struct phy_device *phydev) 535 { 536 struct dp83867_private *dp83867 = phydev->priv; 537 struct device *dev = &phydev->mdio.dev; 538 struct device_node *of_node = dev->of_node; 539 struct nvmem_cell *cell; 540 u8 *buf, val; 541 int ret; 542 543 cell = of_nvmem_cell_get(of_node, "io_impedance_ctrl"); 544 if (IS_ERR(cell)) { 545 ret = PTR_ERR(cell); 546 if (ret != -ENOENT && ret != -EOPNOTSUPP) 547 return phydev_err_probe(phydev, ret, 548 "failed to get nvmem cell io_impedance_ctrl\n"); 549 550 /* If no nvmem cell, check for the boolean properties. */ 551 if (of_property_read_bool(of_node, "ti,max-output-impedance")) 552 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX; 553 else if (of_property_read_bool(of_node, "ti,min-output-impedance")) 554 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN; 555 else 556 dp83867->io_impedance = -1; /* leave at default */ 557 558 return 0; 559 } 560 561 buf = nvmem_cell_read(cell, NULL); 562 nvmem_cell_put(cell); 563 564 if (IS_ERR(buf)) 565 return PTR_ERR(buf); 566 567 val = *buf; 568 kfree(buf); 569 570 if ((val & DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK) != val) { 571 phydev_err(phydev, "nvmem cell 'io_impedance_ctrl' contents out of range\n"); 572 return -ERANGE; 573 } 574 dp83867->io_impedance = val; 575 576 return 0; 577 } 578 579 static int dp83867_of_init(struct phy_device *phydev) 580 { 581 struct dp83867_private *dp83867 = phydev->priv; 582 struct device *dev = &phydev->mdio.dev; 583 struct device_node *of_node = dev->of_node; 584 int ret; 585 586 if (!of_node) 587 return -ENODEV; 588 589 /* Optional configuration */ 590 ret = of_property_read_u32(of_node, "ti,clk-output-sel", 591 &dp83867->clk_output_sel); 592 /* If not set, keep default */ 593 if (!ret) { 594 dp83867->set_clk_output = true; 595 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or 596 * DP83867_CLK_O_SEL_OFF. 597 */ 598 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK && 599 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) { 600 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n", 601 dp83867->clk_output_sel); 602 return -EINVAL; 603 } 604 } 605 606 ret = dp83867_of_init_io_impedance(phydev); 607 if (ret) 608 return ret; 609 610 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node, 611 "ti,dp83867-rxctrl-strap-quirk"); 612 613 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node, 614 "ti,sgmii-ref-clock-output-enable"); 615 616 dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV; 617 ret = of_property_read_u32(of_node, "ti,rx-internal-delay", 618 &dp83867->rx_id_delay); 619 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) { 620 phydev_err(phydev, 621 "ti,rx-internal-delay value of %u out of range\n", 622 dp83867->rx_id_delay); 623 return -EINVAL; 624 } 625 626 dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV; 627 ret = of_property_read_u32(of_node, "ti,tx-internal-delay", 628 &dp83867->tx_id_delay); 629 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) { 630 phydev_err(phydev, 631 "ti,tx-internal-delay value of %u out of range\n", 632 dp83867->tx_id_delay); 633 return -EINVAL; 634 } 635 636 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) 637 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN; 638 639 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap")) 640 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS; 641 642 ret = of_property_read_u32(of_node, "ti,fifo-depth", 643 &dp83867->tx_fifo_depth); 644 if (ret) { 645 ret = of_property_read_u32(of_node, "tx-fifo-depth", 646 &dp83867->tx_fifo_depth); 647 if (ret) 648 dp83867->tx_fifo_depth = 649 DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; 650 } 651 652 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { 653 phydev_err(phydev, "tx-fifo-depth value %u out of range\n", 654 dp83867->tx_fifo_depth); 655 return -EINVAL; 656 } 657 658 ret = of_property_read_u32(of_node, "rx-fifo-depth", 659 &dp83867->rx_fifo_depth); 660 if (ret) 661 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; 662 663 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { 664 phydev_err(phydev, "rx-fifo-depth value %u out of range\n", 665 dp83867->rx_fifo_depth); 666 return -EINVAL; 667 } 668 669 return 0; 670 } 671 #else 672 static int dp83867_of_init(struct phy_device *phydev) 673 { 674 struct dp83867_private *dp83867 = phydev->priv; 675 u16 delay; 676 677 /* For non-OF device, the RX and TX ID values are either strapped 678 * or take from default value. So, we init RX & TX ID values here 679 * so that the RGMIIDCTL is configured correctly later in 680 * dp83867_config_init(); 681 */ 682 delay = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL); 683 dp83867->rx_id_delay = delay & DP83867_RGMII_RX_CLK_DELAY_MAX; 684 dp83867->tx_id_delay = (delay >> DP83867_RGMII_TX_CLK_DELAY_SHIFT) & 685 DP83867_RGMII_TX_CLK_DELAY_MAX; 686 687 /* Per datasheet, IO impedance is default to 50-ohm, so we set the 688 * same here or else the default '0' means highest IO impedance 689 * which is wrong. 690 */ 691 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN / 2; 692 693 /* For non-OF device, the RX and TX FIFO depths are taken from 694 * default value. So, we init RX & TX FIFO depths here 695 * so that it is configured correctly later in dp83867_config_init(); 696 */ 697 dp83867->tx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; 698 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; 699 700 return 0; 701 } 702 #endif /* CONFIG_OF_MDIO */ 703 704 static int dp83867_suspend(struct phy_device *phydev) 705 { 706 /* Disable PHY Interrupts */ 707 if (phy_interrupt_is_valid(phydev)) { 708 phydev->interrupts = PHY_INTERRUPT_DISABLED; 709 dp83867_config_intr(phydev); 710 } 711 712 return genphy_suspend(phydev); 713 } 714 715 static int dp83867_resume(struct phy_device *phydev) 716 { 717 /* Enable PHY Interrupts */ 718 if (phy_interrupt_is_valid(phydev)) { 719 phydev->interrupts = PHY_INTERRUPT_ENABLED; 720 dp83867_config_intr(phydev); 721 } 722 723 genphy_resume(phydev); 724 725 return 0; 726 } 727 728 static int dp83867_probe(struct phy_device *phydev) 729 { 730 struct dp83867_private *dp83867; 731 732 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867), 733 GFP_KERNEL); 734 if (!dp83867) 735 return -ENOMEM; 736 737 phydev->priv = dp83867; 738 739 return dp83867_of_init(phydev); 740 } 741 742 static int dp83867_config_init(struct phy_device *phydev) 743 { 744 struct dp83867_private *dp83867 = phydev->priv; 745 int ret, val, bs; 746 u16 delay; 747 748 /* Force speed optimization for the PHY even if it strapped */ 749 ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN, 750 DP83867_DOWNSHIFT_EN); 751 if (ret) 752 return ret; 753 754 ret = dp83867_verify_rgmii_cfg(phydev); 755 if (ret) 756 return ret; 757 758 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */ 759 if (dp83867->rxctrl_strap_quirk) 760 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 761 BIT(7)); 762 763 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2); 764 if (bs & DP83867_STRAP_STS2_STRAP_FLD) { 765 /* When using strap to enable FLD, the ENERGY_LOST_FLD_THR will 766 * be set to 0x2. This may causes the PHY link to be unstable - 767 * the default value 0x1 need to be restored. 768 */ 769 ret = phy_modify_mmd(phydev, DP83867_DEVADDR, 770 DP83867_FLD_THR_CFG, 771 DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK, 772 0x1); 773 if (ret) 774 return ret; 775 } 776 777 if (phy_interface_is_rgmii(phydev) || 778 phydev->interface == PHY_INTERFACE_MODE_SGMII) { 779 val = phy_read(phydev, MII_DP83867_PHYCTRL); 780 if (val < 0) 781 return val; 782 783 val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK; 784 val |= (dp83867->tx_fifo_depth << 785 DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT); 786 787 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 788 val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK; 789 val |= (dp83867->rx_fifo_depth << 790 DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT); 791 } 792 793 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); 794 if (ret) 795 return ret; 796 } 797 798 if (phy_interface_is_rgmii(phydev)) { 799 val = phy_read(phydev, MII_DP83867_PHYCTRL); 800 if (val < 0) 801 return val; 802 803 /* The code below checks if "port mirroring" N/A MODE4 has been 804 * enabled during power on bootstrap. 805 * 806 * Such N/A mode enabled by mistake can put PHY IC in some 807 * internal testing mode and disable RGMII transmission. 808 * 809 * In this particular case one needs to check STRAP_STS1 810 * register's bit 11 (marked as RESERVED). 811 */ 812 813 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1); 814 if (bs & DP83867_STRAP_STS1_RESERVED) 815 val &= ~DP83867_PHYCR_RESERVED_MASK; 816 817 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); 818 if (ret) 819 return ret; 820 821 /* If rgmii mode with no internal delay is selected, we do NOT use 822 * aligned mode as one might expect. Instead we use the PHY's default 823 * based on pin strapping. And the "mode 0" default is to *use* 824 * internal delay with a value of 7 (2.00 ns). 825 * 826 * Set up RGMII delays 827 */ 828 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL); 829 830 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); 831 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 832 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); 833 834 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 835 val |= DP83867_RGMII_TX_CLK_DELAY_EN; 836 837 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 838 val |= DP83867_RGMII_RX_CLK_DELAY_EN; 839 840 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val); 841 842 delay = 0; 843 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV) 844 delay |= dp83867->rx_id_delay; 845 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV) 846 delay |= dp83867->tx_id_delay << 847 DP83867_RGMII_TX_CLK_DELAY_SHIFT; 848 849 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL, 850 delay); 851 } 852 853 /* If specified, set io impedance */ 854 if (dp83867->io_impedance >= 0) 855 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, 856 DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK, 857 dp83867->io_impedance); 858 859 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 860 /* For support SPEED_10 in SGMII mode 861 * DP83867_10M_SGMII_RATE_ADAPT bit 862 * has to be cleared by software. That 863 * does not affect SPEED_100 and 864 * SPEED_1000. 865 */ 866 ret = phy_modify_mmd(phydev, DP83867_DEVADDR, 867 DP83867_10M_SGMII_CFG, 868 DP83867_10M_SGMII_RATE_ADAPT_MASK, 869 0); 870 if (ret) 871 return ret; 872 873 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5 874 * are 01). That is not enough to finalize autoneg on some 875 * devices. Increase this timer duration to maximum 16ms. 876 */ 877 ret = phy_modify_mmd(phydev, DP83867_DEVADDR, 878 DP83867_CFG4, 879 DP83867_CFG4_SGMII_ANEG_MASK, 880 DP83867_CFG4_SGMII_ANEG_TIMER_16MS); 881 882 if (ret) 883 return ret; 884 885 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL); 886 /* SGMII type is set to 4-wire mode by default. 887 * If we place appropriate property in dts (see above) 888 * switch on 6-wire mode. 889 */ 890 if (dp83867->sgmii_ref_clk_en) 891 val |= DP83867_SGMII_TYPE; 892 else 893 val &= ~DP83867_SGMII_TYPE; 894 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val); 895 896 /* This is a SW workaround for link instability if RX_CTRL is 897 * not strapped to mode 3 or 4 in HW. This is required for SGMII 898 * in addition to clearing bit 7, handled above. 899 */ 900 if (dp83867->rxctrl_strap_quirk) 901 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 902 BIT(8)); 903 } 904 905 val = phy_read(phydev, DP83867_CFG3); 906 /* Enable Interrupt output INT_OE in CFG3 register */ 907 if (phy_interrupt_is_valid(phydev)) 908 val |= DP83867_CFG3_INT_OE; 909 910 val |= DP83867_CFG3_ROBUST_AUTO_MDIX; 911 phy_write(phydev, DP83867_CFG3, val); 912 913 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP) 914 dp83867_config_port_mirroring(phydev); 915 916 /* Clock output selection if muxing property is set */ 917 if (dp83867->set_clk_output) { 918 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE; 919 920 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) { 921 val = DP83867_IO_MUX_CFG_CLK_O_DISABLE; 922 } else { 923 mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK; 924 val = dp83867->clk_output_sel << 925 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT; 926 } 927 928 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, 929 mask, val); 930 } 931 932 return 0; 933 } 934 935 static int dp83867_phy_reset(struct phy_device *phydev) 936 { 937 int err; 938 939 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET); 940 if (err < 0) 941 return err; 942 943 usleep_range(10, 20); 944 945 err = phy_modify(phydev, MII_DP83867_PHYCTRL, 946 DP83867_PHYCR_FORCE_LINK_GOOD, 0); 947 if (err < 0) 948 return err; 949 950 /* Configure the DSP Feedforward Equalizer Configuration register to 951 * improve short cable (< 1 meter) performance. This will not affect 952 * long cable performance. 953 */ 954 err = phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_DSP_FFE_CFG, 955 0x0e81); 956 if (err < 0) 957 return err; 958 959 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART); 960 if (err < 0) 961 return err; 962 963 usleep_range(10, 20); 964 965 return 0; 966 } 967 968 static void dp83867_link_change_notify(struct phy_device *phydev) 969 { 970 /* There is a limitation in DP83867 PHY device where SGMII AN is 971 * only triggered once after the device is booted up. Even after the 972 * PHY TPI is down and up again, SGMII AN is not triggered and 973 * hence no new in-band message from PHY to MAC side SGMII. 974 * This could cause an issue during power up, when PHY is up prior 975 * to MAC. At this condition, once MAC side SGMII is up, MAC side 976 * SGMII wouldn`t receive new in-band message from TI PHY with 977 * correct link status, speed and duplex info. 978 * Thus, implemented a SW solution here to retrigger SGMII Auto-Neg 979 * whenever there is a link change. 980 */ 981 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 982 int val = 0; 983 984 val = phy_clear_bits(phydev, DP83867_CFG2, 985 DP83867_SGMII_AUTONEG_EN); 986 if (val < 0) 987 return; 988 989 phy_set_bits(phydev, DP83867_CFG2, 990 DP83867_SGMII_AUTONEG_EN); 991 } 992 } 993 994 static int dp83867_loopback(struct phy_device *phydev, bool enable) 995 { 996 return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, 997 enable ? BMCR_LOOPBACK : 0); 998 } 999 1000 static int 1001 dp83867_led_brightness_set(struct phy_device *phydev, 1002 u8 index, enum led_brightness brightness) 1003 { 1004 u32 val; 1005 1006 if (index >= DP83867_LED_COUNT) 1007 return -EINVAL; 1008 1009 /* DRV_EN==1: output is DRV_VAL */ 1010 val = DP83867_LED_DRV_EN(index); 1011 1012 if (brightness) 1013 val |= DP83867_LED_DRV_VAL(index); 1014 1015 return phy_modify(phydev, DP83867_LEDCR2, 1016 DP83867_LED_DRV_VAL(index) | 1017 DP83867_LED_DRV_EN(index), 1018 val); 1019 } 1020 1021 static struct phy_driver dp83867_driver[] = { 1022 { 1023 .phy_id = DP83867_PHY_ID, 1024 .phy_id_mask = 0xfffffff0, 1025 .name = "TI DP83867", 1026 /* PHY_GBIT_FEATURES */ 1027 1028 .probe = dp83867_probe, 1029 .config_init = dp83867_config_init, 1030 .soft_reset = dp83867_phy_reset, 1031 1032 .read_status = dp83867_read_status, 1033 .get_tunable = dp83867_get_tunable, 1034 .set_tunable = dp83867_set_tunable, 1035 1036 .get_wol = dp83867_get_wol, 1037 .set_wol = dp83867_set_wol, 1038 1039 /* IRQ related */ 1040 .config_intr = dp83867_config_intr, 1041 .handle_interrupt = dp83867_handle_interrupt, 1042 1043 .suspend = dp83867_suspend, 1044 .resume = dp83867_resume, 1045 1046 .link_change_notify = dp83867_link_change_notify, 1047 .set_loopback = dp83867_loopback, 1048 1049 .led_brightness_set = dp83867_led_brightness_set, 1050 }, 1051 }; 1052 module_phy_driver(dp83867_driver); 1053 1054 static struct mdio_device_id __maybe_unused dp83867_tbl[] = { 1055 { DP83867_PHY_ID, 0xfffffff0 }, 1056 { } 1057 }; 1058 1059 MODULE_DEVICE_TABLE(mdio, dp83867_tbl); 1060 1061 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver"); 1062 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 1063 MODULE_LICENSE("GPL v2"); 1064