1 // SPDX-License-Identifier: GPL-2.0 2 /* Driver for the Texas Instruments DP83867 PHY 3 * 4 * Copyright (C) 2015 Texas Instruments Inc. 5 */ 6 7 #include <linux/ethtool.h> 8 #include <linux/kernel.h> 9 #include <linux/mii.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/phy.h> 13 #include <linux/delay.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/bitfield.h> 17 #include <linux/nvmem-consumer.h> 18 19 #include <dt-bindings/net/ti-dp83867.h> 20 21 #define DP83867_PHY_ID 0x2000a231 22 #define DP83867_DEVADDR 0x1f 23 24 #define MII_DP83867_PHYCTRL 0x10 25 #define MII_DP83867_PHYSTS 0x11 26 #define MII_DP83867_MICR 0x12 27 #define MII_DP83867_ISR 0x13 28 #define DP83867_CFG2 0x14 29 #define DP83867_LEDCR1 0x18 30 #define DP83867_LEDCR2 0x19 31 #define DP83867_CFG3 0x1e 32 #define DP83867_CTRL 0x1f 33 34 /* Extended Registers */ 35 #define DP83867_FLD_THR_CFG 0x002e 36 #define DP83867_CFG4 0x0031 37 #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6)) 38 #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5) 39 #define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5) 40 #define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5) 41 #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5) 42 43 #define DP83867_RGMIICTL 0x0032 44 #define DP83867_STRAP_STS1 0x006E 45 #define DP83867_STRAP_STS2 0x006f 46 #define DP83867_RGMIIDCTL 0x0086 47 #define DP83867_RXFCFG 0x0134 48 #define DP83867_RXFPMD1 0x0136 49 #define DP83867_RXFPMD2 0x0137 50 #define DP83867_RXFPMD3 0x0138 51 #define DP83867_RXFSOP1 0x0139 52 #define DP83867_RXFSOP2 0x013A 53 #define DP83867_RXFSOP3 0x013B 54 #define DP83867_IO_MUX_CFG 0x0170 55 #define DP83867_SGMIICTL 0x00D3 56 #define DP83867_10M_SGMII_CFG 0x016F 57 #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7) 58 59 #define DP83867_SW_RESET BIT(15) 60 #define DP83867_SW_RESTART BIT(14) 61 62 /* MICR Interrupt bits */ 63 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) 64 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) 65 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) 66 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) 67 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) 68 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) 69 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) 70 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) 71 #define MII_DP83867_MICR_WOL_INT_EN BIT(3) 72 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) 73 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) 74 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0) 75 76 /* RGMIICTL bits */ 77 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) 78 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) 79 80 /* SGMIICTL bits */ 81 #define DP83867_SGMII_TYPE BIT(14) 82 83 /* RXFCFG bits*/ 84 #define DP83867_WOL_MAGIC_EN BIT(0) 85 #define DP83867_WOL_BCAST_EN BIT(2) 86 #define DP83867_WOL_UCAST_EN BIT(4) 87 #define DP83867_WOL_SEC_EN BIT(5) 88 #define DP83867_WOL_ENH_MAC BIT(7) 89 90 /* STRAP_STS1 bits */ 91 #define DP83867_STRAP_STS1_RESERVED BIT(11) 92 93 /* STRAP_STS2 bits */ 94 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4) 95 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4 96 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0) 97 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0 98 #define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2) 99 #define DP83867_STRAP_STS2_STRAP_FLD BIT(10) 100 101 /* PHY CTRL bits */ 102 #define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT 14 103 #define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT 12 104 #define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03 105 #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14) 106 #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12) 107 #define DP83867_PHYCR_RESERVED_MASK BIT(11) 108 #define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10) 109 110 /* RGMIIDCTL bits */ 111 #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf 112 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 113 #define DP83867_RGMII_TX_CLK_DELAY_INV (DP83867_RGMII_TX_CLK_DELAY_MAX + 1) 114 #define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf 115 #define DP83867_RGMII_RX_CLK_DELAY_SHIFT 0 116 #define DP83867_RGMII_RX_CLK_DELAY_INV (DP83867_RGMII_RX_CLK_DELAY_MAX + 1) 117 118 /* IO_MUX_CFG bits */ 119 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK 0x1f 120 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 121 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f 122 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6) 123 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8) 124 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 125 126 /* PHY STS bits */ 127 #define DP83867_PHYSTS_1000 BIT(15) 128 #define DP83867_PHYSTS_100 BIT(14) 129 #define DP83867_PHYSTS_DUPLEX BIT(13) 130 #define DP83867_PHYSTS_LINK BIT(10) 131 132 /* CFG2 bits */ 133 #define DP83867_DOWNSHIFT_EN (BIT(8) | BIT(9)) 134 #define DP83867_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11)) 135 #define DP83867_DOWNSHIFT_1_COUNT_VAL 0 136 #define DP83867_DOWNSHIFT_2_COUNT_VAL 1 137 #define DP83867_DOWNSHIFT_4_COUNT_VAL 2 138 #define DP83867_DOWNSHIFT_8_COUNT_VAL 3 139 #define DP83867_DOWNSHIFT_1_COUNT 1 140 #define DP83867_DOWNSHIFT_2_COUNT 2 141 #define DP83867_DOWNSHIFT_4_COUNT 4 142 #define DP83867_DOWNSHIFT_8_COUNT 8 143 #define DP83867_SGMII_AUTONEG_EN BIT(7) 144 145 /* CFG3 bits */ 146 #define DP83867_CFG3_INT_OE BIT(7) 147 #define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9) 148 149 /* CFG4 bits */ 150 #define DP83867_CFG4_PORT_MIRROR_EN BIT(0) 151 152 /* FLD_THR_CFG */ 153 #define DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK 0x7 154 155 #define DP83867_LED_COUNT 4 156 157 /* LED_DRV bits */ 158 #define DP83867_LED_DRV_EN(x) BIT((x) * 4) 159 #define DP83867_LED_DRV_VAL(x) BIT((x) * 4 + 1) 160 161 enum { 162 DP83867_PORT_MIRROING_KEEP, 163 DP83867_PORT_MIRROING_EN, 164 DP83867_PORT_MIRROING_DIS, 165 }; 166 167 struct dp83867_private { 168 u32 rx_id_delay; 169 u32 tx_id_delay; 170 u32 tx_fifo_depth; 171 u32 rx_fifo_depth; 172 int io_impedance; 173 int port_mirroring; 174 bool rxctrl_strap_quirk; 175 bool set_clk_output; 176 u32 clk_output_sel; 177 bool sgmii_ref_clk_en; 178 }; 179 180 static int dp83867_ack_interrupt(struct phy_device *phydev) 181 { 182 int err = phy_read(phydev, MII_DP83867_ISR); 183 184 if (err < 0) 185 return err; 186 187 return 0; 188 } 189 190 static int dp83867_set_wol(struct phy_device *phydev, 191 struct ethtool_wolinfo *wol) 192 { 193 struct net_device *ndev = phydev->attached_dev; 194 u16 val_rxcfg, val_micr; 195 const u8 *mac; 196 197 val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG); 198 val_micr = phy_read(phydev, MII_DP83867_MICR); 199 200 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | 201 WAKE_BCAST)) { 202 val_rxcfg |= DP83867_WOL_ENH_MAC; 203 val_micr |= MII_DP83867_MICR_WOL_INT_EN; 204 205 if (wol->wolopts & WAKE_MAGIC) { 206 mac = (const u8 *)ndev->dev_addr; 207 208 if (!is_valid_ether_addr(mac)) 209 return -EINVAL; 210 211 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1, 212 (mac[1] << 8 | mac[0])); 213 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2, 214 (mac[3] << 8 | mac[2])); 215 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3, 216 (mac[5] << 8 | mac[4])); 217 218 val_rxcfg |= DP83867_WOL_MAGIC_EN; 219 } else { 220 val_rxcfg &= ~DP83867_WOL_MAGIC_EN; 221 } 222 223 if (wol->wolopts & WAKE_MAGICSECURE) { 224 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1, 225 (wol->sopass[1] << 8) | wol->sopass[0]); 226 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2, 227 (wol->sopass[3] << 8) | wol->sopass[2]); 228 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3, 229 (wol->sopass[5] << 8) | wol->sopass[4]); 230 231 val_rxcfg |= DP83867_WOL_SEC_EN; 232 } else { 233 val_rxcfg &= ~DP83867_WOL_SEC_EN; 234 } 235 236 if (wol->wolopts & WAKE_UCAST) 237 val_rxcfg |= DP83867_WOL_UCAST_EN; 238 else 239 val_rxcfg &= ~DP83867_WOL_UCAST_EN; 240 241 if (wol->wolopts & WAKE_BCAST) 242 val_rxcfg |= DP83867_WOL_BCAST_EN; 243 else 244 val_rxcfg &= ~DP83867_WOL_BCAST_EN; 245 } else { 246 val_rxcfg &= ~DP83867_WOL_ENH_MAC; 247 val_micr &= ~MII_DP83867_MICR_WOL_INT_EN; 248 } 249 250 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg); 251 phy_write(phydev, MII_DP83867_MICR, val_micr); 252 253 return 0; 254 } 255 256 static void dp83867_get_wol(struct phy_device *phydev, 257 struct ethtool_wolinfo *wol) 258 { 259 u16 value, sopass_val; 260 261 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC | 262 WAKE_MAGICSECURE); 263 wol->wolopts = 0; 264 265 value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG); 266 267 if (value & DP83867_WOL_UCAST_EN) 268 wol->wolopts |= WAKE_UCAST; 269 270 if (value & DP83867_WOL_BCAST_EN) 271 wol->wolopts |= WAKE_BCAST; 272 273 if (value & DP83867_WOL_MAGIC_EN) 274 wol->wolopts |= WAKE_MAGIC; 275 276 if (value & DP83867_WOL_SEC_EN) { 277 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR, 278 DP83867_RXFSOP1); 279 wol->sopass[0] = (sopass_val & 0xff); 280 wol->sopass[1] = (sopass_val >> 8); 281 282 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR, 283 DP83867_RXFSOP2); 284 wol->sopass[2] = (sopass_val & 0xff); 285 wol->sopass[3] = (sopass_val >> 8); 286 287 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR, 288 DP83867_RXFSOP3); 289 wol->sopass[4] = (sopass_val & 0xff); 290 wol->sopass[5] = (sopass_val >> 8); 291 292 wol->wolopts |= WAKE_MAGICSECURE; 293 } 294 295 if (!(value & DP83867_WOL_ENH_MAC)) 296 wol->wolopts = 0; 297 } 298 299 static int dp83867_config_intr(struct phy_device *phydev) 300 { 301 int micr_status, err; 302 303 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 304 err = dp83867_ack_interrupt(phydev); 305 if (err) 306 return err; 307 308 micr_status = phy_read(phydev, MII_DP83867_MICR); 309 if (micr_status < 0) 310 return micr_status; 311 312 micr_status |= 313 (MII_DP83867_MICR_AN_ERR_INT_EN | 314 MII_DP83867_MICR_SPEED_CHNG_INT_EN | 315 MII_DP83867_MICR_AUTONEG_COMP_INT_EN | 316 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN | 317 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN | 318 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN); 319 320 err = phy_write(phydev, MII_DP83867_MICR, micr_status); 321 } else { 322 micr_status = 0x0; 323 err = phy_write(phydev, MII_DP83867_MICR, micr_status); 324 if (err) 325 return err; 326 327 err = dp83867_ack_interrupt(phydev); 328 } 329 330 return err; 331 } 332 333 static irqreturn_t dp83867_handle_interrupt(struct phy_device *phydev) 334 { 335 int irq_status, irq_enabled; 336 337 irq_status = phy_read(phydev, MII_DP83867_ISR); 338 if (irq_status < 0) { 339 phy_error(phydev); 340 return IRQ_NONE; 341 } 342 343 irq_enabled = phy_read(phydev, MII_DP83867_MICR); 344 if (irq_enabled < 0) { 345 phy_error(phydev); 346 return IRQ_NONE; 347 } 348 349 if (!(irq_status & irq_enabled)) 350 return IRQ_NONE; 351 352 phy_trigger_machine(phydev); 353 354 return IRQ_HANDLED; 355 } 356 357 static int dp83867_read_status(struct phy_device *phydev) 358 { 359 int status = phy_read(phydev, MII_DP83867_PHYSTS); 360 int ret; 361 362 ret = genphy_read_status(phydev); 363 if (ret) 364 return ret; 365 366 if (status < 0) 367 return status; 368 369 if (status & DP83867_PHYSTS_DUPLEX) 370 phydev->duplex = DUPLEX_FULL; 371 else 372 phydev->duplex = DUPLEX_HALF; 373 374 if (status & DP83867_PHYSTS_1000) 375 phydev->speed = SPEED_1000; 376 else if (status & DP83867_PHYSTS_100) 377 phydev->speed = SPEED_100; 378 else 379 phydev->speed = SPEED_10; 380 381 return 0; 382 } 383 384 static int dp83867_get_downshift(struct phy_device *phydev, u8 *data) 385 { 386 int val, cnt, enable, count; 387 388 val = phy_read(phydev, DP83867_CFG2); 389 if (val < 0) 390 return val; 391 392 enable = FIELD_GET(DP83867_DOWNSHIFT_EN, val); 393 cnt = FIELD_GET(DP83867_DOWNSHIFT_ATTEMPT_MASK, val); 394 395 switch (cnt) { 396 case DP83867_DOWNSHIFT_1_COUNT_VAL: 397 count = DP83867_DOWNSHIFT_1_COUNT; 398 break; 399 case DP83867_DOWNSHIFT_2_COUNT_VAL: 400 count = DP83867_DOWNSHIFT_2_COUNT; 401 break; 402 case DP83867_DOWNSHIFT_4_COUNT_VAL: 403 count = DP83867_DOWNSHIFT_4_COUNT; 404 break; 405 case DP83867_DOWNSHIFT_8_COUNT_VAL: 406 count = DP83867_DOWNSHIFT_8_COUNT; 407 break; 408 default: 409 return -EINVAL; 410 } 411 412 *data = enable ? count : DOWNSHIFT_DEV_DISABLE; 413 414 return 0; 415 } 416 417 static int dp83867_set_downshift(struct phy_device *phydev, u8 cnt) 418 { 419 int val, count; 420 421 if (cnt > DP83867_DOWNSHIFT_8_COUNT) 422 return -E2BIG; 423 424 if (!cnt) 425 return phy_clear_bits(phydev, DP83867_CFG2, 426 DP83867_DOWNSHIFT_EN); 427 428 switch (cnt) { 429 case DP83867_DOWNSHIFT_1_COUNT: 430 count = DP83867_DOWNSHIFT_1_COUNT_VAL; 431 break; 432 case DP83867_DOWNSHIFT_2_COUNT: 433 count = DP83867_DOWNSHIFT_2_COUNT_VAL; 434 break; 435 case DP83867_DOWNSHIFT_4_COUNT: 436 count = DP83867_DOWNSHIFT_4_COUNT_VAL; 437 break; 438 case DP83867_DOWNSHIFT_8_COUNT: 439 count = DP83867_DOWNSHIFT_8_COUNT_VAL; 440 break; 441 default: 442 phydev_err(phydev, 443 "Downshift count must be 1, 2, 4 or 8\n"); 444 return -EINVAL; 445 } 446 447 val = DP83867_DOWNSHIFT_EN; 448 val |= FIELD_PREP(DP83867_DOWNSHIFT_ATTEMPT_MASK, count); 449 450 return phy_modify(phydev, DP83867_CFG2, 451 DP83867_DOWNSHIFT_EN | DP83867_DOWNSHIFT_ATTEMPT_MASK, 452 val); 453 } 454 455 static int dp83867_get_tunable(struct phy_device *phydev, 456 struct ethtool_tunable *tuna, void *data) 457 { 458 switch (tuna->id) { 459 case ETHTOOL_PHY_DOWNSHIFT: 460 return dp83867_get_downshift(phydev, data); 461 default: 462 return -EOPNOTSUPP; 463 } 464 } 465 466 static int dp83867_set_tunable(struct phy_device *phydev, 467 struct ethtool_tunable *tuna, const void *data) 468 { 469 switch (tuna->id) { 470 case ETHTOOL_PHY_DOWNSHIFT: 471 return dp83867_set_downshift(phydev, *(const u8 *)data); 472 default: 473 return -EOPNOTSUPP; 474 } 475 } 476 477 static int dp83867_config_port_mirroring(struct phy_device *phydev) 478 { 479 struct dp83867_private *dp83867 = phydev->priv; 480 481 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN) 482 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 483 DP83867_CFG4_PORT_MIRROR_EN); 484 else 485 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 486 DP83867_CFG4_PORT_MIRROR_EN); 487 return 0; 488 } 489 490 static int dp83867_verify_rgmii_cfg(struct phy_device *phydev) 491 { 492 struct dp83867_private *dp83867 = phydev->priv; 493 494 /* Existing behavior was to use default pin strapping delay in rgmii 495 * mode, but rgmii should have meant no delay. Warn existing users. 496 */ 497 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { 498 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR, 499 DP83867_STRAP_STS2); 500 const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >> 501 DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT; 502 const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >> 503 DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT; 504 505 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE || 506 rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE) 507 phydev_warn(phydev, 508 "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n" 509 "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n", 510 txskew, rxskew); 511 } 512 513 /* RX delay *must* be specified if internal delay of RX is used. */ 514 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 515 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) && 516 dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) { 517 phydev_err(phydev, "ti,rx-internal-delay must be specified\n"); 518 return -EINVAL; 519 } 520 521 /* TX delay *must* be specified if internal delay of TX is used. */ 522 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 523 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) && 524 dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) { 525 phydev_err(phydev, "ti,tx-internal-delay must be specified\n"); 526 return -EINVAL; 527 } 528 529 return 0; 530 } 531 532 #if IS_ENABLED(CONFIG_OF_MDIO) 533 static int dp83867_of_init_io_impedance(struct phy_device *phydev) 534 { 535 struct dp83867_private *dp83867 = phydev->priv; 536 struct device *dev = &phydev->mdio.dev; 537 struct device_node *of_node = dev->of_node; 538 struct nvmem_cell *cell; 539 u8 *buf, val; 540 int ret; 541 542 cell = of_nvmem_cell_get(of_node, "io_impedance_ctrl"); 543 if (IS_ERR(cell)) { 544 ret = PTR_ERR(cell); 545 if (ret != -ENOENT && ret != -EOPNOTSUPP) 546 return phydev_err_probe(phydev, ret, 547 "failed to get nvmem cell io_impedance_ctrl\n"); 548 549 /* If no nvmem cell, check for the boolean properties. */ 550 if (of_property_read_bool(of_node, "ti,max-output-impedance")) 551 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX; 552 else if (of_property_read_bool(of_node, "ti,min-output-impedance")) 553 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN; 554 else 555 dp83867->io_impedance = -1; /* leave at default */ 556 557 return 0; 558 } 559 560 buf = nvmem_cell_read(cell, NULL); 561 nvmem_cell_put(cell); 562 563 if (IS_ERR(buf)) 564 return PTR_ERR(buf); 565 566 val = *buf; 567 kfree(buf); 568 569 if ((val & DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK) != val) { 570 phydev_err(phydev, "nvmem cell 'io_impedance_ctrl' contents out of range\n"); 571 return -ERANGE; 572 } 573 dp83867->io_impedance = val; 574 575 return 0; 576 } 577 578 static int dp83867_of_init(struct phy_device *phydev) 579 { 580 struct dp83867_private *dp83867 = phydev->priv; 581 struct device *dev = &phydev->mdio.dev; 582 struct device_node *of_node = dev->of_node; 583 int ret; 584 585 if (!of_node) 586 return -ENODEV; 587 588 /* Optional configuration */ 589 ret = of_property_read_u32(of_node, "ti,clk-output-sel", 590 &dp83867->clk_output_sel); 591 /* If not set, keep default */ 592 if (!ret) { 593 dp83867->set_clk_output = true; 594 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or 595 * DP83867_CLK_O_SEL_OFF. 596 */ 597 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK && 598 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) { 599 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n", 600 dp83867->clk_output_sel); 601 return -EINVAL; 602 } 603 } 604 605 ret = dp83867_of_init_io_impedance(phydev); 606 if (ret) 607 return ret; 608 609 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node, 610 "ti,dp83867-rxctrl-strap-quirk"); 611 612 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node, 613 "ti,sgmii-ref-clock-output-enable"); 614 615 dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV; 616 ret = of_property_read_u32(of_node, "ti,rx-internal-delay", 617 &dp83867->rx_id_delay); 618 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) { 619 phydev_err(phydev, 620 "ti,rx-internal-delay value of %u out of range\n", 621 dp83867->rx_id_delay); 622 return -EINVAL; 623 } 624 625 dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV; 626 ret = of_property_read_u32(of_node, "ti,tx-internal-delay", 627 &dp83867->tx_id_delay); 628 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) { 629 phydev_err(phydev, 630 "ti,tx-internal-delay value of %u out of range\n", 631 dp83867->tx_id_delay); 632 return -EINVAL; 633 } 634 635 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) 636 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN; 637 638 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap")) 639 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS; 640 641 ret = of_property_read_u32(of_node, "ti,fifo-depth", 642 &dp83867->tx_fifo_depth); 643 if (ret) { 644 ret = of_property_read_u32(of_node, "tx-fifo-depth", 645 &dp83867->tx_fifo_depth); 646 if (ret) 647 dp83867->tx_fifo_depth = 648 DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; 649 } 650 651 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { 652 phydev_err(phydev, "tx-fifo-depth value %u out of range\n", 653 dp83867->tx_fifo_depth); 654 return -EINVAL; 655 } 656 657 ret = of_property_read_u32(of_node, "rx-fifo-depth", 658 &dp83867->rx_fifo_depth); 659 if (ret) 660 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; 661 662 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { 663 phydev_err(phydev, "rx-fifo-depth value %u out of range\n", 664 dp83867->rx_fifo_depth); 665 return -EINVAL; 666 } 667 668 return 0; 669 } 670 #else 671 static int dp83867_of_init(struct phy_device *phydev) 672 { 673 struct dp83867_private *dp83867 = phydev->priv; 674 u16 delay; 675 676 /* For non-OF device, the RX and TX ID values are either strapped 677 * or take from default value. So, we init RX & TX ID values here 678 * so that the RGMIIDCTL is configured correctly later in 679 * dp83867_config_init(); 680 */ 681 delay = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL); 682 dp83867->rx_id_delay = delay & DP83867_RGMII_RX_CLK_DELAY_MAX; 683 dp83867->tx_id_delay = (delay >> DP83867_RGMII_TX_CLK_DELAY_SHIFT) & 684 DP83867_RGMII_TX_CLK_DELAY_MAX; 685 686 /* Per datasheet, IO impedance is default to 50-ohm, so we set the 687 * same here or else the default '0' means highest IO impedance 688 * which is wrong. 689 */ 690 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN / 2; 691 692 /* For non-OF device, the RX and TX FIFO depths are taken from 693 * default value. So, we init RX & TX FIFO depths here 694 * so that it is configured correctly later in dp83867_config_init(); 695 */ 696 dp83867->tx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; 697 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; 698 699 return 0; 700 } 701 #endif /* CONFIG_OF_MDIO */ 702 703 static int dp83867_suspend(struct phy_device *phydev) 704 { 705 /* Disable PHY Interrupts */ 706 if (phy_interrupt_is_valid(phydev)) { 707 phydev->interrupts = PHY_INTERRUPT_DISABLED; 708 dp83867_config_intr(phydev); 709 } 710 711 return genphy_suspend(phydev); 712 } 713 714 static int dp83867_resume(struct phy_device *phydev) 715 { 716 /* Enable PHY Interrupts */ 717 if (phy_interrupt_is_valid(phydev)) { 718 phydev->interrupts = PHY_INTERRUPT_ENABLED; 719 dp83867_config_intr(phydev); 720 } 721 722 genphy_resume(phydev); 723 724 return 0; 725 } 726 727 static int dp83867_probe(struct phy_device *phydev) 728 { 729 struct dp83867_private *dp83867; 730 731 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867), 732 GFP_KERNEL); 733 if (!dp83867) 734 return -ENOMEM; 735 736 phydev->priv = dp83867; 737 738 return dp83867_of_init(phydev); 739 } 740 741 static int dp83867_config_init(struct phy_device *phydev) 742 { 743 struct dp83867_private *dp83867 = phydev->priv; 744 int ret, val, bs; 745 u16 delay; 746 747 /* Force speed optimization for the PHY even if it strapped */ 748 ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN, 749 DP83867_DOWNSHIFT_EN); 750 if (ret) 751 return ret; 752 753 ret = dp83867_verify_rgmii_cfg(phydev); 754 if (ret) 755 return ret; 756 757 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */ 758 if (dp83867->rxctrl_strap_quirk) 759 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 760 BIT(7)); 761 762 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2); 763 if (bs & DP83867_STRAP_STS2_STRAP_FLD) { 764 /* When using strap to enable FLD, the ENERGY_LOST_FLD_THR will 765 * be set to 0x2. This may causes the PHY link to be unstable - 766 * the default value 0x1 need to be restored. 767 */ 768 ret = phy_modify_mmd(phydev, DP83867_DEVADDR, 769 DP83867_FLD_THR_CFG, 770 DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK, 771 0x1); 772 if (ret) 773 return ret; 774 } 775 776 if (phy_interface_is_rgmii(phydev) || 777 phydev->interface == PHY_INTERFACE_MODE_SGMII) { 778 val = phy_read(phydev, MII_DP83867_PHYCTRL); 779 if (val < 0) 780 return val; 781 782 val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK; 783 val |= (dp83867->tx_fifo_depth << 784 DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT); 785 786 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 787 val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK; 788 val |= (dp83867->rx_fifo_depth << 789 DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT); 790 } 791 792 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); 793 if (ret) 794 return ret; 795 } 796 797 if (phy_interface_is_rgmii(phydev)) { 798 val = phy_read(phydev, MII_DP83867_PHYCTRL); 799 if (val < 0) 800 return val; 801 802 /* The code below checks if "port mirroring" N/A MODE4 has been 803 * enabled during power on bootstrap. 804 * 805 * Such N/A mode enabled by mistake can put PHY IC in some 806 * internal testing mode and disable RGMII transmission. 807 * 808 * In this particular case one needs to check STRAP_STS1 809 * register's bit 11 (marked as RESERVED). 810 */ 811 812 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1); 813 if (bs & DP83867_STRAP_STS1_RESERVED) 814 val &= ~DP83867_PHYCR_RESERVED_MASK; 815 816 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); 817 if (ret) 818 return ret; 819 820 /* If rgmii mode with no internal delay is selected, we do NOT use 821 * aligned mode as one might expect. Instead we use the PHY's default 822 * based on pin strapping. And the "mode 0" default is to *use* 823 * internal delay with a value of 7 (2.00 ns). 824 * 825 * Set up RGMII delays 826 */ 827 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL); 828 829 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); 830 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 831 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); 832 833 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 834 val |= DP83867_RGMII_TX_CLK_DELAY_EN; 835 836 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 837 val |= DP83867_RGMII_RX_CLK_DELAY_EN; 838 839 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val); 840 841 delay = 0; 842 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV) 843 delay |= dp83867->rx_id_delay; 844 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV) 845 delay |= dp83867->tx_id_delay << 846 DP83867_RGMII_TX_CLK_DELAY_SHIFT; 847 848 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL, 849 delay); 850 } 851 852 /* If specified, set io impedance */ 853 if (dp83867->io_impedance >= 0) 854 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, 855 DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK, 856 dp83867->io_impedance); 857 858 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 859 /* For support SPEED_10 in SGMII mode 860 * DP83867_10M_SGMII_RATE_ADAPT bit 861 * has to be cleared by software. That 862 * does not affect SPEED_100 and 863 * SPEED_1000. 864 */ 865 ret = phy_modify_mmd(phydev, DP83867_DEVADDR, 866 DP83867_10M_SGMII_CFG, 867 DP83867_10M_SGMII_RATE_ADAPT_MASK, 868 0); 869 if (ret) 870 return ret; 871 872 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5 873 * are 01). That is not enough to finalize autoneg on some 874 * devices. Increase this timer duration to maximum 16ms. 875 */ 876 ret = phy_modify_mmd(phydev, DP83867_DEVADDR, 877 DP83867_CFG4, 878 DP83867_CFG4_SGMII_ANEG_MASK, 879 DP83867_CFG4_SGMII_ANEG_TIMER_16MS); 880 881 if (ret) 882 return ret; 883 884 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL); 885 /* SGMII type is set to 4-wire mode by default. 886 * If we place appropriate property in dts (see above) 887 * switch on 6-wire mode. 888 */ 889 if (dp83867->sgmii_ref_clk_en) 890 val |= DP83867_SGMII_TYPE; 891 else 892 val &= ~DP83867_SGMII_TYPE; 893 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val); 894 895 /* This is a SW workaround for link instability if RX_CTRL is 896 * not strapped to mode 3 or 4 in HW. This is required for SGMII 897 * in addition to clearing bit 7, handled above. 898 */ 899 if (dp83867->rxctrl_strap_quirk) 900 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 901 BIT(8)); 902 } 903 904 val = phy_read(phydev, DP83867_CFG3); 905 /* Enable Interrupt output INT_OE in CFG3 register */ 906 if (phy_interrupt_is_valid(phydev)) 907 val |= DP83867_CFG3_INT_OE; 908 909 val |= DP83867_CFG3_ROBUST_AUTO_MDIX; 910 phy_write(phydev, DP83867_CFG3, val); 911 912 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP) 913 dp83867_config_port_mirroring(phydev); 914 915 /* Clock output selection if muxing property is set */ 916 if (dp83867->set_clk_output) { 917 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE; 918 919 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) { 920 val = DP83867_IO_MUX_CFG_CLK_O_DISABLE; 921 } else { 922 mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK; 923 val = dp83867->clk_output_sel << 924 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT; 925 } 926 927 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, 928 mask, val); 929 } 930 931 return 0; 932 } 933 934 static int dp83867_phy_reset(struct phy_device *phydev) 935 { 936 int err; 937 938 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART); 939 if (err < 0) 940 return err; 941 942 usleep_range(10, 20); 943 944 return phy_modify(phydev, MII_DP83867_PHYCTRL, 945 DP83867_PHYCR_FORCE_LINK_GOOD, 0); 946 } 947 948 static void dp83867_link_change_notify(struct phy_device *phydev) 949 { 950 /* There is a limitation in DP83867 PHY device where SGMII AN is 951 * only triggered once after the device is booted up. Even after the 952 * PHY TPI is down and up again, SGMII AN is not triggered and 953 * hence no new in-band message from PHY to MAC side SGMII. 954 * This could cause an issue during power up, when PHY is up prior 955 * to MAC. At this condition, once MAC side SGMII is up, MAC side 956 * SGMII wouldn`t receive new in-band message from TI PHY with 957 * correct link status, speed and duplex info. 958 * Thus, implemented a SW solution here to retrigger SGMII Auto-Neg 959 * whenever there is a link change. 960 */ 961 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 962 int val = 0; 963 964 val = phy_clear_bits(phydev, DP83867_CFG2, 965 DP83867_SGMII_AUTONEG_EN); 966 if (val < 0) 967 return; 968 969 phy_set_bits(phydev, DP83867_CFG2, 970 DP83867_SGMII_AUTONEG_EN); 971 } 972 } 973 974 static int dp83867_loopback(struct phy_device *phydev, bool enable) 975 { 976 return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, 977 enable ? BMCR_LOOPBACK : 0); 978 } 979 980 static int 981 dp83867_led_brightness_set(struct phy_device *phydev, 982 u8 index, enum led_brightness brightness) 983 { 984 u32 val; 985 986 if (index >= DP83867_LED_COUNT) 987 return -EINVAL; 988 989 /* DRV_EN==1: output is DRV_VAL */ 990 val = DP83867_LED_DRV_EN(index); 991 992 if (brightness) 993 val |= DP83867_LED_DRV_VAL(index); 994 995 return phy_modify(phydev, DP83867_LEDCR2, 996 DP83867_LED_DRV_VAL(index) | 997 DP83867_LED_DRV_EN(index), 998 val); 999 } 1000 1001 static struct phy_driver dp83867_driver[] = { 1002 { 1003 .phy_id = DP83867_PHY_ID, 1004 .phy_id_mask = 0xfffffff0, 1005 .name = "TI DP83867", 1006 /* PHY_GBIT_FEATURES */ 1007 1008 .probe = dp83867_probe, 1009 .config_init = dp83867_config_init, 1010 .soft_reset = dp83867_phy_reset, 1011 1012 .read_status = dp83867_read_status, 1013 .get_tunable = dp83867_get_tunable, 1014 .set_tunable = dp83867_set_tunable, 1015 1016 .get_wol = dp83867_get_wol, 1017 .set_wol = dp83867_set_wol, 1018 1019 /* IRQ related */ 1020 .config_intr = dp83867_config_intr, 1021 .handle_interrupt = dp83867_handle_interrupt, 1022 1023 .suspend = dp83867_suspend, 1024 .resume = dp83867_resume, 1025 1026 .link_change_notify = dp83867_link_change_notify, 1027 .set_loopback = dp83867_loopback, 1028 1029 .led_brightness_set = dp83867_led_brightness_set, 1030 }, 1031 }; 1032 module_phy_driver(dp83867_driver); 1033 1034 static struct mdio_device_id __maybe_unused dp83867_tbl[] = { 1035 { DP83867_PHY_ID, 0xfffffff0 }, 1036 { } 1037 }; 1038 1039 MODULE_DEVICE_TABLE(mdio, dp83867_tbl); 1040 1041 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver"); 1042 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 1043 MODULE_LICENSE("GPL v2"); 1044