1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Texas Instruments DP83867 PHY 4 * 5 * Copyright (C) 2015 Texas Instruments Inc. 6 */ 7 8 #include <linux/ethtool.h> 9 #include <linux/kernel.h> 10 #include <linux/mii.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/phy.h> 14 #include <linux/delay.h> 15 #include <linux/netdevice.h> 16 #include <linux/etherdevice.h> 17 #include <linux/bitfield.h> 18 19 #include <dt-bindings/net/ti-dp83867.h> 20 21 #define DP83867_PHY_ID 0x2000a231 22 #define DP83867_DEVADDR 0x1f 23 24 #define MII_DP83867_PHYCTRL 0x10 25 #define MII_DP83867_PHYSTS 0x11 26 #define MII_DP83867_MICR 0x12 27 #define MII_DP83867_ISR 0x13 28 #define DP83867_CFG2 0x14 29 #define DP83867_CFG3 0x1e 30 #define DP83867_CTRL 0x1f 31 32 /* Extended Registers */ 33 #define DP83867_CFG4 0x0031 34 #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6)) 35 #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5) 36 #define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5) 37 #define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5) 38 #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5) 39 40 #define DP83867_RGMIICTL 0x0032 41 #define DP83867_STRAP_STS1 0x006E 42 #define DP83867_STRAP_STS2 0x006f 43 #define DP83867_RGMIIDCTL 0x0086 44 #define DP83867_RXFCFG 0x0134 45 #define DP83867_RXFPMD1 0x0136 46 #define DP83867_RXFPMD2 0x0137 47 #define DP83867_RXFPMD3 0x0138 48 #define DP83867_RXFSOP1 0x0139 49 #define DP83867_RXFSOP2 0x013A 50 #define DP83867_RXFSOP3 0x013B 51 #define DP83867_IO_MUX_CFG 0x0170 52 #define DP83867_SGMIICTL 0x00D3 53 #define DP83867_10M_SGMII_CFG 0x016F 54 #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7) 55 56 #define DP83867_SW_RESET BIT(15) 57 #define DP83867_SW_RESTART BIT(14) 58 59 /* MICR Interrupt bits */ 60 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) 61 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) 62 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) 63 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) 64 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) 65 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) 66 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) 67 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) 68 #define MII_DP83867_MICR_WOL_INT_EN BIT(3) 69 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) 70 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) 71 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0) 72 73 /* RGMIICTL bits */ 74 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) 75 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) 76 77 /* SGMIICTL bits */ 78 #define DP83867_SGMII_TYPE BIT(14) 79 80 /* RXFCFG bits*/ 81 #define DP83867_WOL_MAGIC_EN BIT(0) 82 #define DP83867_WOL_BCAST_EN BIT(2) 83 #define DP83867_WOL_UCAST_EN BIT(4) 84 #define DP83867_WOL_SEC_EN BIT(5) 85 #define DP83867_WOL_ENH_MAC BIT(7) 86 87 /* STRAP_STS1 bits */ 88 #define DP83867_STRAP_STS1_RESERVED BIT(11) 89 90 /* STRAP_STS2 bits */ 91 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4) 92 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4 93 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0) 94 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0 95 #define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2) 96 97 /* PHY CTRL bits */ 98 #define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT 14 99 #define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT 12 100 #define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03 101 #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14) 102 #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12) 103 #define DP83867_PHYCR_RESERVED_MASK BIT(11) 104 #define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10) 105 106 /* RGMIIDCTL bits */ 107 #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf 108 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 109 #define DP83867_RGMII_TX_CLK_DELAY_INV (DP83867_RGMII_TX_CLK_DELAY_MAX + 1) 110 #define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf 111 #define DP83867_RGMII_RX_CLK_DELAY_SHIFT 0 112 #define DP83867_RGMII_RX_CLK_DELAY_INV (DP83867_RGMII_RX_CLK_DELAY_MAX + 1) 113 114 115 /* IO_MUX_CFG bits */ 116 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK 0x1f 117 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 118 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f 119 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6) 120 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8) 121 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 122 123 /* PHY STS bits */ 124 #define DP83867_PHYSTS_1000 BIT(15) 125 #define DP83867_PHYSTS_100 BIT(14) 126 #define DP83867_PHYSTS_DUPLEX BIT(13) 127 #define DP83867_PHYSTS_LINK BIT(10) 128 129 /* CFG2 bits */ 130 #define DP83867_DOWNSHIFT_EN (BIT(8) | BIT(9)) 131 #define DP83867_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11)) 132 #define DP83867_DOWNSHIFT_1_COUNT_VAL 0 133 #define DP83867_DOWNSHIFT_2_COUNT_VAL 1 134 #define DP83867_DOWNSHIFT_4_COUNT_VAL 2 135 #define DP83867_DOWNSHIFT_8_COUNT_VAL 3 136 #define DP83867_DOWNSHIFT_1_COUNT 1 137 #define DP83867_DOWNSHIFT_2_COUNT 2 138 #define DP83867_DOWNSHIFT_4_COUNT 4 139 #define DP83867_DOWNSHIFT_8_COUNT 8 140 141 /* CFG3 bits */ 142 #define DP83867_CFG3_INT_OE BIT(7) 143 #define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9) 144 145 /* CFG4 bits */ 146 #define DP83867_CFG4_PORT_MIRROR_EN BIT(0) 147 148 enum { 149 DP83867_PORT_MIRROING_KEEP, 150 DP83867_PORT_MIRROING_EN, 151 DP83867_PORT_MIRROING_DIS, 152 }; 153 154 struct dp83867_private { 155 u32 rx_id_delay; 156 u32 tx_id_delay; 157 u32 tx_fifo_depth; 158 u32 rx_fifo_depth; 159 int io_impedance; 160 int port_mirroring; 161 bool rxctrl_strap_quirk; 162 bool set_clk_output; 163 u32 clk_output_sel; 164 bool sgmii_ref_clk_en; 165 }; 166 167 static int dp83867_ack_interrupt(struct phy_device *phydev) 168 { 169 int err = phy_read(phydev, MII_DP83867_ISR); 170 171 if (err < 0) 172 return err; 173 174 return 0; 175 } 176 177 static int dp83867_set_wol(struct phy_device *phydev, 178 struct ethtool_wolinfo *wol) 179 { 180 struct net_device *ndev = phydev->attached_dev; 181 u16 val_rxcfg, val_micr; 182 u8 *mac; 183 184 val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG); 185 val_micr = phy_read(phydev, MII_DP83867_MICR); 186 187 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | 188 WAKE_BCAST)) { 189 val_rxcfg |= DP83867_WOL_ENH_MAC; 190 val_micr |= MII_DP83867_MICR_WOL_INT_EN; 191 192 if (wol->wolopts & WAKE_MAGIC) { 193 mac = (u8 *)ndev->dev_addr; 194 195 if (!is_valid_ether_addr(mac)) 196 return -EINVAL; 197 198 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1, 199 (mac[1] << 8 | mac[0])); 200 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2, 201 (mac[3] << 8 | mac[2])); 202 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3, 203 (mac[5] << 8 | mac[4])); 204 205 val_rxcfg |= DP83867_WOL_MAGIC_EN; 206 } else { 207 val_rxcfg &= ~DP83867_WOL_MAGIC_EN; 208 } 209 210 if (wol->wolopts & WAKE_MAGICSECURE) { 211 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1, 212 (wol->sopass[1] << 8) | wol->sopass[0]); 213 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1, 214 (wol->sopass[3] << 8) | wol->sopass[2]); 215 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1, 216 (wol->sopass[5] << 8) | wol->sopass[4]); 217 218 val_rxcfg |= DP83867_WOL_SEC_EN; 219 } else { 220 val_rxcfg &= ~DP83867_WOL_SEC_EN; 221 } 222 223 if (wol->wolopts & WAKE_UCAST) 224 val_rxcfg |= DP83867_WOL_UCAST_EN; 225 else 226 val_rxcfg &= ~DP83867_WOL_UCAST_EN; 227 228 if (wol->wolopts & WAKE_BCAST) 229 val_rxcfg |= DP83867_WOL_BCAST_EN; 230 else 231 val_rxcfg &= ~DP83867_WOL_BCAST_EN; 232 } else { 233 val_rxcfg &= ~DP83867_WOL_ENH_MAC; 234 val_micr &= ~MII_DP83867_MICR_WOL_INT_EN; 235 } 236 237 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg); 238 phy_write(phydev, MII_DP83867_MICR, val_micr); 239 240 return 0; 241 } 242 243 static void dp83867_get_wol(struct phy_device *phydev, 244 struct ethtool_wolinfo *wol) 245 { 246 u16 value, sopass_val; 247 248 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC | 249 WAKE_MAGICSECURE); 250 wol->wolopts = 0; 251 252 value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG); 253 254 if (value & DP83867_WOL_UCAST_EN) 255 wol->wolopts |= WAKE_UCAST; 256 257 if (value & DP83867_WOL_BCAST_EN) 258 wol->wolopts |= WAKE_BCAST; 259 260 if (value & DP83867_WOL_MAGIC_EN) 261 wol->wolopts |= WAKE_MAGIC; 262 263 if (value & DP83867_WOL_SEC_EN) { 264 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR, 265 DP83867_RXFSOP1); 266 wol->sopass[0] = (sopass_val & 0xff); 267 wol->sopass[1] = (sopass_val >> 8); 268 269 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR, 270 DP83867_RXFSOP2); 271 wol->sopass[2] = (sopass_val & 0xff); 272 wol->sopass[3] = (sopass_val >> 8); 273 274 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR, 275 DP83867_RXFSOP3); 276 wol->sopass[4] = (sopass_val & 0xff); 277 wol->sopass[5] = (sopass_val >> 8); 278 279 wol->wolopts |= WAKE_MAGICSECURE; 280 } 281 282 if (!(value & DP83867_WOL_ENH_MAC)) 283 wol->wolopts = 0; 284 } 285 286 static int dp83867_config_intr(struct phy_device *phydev) 287 { 288 int micr_status; 289 290 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 291 micr_status = phy_read(phydev, MII_DP83867_MICR); 292 if (micr_status < 0) 293 return micr_status; 294 295 micr_status |= 296 (MII_DP83867_MICR_AN_ERR_INT_EN | 297 MII_DP83867_MICR_SPEED_CHNG_INT_EN | 298 MII_DP83867_MICR_AUTONEG_COMP_INT_EN | 299 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN | 300 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN | 301 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN); 302 303 return phy_write(phydev, MII_DP83867_MICR, micr_status); 304 } 305 306 micr_status = 0x0; 307 return phy_write(phydev, MII_DP83867_MICR, micr_status); 308 } 309 310 static int dp83867_read_status(struct phy_device *phydev) 311 { 312 int status = phy_read(phydev, MII_DP83867_PHYSTS); 313 int ret; 314 315 ret = genphy_read_status(phydev); 316 if (ret) 317 return ret; 318 319 if (status < 0) 320 return status; 321 322 if (status & DP83867_PHYSTS_DUPLEX) 323 phydev->duplex = DUPLEX_FULL; 324 else 325 phydev->duplex = DUPLEX_HALF; 326 327 if (status & DP83867_PHYSTS_1000) 328 phydev->speed = SPEED_1000; 329 else if (status & DP83867_PHYSTS_100) 330 phydev->speed = SPEED_100; 331 else 332 phydev->speed = SPEED_10; 333 334 return 0; 335 } 336 337 static int dp83867_get_downshift(struct phy_device *phydev, u8 *data) 338 { 339 int val, cnt, enable, count; 340 341 val = phy_read(phydev, DP83867_CFG2); 342 if (val < 0) 343 return val; 344 345 enable = FIELD_GET(DP83867_DOWNSHIFT_EN, val); 346 cnt = FIELD_GET(DP83867_DOWNSHIFT_ATTEMPT_MASK, val); 347 348 switch (cnt) { 349 case DP83867_DOWNSHIFT_1_COUNT_VAL: 350 count = DP83867_DOWNSHIFT_1_COUNT; 351 break; 352 case DP83867_DOWNSHIFT_2_COUNT_VAL: 353 count = DP83867_DOWNSHIFT_2_COUNT; 354 break; 355 case DP83867_DOWNSHIFT_4_COUNT_VAL: 356 count = DP83867_DOWNSHIFT_4_COUNT; 357 break; 358 case DP83867_DOWNSHIFT_8_COUNT_VAL: 359 count = DP83867_DOWNSHIFT_8_COUNT; 360 break; 361 default: 362 return -EINVAL; 363 }; 364 365 *data = enable ? count : DOWNSHIFT_DEV_DISABLE; 366 367 return 0; 368 } 369 370 static int dp83867_set_downshift(struct phy_device *phydev, u8 cnt) 371 { 372 int val, count; 373 374 if (cnt > DP83867_DOWNSHIFT_8_COUNT) 375 return -E2BIG; 376 377 if (!cnt) 378 return phy_clear_bits(phydev, DP83867_CFG2, 379 DP83867_DOWNSHIFT_EN); 380 381 switch (cnt) { 382 case DP83867_DOWNSHIFT_1_COUNT: 383 count = DP83867_DOWNSHIFT_1_COUNT_VAL; 384 break; 385 case DP83867_DOWNSHIFT_2_COUNT: 386 count = DP83867_DOWNSHIFT_2_COUNT_VAL; 387 break; 388 case DP83867_DOWNSHIFT_4_COUNT: 389 count = DP83867_DOWNSHIFT_4_COUNT_VAL; 390 break; 391 case DP83867_DOWNSHIFT_8_COUNT: 392 count = DP83867_DOWNSHIFT_8_COUNT_VAL; 393 break; 394 default: 395 phydev_err(phydev, 396 "Downshift count must be 1, 2, 4 or 8\n"); 397 return -EINVAL; 398 }; 399 400 val = DP83867_DOWNSHIFT_EN; 401 val |= FIELD_PREP(DP83867_DOWNSHIFT_ATTEMPT_MASK, count); 402 403 return phy_modify(phydev, DP83867_CFG2, 404 DP83867_DOWNSHIFT_EN | DP83867_DOWNSHIFT_ATTEMPT_MASK, 405 val); 406 } 407 408 static int dp83867_get_tunable(struct phy_device *phydev, 409 struct ethtool_tunable *tuna, void *data) 410 { 411 switch (tuna->id) { 412 case ETHTOOL_PHY_DOWNSHIFT: 413 return dp83867_get_downshift(phydev, data); 414 default: 415 return -EOPNOTSUPP; 416 } 417 } 418 419 static int dp83867_set_tunable(struct phy_device *phydev, 420 struct ethtool_tunable *tuna, const void *data) 421 { 422 switch (tuna->id) { 423 case ETHTOOL_PHY_DOWNSHIFT: 424 return dp83867_set_downshift(phydev, *(const u8 *)data); 425 default: 426 return -EOPNOTSUPP; 427 } 428 } 429 430 static int dp83867_config_port_mirroring(struct phy_device *phydev) 431 { 432 struct dp83867_private *dp83867 = 433 (struct dp83867_private *)phydev->priv; 434 435 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN) 436 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 437 DP83867_CFG4_PORT_MIRROR_EN); 438 else 439 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 440 DP83867_CFG4_PORT_MIRROR_EN); 441 return 0; 442 } 443 444 static int dp83867_verify_rgmii_cfg(struct phy_device *phydev) 445 { 446 struct dp83867_private *dp83867 = phydev->priv; 447 448 /* Existing behavior was to use default pin strapping delay in rgmii 449 * mode, but rgmii should have meant no delay. Warn existing users. 450 */ 451 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { 452 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR, 453 DP83867_STRAP_STS2); 454 const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >> 455 DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT; 456 const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >> 457 DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT; 458 459 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE || 460 rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE) 461 phydev_warn(phydev, 462 "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n" 463 "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n", 464 txskew, rxskew); 465 } 466 467 /* RX delay *must* be specified if internal delay of RX is used. */ 468 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 469 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) && 470 dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) { 471 phydev_err(phydev, "ti,rx-internal-delay must be specified\n"); 472 return -EINVAL; 473 } 474 475 /* TX delay *must* be specified if internal delay of TX is used. */ 476 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 477 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) && 478 dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) { 479 phydev_err(phydev, "ti,tx-internal-delay must be specified\n"); 480 return -EINVAL; 481 } 482 483 return 0; 484 } 485 486 #ifdef CONFIG_OF_MDIO 487 static int dp83867_of_init(struct phy_device *phydev) 488 { 489 struct dp83867_private *dp83867 = phydev->priv; 490 struct device *dev = &phydev->mdio.dev; 491 struct device_node *of_node = dev->of_node; 492 int ret; 493 494 if (!of_node) 495 return -ENODEV; 496 497 /* Optional configuration */ 498 ret = of_property_read_u32(of_node, "ti,clk-output-sel", 499 &dp83867->clk_output_sel); 500 /* If not set, keep default */ 501 if (!ret) { 502 dp83867->set_clk_output = true; 503 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or 504 * DP83867_CLK_O_SEL_OFF. 505 */ 506 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK && 507 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) { 508 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n", 509 dp83867->clk_output_sel); 510 return -EINVAL; 511 } 512 } 513 514 if (of_property_read_bool(of_node, "ti,max-output-impedance")) 515 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX; 516 else if (of_property_read_bool(of_node, "ti,min-output-impedance")) 517 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN; 518 else 519 dp83867->io_impedance = -1; /* leave at default */ 520 521 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node, 522 "ti,dp83867-rxctrl-strap-quirk"); 523 524 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node, 525 "ti,sgmii-ref-clock-output-enable"); 526 527 528 dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV; 529 ret = of_property_read_u32(of_node, "ti,rx-internal-delay", 530 &dp83867->rx_id_delay); 531 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) { 532 phydev_err(phydev, 533 "ti,rx-internal-delay value of %u out of range\n", 534 dp83867->rx_id_delay); 535 return -EINVAL; 536 } 537 538 dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV; 539 ret = of_property_read_u32(of_node, "ti,tx-internal-delay", 540 &dp83867->tx_id_delay); 541 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) { 542 phydev_err(phydev, 543 "ti,tx-internal-delay value of %u out of range\n", 544 dp83867->tx_id_delay); 545 return -EINVAL; 546 } 547 548 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) 549 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN; 550 551 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap")) 552 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS; 553 554 ret = of_property_read_u32(of_node, "ti,fifo-depth", 555 &dp83867->tx_fifo_depth); 556 if (ret) { 557 ret = of_property_read_u32(of_node, "tx-fifo-depth", 558 &dp83867->tx_fifo_depth); 559 if (ret) 560 dp83867->tx_fifo_depth = 561 DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; 562 } 563 564 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { 565 phydev_err(phydev, "tx-fifo-depth value %u out of range\n", 566 dp83867->tx_fifo_depth); 567 return -EINVAL; 568 } 569 570 ret = of_property_read_u32(of_node, "rx-fifo-depth", 571 &dp83867->rx_fifo_depth); 572 if (ret) 573 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; 574 575 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { 576 phydev_err(phydev, "rx-fifo-depth value %u out of range\n", 577 dp83867->rx_fifo_depth); 578 return -EINVAL; 579 } 580 581 return 0; 582 } 583 #else 584 static int dp83867_of_init(struct phy_device *phydev) 585 { 586 return 0; 587 } 588 #endif /* CONFIG_OF_MDIO */ 589 590 static int dp83867_probe(struct phy_device *phydev) 591 { 592 struct dp83867_private *dp83867; 593 594 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867), 595 GFP_KERNEL); 596 if (!dp83867) 597 return -ENOMEM; 598 599 phydev->priv = dp83867; 600 601 return dp83867_of_init(phydev); 602 } 603 604 static int dp83867_config_init(struct phy_device *phydev) 605 { 606 struct dp83867_private *dp83867 = phydev->priv; 607 int ret, val, bs; 608 u16 delay; 609 610 /* Force speed optimization for the PHY even if it strapped */ 611 ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN, 612 DP83867_DOWNSHIFT_EN); 613 if (ret) 614 return ret; 615 616 ret = dp83867_verify_rgmii_cfg(phydev); 617 if (ret) 618 return ret; 619 620 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */ 621 if (dp83867->rxctrl_strap_quirk) 622 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 623 BIT(7)); 624 625 if (phy_interface_is_rgmii(phydev) || 626 phydev->interface == PHY_INTERFACE_MODE_SGMII) { 627 val = phy_read(phydev, MII_DP83867_PHYCTRL); 628 if (val < 0) 629 return val; 630 631 val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK; 632 val |= (dp83867->tx_fifo_depth << 633 DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT); 634 635 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 636 val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK; 637 val |= (dp83867->rx_fifo_depth << 638 DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT); 639 } 640 641 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); 642 if (ret) 643 return ret; 644 } 645 646 if (phy_interface_is_rgmii(phydev)) { 647 val = phy_read(phydev, MII_DP83867_PHYCTRL); 648 if (val < 0) 649 return val; 650 651 /* The code below checks if "port mirroring" N/A MODE4 has been 652 * enabled during power on bootstrap. 653 * 654 * Such N/A mode enabled by mistake can put PHY IC in some 655 * internal testing mode and disable RGMII transmission. 656 * 657 * In this particular case one needs to check STRAP_STS1 658 * register's bit 11 (marked as RESERVED). 659 */ 660 661 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1); 662 if (bs & DP83867_STRAP_STS1_RESERVED) 663 val &= ~DP83867_PHYCR_RESERVED_MASK; 664 665 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); 666 if (ret) 667 return ret; 668 669 /* If rgmii mode with no internal delay is selected, we do NOT use 670 * aligned mode as one might expect. Instead we use the PHY's default 671 * based on pin strapping. And the "mode 0" default is to *use* 672 * internal delay with a value of 7 (2.00 ns). 673 * 674 * Set up RGMII delays 675 */ 676 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL); 677 678 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); 679 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 680 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); 681 682 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 683 val |= DP83867_RGMII_TX_CLK_DELAY_EN; 684 685 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 686 val |= DP83867_RGMII_RX_CLK_DELAY_EN; 687 688 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val); 689 690 delay = 0; 691 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV) 692 delay |= dp83867->rx_id_delay; 693 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV) 694 delay |= dp83867->tx_id_delay << 695 DP83867_RGMII_TX_CLK_DELAY_SHIFT; 696 697 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL, 698 delay); 699 } 700 701 /* If specified, set io impedance */ 702 if (dp83867->io_impedance >= 0) 703 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, 704 DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK, 705 dp83867->io_impedance); 706 707 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 708 /* For support SPEED_10 in SGMII mode 709 * DP83867_10M_SGMII_RATE_ADAPT bit 710 * has to be cleared by software. That 711 * does not affect SPEED_100 and 712 * SPEED_1000. 713 */ 714 ret = phy_modify_mmd(phydev, DP83867_DEVADDR, 715 DP83867_10M_SGMII_CFG, 716 DP83867_10M_SGMII_RATE_ADAPT_MASK, 717 0); 718 if (ret) 719 return ret; 720 721 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5 722 * are 01). That is not enough to finalize autoneg on some 723 * devices. Increase this timer duration to maximum 16ms. 724 */ 725 ret = phy_modify_mmd(phydev, DP83867_DEVADDR, 726 DP83867_CFG4, 727 DP83867_CFG4_SGMII_ANEG_MASK, 728 DP83867_CFG4_SGMII_ANEG_TIMER_16MS); 729 730 if (ret) 731 return ret; 732 733 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL); 734 /* SGMII type is set to 4-wire mode by default. 735 * If we place appropriate property in dts (see above) 736 * switch on 6-wire mode. 737 */ 738 if (dp83867->sgmii_ref_clk_en) 739 val |= DP83867_SGMII_TYPE; 740 else 741 val &= ~DP83867_SGMII_TYPE; 742 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val); 743 } 744 745 val = phy_read(phydev, DP83867_CFG3); 746 /* Enable Interrupt output INT_OE in CFG3 register */ 747 if (phy_interrupt_is_valid(phydev)) 748 val |= DP83867_CFG3_INT_OE; 749 750 val |= DP83867_CFG3_ROBUST_AUTO_MDIX; 751 phy_write(phydev, DP83867_CFG3, val); 752 753 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP) 754 dp83867_config_port_mirroring(phydev); 755 756 /* Clock output selection if muxing property is set */ 757 if (dp83867->set_clk_output) { 758 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE; 759 760 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) { 761 val = DP83867_IO_MUX_CFG_CLK_O_DISABLE; 762 } else { 763 mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK; 764 val = dp83867->clk_output_sel << 765 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT; 766 } 767 768 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, 769 mask, val); 770 } 771 772 return 0; 773 } 774 775 static int dp83867_phy_reset(struct phy_device *phydev) 776 { 777 int err; 778 779 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET); 780 if (err < 0) 781 return err; 782 783 usleep_range(10, 20); 784 785 /* After reset FORCE_LINK_GOOD bit is set. Although the 786 * default value should be unset. Disable FORCE_LINK_GOOD 787 * for the phy to work properly. 788 */ 789 return phy_modify(phydev, MII_DP83867_PHYCTRL, 790 DP83867_PHYCR_FORCE_LINK_GOOD, 0); 791 } 792 793 static struct phy_driver dp83867_driver[] = { 794 { 795 .phy_id = DP83867_PHY_ID, 796 .phy_id_mask = 0xfffffff0, 797 .name = "TI DP83867", 798 /* PHY_GBIT_FEATURES */ 799 800 .probe = dp83867_probe, 801 .config_init = dp83867_config_init, 802 .soft_reset = dp83867_phy_reset, 803 804 .read_status = dp83867_read_status, 805 .get_tunable = dp83867_get_tunable, 806 .set_tunable = dp83867_set_tunable, 807 808 .get_wol = dp83867_get_wol, 809 .set_wol = dp83867_set_wol, 810 811 /* IRQ related */ 812 .ack_interrupt = dp83867_ack_interrupt, 813 .config_intr = dp83867_config_intr, 814 815 .suspend = genphy_suspend, 816 .resume = genphy_resume, 817 }, 818 }; 819 module_phy_driver(dp83867_driver); 820 821 static struct mdio_device_id __maybe_unused dp83867_tbl[] = { 822 { DP83867_PHY_ID, 0xfffffff0 }, 823 { } 824 }; 825 826 MODULE_DEVICE_TABLE(mdio, dp83867_tbl); 827 828 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver"); 829 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 830 MODULE_LICENSE("GPL v2"); 831