1 /* 2 * Driver for the Texas Instruments DP83867 PHY 3 * 4 * Copyright (C) 2015 Texas Instruments Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/ethtool.h> 17 #include <linux/kernel.h> 18 #include <linux/mii.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/phy.h> 22 23 #include <dt-bindings/net/ti-dp83867.h> 24 25 #define DP83867_PHY_ID 0x2000a231 26 #define DP83867_DEVADDR 0x1f 27 28 #define MII_DP83867_PHYCTRL 0x10 29 #define MII_DP83867_MICR 0x12 30 #define MII_DP83867_ISR 0x13 31 #define DP83867_CTRL 0x1f 32 33 /* Extended Registers */ 34 #define DP83867_RGMIICTL 0x0032 35 #define DP83867_RGMIIDCTL 0x0086 36 37 #define DP83867_SW_RESET BIT(15) 38 #define DP83867_SW_RESTART BIT(14) 39 40 /* MICR Interrupt bits */ 41 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) 42 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) 43 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) 44 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) 45 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) 46 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) 47 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) 48 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) 49 #define MII_DP83867_MICR_WOL_INT_EN BIT(3) 50 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) 51 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) 52 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0) 53 54 /* RGMIICTL bits */ 55 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) 56 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) 57 58 /* PHY CTRL bits */ 59 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 60 #define DP83867_PHYCR_FIFO_DEPTH_MASK (3 << 14) 61 62 /* RGMIIDCTL bits */ 63 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 64 65 struct dp83867_private { 66 int rx_id_delay; 67 int tx_id_delay; 68 int fifo_depth; 69 }; 70 71 static int dp83867_ack_interrupt(struct phy_device *phydev) 72 { 73 int err = phy_read(phydev, MII_DP83867_ISR); 74 75 if (err < 0) 76 return err; 77 78 return 0; 79 } 80 81 static int dp83867_config_intr(struct phy_device *phydev) 82 { 83 int micr_status; 84 85 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 86 micr_status = phy_read(phydev, MII_DP83867_MICR); 87 if (micr_status < 0) 88 return micr_status; 89 90 micr_status |= 91 (MII_DP83867_MICR_AN_ERR_INT_EN | 92 MII_DP83867_MICR_SPEED_CHNG_INT_EN | 93 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN | 94 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN); 95 96 return phy_write(phydev, MII_DP83867_MICR, micr_status); 97 } 98 99 micr_status = 0x0; 100 return phy_write(phydev, MII_DP83867_MICR, micr_status); 101 } 102 103 #ifdef CONFIG_OF_MDIO 104 static int dp83867_of_init(struct phy_device *phydev) 105 { 106 struct dp83867_private *dp83867 = phydev->priv; 107 struct device *dev = &phydev->mdio.dev; 108 struct device_node *of_node = dev->of_node; 109 int ret; 110 111 if (!of_node) 112 return -ENODEV; 113 114 ret = of_property_read_u32(of_node, "ti,rx-internal-delay", 115 &dp83867->rx_id_delay); 116 if (ret) 117 return ret; 118 119 ret = of_property_read_u32(of_node, "ti,tx-internal-delay", 120 &dp83867->tx_id_delay); 121 if (ret) 122 return ret; 123 124 return of_property_read_u32(of_node, "ti,fifo-depth", 125 &dp83867->fifo_depth); 126 } 127 #else 128 static int dp83867_of_init(struct phy_device *phydev) 129 { 130 return 0; 131 } 132 #endif /* CONFIG_OF_MDIO */ 133 134 static int dp83867_config_init(struct phy_device *phydev) 135 { 136 struct dp83867_private *dp83867; 137 int ret, val; 138 u16 delay; 139 140 if (!phydev->priv) { 141 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867), 142 GFP_KERNEL); 143 if (!dp83867) 144 return -ENOMEM; 145 146 phydev->priv = dp83867; 147 ret = dp83867_of_init(phydev); 148 if (ret) 149 return ret; 150 } else { 151 dp83867 = (struct dp83867_private *)phydev->priv; 152 } 153 154 if (phy_interface_is_rgmii(phydev)) { 155 val = phy_read(phydev, MII_DP83867_PHYCTRL); 156 if (val < 0) 157 return val; 158 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK; 159 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT); 160 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); 161 if (ret) 162 return ret; 163 } 164 165 if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) && 166 (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) { 167 val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL, 168 DP83867_DEVADDR); 169 170 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 171 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); 172 173 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 174 val |= DP83867_RGMII_TX_CLK_DELAY_EN; 175 176 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 177 val |= DP83867_RGMII_RX_CLK_DELAY_EN; 178 179 phy_write_mmd_indirect(phydev, DP83867_RGMIICTL, 180 DP83867_DEVADDR, val); 181 182 delay = (dp83867->rx_id_delay | 183 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); 184 185 phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL, 186 DP83867_DEVADDR, delay); 187 } 188 189 return 0; 190 } 191 192 static int dp83867_phy_reset(struct phy_device *phydev) 193 { 194 int err; 195 196 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET); 197 if (err < 0) 198 return err; 199 200 return dp83867_config_init(phydev); 201 } 202 203 static struct phy_driver dp83867_driver[] = { 204 { 205 .phy_id = DP83867_PHY_ID, 206 .phy_id_mask = 0xfffffff0, 207 .name = "TI DP83867", 208 .features = PHY_GBIT_FEATURES, 209 .flags = PHY_HAS_INTERRUPT, 210 211 .config_init = dp83867_config_init, 212 .soft_reset = dp83867_phy_reset, 213 214 /* IRQ related */ 215 .ack_interrupt = dp83867_ack_interrupt, 216 .config_intr = dp83867_config_intr, 217 218 .config_aneg = genphy_config_aneg, 219 .read_status = genphy_read_status, 220 .suspend = genphy_suspend, 221 .resume = genphy_resume, 222 }, 223 }; 224 module_phy_driver(dp83867_driver); 225 226 static struct mdio_device_id __maybe_unused dp83867_tbl[] = { 227 { DP83867_PHY_ID, 0xfffffff0 }, 228 { } 229 }; 230 231 MODULE_DEVICE_TABLE(mdio, dp83867_tbl); 232 233 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver"); 234 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 235 MODULE_LICENSE("GPL"); 236